From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 92335 invoked by alias); 19 Feb 2020 01:42:21 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 92319 invoked by uid 89); 19 Feb 2020 01:42:20 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.5 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.1 spammy=compressed X-HELO: mail-pg1-f194.google.com Received: from mail-pg1-f194.google.com (HELO mail-pg1-f194.google.com) (209.85.215.194) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 19 Feb 2020 01:42:19 +0000 Received: by mail-pg1-f194.google.com with SMTP id j4so11886576pgi.1 for ; Tue, 18 Feb 2020 17:42:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id; bh=M0y5nB1lSUVYPYFa7DhaNj576qzlklUkbFlPMOY8H+0=; b=Qud+S13nauG7EecDPRzhrFP03odwl/+EPvcDHoZxMJWE2HhAwzbV/vo3HUI6LO+Yle HaXa2ivC1epSAy4fszb+2qHJ39W1pfp1ohalgLyCWyAF225c3yE2fPbgaLaOSI0Sf78o AwvQOy0FOpnuCGvnpgXEqwsWR/O0CVWZZHhJi9SDEhWcxt6xUNBYEJAPypm6Qh+r8FY6 wuzCpeYB7uHs9AAsRS6hW6KNSc2S96MK7JzulPCuSusSYlbmYMKaZl3a2r/qk54zZ2mK BHeYnvecQJKxUFqIWCpqHj5UFDY5Zeo7QnoRFfghxbGn/OIpElCDb/8JXqKSU0URNQ9E UgRQ== Return-Path: Received: from gamma05.internal.sifive.com ([64.62.193.194]) by smtp.gmail.com with ESMTPSA id k5sm185817pju.29.2020.02.18.17.42.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Feb 2020 17:42:17 -0800 (PST) From: Nelson Chu To: binutils@sourceware.org Cc: jimw@sifive.com, kito.cheng@sifive.com Subject: [PATCH] RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero. Date: Wed, 19 Feb 2020 01:42:00 -0000 Message-Id: <1582076536-10638-1-git-send-email-nelson.chu@sifive.com> X-IsSubscribed: yes X-SW-Source: 2020-02/txt/msg00431.txt.bz2 gas/ * testsuite/gas/riscv/c-add-addi.d: New testcase. * testsuite/gas/riscv/c-add-addi.s: Likewise. opcodes/ * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed c.mv/c.li if rs1 is zero. --- gas/testsuite/gas/riscv/c-add-addi.d | 11 +++++++++++ gas/testsuite/gas/riscv/c-add-addi.s | 3 +++ opcodes/riscv-opc.c | 2 ++ 3 files changed, 16 insertions(+) create mode 100644 gas/testsuite/gas/riscv/c-add-addi.d create mode 100644 gas/testsuite/gas/riscv/c-add-addi.s diff --git a/gas/testsuite/gas/riscv/c-add-addi.d b/gas/testsuite/gas/riscv/c-add-addi.d new file mode 100644 index 0000000..14913df --- /dev/null +++ b/gas/testsuite/gas/riscv/c-add-addi.d @@ -0,0 +1,11 @@ +#as: +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+0:[ ]+4605[ ]+li[ ]+a2,1 +[ ]+2:[ ]+852e[ ]+mv[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/c-add-addi.s b/gas/testsuite/gas/riscv/c-add-addi.s new file mode 100644 index 0000000..5274491 --- /dev/null +++ b/gas/testsuite/gas/riscv/c-add-addi.s @@ -0,0 +1,3 @@ +.option rvc +addi a2, zero, 1 +add a0, zero, a1 diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index cc46d16..ceedcaf 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -269,12 +269,14 @@ const struct riscv_opcode riscv_opcodes[] = {"addi", 0, INSN_CLASS_C, "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, {"addi", 0, INSN_CLASS_C, "d,CU,z", MATCH_C_NOP, MASK_C_ADDI | MASK_RVC_IMM, match_c_nop, INSN_ALIAS }, {"addi", 0, INSN_CLASS_C, "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS }, +{"addi", 0, INSN_CLASS_C, "d,Cz,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS }, {"addi", 0, INSN_CLASS_I, "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 }, {"add", 0, INSN_CLASS_C, "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, {"add", 0, INSN_CLASS_C, "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, {"add", 0, INSN_CLASS_C, "d,CU,Co", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, {"add", 0, INSN_CLASS_C, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS }, {"add", 0, INSN_CLASS_C, "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS }, +{"add", 0, INSN_CLASS_C, "d,Cz,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, {"add", 0, INSN_CLASS_I, "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 }, /* This is used for TLS, where the fourth arg is %tprel_add, to get a reloc applied to an add instruction, for relaxation to use. */ -- 2.7.4