[PATCH 1/2] RISC-V: Add description for RISC-V Modifiers to as doc.

[Nelson Chu <nelson.chu@sifive.com>]

	gas/
	* doc/c-riscv.texi (relocation modifiers): Add documentation.
	(RISC-V-Formats): Update the section name from "Instruction Formats"
	to "RISC-V Instruction Formats".
---
 gas/doc/c-riscv.texi | 103 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 102 insertions(+), 1 deletion(-)

diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 599b5cf..8212a17 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -17,6 +17,7 @@
 @menu
 * RISC-V-Options::        RISC-V Options
 * RISC-V-Directives::     RISC-V Directives
+* RISC-V-Modifiers::      RISC-V Assembler Modifiers
 * RISC-V-Formats::        RISC-V Instruction Formats
 * RISC-V-ATTRIBUTE::      RISC-V Object Attribute
 @end menu
@@ -207,8 +208,108 @@ The @var{tag} is either an attribute number, or one of the following:
 
 @end table
 
+@node RISC-V-Modifiers
+@section RISC-V Assembler Modifiers
+
+RISC-V assembler supports following modifiers for relocatable address
+used in RISC-V instruction operands.  However, we also support some
+pseudo instructions to reduce the use of error-prone for these modifiers.
+
+@table @code
+@item %lo(@var{symbol})
+The low 12-bit of absolute address for @var{symbol}.
+
+@item %hi(@var{symbol})
+The high 20-bit of absolute address for @var{symbol}.  This is usually
+used with the %lo to represent a 32-bit absolute address.
+
+@smallexample
+	lui             a0, %hi(@var{symbol})     // R_RISCV_HI20
+	addi/load/store a0, a0, %lo(@var{symbol}) // R_RISCV_LO12_I/S
+@end smallexample
+
+@item %pcrel_lo(@var{label})
+The low 12-bit of relative address between pc and @var{symbol}.
+The @var{symbol} is related to the high part instrcution which marked
+by @var{label}.
+
+@item %pcrel_hi(@var{symbol})
+The high 20-bit of relative address between pc and @var{symbol}.
+This is usually used with the %pcrel_lo to represent a 4GB pc-relative range.
+
+@smallexample
+@var{label}:
+	auipc           a0, %pcrel_hi(@var{symbol})    // R_RISCV_PCREL_HI20
+	addi/load/store a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I/S
+@end smallexample
+
+Or you can use the pseudo lla/lw/sw/... instruction to do this.
+
+@smallexample
+	lla  a0, @var{symbol}
+@end smallexample
+
+@item %tprel_add(@var{symbol}
+This is used purely to associate the R_RISCV_TPREL_ADD relocation for
+TLS relaxation.
+
+@item %tprel_lo(@var{symbol})
+The low 12-bit of relative address between tp and @var{symbol}
+
+@item %tprel_hi(@var{symbol})
+The high 20-bit of relative address between tp and @var{symbol}.  This is
+usually used with the %tprel_lo and %tprel_add to access the thread local
+variable @var{symbol} in TLS Local Exec.
+
+@smallexample
+	lui        a5, %tprel_hi(@var{symbol})          // R_RISCV_TPREL_HI20
+	add        a5, a5, tp, %tprel_add(@var{symbol}) // R_RISCV_TPREL_ADD
+	load/store t0, %tprel_lo(@var{symbol})(a5)      // R_RISCV_TPREL_LO12_I/S
+@end smallexample
+
+@item %tls_ie_pcrel_hi(@var{symbol})
+The high 20-bit of relative address between pc and GOT entry.  It is usually
+used with the %pcrel_lo to access the thread local variable @var{symbol} in
+TLS Inital Exec.
+
+@smallexample
+	la.tls.ie  a5, @var{symbol}
+	add        a5, a5, tp
+	load/store t0, 0(a5)
+@end smallexample
+
+The pseudo la.tls.ie instruction can be expended to
+
+@smallexample
+@var{label}:
+	auipc a5, %tls_ie_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GOT_HI20
+	ld/lw a5, %pcrel_lo(@var{label})(a5)     // R_RISCV_PCREL_LO12_I/S
+@end smallexample
+
+@item %tls_gd_pcrel_hi(@var{symbol})
+The high 20-bit of relative address between pc and GOT entry.  It is usually
+used with the %pcrel_lo to access the thread local variable @var{symbol} in
+TLS Global Dynamic.
+
+@smallexample
+	la.tls.gd  a0, @var{symbol}
+	call       __tls_get_addr@@plt
+	mv         a5, a0
+	load/store t0, 0(a5)
+@end smallexample
+
+The pseudo la.tls.gd instruction can be expended to
+
+@smallexample
+@var{label}:
+	auipc a0, %tls_gd_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GD_HI20
+	addi  a0, a0, %pcrel_lo(@var{label})     // R_RISCV_PCREL_LO12_I/S
+@end smallexample
+
+@end table
+
 @node RISC-V-Formats
-@section Instruction Formats
+@section RISC-V Instruction Formats
 @cindex instruction formats, risc-v
 @cindex RISC-V instruction formats
 
-- 
2.7.4