From: Nelson Chu <nelson.chu@sifive.com>
To: binutils@sourceware.org, jrtc27@jrtc27.com
Cc: jimw@sifive.com, kito.cheng@sifive.com, palmerdabbelt@google.com
Subject: [PATCH 2/2] RISC-V: Support assembler modifier %got_pcrel_hi.
Date: Tue, 03 Mar 2020 10:22:00 -0000 [thread overview]
Message-ID: <1583230959-11401-3-git-send-email-nelson.chu@sifive.com> (raw)
In-Reply-To: <1583230959-11401-1-git-send-email-nelson.chu@sifive.com>
gas/
* config/tc-riscv.c: Support the modifier %got_pcrel_hi.
* doc/c-riscv.texi: Add documentation.
* testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new
modifier %got_pcrel_hi.
* testsuite/gas/riscv/no-relax-reloc.s: Likewise.
* testsuite/gas/riscv/relax-reloc.d: Likewise.
* testsuite/gas/riscv/relax-reloc.s: Likewise.
---
gas/config/tc-riscv.c | 1 +
gas/doc/c-riscv.texi | 12 ++++++++++++
gas/testsuite/gas/riscv/no-relax-reloc.d | 4 +++-
gas/testsuite/gas/riscv/no-relax-reloc.s | 7 +++++--
gas/testsuite/gas/riscv/relax-reloc.d | 7 +++++--
gas/testsuite/gas/riscv/relax-reloc.s | 7 +++++--
6 files changed, 31 insertions(+), 7 deletions(-)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index ddd4d14..168561e 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1308,6 +1308,7 @@ static const struct percent_op_match percent_op_utype[] =
{
{"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
{"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
+ {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20},
{"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
{"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
{"%hi", BFD_RELOC_RISCV_HI20},
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 8212a17..72605e7 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -249,6 +249,18 @@ Or you can use the pseudo lla/lw/sw/... instruction to do this.
lla a0, @var{symbol}
@end smallexample
+@item %got_pcrel_hi(@var{symbol}
+The high 20-bit of relative address between pc and the GOT entry of
+@var{symbol}. This is usually used with the %pcrel_lo to access the GOT entry.
+
+@smallexample
+@var{label}:
+ auipc a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20
+ addi/load/store a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I/S
+@end smallexample
+
+Also, the pseudo la instruction with PIC has the similar behavior.
+
@item %tprel_add(@var{symbol}
This is used purely to associate the R_RISCV_TPREL_ADD relocation for
TLS relaxation.
diff --git a/gas/testsuite/gas/riscv/no-relax-reloc.d b/gas/testsuite/gas/riscv/no-relax-reloc.d
index 62f28e0..c2ca1aa 100644
--- a/gas/testsuite/gas/riscv/no-relax-reloc.d
+++ b/gas/testsuite/gas/riscv/no-relax-reloc.d
@@ -9,4 +9,6 @@ RELOCATION RECORDS FOR .*
0+4 R_RISCV_LO12_I.*
0+8 R_RISCV_PCREL_HI20.*
0+c R_RISCV_PCREL_LO12_I.*
-0+10 R_RISCV_CALL.*
+0+10 R_RISCV_GOT_HI20.*
+0+14 R_RISCV_PCREL_LO12_I.*
+0+18 R_RISCV_CALL.*
diff --git a/gas/testsuite/gas/riscv/no-relax-reloc.s b/gas/testsuite/gas/riscv/no-relax-reloc.s
index 7f1a484..2aab995 100644
--- a/gas/testsuite/gas/riscv/no-relax-reloc.s
+++ b/gas/testsuite/gas/riscv/no-relax-reloc.s
@@ -2,7 +2,10 @@ target:
lui a5,%hi(target)
lw a5,%lo(target)(a5)
- .LA0: auipc a5,%pcrel_hi(bar)
- lw a0,%pcrel_lo(.LA0)(a5)
+ .LA0: auipc a5,%pcrel_hi(symbol1)
+ lw a0,%pcrel_lo(.LA0)(a5)
+
+ .LA1: auipc a5,%got_pcrel_hi(symbol2)
+ lw a0,%pcrel_lo(.LA1)(a5)
call target
diff --git a/gas/testsuite/gas/riscv/relax-reloc.d b/gas/testsuite/gas/riscv/relax-reloc.d
index f5f592c..623218e 100644
--- a/gas/testsuite/gas/riscv/relax-reloc.d
+++ b/gas/testsuite/gas/riscv/relax-reloc.d
@@ -13,5 +13,8 @@ RELOCATION RECORDS FOR .*
0+8 R_RISCV_RELAX.*
0+c R_RISCV_PCREL_LO12_I.*
0+c R_RISCV_RELAX.*
-0+10 R_RISCV_CALL.*
-0+10 R_RISCV_RELAX.*
+0+10 R_RISCV_GOT_HI20.*
+0+14 R_RISCV_PCREL_LO12_I.*
+0+14 R_RISCV_RELAX.*
+0+18 R_RISCV_CALL.*
+0+18 R_RISCV_RELAX.*
diff --git a/gas/testsuite/gas/riscv/relax-reloc.s b/gas/testsuite/gas/riscv/relax-reloc.s
index 7f1a484..2aab995 100644
--- a/gas/testsuite/gas/riscv/relax-reloc.s
+++ b/gas/testsuite/gas/riscv/relax-reloc.s
@@ -2,7 +2,10 @@ target:
lui a5,%hi(target)
lw a5,%lo(target)(a5)
- .LA0: auipc a5,%pcrel_hi(bar)
- lw a0,%pcrel_lo(.LA0)(a5)
+ .LA0: auipc a5,%pcrel_hi(symbol1)
+ lw a0,%pcrel_lo(.LA0)(a5)
+
+ .LA1: auipc a5,%got_pcrel_hi(symbol2)
+ lw a0,%pcrel_lo(.LA1)(a5)
call target
--
2.7.4
next prev parent reply other threads:[~2020-03-03 10:22 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-03 10:22 [PATCH 0/2] Add description for the RISC-V relocatable modifiers in as doc Nelson Chu
2020-03-03 10:22 ` Nelson Chu [this message]
2020-03-03 22:16 ` [PATCH 2/2] RISC-V: Support assembler modifier %got_pcrel_hi Jim Wilson
2020-03-04 0:07 ` Fangrui Song
2020-03-04 1:54 ` Nelson Chu
2020-03-03 10:22 ` [PATCH 1/2] RISC-V: Add description for RISC-V Modifiers to as doc Nelson Chu
2020-03-03 22:12 ` Jim Wilson
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