From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 3199 invoked by alias); 3 Mar 2020 10:22:53 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 3105 invoked by uid 89); 3 Mar 2020 10:22:52 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.3 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.1 spammy=2496 X-HELO: mail-pl1-f196.google.com Received: from mail-pl1-f196.google.com (HELO mail-pl1-f196.google.com) (209.85.214.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 03 Mar 2020 10:22:47 +0000 Received: by mail-pl1-f196.google.com with SMTP id t14so1117594plr.8 for ; Tue, 03 Mar 2020 02:22:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2bu0b1/ZwHGSOFZfx4OtbfH/rk9hfOxT3wEN5nkyvpo=; b=kGpa+ruPWAhOD5L2ohStNUshBm4GHxGzNuFs76Yee+zflZ0drw1hwiOJtqsxFDsB04 +MsWvQrifpmMj7mli+V3Z6OMAIJnihpRSKgL4oXRwA/MT0KP+JIOt1iU9P5i03KsmJ4u +OzZuqztBcGU3tkwUz/boOklAcutR5zCrXCIDFQcnz+BC3m4Mb+RnxMkMKd2jJD2/JCn bWkvzwOAO+e1wk+L4U+kJXwN4Di2RZIGyZlfFW/RPdUfv2elwP3qQ2Clskf3KlsIJs9Z r/aygmly0kAWTs1i3RMs+unT+GumwYfyl1BrZZK2KM2BFzySyJoz6SV1CxH/Ayu2z+66 yuGA== Return-Path: Received: from gamma05.internal.sifive.com ([64.62.193.194]) by smtp.gmail.com with ESMTPSA id c26sm23921083pfi.46.2020.03.03.02.22.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 03 Mar 2020 02:22:44 -0800 (PST) From: Nelson Chu To: binutils@sourceware.org, jrtc27@jrtc27.com Cc: jimw@sifive.com, kito.cheng@sifive.com, palmerdabbelt@google.com Subject: [PATCH 2/2] RISC-V: Support assembler modifier %got_pcrel_hi. Date: Tue, 03 Mar 2020 10:22:00 -0000 Message-Id: <1583230959-11401-3-git-send-email-nelson.chu@sifive.com> In-Reply-To: <1583230959-11401-1-git-send-email-nelson.chu@sifive.com> References: <1583230959-11401-1-git-send-email-nelson.chu@sifive.com> X-IsSubscribed: yes X-SW-Source: 2020-03/txt/msg00039.txt gas/ * config/tc-riscv.c: Support the modifier %got_pcrel_hi. * doc/c-riscv.texi: Add documentation. * testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new modifier %got_pcrel_hi. * testsuite/gas/riscv/no-relax-reloc.s: Likewise. * testsuite/gas/riscv/relax-reloc.d: Likewise. * testsuite/gas/riscv/relax-reloc.s: Likewise. --- gas/config/tc-riscv.c | 1 + gas/doc/c-riscv.texi | 12 ++++++++++++ gas/testsuite/gas/riscv/no-relax-reloc.d | 4 +++- gas/testsuite/gas/riscv/no-relax-reloc.s | 7 +++++-- gas/testsuite/gas/riscv/relax-reloc.d | 7 +++++-- gas/testsuite/gas/riscv/relax-reloc.s | 7 +++++-- 6 files changed, 31 insertions(+), 7 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index ddd4d14..168561e 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1308,6 +1308,7 @@ static const struct percent_op_match percent_op_utype[] = { {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20}, {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20}, + {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20}, {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20}, {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20}, {"%hi", BFD_RELOC_RISCV_HI20}, diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 8212a17..72605e7 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -249,6 +249,18 @@ Or you can use the pseudo lla/lw/sw/... instruction to do this. lla a0, @var{symbol} @end smallexample +@item %got_pcrel_hi(@var{symbol} +The high 20-bit of relative address between pc and the GOT entry of +@var{symbol}. This is usually used with the %pcrel_lo to access the GOT entry. + +@smallexample +@var{label}: + auipc a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20 + addi/load/store a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I/S +@end smallexample + +Also, the pseudo la instruction with PIC has the similar behavior. + @item %tprel_add(@var{symbol} This is used purely to associate the R_RISCV_TPREL_ADD relocation for TLS relaxation. diff --git a/gas/testsuite/gas/riscv/no-relax-reloc.d b/gas/testsuite/gas/riscv/no-relax-reloc.d index 62f28e0..c2ca1aa 100644 --- a/gas/testsuite/gas/riscv/no-relax-reloc.d +++ b/gas/testsuite/gas/riscv/no-relax-reloc.d @@ -9,4 +9,6 @@ RELOCATION RECORDS FOR .* 0+4 R_RISCV_LO12_I.* 0+8 R_RISCV_PCREL_HI20.* 0+c R_RISCV_PCREL_LO12_I.* -0+10 R_RISCV_CALL.* +0+10 R_RISCV_GOT_HI20.* +0+14 R_RISCV_PCREL_LO12_I.* +0+18 R_RISCV_CALL.* diff --git a/gas/testsuite/gas/riscv/no-relax-reloc.s b/gas/testsuite/gas/riscv/no-relax-reloc.s index 7f1a484..2aab995 100644 --- a/gas/testsuite/gas/riscv/no-relax-reloc.s +++ b/gas/testsuite/gas/riscv/no-relax-reloc.s @@ -2,7 +2,10 @@ target: lui a5,%hi(target) lw a5,%lo(target)(a5) - .LA0: auipc a5,%pcrel_hi(bar) - lw a0,%pcrel_lo(.LA0)(a5) + .LA0: auipc a5,%pcrel_hi(symbol1) + lw a0,%pcrel_lo(.LA0)(a5) + + .LA1: auipc a5,%got_pcrel_hi(symbol2) + lw a0,%pcrel_lo(.LA1)(a5) call target diff --git a/gas/testsuite/gas/riscv/relax-reloc.d b/gas/testsuite/gas/riscv/relax-reloc.d index f5f592c..623218e 100644 --- a/gas/testsuite/gas/riscv/relax-reloc.d +++ b/gas/testsuite/gas/riscv/relax-reloc.d @@ -13,5 +13,8 @@ RELOCATION RECORDS FOR .* 0+8 R_RISCV_RELAX.* 0+c R_RISCV_PCREL_LO12_I.* 0+c R_RISCV_RELAX.* -0+10 R_RISCV_CALL.* -0+10 R_RISCV_RELAX.* +0+10 R_RISCV_GOT_HI20.* +0+14 R_RISCV_PCREL_LO12_I.* +0+14 R_RISCV_RELAX.* +0+18 R_RISCV_CALL.* +0+18 R_RISCV_RELAX.* diff --git a/gas/testsuite/gas/riscv/relax-reloc.s b/gas/testsuite/gas/riscv/relax-reloc.s index 7f1a484..2aab995 100644 --- a/gas/testsuite/gas/riscv/relax-reloc.s +++ b/gas/testsuite/gas/riscv/relax-reloc.s @@ -2,7 +2,10 @@ target: lui a5,%hi(target) lw a5,%lo(target)(a5) - .LA0: auipc a5,%pcrel_hi(bar) - lw a0,%pcrel_lo(.LA0)(a5) + .LA0: auipc a5,%pcrel_hi(symbol1) + lw a0,%pcrel_lo(.LA0)(a5) + + .LA1: auipc a5,%got_pcrel_hi(symbol2) + lw a0,%pcrel_lo(.LA1)(a5) call target -- 2.7.4