From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 38971 invoked by alias); 4 Mar 2020 05:08:15 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 38912 invoked by uid 89); 4 Mar 2020 05:08:14 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.1 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mail-pl1-f178.google.com Received: from mail-pl1-f178.google.com (HELO mail-pl1-f178.google.com) (209.85.214.178) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 04 Mar 2020 05:08:12 +0000 Received: by mail-pl1-f178.google.com with SMTP id t14so464720plr.8 for ; Tue, 03 Mar 2020 21:08:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ytpjXnYOdMfOHxFLWmDUG0vD3CrDxmJyL1y5H6g5kTE=; b=Ur7LOItghJcSa/XtiOXSyqSdBRDv7gjmAz8cnJlNYLM+slAO14hBZuQkHKDCF7Nb6O 8g5NZBhZuhEdA0Hb3Qr1Rs/WiH0kIIHahLFZO37TC3sawdRp/JGAtyGu3QkGtTlsCeCg DQThwjw4vLwRFTkLKdHoRkNen4HYKkKpmO1vIYukCx/pfftX7/fAHE37DaUYlOaMBhIN 7Gs4wJ2BmqYqhJBZ8yzCThSfeNCECpMCoIFyJqr8P9ia8IaEcGytbEVnTf8aCgqwA4dI qkEUfRxKG0WmhfnOlvXqj2dBKF6Fzax/sIInL3b9dLrPvsxlUqMH1Y03Uq1IlS9RxHks xCHA== Return-Path: Received: from gamma05.internal.sifive.com ([64.62.193.194]) by smtp.gmail.com with ESMTPSA id g20sm845782pjv.20.2020.03.03.21.08.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 03 Mar 2020 21:08:09 -0800 (PST) From: Nelson Chu To: binutils@sourceware.org, jimw@sifive.com, jrtc27@jrtc27.com Cc: kito.cheng@sifive.com, palmerdabbelt@google.com Subject: [PATCH v2 1/2] RISC-V: Add description for RISC-V Modifiers to as doc. Date: Wed, 04 Mar 2020 05:08:00 -0000 Message-Id: <1583298485-8506-2-git-send-email-nelson.chu@sifive.com> In-Reply-To: <1583298485-8506-1-git-send-email-nelson.chu@sifive.com> References: <1583298485-8506-1-git-send-email-nelson.chu@sifive.com> X-IsSubscribed: yes X-SW-Source: 2020-03/txt/msg00069.txt gas/ * doc/c-riscv.texi (relocation modifiers): Add documentation. (RISC-V-Formats): Update the section name from "Instruction Formats" to "RISC-V Instruction Formats". --- gas/doc/c-riscv.texi | 112 ++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 111 insertions(+), 1 deletion(-) diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 599b5cf..6e932dc 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -17,6 +17,7 @@ @menu * RISC-V-Options:: RISC-V Options * RISC-V-Directives:: RISC-V Directives +* RISC-V-Modifiers:: RISC-V Assembler Modifiers * RISC-V-Formats:: RISC-V Instruction Formats * RISC-V-ATTRIBUTE:: RISC-V Object Attribute @end menu @@ -207,8 +208,117 @@ The @var{tag} is either an attribute number, or one of the following: @end table +@node RISC-V-Modifiers +@section RISC-V Assembler Modifiers + +The RISC-V assembler supports following modifiers for relocatable addresses +used in RISC-V instruction operands. However, we also support some pseudo +instructions that are easier to use than these modifiers. + +@table @code +@item %lo(@var{symbol}) +The low 12 bits of absolute address for @var{symbol}. + +@item %hi(@var{symbol}) +The high 20 bits of absolute address for @var{symbol}. This is usually +used with the %lo modifier to represent a 32-bit absolute address. + +@smallexample + lui a0, %hi(@var{symbol}) // R_RISCV_HI20 + addi a0, a0, %lo(@var{symbol}) // R_RISCV_LO12_I + + lui a0, %hi(@var{symbol}) // R_RISCV_HI20 + load/store a0, %lo(@var{symbol})(a0) // R_RISCV_LO12_I/S +@end smallexample + +@item %pcrel_lo(@var{label}) +The low 12 bits of relative address between pc and @var{symbol}. +The @var{symbol} is related to the high part instruction which is marked +by @var{label}. + +@item %pcrel_hi(@var{symbol}) +The high 20 bits of relative address between pc and @var{symbol}. +This is usually used with the %pcrel_lo modifier to represent a +/-2GB +pc-relative range. + +@smallexample +@var{label}: + auipc a0, %pcrel_hi(@var{symbol}) // R_RISCV_PCREL_HI20 + addi a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I + +@var{label}: + auipc a0, %pcrel_hi(@var{symbol}) // R_RISCV_PCREL_HI20 + load/store a0, %pcrel_lo(@var{label})(a0) // R_RISCV_PCREL_LO12_I/S +@end smallexample + +Or you can use the pseudo lla/lw/sw/... instruction to do this. + +@smallexample + lla a0, @var{symbol} +@end smallexample + +@item %tprel_add(@var{symbol}) +This is used purely to associate the R_RISCV_TPREL_ADD relocation for +TLS relaxation. This one is only valid as the fourth operand to the normally +3 operand add instruction. + +@item %tprel_lo(@var{symbol}) +The low 12 bits of relative address between tp and @var{symbol}. + +@item %tprel_hi(@var{symbol}) +The high 20 bits of relative address between tp and @var{symbol}. This is +usually used with the %tprel_lo and %tprel_add modifiers to access the thread +local variable @var{symbol} in TLS Local Exec. + +@smallexample + lui a5, %tprel_hi(@var{symbol}) // R_RISCV_TPREL_HI20 + add a5, a5, tp, %tprel_add(@var{symbol}) // R_RISCV_TPREL_ADD + load/store t0, %tprel_lo(@var{symbol})(a5) // R_RISCV_TPREL_LO12_I/S +@end smallexample + +@item %tls_ie_pcrel_hi(@var{symbol}) +The high 20 bits of relative address between pc and GOT entry. It is +usually used with the %pcrel_lo modifier to access the thread local +variable @var{symbol} in TLS Initial Exec. + +@smallexample + la.tls.ie a5, @var{symbol} + add a5, a5, tp + load/store t0, 0(a5) +@end smallexample + +The pseudo la.tls.ie instruction can be expended to + +@smallexample +@var{label}: + auipc a5, %tls_ie_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GOT_HI20 + load a5, %pcrel_lo(@var{label})(a5) // R_RISCV_PCREL_LO12_I +@end smallexample + +@item %tls_gd_pcrel_hi(@var{symbol}) +The high 20 bits of relative address between pc and GOT entry. It is +usually used with the %pcrel_lo modifier to access the thread local variable +@var{symbol} in TLS Global Dynamic. + +@smallexample + la.tls.gd a0, @var{symbol} + call __tls_get_addr@@plt + mv a5, a0 + load/store t0, 0(a5) +@end smallexample + +The pseudo la.tls.gd instruction can be expended to + +@smallexample +@var{label}: + auipc a0, %tls_gd_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GD_HI20 + addi a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I +@end smallexample + +@end table + @node RISC-V-Formats -@section Instruction Formats +@section RISC-V Instruction Formats @cindex instruction formats, risc-v @cindex RISC-V instruction formats -- 2.7.4