From: Nelson Chu <nelson.chu@sifive.com>
To: binutils@sourceware.org, gdb-patches@sourceware.org
Cc: palmer@dabbelt.com, kito.cheng@sifive.com, jimw@sifive.com,
andrew@sifive.com, andrew.burgess@embecosm.com, asb@lowrisc.org,
maxim.blinov@embecosm.com, nelson.chu@sifive.com
Subject: [PATCH v2 8/9] RISC-V: Disassembler dumps the CSR according to the chosen privilege spec.
Date: Tue, 5 May 2020 19:55:46 -0700 [thread overview]
Message-ID: <1588733747-18787-9-git-send-email-nelson.chu@sifive.com> (raw)
In-Reply-To: <1588733747-18787-1-git-send-email-nelson.chu@sifive.com>
Add new disassembler option -Mpriv-spec=[1.9|1.9.1|1.10|1.11] to dump the CSR
correctly. Report error message if the chosen priv version isn't supported.
Dump the CSR address direclty if it is invalid for the chosen spec.
gas/
* testsuite/gas/riscv/priv-reg.d: Removed.
* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the
CSR according to the priv spec 1.9.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the
CSR according to the priv spec 1.9.1.
* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the
CSR according to the priv spec 1.10.
* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the
CSR according to the priv spec 1.11.
opcodes/
* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
according to the chosen version. Build a hash table riscv_csr_hash to
store the valid CSR for the chosen pirv verison. Dump the direct
CSR address rather than it's name if it is invalid.
(parse_riscv_dis_option_without_args): New function. Parse the options
without arguments.
(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
parse the options without arguments first, and then handle the options
with arguments. Add the new option -Mpriv-spec, which has argument.
---
gas/testsuite/gas/riscv/priv-reg-version-1p10.d | 257 +++++++++++++++++++++++
gas/testsuite/gas/riscv/priv-reg-version-1p11.d | 257 +++++++++++++++++++++++
gas/testsuite/gas/riscv/priv-reg-version-1p9.d | 257 +++++++++++++++++++++++
gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d | 257 +++++++++++++++++++++++
gas/testsuite/gas/riscv/priv-reg.d | 256 ----------------------
opcodes/riscv-dis.c | 69 +++++-
6 files changed, 1090 insertions(+), 263 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p10.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p11.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p9.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
delete mode 100644 gas/testsuite/gas/riscv/priv-reg.d
diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
new file mode 100644
index 0000000..3739b89
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
@@ -0,0 +1,257 @@
+#as: -march=rv32if -mpriv-spec=1.10
+#source: priv-reg.s
+#objdump: -dr -Mpriv-spec=1.10
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
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diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
new file mode 100644
index 0000000..ca48abcc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
@@ -0,0 +1,257 @@
+#as: -march=rv32if -mpriv-spec=1.11
+#source: priv-reg.s
+#objdump: -dr -Mpriv-spec=1.11
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
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diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9.d
new file mode 100644
index 0000000..fa3c08f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9.d
@@ -0,0 +1,257 @@
+#as: -march=rv32if -mpriv-spec=1.9
+#source: priv-reg.s
+#objdump: -dr -Mpriv-spec=1.9
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
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diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
new file mode 100644
index 0000000..18011ed
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
@@ -0,0 +1,257 @@
+#as: -march=rv32if -mpriv-spec=1.9.1
+#source: priv-reg.s
+#objdump: -dr -Mpriv-spec=1.9.1
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
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diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d
deleted file mode 100644
index a0c3cd7..0000000
--- a/gas/testsuite/gas/riscv/priv-reg.d
+++ /dev/null
@@ -1,256 +0,0 @@
-#as: -march=rv32if -mpriv-spec=1.11
-#objdump: -dr
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
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-[ ]+[0-9a-f]+:[ ]+f1202573[ ]+csrr[ ]+a0,marchid
-[ ]+[0-9a-f]+:[ ]+f1302573[ ]+csrr[ ]+a0,mimpid
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-[ ]+[0-9a-f]+:[ ]+3b702573[ ]+csrr[ ]+a0,pmpaddr7
-[ ]+[0-9a-f]+:[ ]+3b802573[ ]+csrr[ ]+a0,pmpaddr8
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-[ ]+[0-9a-f]+:[ ]+b0002573[ ]+csrr[ ]+a0,mcycle
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-[ ]+[0-9a-f]+:[ ]+b0502573[ ]+csrr[ ]+a0,mhpmcounter5
-[ ]+[0-9a-f]+:[ ]+b0602573[ ]+csrr[ ]+a0,mhpmcounter6
-[ ]+[0-9a-f]+:[ ]+b0702573[ ]+csrr[ ]+a0,mhpmcounter7
-[ ]+[0-9a-f]+:[ ]+b0802573[ ]+csrr[ ]+a0,mhpmcounter8
-[ ]+[0-9a-f]+:[ ]+b0902573[ ]+csrr[ ]+a0,mhpmcounter9
-[ ]+[0-9a-f]+:[ ]+b0a02573[ ]+csrr[ ]+a0,mhpmcounter10
-[ ]+[0-9a-f]+:[ ]+b0b02573[ ]+csrr[ ]+a0,mhpmcounter11
-[ ]+[0-9a-f]+:[ ]+b0c02573[ ]+csrr[ ]+a0,mhpmcounter12
-[ ]+[0-9a-f]+:[ ]+b0d02573[ ]+csrr[ ]+a0,mhpmcounter13
-[ ]+[0-9a-f]+:[ ]+b0e02573[ ]+csrr[ ]+a0,mhpmcounter14
-[ ]+[0-9a-f]+:[ ]+b0f02573[ ]+csrr[ ]+a0,mhpmcounter15
-[ ]+[0-9a-f]+:[ ]+b1002573[ ]+csrr[ ]+a0,mhpmcounter16
-[ ]+[0-9a-f]+:[ ]+b1102573[ ]+csrr[ ]+a0,mhpmcounter17
-[ ]+[0-9a-f]+:[ ]+b1202573[ ]+csrr[ ]+a0,mhpmcounter18
-[ ]+[0-9a-f]+:[ ]+b1302573[ ]+csrr[ ]+a0,mhpmcounter19
-[ ]+[0-9a-f]+:[ ]+b1402573[ ]+csrr[ ]+a0,mhpmcounter20
-[ ]+[0-9a-f]+:[ ]+b1502573[ ]+csrr[ ]+a0,mhpmcounter21
-[ ]+[0-9a-f]+:[ ]+b1602573[ ]+csrr[ ]+a0,mhpmcounter22
-[ ]+[0-9a-f]+:[ ]+b1702573[ ]+csrr[ ]+a0,mhpmcounter23
-[ ]+[0-9a-f]+:[ ]+b1802573[ ]+csrr[ ]+a0,mhpmcounter24
-[ ]+[0-9a-f]+:[ ]+b1902573[ ]+csrr[ ]+a0,mhpmcounter25
-[ ]+[0-9a-f]+:[ ]+b1a02573[ ]+csrr[ ]+a0,mhpmcounter26
-[ ]+[0-9a-f]+:[ ]+b1b02573[ ]+csrr[ ]+a0,mhpmcounter27
-[ ]+[0-9a-f]+:[ ]+b1c02573[ ]+csrr[ ]+a0,mhpmcounter28
-[ ]+[0-9a-f]+:[ ]+b1d02573[ ]+csrr[ ]+a0,mhpmcounter29
-[ ]+[0-9a-f]+:[ ]+b1e02573[ ]+csrr[ ]+a0,mhpmcounter30
-[ ]+[0-9a-f]+:[ ]+b1f02573[ ]+csrr[ ]+a0,mhpmcounter31
-[ ]+[0-9a-f]+:[ ]+b8002573[ ]+csrr[ ]+a0,mcycleh
-[ ]+[0-9a-f]+:[ ]+b8202573[ ]+csrr[ ]+a0,minstreth
-[ ]+[0-9a-f]+:[ ]+b8302573[ ]+csrr[ ]+a0,mhpmcounter3h
-[ ]+[0-9a-f]+:[ ]+b8402573[ ]+csrr[ ]+a0,mhpmcounter4h
-[ ]+[0-9a-f]+:[ ]+b8502573[ ]+csrr[ ]+a0,mhpmcounter5h
-[ ]+[0-9a-f]+:[ ]+b8602573[ ]+csrr[ ]+a0,mhpmcounter6h
-[ ]+[0-9a-f]+:[ ]+b8702573[ ]+csrr[ ]+a0,mhpmcounter7h
-[ ]+[0-9a-f]+:[ ]+b8802573[ ]+csrr[ ]+a0,mhpmcounter8h
-[ ]+[0-9a-f]+:[ ]+b8902573[ ]+csrr[ ]+a0,mhpmcounter9h
-[ ]+[0-9a-f]+:[ ]+b8a02573[ ]+csrr[ ]+a0,mhpmcounter10h
-[ ]+[0-9a-f]+:[ ]+b8b02573[ ]+csrr[ ]+a0,mhpmcounter11h
-[ ]+[0-9a-f]+:[ ]+b8c02573[ ]+csrr[ ]+a0,mhpmcounter12h
-[ ]+[0-9a-f]+:[ ]+b8d02573[ ]+csrr[ ]+a0,mhpmcounter13h
-[ ]+[0-9a-f]+:[ ]+b8e02573[ ]+csrr[ ]+a0,mhpmcounter14h
-[ ]+[0-9a-f]+:[ ]+b8f02573[ ]+csrr[ ]+a0,mhpmcounter15h
-[ ]+[0-9a-f]+:[ ]+b9002573[ ]+csrr[ ]+a0,mhpmcounter16h
-[ ]+[0-9a-f]+:[ ]+b9102573[ ]+csrr[ ]+a0,mhpmcounter17h
-[ ]+[0-9a-f]+:[ ]+b9202573[ ]+csrr[ ]+a0,mhpmcounter18h
-[ ]+[0-9a-f]+:[ ]+b9302573[ ]+csrr[ ]+a0,mhpmcounter19h
-[ ]+[0-9a-f]+:[ ]+b9402573[ ]+csrr[ ]+a0,mhpmcounter20h
-[ ]+[0-9a-f]+:[ ]+b9502573[ ]+csrr[ ]+a0,mhpmcounter21h
-[ ]+[0-9a-f]+:[ ]+b9602573[ ]+csrr[ ]+a0,mhpmcounter22h
-[ ]+[0-9a-f]+:[ ]+b9702573[ ]+csrr[ ]+a0,mhpmcounter23h
-[ ]+[0-9a-f]+:[ ]+b9802573[ ]+csrr[ ]+a0,mhpmcounter24h
-[ ]+[0-9a-f]+:[ ]+b9902573[ ]+csrr[ ]+a0,mhpmcounter25h
-[ ]+[0-9a-f]+:[ ]+b9a02573[ ]+csrr[ ]+a0,mhpmcounter26h
-[ ]+[0-9a-f]+:[ ]+b9b02573[ ]+csrr[ ]+a0,mhpmcounter27h
-[ ]+[0-9a-f]+:[ ]+b9c02573[ ]+csrr[ ]+a0,mhpmcounter28h
-[ ]+[0-9a-f]+:[ ]+b9d02573[ ]+csrr[ ]+a0,mhpmcounter29h
-[ ]+[0-9a-f]+:[ ]+b9e02573[ ]+csrr[ ]+a0,mhpmcounter30h
-[ ]+[0-9a-f]+:[ ]+b9f02573[ ]+csrr[ ]+a0,mhpmcounter31h
-[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
-[ ]+[0-9a-f]+:[ ]+32302573[ ]+csrr[ ]+a0,mhpmevent3
-[ ]+[0-9a-f]+:[ ]+32402573[ ]+csrr[ ]+a0,mhpmevent4
-[ ]+[0-9a-f]+:[ ]+32502573[ ]+csrr[ ]+a0,mhpmevent5
-[ ]+[0-9a-f]+:[ ]+32602573[ ]+csrr[ ]+a0,mhpmevent6
-[ ]+[0-9a-f]+:[ ]+32702573[ ]+csrr[ ]+a0,mhpmevent7
-[ ]+[0-9a-f]+:[ ]+32802573[ ]+csrr[ ]+a0,mhpmevent8
-[ ]+[0-9a-f]+:[ ]+32902573[ ]+csrr[ ]+a0,mhpmevent9
-[ ]+[0-9a-f]+:[ ]+32a02573[ ]+csrr[ ]+a0,mhpmevent10
-[ ]+[0-9a-f]+:[ ]+32b02573[ ]+csrr[ ]+a0,mhpmevent11
-[ ]+[0-9a-f]+:[ ]+32c02573[ ]+csrr[ ]+a0,mhpmevent12
-[ ]+[0-9a-f]+:[ ]+32d02573[ ]+csrr[ ]+a0,mhpmevent13
-[ ]+[0-9a-f]+:[ ]+32e02573[ ]+csrr[ ]+a0,mhpmevent14
-[ ]+[0-9a-f]+:[ ]+32f02573[ ]+csrr[ ]+a0,mhpmevent15
-[ ]+[0-9a-f]+:[ ]+33002573[ ]+csrr[ ]+a0,mhpmevent16
-[ ]+[0-9a-f]+:[ ]+33102573[ ]+csrr[ ]+a0,mhpmevent17
-[ ]+[0-9a-f]+:[ ]+33202573[ ]+csrr[ ]+a0,mhpmevent18
-[ ]+[0-9a-f]+:[ ]+33302573[ ]+csrr[ ]+a0,mhpmevent19
-[ ]+[0-9a-f]+:[ ]+33402573[ ]+csrr[ ]+a0,mhpmevent20
-[ ]+[0-9a-f]+:[ ]+33502573[ ]+csrr[ ]+a0,mhpmevent21
-[ ]+[0-9a-f]+:[ ]+33602573[ ]+csrr[ ]+a0,mhpmevent22
-[ ]+[0-9a-f]+:[ ]+33702573[ ]+csrr[ ]+a0,mhpmevent23
-[ ]+[0-9a-f]+:[ ]+33802573[ ]+csrr[ ]+a0,mhpmevent24
-[ ]+[0-9a-f]+:[ ]+33902573[ ]+csrr[ ]+a0,mhpmevent25
-[ ]+[0-9a-f]+:[ ]+33a02573[ ]+csrr[ ]+a0,mhpmevent26
-[ ]+[0-9a-f]+:[ ]+33b02573[ ]+csrr[ ]+a0,mhpmevent27
-[ ]+[0-9a-f]+:[ ]+33c02573[ ]+csrr[ ]+a0,mhpmevent28
-[ ]+[0-9a-f]+:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
-[ ]+[0-9a-f]+:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
-[ ]+[0-9a-f]+:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
-[ ]+[0-9a-f]+:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
-[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
-[ ]+[0-9a-f]+:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
-[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
-[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
-[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
-[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
-[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,dscratch1
-[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
-[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
-[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
-[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
-[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
-[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
-[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,hstatus
-[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg
-[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,hideleg
-[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,hie
-[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,htvec
-[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,hscratch
-[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,hepc
-[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,hcause
-[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,hbadaddr
-[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,hip
-[ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,mbase
-[ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,mbound
-[ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,mibase
-[ ]+[0-9a-f]+:[ ]+38302573[ ]+csrr[ ]+a0,mibound
-[ ]+[0-9a-f]+:[ ]+38402573[ ]+csrr[ ]+a0,mdbase
-[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
-[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
-[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 98302ff..c5a0d36 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -31,6 +31,8 @@
#include "bfd_stdint.h"
#include <ctype.h>
+static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
+
struct riscv_private_data
{
bfd_vma gp;
@@ -52,8 +54,8 @@ set_default_riscv_dis_options (void)
no_aliases = 0;
}
-static void
-parse_riscv_dis_option (const char *option)
+static bfd_boolean
+parse_riscv_dis_option_without_args (const char *option)
{
if (strcmp (option, "no-aliases") == 0)
no_aliases = 1;
@@ -63,6 +65,44 @@ parse_riscv_dis_option (const char *option)
riscv_fpr_names = riscv_fpr_names_numeric;
}
else
+ return FALSE;
+ return TRUE;
+}
+
+static void
+parse_riscv_dis_option (const char *option)
+{
+ char *equal, *value;
+
+ if (parse_riscv_dis_option_without_args (option))
+ return;
+
+ equal = strchr (option, '=');
+ if (equal == NULL)
+ {
+ /* The option without '=' should be defined above. */
+ opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
+ return;
+ }
+ if (equal == option
+ || *(equal + 1) == '\0')
+ {
+ /* Invalid options with '=', no option name before '=',
+ and no value after '='. */
+ opcodes_error_handler (_("unrecognized disassembler option with '=': %s"),
+ option);
+ return;
+ }
+
+ *equal = '\0';
+ value = equal + 1;
+ if (strcmp (option, "priv-spec") == 0)
+ {
+ if (!riscv_get_priv_spec_class (value, &default_priv_spec))
+ opcodes_error_handler (_("unknown privilege spec set by %s=%s"),
+ option, value);
+ }
+ else
{
/* xgettext:c-format */
opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
@@ -322,17 +362,32 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
case 'E':
{
- const char* csr_name = NULL;
+ static const char *riscv_csr_hash[4096]; /* Total 2^12 CSR */
+ static bfd_boolean init_csr = FALSE;
unsigned int csr = EXTRACT_OPERAND (CSR, l);
- switch (csr)
+
+ if (!init_csr)
{
+ unsigned int i;
+ for (i = 0; i < 4096; i++)
+ riscv_csr_hash[i] = NULL;
+
+ /* Set to the newest privilege version. */
+ if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
+ default_priv_spec = PRIV_SPEC_CLASS_DRAFT - 1;
+
#define DECLARE_CSR(name, num, class, define_version, abort_version) \
- case num: csr_name = #name; break;
+ if (default_priv_spec >= define_version \
+ && default_priv_spec < abort_version) \
+ riscv_csr_hash[num] = #name;
+#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
+ DECLARE_CSR(name, num, class, define_version, abort_version)
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
}
- if (csr_name)
- print (info->stream, "%s", csr_name);
+
+ if (riscv_csr_hash[csr] != NULL)
+ print (info->stream, "%s", riscv_csr_hash[csr]);
else
print (info->stream, "0x%x", csr);
break;
--
2.7.4
next prev parent reply other threads:[~2020-05-06 2:56 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-06 2:55 [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR Nelson Chu
2020-05-06 2:55 ` [PATCH v2 1/9] RISC-V: Remove the redundant gas test file Nelson Chu
2020-05-19 9:07 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 2/9] RISC-V: Forgot to update the priv-reg-fail-read-only-01 test case Nelson Chu
2020-05-19 9:07 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions Nelson Chu
2020-05-19 9:07 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default Nelson Chu
2020-05-19 9:07 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version Nelson Chu
2020-05-19 9:08 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 6/9] RISC-V: Support configure option to choose the " Nelson Chu
2020-05-19 9:08 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 7/9] RISC-V: Make privilege spec attributes workable Nelson Chu
2020-05-19 9:08 ` Nelson Chu
2020-05-06 2:55 ` Nelson Chu [this message]
2020-05-19 9:08 ` [PATCH v2 8/9] RISC-V: Disassembler dumps the CSR according to the chosen privilege spec Nelson Chu
2020-05-06 2:55 ` [PATCH v2 9/9] RISC-V: Add documents and --help for the new GAS and OBJDUMP options Nelson Chu
2020-05-19 9:08 ` Nelson Chu
2020-05-19 9:07 ` [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR Nelson Chu
2020-05-20 16:27 ` Nick Clifton
2020-05-21 2:38 ` Nelson Chu
2020-05-21 7:29 ` Nick Clifton
2020-05-21 9:11 ` Nelson Chu
2020-05-28 20:09 ` Jim Wilson
2020-05-29 1:02 ` Nelson Chu
2020-06-01 21:35 ` Jim Wilson
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