From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by sourceware.org (Postfix) with ESMTPS id 96BB73858C3A for ; Thu, 30 Dec 2021 16:00:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 96BB73858C3A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-pj1-x1034.google.com with SMTP id y16-20020a17090a6c9000b001b13ffaa625so28344049pjj.2 for ; Thu, 30 Dec 2021 08:00:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VeK4TYNaURqJoXKwaKjE0zsKeSu3cyuRP2EDuKxctjg=; b=nFRQhK5ZeS2utHuVcwx/SIL7VrlJcarBr5aLFdCJv8Vu29KYOzVnmIkvmD8Mcshlmn lTYqjuvZPeLLztroo8Kph/YTSOJ3xyabpnZCKlUuR5YvM+VTEPWKJv8STFy8paylNMBU r8TPR9RJCVLd/X06+8yit0+GN6Qy+w5/gbCaUQK1NuyfahiF3htZEyeuk741/e0LGOal LWq5JzQXG7gSRavYhHM1wlwgrmHSPWVFNTtno62iIFwtudH1EAnKhl3mls4NqBUS8S+v xb2+k+bpYR+fc4uttBwpO+GdVmtNOzmFtTtfvuf5zJ0Nk021itUdj0cWGRHt0g7jOqS+ Ow7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VeK4TYNaURqJoXKwaKjE0zsKeSu3cyuRP2EDuKxctjg=; b=Rrjz9d0jPaTpr84YCeCtP0HCGelNUsmBxPxmnEVLjNiPDWcNf7UnSk8ilhjK8EBwUo AMA5X4NDlIfgyAD3SDsTIN9pC52eVAv4jO5oMUQRbLft9THNS1gl57Gbfb8EIOxgUUp/ uS7a8GaMBri5NkLyhsNr9a87UGfASVRFdwp0ntiegIaAUS+EXXPRo7QyIH81O60w2Ezb zBQfv+AA3j6sg0l8Fy6QebVNpZGUlx8Zke2P4ZKKwa6EBXrYDybJtDdm354+oyDMC6Yd HVfiJmFAxD47QN7neAQ1MbvOxytGoQABbTsBRZjXQNdTukyF1Tigocxh4f7IDJRRBnm1 dcSA== X-Gm-Message-State: AOAM533t4buSKetC+S91/6XOYkyl3V0vod4zFCzQ9VI4UQh/Sq9T3mm0 2/2gTwYgWOnM9F19+/q+jBp7AQuqx2lidQ== X-Google-Smtp-Source: ABdhPJxICQ8tUWmYp4CBqnJF58qIawgFmojbK8XqJvyUaNlqlXPEUy6O/yI17BtDVdzUccrz8YFu8Q== X-Received: by 2002:a17:90b:190f:: with SMTP id mp15mr38833862pjb.210.1640880030389; Thu, 30 Dec 2021 08:00:30 -0800 (PST) Received: from gamma00.internal.sifive.com ([64.62.193.194]) by smtp.gmail.com with ESMTPSA id c19sm28673386pjv.39.2021.12.30.08.00.29 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 Dec 2021 08:00:29 -0800 (PST) From: Nelson Chu To: binutils@sourceware.org, jim.wilson.gcc@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com, andrew@sifive.com Subject: [PATCH 2/2] RISC-V: Updated the default ISA spec to 20191213. Date: Thu, 30 Dec 2021 08:00:28 -0800 Message-Id: <1640880028-16820-2-git-send-email-nelson.chu@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1640880028-16820-1-git-send-email-nelson.chu@sifive.com> References: <1640880028-16820-1-git-send-email-nelson.chu@sifive.com> X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Dec 2021 16:00:35 -0000 Update the default ISA spec from 2.2 to 20191213 will change the default version of i from 2.0 to 2.1. Since zicsr and zifencei are separated from i 2.1, users need to add them in the architecture string if they need fence.i and csr instructions. Besides, we also allow old ISA spec can recognize zicsr and zifencei, but we won't output them since they are already included in the i extension when i's version is less than 2.1. bfd/ * elfxx-riscv.c (riscv_parse_add_subset): Allow old ISA spec can recognize zicsr and zifencei. gas/ * config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Updated to 20191213. * testsuite/gas/riscv/csr-version-1p10.d: Added zicsr to -march since the default version of i is 2.1. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/option-arch-03.d: Updated i's version to 2.1. * testsuite/gas/riscv/option-arch-03.s: Likewise. ld/ * testsuite/ld-riscv-elf/call-relax.d: Added zicsr to -march since the default version of i is 2.1. * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated i's version to 2.1. * testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-01b.: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-c.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-d.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified.d: Likewise. --- bfd/elfxx-riscv.c | 4 +++- gas/config/tc-riscv.c | 2 +- gas/testsuite/gas/riscv/csr-version-1p10.d | 2 +- gas/testsuite/gas/riscv/csr-version-1p11.d | 2 +- gas/testsuite/gas/riscv/csr-version-1p12.d | 2 +- gas/testsuite/gas/riscv/csr-version-1p9p1.d | 2 +- gas/testsuite/gas/riscv/option-arch-03.d | 2 +- gas/testsuite/gas/riscv/option-arch-03.s | 2 +- ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d | 2 +- ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s | 2 +- ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s | 2 +- ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d | 2 +- ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s | 2 +- ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s | 2 +- ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d | 2 +- ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s | 2 +- ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s | 2 +- ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-a.s | 2 +- ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-b.s | 2 +- ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-c.s | 2 +- ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-d.s | 2 +- ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified.d | 4 +--- ld/testsuite/ld-riscv-elf/call-relax.d | 2 +- 23 files changed, 25 insertions(+), 25 deletions(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index c575ab0..83705ec 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1562,7 +1562,9 @@ riscv_parse_add_subset (riscv_parse_subset_t *rps, rps->error_handler (_("x ISA extension `%s' must be set with the versions"), subset); - else + /* Allow old ISA spec can recognize zicsr and zifencei. */ + else if (strcmp (subset, "zicsr") != 0 + && strcmp (subset, "zifencei") != 0) rps->error_handler (_("cannot find default versions of the ISA extension `%s'"), subset); diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index dbf0e23..debe6bf 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -104,7 +104,7 @@ struct riscv_csr_extra /* Need to sync the version with RISC-V compiler. */ #ifndef DEFAULT_RISCV_ISA_SPEC -#define DEFAULT_RISCV_ISA_SPEC "2.2" +#define DEFAULT_RISCV_ISA_SPEC "20191213" #endif #ifndef DEFAULT_RISCV_PRIV_SPEC diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d index ee56ae3..88da724 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p10.d +++ b/gas/testsuite/gas/riscv/csr-version-1p10.d @@ -1,4 +1,4 @@ -#as: -march=rv64i -mcsr-check -mpriv-spec=1.10 +#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.10 #source: csr.s #warning_output: csr-version-1p10.l #objdump: -dr -Mpriv-spec=1.10 diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d index a1d8169..b40c1d5 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p11.d +++ b/gas/testsuite/gas/riscv/csr-version-1p11.d @@ -1,4 +1,4 @@ -#as: -march=rv64i -mcsr-check -mpriv-spec=1.11 +#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.11 #source: csr.s #warning_output: csr-version-1p11.l #objdump: -dr -Mpriv-spec=1.11 diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d index c4c2118..fbc30ee 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p12.d +++ b/gas/testsuite/gas/riscv/csr-version-1p12.d @@ -1,4 +1,4 @@ -#as: -march=rv64i -mcsr-check -mpriv-spec=1.12 +#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.12 #source: csr.s #warning_output: csr-version-1p12.l #objdump: -dr -Mpriv-spec=1.12 diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d index 01e05ae..a96e8c9 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d @@ -1,4 +1,4 @@ -#as: -march=rv64i -mcsr-check -mpriv-spec=1.9.1 +#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.9.1 #source: csr.s #warning_output: csr-version-1p9p1.l #objdump: -dr -Mpriv-spec=1.9.1 diff --git a/gas/testsuite/gas/riscv/option-arch-03.d b/gas/testsuite/gas/riscv/option-arch-03.d index b621d03..62d7f7d 100644 --- a/gas/testsuite/gas/riscv/option-arch-03.d +++ b/gas/testsuite/gas/riscv/option-arch-03.d @@ -4,5 +4,5 @@ Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv32i2p0_c2p0" + Tag_RISCV_arch: "rv32i2p1_c2p0" #... diff --git a/gas/testsuite/gas/riscv/option-arch-03.s b/gas/testsuite/gas/riscv/option-arch-03.s index d982a0b..ccdb1c3 100644 --- a/gas/testsuite/gas/riscv/option-arch-03.s +++ b/gas/testsuite/gas/riscv/option-arch-03.s @@ -1,3 +1,3 @@ .attribute arch, "rv64ic" .option arch, +d2p0, -c -.option arch, rv32ic +.option arch, rv32i2p1c2p0 diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d index c148cdb..a4b0322 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d @@ -6,4 +6,4 @@ Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv32i2p0_m2p0" + Tag_RISCV_arch: "rv32i2p1_m2p0" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s index acc98a5..ea097f9 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s @@ -1 +1 @@ - .attribute arch, "rv32i2p0_m2p0" + .attribute arch, "rv32i2p1_m2p0" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s index acc98a5..ea097f9 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s @@ -1 +1 @@ - .attribute arch, "rv32i2p0_m2p0" + .attribute arch, "rv32i2p1_m2p0" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d index bc0e0fd..852fd55 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d @@ -6,4 +6,4 @@ Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv32i2p0_m2p0" + Tag_RISCV_arch: "rv32i2p1_m2p0" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s index acc98a5..ea097f9 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s @@ -1 +1 @@ - .attribute arch, "rv32i2p0_m2p0" + .attribute arch, "rv32i2p1_m2p0" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s index 65d0fef..610c7e5 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s @@ -1 +1 @@ - .attribute arch, "rv32i2p0" + .attribute arch, "rv32i2p1" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d index 374a043..c1cf808 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d @@ -6,4 +6,4 @@ Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0" + Tag_RISCV_arch: "rv32i2p1_m2p0_xbar2p0_xfoo2p0" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s index b86cc55..3a9fb97 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s @@ -1 +1 @@ - .attribute arch, "rv32i2p0_m2p0_xfoo2p0" + .attribute arch, "rv32i2p1_m2p0_xfoo2p0" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s index 376e373..878f2de 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s @@ -1 +1 @@ - .attribute arch, "rv32i2p0_xbar2p0" + .attribute arch, "rv32i2p1_xbar2p0" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-a.s index e7fadf0..e05cb1e 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-a.s +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-a.s @@ -1 +1 @@ - .attribute arch, "rv32i0p1_m0p1_a0p1_zicsr0p1_xunknown0p1" + .attribute arch, "rv32i2p1_m0p1_a0p1_zicsr0p1_xunknown0p1" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-b.s index 1a7a11c..91de4f4 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-b.s +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-b.s @@ -1 +1 @@ - .attribute arch, "rv32i0p9_m0p9_a0p9_zicsr0p9_xunknown0p9" + .attribute arch, "rv32i2p1_m0p9_a0p9_zicsr0p9_xunknown0p9" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-c.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-c.s index 1a935e7..5b42d52 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-c.s +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-c.s @@ -1 +1 @@ - .attribute arch, "rv32i1p0_m1p0_a1p0_zicsr1p0_xunknown1p0" + .attribute arch, "rv32i2p1_m1p0_a1p0_zicsr1p0_xunknown1p0" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-d.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-d.s index 3dbf8a2..4c4421b 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-d.s +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-d.s @@ -1 +1 @@ - .attribute arch, "rv32i2p0_m2p0_a2p0_zicsr2p0_xunknown2p0" + .attribute arch, "rv32i2p1_m2p0_a2p0_zicsr2p0_xunknown2p0" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified.d index b835aa3..8b9140c 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified.d @@ -4,12 +4,10 @@ #source: attr-merge-arch-failed-ratified-d.s #as: -march-attr #ld: -r -m[riscv_choose_ilp32_emul] -#warning: .*mis-matched ISA version 0.9 for 'i' extension, the output version is 0.1 #warning: .*mis-matched ISA version 0.9 for 'm' extension, the output version is 0.1 #warning: .*mis-matched ISA version 0.9 for 'a' extension, the output version is 0.1 #warning: .*mis-matched ISA version 0.9 for 'zicsr' extension, the output version is 0.1 #warning: .*mis-matched ISA version 0.9 for 'xunknown' extension, the output version is 0.1 -#warning: .*mis-matched ISA version 1.0 for 'i' extension, the output version is 0.9 #warning: .*mis-matched ISA version 1.0 for 'm' extension, the output version is 0.9 #warning: .*mis-matched ISA version 1.0 for 'a' extension, the output version is 0.9 #warning: .*mis-matched ISA version 1.0 for 'zicsr' extension, the output version is 0.9 @@ -18,5 +16,5 @@ Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_zicsr2p0_xunknown2p0" + Tag_RISCV_arch: "rv32i2p1_m2p0_a2p0_zicsr2p0_xunknown2p0" #.. diff --git a/ld/testsuite/ld-riscv-elf/call-relax.d b/ld/testsuite/ld-riscv-elf/call-relax.d index c6022be..f8f0229 100644 --- a/ld/testsuite/ld-riscv-elf/call-relax.d +++ b/ld/testsuite/ld-riscv-elf/call-relax.d @@ -3,7 +3,7 @@ #source: call-relax-1.s #source: call-relax-2.s #source: call-relax-3.s -#as: -march=rv32ic -mno-arch-attr +#as: -march=rv32ic_zicsr -mno-arch-attr #ld: -m[riscv_choose_ilp32_emul] #objdump: -d #pass -- 2.7.4