From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 113982 invoked by alias); 12 Apr 2019 10:40:03 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 113879 invoked by uid 89); 12 Apr 2019 10:40:02 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.5 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LOTSOFHASH autolearn=ham version=3.3.1 spammy=Neon, helpers, 0xffffffff X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 12 Apr 2019 10:39:58 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 81B0A15AB; Fri, 12 Apr 2019 03:39:57 -0700 (PDT) Received: from [10.2.207.62] (e107157-lin.cambridge.arm.com [10.2.207.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D7C073F718; Fri, 12 Apr 2019 03:39:56 -0700 (PDT) Subject: Re: [PATCH, binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Mainline To: binutils@sourceware.org References: <1b0a8ea3-6226-2d81-7453-542e9c15f6bb@arm.com> Cc: nickc@redhat.com From: "Andre Vieira (lists)" Message-ID: <17713663-3d02-1e4d-2a14-ec2941044cb0@arm.com> Date: Fri, 12 Apr 2019 10:40:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 MIME-Version: 1.0 In-Reply-To: <1b0a8ea3-6226-2d81-7453-542e9c15f6bb@arm.com> Content-Type: multipart/mixed; boundary="------------541EFE71D9F7D6CDD5709666" X-IsSubscribed: yes X-SW-Source: 2019-04/txt/msg00147.txt.bz2 This is a multi-part message in MIME format. --------------541EFE71D9F7D6CDD5709666 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-length: 3702 Hi, The former patch had an issue with the LE branch value sign flip. It wasn't doing it for big-endian because of the wrong use of 'md_ chars_to_number'. Swapping it for 'get_thumb32_insn' fixes the issue. Also fixed a testism. Is this OK? Cheers, Andre *** bfd/ChnageLog *** 2019-04-12 Sudakshina Das * reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. *** gas/ChangeLog *** 2019-04-12 Sudakshina Das Andre Vieira * config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR for the LR operand and optional LR operand. (parse_operands): Add switch cases for OP_LR and OP_oLR for both type checking and value checking. (encode_thumb32_addr_mode): New entries for DLS, WLS and LE. (v8_1_loop_reloc): New helper function for handling labels for the low overhead loop instructions. (do_t_loloop): New function to encode DLS, WLS and LE. (insns): New entries for WLS, DLS and LE. (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_LOOP12. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-tloop.s: New. * testsuite/gas/arm/armv8_1-m-tloop.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.s: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.l: New. *** opcodes/ChangeLog *** 2019-04-12 Sudakshina Das * arm-dis.c (print_insn_thumb32): Updated to accept new %P and %Q patterns. On 04/04/2019 14:41, Andre Vieira (lists) wrote: > Hi > > This patch is part of a series of patches to add support for Armv8.1-M > Mainline instructions to binutils. > This patch adds support to the Scalar low overhead loop instructions: > LE > WLS > DLS > > We also add a new assembler resolvable relocation bfd_reloc_code_real > enum for the 12-bit branch offset used in these instructions. > Testing: Builds successfully and no regressions. Added new tests for the > valid and invalid instructions operands. Testsuite shows no regression > when run for arm-none-eabi targets. > > Thanks > Sudi > > > ChangeLog entries are as follows : > > *** bfd/ChnageLog *** > > 2019-04-04  Sudakshina Das  > >     * reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New. >     * bfd-in2.h: Regenerated. >     * libbfd.h: Regenerated. > > *** gas/ChangeLog *** > > 2019-04-04  Sudakshina Das  > >     * config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR >     for the LR operand and optional LR operand. >     (parse_operands): Add switch cases for OP_LR and OP_oLR for >     both type checking and value checking. >     (encode_thumb32_addr_mode): New entries for DLS, WLS and LE. >     (v8_1_loop_reloc): New helper function for handling labels >     for the low overhead loop instructions. >     (do_t_loloop): New function to encode DLS, WLS and LE. >     (insns): New entries for WLS, DLS and LE. >     (md_pcrel_from_section): New switch case >     for BFD_RELOC_ARM_THUMB_LOOP12. >     (md_appdy_fix): Likewise. >     (tc_gen_reloc): Likewise. >     * testsuite/gas/arm/armv8_1-m-tloop.s: New. >     * testsuite/gas/arm/armv8_1-m-tloop.d: New. >     * testsuite/gas/arm/armv8_1-m-tloop-bad.s: New. >     * testsuite/gas/arm/armv8_1-m-tloop-bad.d: New. >     * testsuite/gas/arm/armv8_1-m-tloop-bad.l: New. > > *** opcodes/ChangeLog *** > > 2019-04-04  Sudakshina Das  > >     * arm-dis.c (print_insn_thumb32): Updated to accept new %P >     and %Q patterns. --------------541EFE71D9F7D6CDD5709666 Content-Type: text/x-patch; name="12.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="12.patch" Content-length: 13162 diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 4a3fa75867c814f082ba3ab3079cf60c30ad2b62..540b9f71c181841ea782c63d87d0d5271c864966 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -3579,6 +3579,9 @@ field in the instruction. */ /* ARM 19-bit pc-relative branch for Branch Future Link instruction. */ BFD_RELOC_ARM_THUMB_BF19, +/* ARM 12-bit pc-relative branch for Low Overhead Loop instructions. */ + BFD_RELOC_ARM_THUMB_LOOP12, + /* Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches. The lowest bit must be zero and is not stored in the instruction. Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an diff --git a/bfd/libbfd.h b/bfd/libbfd.h index 32080db8c3f6141ae9aa9674c8776694db29905a..f64a8f3892ad3aff5c4570f0281875bce35846a6 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -1534,6 +1534,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_ARM_THUMB_BF17", "BFD_RELOC_ARM_THUMB_BF13", "BFD_RELOC_ARM_THUMB_BF19", + "BFD_RELOC_ARM_THUMB_LOOP12", "BFD_RELOC_THUMB_PCREL_BRANCH7", "BFD_RELOC_THUMB_PCREL_BRANCH9", "BFD_RELOC_THUMB_PCREL_BRANCH12", diff --git a/bfd/reloc.c b/bfd/reloc.c index c0e413cd19dbfaf5100143c8879d84cb63ba4a17..e6ba9e265027a6c34a8ad183dd5825a9af9c1f82 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -3039,6 +3039,11 @@ ENUM ENUMDOC ARM 19-bit pc-relative branch for Branch Future Link instruction. +ENUM + BFD_RELOC_ARM_THUMB_LOOP12 +ENUMDOC + ARM 12-bit pc-relative branch for Low Overhead Loop instructions. + ENUM BFD_RELOC_THUMB_PCREL_BRANCH7 ENUMX diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 5e59078890752b0580ae443c7b330e32baecccf6..828dfc1eddce9857a1c038b2ff927d71eccda6e9 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -6543,6 +6543,10 @@ enum operand_parse_code OP_RIWG, /* iWMMXt wCG register */ OP_RXA, /* XScale accumulator register */ + /* New operands for Armv8.1-M Mainline. */ + OP_LR, /* ARM LR register */ + OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */ + OP_REGLST, /* ARM register list */ OP_VRSLST, /* VFP single-precision register list */ OP_VRDLST, /* VFP double-precision register list */ @@ -6622,6 +6626,7 @@ enum operand_parse_code OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ OP_oRR, /* ARM register */ + OP_oLR, /* ARM LR register */ OP_oRRnpc, /* ARM register, not the PC */ OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */ OP_oRRw, /* ARM register, not r15, optional trailing ! */ @@ -6790,6 +6795,8 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) case OP_RRnpc: case OP_RRnpcsp: case OP_oRR: + case OP_LR: + case OP_oLR: case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; @@ -7307,6 +7314,12 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) inst.operands[i].imm = val; break; + case OP_LR: + case OP_oLR: + if (inst.operands[i].reg != REG_LR) + inst.error = _("operand must be LR register"); + break; + default: break; } @@ -10518,6 +10531,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) X(_cpsid, b670, f3af8600), \ X(_cpy, 4600, ea4f0000), \ X(_dec_sp,80dd, f1ad0d00), \ + X(_dls, 0000, f040e001), \ X(_eor, 4040, ea800000), \ X(_eors, 4040, ea900000), \ X(_inc_sp,00dd, f10d0d00), \ @@ -10530,6 +10544,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) X(_ldr_pc,4800, f85f0000), \ X(_ldr_pc2,4800, f85f0000), \ X(_ldr_sp,9800, f85d0000), \ + X(_le, 0000, f00fc001), \ X(_lsl, 0000, fa00f000), \ X(_lsls, 0000, fa10f000), \ X(_lsr, 0800, fa20f000), \ @@ -10571,6 +10586,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) X(_yield, bf10, f3af8001), \ X(_wfe, bf20, f3af8002), \ X(_wfi, bf30, f3af8003), \ + X(_wls, 0000, f040c001), \ X(_sev, bf40, f3af8004), \ X(_sevl, bf50, f3af8005), \ X(_udf, de00, f7f0a000) @@ -13434,6 +13450,64 @@ do_t_branch_future (void) } } +/* Helper function for do_t_loloop to handle relocations. */ +static void +v8_1_loop_reloc (int is_le) +{ + if (inst.relocs[0].exp.X_op == O_constant) + { + int value = inst.relocs[0].exp.X_add_number; + value = (is_le) ? -value : value; + + if (v8_1_branch_value_check (value, 12, FALSE) == FAIL) + as_bad (BAD_BRANCH_OFF); + + int imml, immh; + + immh = (value & 0x00000ffc) >> 2; + imml = (value & 0x00000002) >> 1; + + inst.instruction |= (imml << 11) | (immh << 1); + } + else + { + inst.relocs[0].type = BFD_RELOC_ARM_THUMB_LOOP12; + inst.relocs[0].pc_rel = 1; + } +} + +/* To handle the Scalar Low Overhead Loop instructions + in Armv8.1-M Mainline. */ +static void +do_t_loloop (void) +{ + unsigned long insn = inst.instruction; + + set_it_insn_type (OUTSIDE_IT_INSN); + inst.instruction = THUMB_OP32 (inst.instruction); + + switch (insn) + { + case T_MNEM_le: + /* le