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X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT018.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR08MB6079 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_DMARC_NONE,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 10/4/23 11:15, Victor Do Nascimento via Binutils wrote: > On 10/3/23 14:46, Richard Earnshaw (lists) wrote: >> On 03/10/2023 11:51, Victor Do Nascimento via Binutils wrote: >>> This patch  moves instances of system register definitions, represented >>> by the SYSREG macro, out of their original place in `aarch64-opc.c' >>> and into a dedicated .def file, `aarch64-sys-regs.def'. >>> >>> System register entries in this new file are ordered alphabetically by >>> name.  This choice is made to enable the use of fast search algorithms >>> such as binary search when validating register names. >>> >>> The SYSREG macro, defined as SYSREG (name, encoding, flags, features) >>> is kept as is and used in the def file, but all other SR_* macros >>> which previously served as indirections to SYSREG are removed. >>> >>> opcodes/ChangeLog: >>>     * aarch64-opc.c (SR_CORE): Macro definition and uses deleted. >>>     (SR_FEAT): Likewise. >>>     (SR_FEAT2): Likewise. >>>     (SR_V8_1_A): Likewise. >>>     (SR_V8_4_A): Likewise. >>>     (SR_V8A): Likewise. >>>     (SR_V8R): Likewise. >>>     (SR_V8_1A): Likewise. >>>     (SR_V8_2A): Likewise. >>>     (SR_V8_3A): Likewise. >>>     (SR_V8_4A): Likewise. >>>     (SR_V8_6A): Likewise. >>>     (SR_V8_7A): Likewise. >>>     (SR_V8_8A): Likewise. >>>     (SR_GIC): Likewise. >>>     (SR_AMU): Likewise. >>>     (SR_LOR): Likewise. >>>     (SR_PAN): Likewise. >>>     (SR_RAS): Likewise. >>>     (SR_RNG): Likewise. >>>     (SR_SME): Likewise. >>>     (SR_SSBS): Likewise. >>>     (SR_SVE): Likewise. >>>     (SR_ID_PFR2): Likewise. >>>     (SR_PROFILE): Likewise. >>>     (SR_MEMTAG): Likewise. >>>     (SR_SCXTNUM): Likewise. >>>     (SR_EXPAND_ELx): Likewise. >>>     (SR_EXPAND_EL12): Likewise. >>>     (FEAT): New >>>     * opcodes/aarch64-sys-regs.def: New. >> >> Missing new line at the end of the new .def file.  Otherwise OK. >> >> Are there any build- (or run-) time checks that we've caught all the >> possible aliases and flagged them? > > The testsuite already included tests for the trcextinselr trcextinselr0 > aliasing. > > As for checking for other possible aliases we may have had missed, this > was done with the help of a Python script I ran when I added the new > F_REG_ALIAS.  I'd see which CPENCs were mapped to more than one name and > whether any duplicated CPENCs needed special handling. > > It essentially boils down to checking whether any two SYSREG entries > sharing CPENCs differ in either their specified `flags' or `features'. > When both `flags' and `features' match, chances are we need to > disambiguate them with the F_REG_ALIAS flag. > > In the interest of having my findings recorded publicly, I am attaching > them below. > > I had not planned on committing anything to be distributed with the > Binutils source and subsequently run at build- or run-time to check > whether anything was missed.  I believe that my check and due prudence > when implementing novel system registers in the future should be enough. > > CPENC duplication findings > ========================== > > -------------------------------------------------------------------- > The Debug Data Transfer Register, CPENC(2,3,0,5,0), is aliased > differently depending whether it's being read from (via MRS insn) or > written to (via MSR insn), so they are flagged `F_REG_READ' and > `F_REG_WRITE', respectively.  These flags are enough to disambiguate > the name to which the encoding should be mapped to on disassembly. > -------------------------------------------------------------------- > DBGDTRRX_EL0: Debug Data Transfer Register, Receive > DBGDTRTX_EL0: Debug Data Transfer Register, Transmit > > ------------------------------------------------------------------- > The CPENC(3,4,2,0,0) is interpreted differently depending on the > target architecture, thus there's no ambiguity when disassembling a > binary assembled for a given arch: > ------------------------------------------------------------------- > VSCTLR_EL2: V8R > TTBR0_EL2: V8A > > ------------------------------------------------------------------- > The degeneracy in nomenclature for CPENC(3,0,4,0,0) and > CPENC(3,4,4,0,0) was addressed by "[PATCH, AArch64] Deprecate the > alias system registers spsr_svc and spsr_hyp", whereby SPSR_SVC and > SPSR_HYP are deprecated and flagged as such via the `F_DEPRECATED' > flag.  As such, these aliases are never chosen at disassemble time. > ------------------------------------------------------------------- > SPSR_SVC maps onto SPSR_EL1, deprecated > SPSR_EL2: maps onto SPSR_HYP, deprecated Errata: "SPSR_EL2: maps onto SPSR_HYP, deprecated" above should read: SPSR_HYP: maps onto SPSR_EL2, deprecated Apologies, V. > > Regards, > Victor > >> Reviewed-by: Richard.Earnshaw@arm.com >> >> R. >> >>> --- >>>   opcodes/aarch64-opc.c        | 1088 +--------------------------------- >>>   opcodes/aarch64-sys-regs.def | 1060 +++++++++++++++++++++++++++++++++ >>>   2 files changed, 1080 insertions(+), 1068 deletions(-) >>>   create mode 100644 opcodes/aarch64-sys-regs.def >>> >>> diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c >>> index c901d3d587b..295638d6d8c 100644 >>> --- a/opcodes/aarch64-opc.c >>> +++ b/opcodes/aarch64-opc.c >>> @@ -4675,64 +4675,6 @@ aarch64_print_operand (char *buf, size_t size, >>> bfd_vma pc, >>>   #define C14 14 >>>   #define C15 15 >>> -#define SR_CORE(n,e,f) {n,e,f,AARCH64_NO_FEATURES} >>> - >>> -#define SR_FEAT(n,e,f,feat) \ >>> -  { (n), (e), (f) | F_ARCHEXT, AARCH64_FEATURE (feat) } >>> - >>> -#define SR_FEAT2(n,e,f,fe1,fe2) \ >>> -  { (n), (e), (f) | F_ARCHEXT, \ >>> -    AARCH64_FEATURES (2, fe1, fe2) } >>> - >>> -#define SR_V8_1_A(n,e,f) SR_FEAT2(n,e,f,V8A,V8_1A) >>> -#define SR_V8_4_A(n,e,f) SR_FEAT2(n,e,f,V8A,V8_4A) >>> - >>> -#define SR_V8A(n,e,f)      SR_FEAT (n,e,f,V8A) >>> -#define SR_V8R(n,e,f)      SR_FEAT (n,e,f,V8R) >>> -#define SR_V8_1A(n,e,f)      SR_FEAT (n,e,f,V8_1A) >>> -#define SR_V8_2A(n,e,f)      SR_FEAT (n,e,f,V8_2A) >>> -#define SR_V8_3A(n,e,f)      SR_FEAT (n,e,f,V8_3A) >>> -#define SR_V8_4A(n,e,f)      SR_FEAT (n,e,f,V8_4A) >>> -#define SR_V8_6A(n,e,f)      SR_FEAT (n,e,f,V8_6A) >>> -#define SR_V8_7A(n,e,f)      SR_FEAT (n,e,f,V8_7A) >>> -#define SR_V8_8A(n,e,f)      SR_FEAT (n,e,f,V8_8A) >>> -/* Has no separate libopcodes feature flag, but separated out for >>> clarity.  */ >>> -#define SR_GIC(n,e,f)      SR_CORE (n,e,f) >>> -/* Has no separate libopcodes feature flag, but separated out for >>> clarity.  */ >>> -#define SR_AMU(n,e,f)      SR_FEAT (n,e,f,V8_4A) >>> -#define SR_LOR(n,e,f)      SR_FEAT (n,e,f,LOR) >>> -#define SR_PAN(n,e,f)      SR_FEAT (n,e,f,PAN) >>> -#define SR_RAS(n,e,f)      SR_FEAT (n,e,f,RAS) >>> -#define SR_RNG(n,e,f)      SR_FEAT (n,e,f,RNG) >>> -#define SR_SME(n,e,f)      SR_FEAT (n,e,f,SME) >>> -#define SR_SSBS(n,e,f)      SR_FEAT (n,e,f,SSBS) >>> -#define SR_SVE(n,e,f)      SR_FEAT (n,e,f,SVE) >>> -#define SR_ID_PFR2(n,e,f) SR_FEAT (n,e,f,ID_PFR2) >>> -#define SR_PROFILE(n,e,f) SR_FEAT (n,e,f,PROFILE) >>> -#define SR_MEMTAG(n,e,f)  SR_FEAT (n,e,f,MEMTAG) >>> -#define SR_SCXTNUM(n,e,f) SR_FEAT (n,e,f,SCXTNUM) >>> - >>> -#define SR_EXPAND_ELx(f,x) \ >>> -  f (x, 1),  \ >>> -  f (x, 2),  \ >>> -  f (x, 3),  \ >>> -  f (x, 4),  \ >>> -  f (x, 5),  \ >>> -  f (x, 6),  \ >>> -  f (x, 7),  \ >>> -  f (x, 8),  \ >>> -  f (x, 9),  \ >>> -  f (x, 10), \ >>> -  f (x, 11), \ >>> -  f (x, 12), \ >>> -  f (x, 13), \ >>> -  f (x, 14), \ >>> -  f (x, 15), >>> - >>> -#define SR_EXPAND_EL12(f) \ >>> -  SR_EXPAND_ELx (f,1) \ >>> -  SR_EXPAND_ELx (f,2) >>> - >>>   /* TODO there is one more issues need to be resolved >>>      1. handle cpu-implementation-defined system registers. >>> @@ -4740,1001 +4682,11 @@ aarch64_print_operand (char *buf, size_t >>> size, bfd_vma pc, >>>      respectively.  If neither of these are set then the register is >>> read-write.  */ >>>   const aarch64_sys_reg aarch64_sys_regs [] = >>>   { >>> -  SR_CORE ("spsr_el1",        CPEN_ (0,C0,0),        0), /* = >>> spsr_svc.  */ >>> -  SR_V8_1A ("spsr_el12",        CPEN_ (5,C0,0),        0), >>> -  SR_CORE ("elr_el1",        CPEN_ (0,C0,1),        0), >>> -  SR_V8_1A ("elr_el12",        CPEN_ (5,C0,1),        0), >>> -  SR_CORE ("sp_el0",        CPEN_ (0,C1,0),        0), >>> -  SR_CORE ("spsel",        CPEN_ (0,C2,0),        0), >>> -  SR_CORE ("daif",        CPEN_ (3,C2,1),        0), >>> -  SR_CORE ("currentel",        CPEN_ (0,C2,2),        F_REG_READ), >>> -  SR_PAN  ("pan",        CPEN_ (0,C2,3),        0), >>> -  SR_V8_2A ("uao",        CPEN_ (0,C2,4),        0), >>> -  SR_CORE ("nzcv",        CPEN_ (3,C2,0),        0), >>> -  SR_SSBS ("ssbs",        CPEN_ (3,C2,6),        0), >>> -  SR_CORE ("fpcr",        CPEN_ (3,C4,0),        0), >>> -  SR_CORE ("fpsr",        CPEN_ (3,C4,1),        0), >>> -  SR_CORE ("dspsr_el0",        CPEN_ (3,C5,0),        0), >>> -  SR_CORE ("dlr_el0",        CPEN_ (3,C5,1),        0), >>> -  SR_CORE ("spsr_el2",        CPEN_ (4,C0,0),        0), /* = >>> spsr_hyp.  */ >>> -  SR_CORE ("elr_el2",        CPEN_ (4,C0,1),        0), >>> -  SR_CORE ("sp_el1",        CPEN_ (4,C1,0),        0), >>> -  SR_CORE ("spsr_irq",        CPEN_ (4,C3,0),        0), >>> -  SR_CORE ("spsr_abt",        CPEN_ (4,C3,1),        0), >>> -  SR_CORE ("spsr_und",        CPEN_ (4,C3,2),        0), >>> -  SR_CORE ("spsr_fiq",        CPEN_ (4,C3,3),        0), >>> -  SR_CORE ("spsr_el3",        CPEN_ (6,C0,0),        0), >>> -  SR_CORE ("elr_el3",        CPEN_ (6,C0,1),        0), >>> -  SR_CORE ("sp_el2",        CPEN_ (6,C1,0),        0), >>> -  SR_CORE ("spsr_svc",        CPEN_ (0,C0,0),        F_DEPRECATED), >>> /* = spsr_el1.  */ >>> -  SR_CORE ("spsr_hyp",        CPEN_ (4,C0,0),        F_DEPRECATED), >>> /* = spsr_el2.  */ >>> -  SR_CORE ("midr_el1",        CPENC (3,0,C0,C0,0),    F_REG_READ), >>> -  SR_CORE ("ctr_el0",        CPENC (3,3,C0,C0,1),    F_REG_READ), >>> -  SR_CORE ("mpidr_el1",        CPENC (3,0,C0,C0,5),    F_REG_READ), >>> -  SR_CORE ("revidr_el1",    CPENC (3,0,C0,C0,6),    F_REG_READ), >>> -  SR_CORE ("aidr_el1",        CPENC (3,1,C0,C0,7),    F_REG_READ), >>> -  SR_CORE ("dczid_el0",        CPENC (3,3,C0,C0,7),    F_REG_READ), >>> -  SR_CORE ("id_dfr0_el1",    CPENC (3,0,C0,C1,2),    F_REG_READ), >>> -  SR_CORE ("id_dfr1_el1",    CPENC (3,0,C0,C3,5),    F_REG_READ), >>> -  SR_CORE ("id_pfr0_el1",    CPENC (3,0,C0,C1,0),    F_REG_READ), >>> -  SR_CORE ("id_pfr1_el1",    CPENC (3,0,C0,C1,1),    F_REG_READ), >>> -  SR_ID_PFR2 ("id_pfr2_el1",    CPENC (3,0,C0,C3,4),    F_REG_READ), >>> -  SR_CORE ("id_afr0_el1",    CPENC (3,0,C0,C1,3),    F_REG_READ), >>> -  SR_CORE ("id_mmfr0_el1",    CPENC (3,0,C0,C1,4),    F_REG_READ), >>> -  SR_CORE ("id_mmfr1_el1",    CPENC (3,0,C0,C1,5),    F_REG_READ), >>> -  SR_CORE ("id_mmfr2_el1",    CPENC (3,0,C0,C1,6),    F_REG_READ), >>> -  SR_CORE ("id_mmfr3_el1",    CPENC (3,0,C0,C1,7),    F_REG_READ), >>> -  SR_CORE ("id_mmfr4_el1",    CPENC (3,0,C0,C2,6),    F_REG_READ), >>> -  SR_CORE ("id_mmfr5_el1",    CPENC (3,0,C0,C3,6),    F_REG_READ), >>> -  SR_CORE ("id_isar0_el1",    CPENC (3,0,C0,C2,0),    F_REG_READ), >>> -  SR_CORE ("id_isar1_el1",    CPENC (3,0,C0,C2,1),    F_REG_READ), >>> -  SR_CORE ("id_isar2_el1",    CPENC (3,0,C0,C2,2),    F_REG_READ), >>> -  SR_CORE ("id_isar3_el1",    CPENC (3,0,C0,C2,3),    F_REG_READ), >>> -  SR_CORE ("id_isar4_el1",    CPENC (3,0,C0,C2,4),    F_REG_READ), >>> -  SR_CORE ("id_isar5_el1",    CPENC (3,0,C0,C2,5),    F_REG_READ), >>> -  SR_CORE ("id_isar6_el1",    CPENC (3,0,C0,C2,7),    F_REG_READ), >>> -  SR_CORE ("mvfr0_el1",        CPENC (3,0,C0,C3,0),    F_REG_READ), >>> -  SR_CORE ("mvfr1_el1",        CPENC (3,0,C0,C3,1),    F_REG_READ), >>> -  SR_CORE ("mvfr2_el1",        CPENC (3,0,C0,C3,2),    F_REG_READ), >>> -  SR_CORE ("ccsidr_el1",    CPENC (3,1,C0,C0,0),    F_REG_READ), >>> -  SR_V8_3A ("ccsidr2_el1",       CPENC (3,1,C0,C0,2),    F_REG_READ), >>> -  SR_CORE ("id_aa64pfr0_el1",    CPENC (3,0,C0,C4,0),    F_REG_READ), >>> -  SR_CORE ("id_aa64pfr1_el1",    CPENC (3,0,C0,C4,1),    F_REG_READ), >>> -  SR_CORE ("id_aa64dfr0_el1",    CPENC (3,0,C0,C5,0),    F_REG_READ), >>> -  SR_CORE ("id_aa64dfr1_el1",    CPENC (3,0,C0,C5,1),    F_REG_READ), >>> -  SR_CORE ("id_aa64isar0_el1",    CPENC (3,0,C0,C6,0),    F_REG_READ), >>> -  SR_CORE ("id_aa64isar1_el1",    CPENC (3,0,C0,C6,1),    F_REG_READ), >>> -  SR_CORE ("id_aa64isar2_el1",    CPENC (3,0,C0,C6,2),    F_REG_READ), >>> -  SR_CORE ("id_aa64mmfr0_el1",    CPENC (3,0,C0,C7,0),    F_REG_READ), >>> -  SR_CORE ("id_aa64mmfr1_el1",    CPENC (3,0,C0,C7,1),    F_REG_READ), >>> -  SR_CORE ("id_aa64mmfr2_el1",    CPENC (3,0,C0,C7,2),    F_REG_READ), >>> -  SR_CORE ("id_aa64afr0_el1",    CPENC (3,0,C0,C5,4),    F_REG_READ), >>> -  SR_CORE ("id_aa64afr1_el1",    CPENC (3,0,C0,C5,5),    F_REG_READ), >>> -  SR_SVE  ("id_aa64zfr0_el1",    CPENC (3,0,C0,C4,4),    F_REG_READ), >>> -  SR_CORE ("clidr_el1",        CPENC (3,1,C0,C0,1),    F_REG_READ), >>> -  SR_CORE ("csselr_el1",    CPENC (3,2,C0,C0,0),    0), >>> -  SR_CORE ("vpidr_el2",        CPENC (3,4,C0,C0,0),    0), >>> -  SR_CORE ("vmpidr_el2",    CPENC (3,4,C0,C0,5),    0), >>> -  SR_CORE ("sctlr_el1",        CPENC (3,0,C1,C0,0),    0), >>> -  SR_CORE ("sctlr_el2",        CPENC (3,4,C1,C0,0),    0), >>> -  SR_CORE ("sctlr_el3",        CPENC (3,6,C1,C0,0),    0), >>> -  SR_V8_1A ("sctlr_el12",    CPENC (3,5,C1,C0,0),    0), >>> -  SR_CORE ("actlr_el1",        CPENC (3,0,C1,C0,1),    0), >>> -  SR_CORE ("actlr_el2",        CPENC (3,4,C1,C0,1),    0), >>> -  SR_CORE ("actlr_el3",        CPENC (3,6,C1,C0,1),    0), >>> -  SR_CORE ("cpacr_el1",        CPENC (3,0,C1,C0,2),    0), >>> -  SR_V8_1A ("cpacr_el12",    CPENC (3,5,C1,C0,2),    0), >>> -  SR_CORE ("cptr_el2",        CPENC (3,4,C1,C1,2),    0), >>> -  SR_CORE ("cptr_el3",        CPENC (3,6,C1,C1,2),    0), >>> -  SR_CORE ("scr_el3",        CPENC (3,6,C1,C1,0),    0), >>> -  SR_CORE ("hcr_el2",        CPENC (3,4,C1,C1,0),    0), >>> -  SR_CORE ("mdcr_el2",        CPENC (3,4,C1,C1,1),    0), >>> -  SR_CORE ("mdcr_el3",        CPENC (3,6,C1,C3,1),    0), >>> -  SR_CORE ("hstr_el2",        CPENC (3,4,C1,C1,3),    0), >>> -  SR_CORE ("hacr_el2",        CPENC (3,4,C1,C1,7),    0), >>> -  SR_SVE  ("zcr_el1",        CPENC (3,0,C1,C2,0),    0), >>> -  SR_SVE  ("zcr_el12",        CPENC (3,5,C1,C2,0),    0), >>> -  SR_SVE  ("zcr_el2",        CPENC (3,4,C1,C2,0),    0), >>> -  SR_SVE  ("zcr_el3",        CPENC (3,6,C1,C2,0),    0), >>> -  SR_CORE ("ttbr0_el1",        CPENC (3,0,C2,C0,0),    0), >>> -  SR_CORE ("ttbr1_el1",        CPENC (3,0,C2,C0,1),    0), >>> -  SR_V8A ("ttbr0_el2",        CPENC (3,4,C2,C0,0),    0), >>> -  SR_V8_1_A ("ttbr1_el2",    CPENC (3,4,C2,C0,1),    0), >>> -  SR_CORE ("ttbr0_el3",        CPENC (3,6,C2,C0,0),    0), >>> -  SR_V8_1A ("ttbr0_el12",    CPENC (3,5,C2,C0,0),    0), >>> -  SR_V8_1A ("ttbr1_el12",    CPENC (3,5,C2,C0,1),    0), >>> -  SR_V8A ("vttbr_el2",        CPENC (3,4,C2,C1,0),    0), >>> -  SR_CORE ("tcr_el1",        CPENC (3,0,C2,C0,2),    0), >>> -  SR_CORE ("tcr_el2",        CPENC (3,4,C2,C0,2),    0), >>> -  SR_CORE ("tcr_el3",        CPENC (3,6,C2,C0,2),    0), >>> -  SR_V8_1A ("tcr_el12",        CPENC (3,5,C2,C0,2),    0), >>> -  SR_CORE ("vtcr_el2",        CPENC (3,4,C2,C1,2),    0), >>> -  SR_V8_3A ("apiakeylo_el1",    CPENC (3,0,C2,C1,0),    0), >>> -  SR_V8_3A ("apiakeyhi_el1",    CPENC (3,0,C2,C1,1),    0), >>> -  SR_V8_3A ("apibkeylo_el1",    CPENC (3,0,C2,C1,2),    0), >>> -  SR_V8_3A ("apibkeyhi_el1",    CPENC (3,0,C2,C1,3),    0), >>> -  SR_V8_3A ("apdakeylo_el1",    CPENC (3,0,C2,C2,0),    0), >>> -  SR_V8_3A ("apdakeyhi_el1",    CPENC (3,0,C2,C2,1),    0), >>> -  SR_V8_3A ("apdbkeylo_el1",    CPENC (3,0,C2,C2,2),    0), >>> -  SR_V8_3A ("apdbkeyhi_el1",    CPENC (3,0,C2,C2,3),    0), >>> -  SR_V8_3A ("apgakeylo_el1",    CPENC (3,0,C2,C3,0),    0), >>> -  SR_V8_3A ("apgakeyhi_el1",    CPENC (3,0,C2,C3,1),    0), >>> -  SR_CORE ("afsr0_el1",        CPENC (3,0,C5,C1,0),    0), >>> -  SR_CORE ("afsr1_el1",        CPENC (3,0,C5,C1,1),    0), >>> -  SR_CORE ("afsr0_el2",        CPENC (3,4,C5,C1,0),    0), >>> -  SR_CORE ("afsr1_el2",        CPENC (3,4,C5,C1,1),    0), >>> -  SR_CORE ("afsr0_el3",        CPENC (3,6,C5,C1,0),    0), >>> -  SR_V8_1A ("afsr0_el12",    CPENC (3,5,C5,C1,0),    0), >>> -  SR_CORE ("afsr1_el3",        CPENC (3,6,C5,C1,1),    0), >>> -  SR_V8_1A ("afsr1_el12",    CPENC (3,5,C5,C1,1),    0), >>> -  SR_CORE ("esr_el1",        CPENC (3,0,C5,C2,0),    0), >>> -  SR_CORE ("esr_el2",        CPENC (3,4,C5,C2,0),    0), >>> -  SR_CORE ("esr_el3",        CPENC (3,6,C5,C2,0),    0), >>> -  SR_V8_1A ("esr_el12",        CPENC (3,5,C5,C2,0),    0), >>> -  SR_RAS  ("vsesr_el2",        CPENC (3,4,C5,C2,3),    0), >>> -  SR_CORE ("fpexc32_el2",    CPENC (3,4,C5,C3,0),    0), >>> -  SR_RAS  ("erridr_el1",    CPENC (3,0,C5,C3,0),    F_REG_READ), >>> -  SR_RAS  ("errselr_el1",    CPENC (3,0,C5,C3,1),    0), >>> -  SR_RAS  ("erxfr_el1",        CPENC (3,0,C5,C4,0),    F_REG_READ), >>> -  SR_RAS  ("erxctlr_el1",    CPENC (3,0,C5,C4,1),    0), >>> -  SR_RAS  ("erxstatus_el1",    CPENC (3,0,C5,C4,2),    0), >>> -  SR_RAS  ("erxaddr_el1",    CPENC (3,0,C5,C4,3),    0), >>> -  SR_RAS  ("erxmisc0_el1",    CPENC (3,0,C5,C5,0),    0), >>> -  SR_RAS  ("erxmisc1_el1",    CPENC (3,0,C5,C5,1),    0), >>> -  SR_RAS  ("erxmisc2_el1",    CPENC (3,0,C5,C5,2),    0), >>> -  SR_RAS  ("erxmisc3_el1",    CPENC (3,0,C5,C5,3),    0), >>> -  SR_RAS  ("erxpfgcdn_el1",    CPENC (3,0,C5,C4,6),    0), >>> -  SR_RAS  ("erxpfgctl_el1",    CPENC (3,0,C5,C4,5),    0), >>> -  SR_RAS  ("erxpfgf_el1",    CPENC (3,0,C5,C4,4),    F_REG_READ), >>> -  SR_CORE ("far_el1",        CPENC (3,0,C6,C0,0),    0), >>> -  SR_CORE ("far_el2",        CPENC (3,4,C6,C0,0),    0), >>> -  SR_CORE ("far_el3",        CPENC (3,6,C6,C0,0),    0), >>> -  SR_V8_1A ("far_el12",        CPENC (3,5,C6,C0,0),    0), >>> -  SR_CORE ("hpfar_el2",        CPENC (3,4,C6,C0,4),    0), >>> -  SR_CORE ("par_el1",        CPENC (3,0,C7,C4,0),    0), >>> -  SR_CORE ("mair_el1",        CPENC (3,0,C10,C2,0),    0), >>> -  SR_CORE ("mair_el2",        CPENC (3,4,C10,C2,0),    0), >>> -  SR_CORE ("mair_el3",        CPENC (3,6,C10,C2,0),    0), >>> -  SR_V8_1A ("mair_el12",        CPENC (3,5,C10,C2,0),    0), >>> -  SR_CORE ("amair_el1",        CPENC (3,0,C10,C3,0),    0), >>> -  SR_CORE ("amair_el2",        CPENC (3,4,C10,C3,0),    0), >>> -  SR_CORE ("amair_el3",        CPENC (3,6,C10,C3,0),    0), >>> -  SR_V8_1A ("amair_el12",    CPENC (3,5,C10,C3,0),    0), >>> -  SR_CORE ("vbar_el1",        CPENC (3,0,C12,C0,0),    0), >>> -  SR_CORE ("vbar_el2",        CPENC (3,4,C12,C0,0),    0), >>> -  SR_CORE ("vbar_el3",        CPENC (3,6,C12,C0,0),    0), >>> -  SR_V8_1A ("vbar_el12",        CPENC (3,5,C12,C0,0),    0), >>> -  SR_CORE ("rvbar_el1",        CPENC (3,0,C12,C0,1),    F_REG_READ), >>> -  SR_CORE ("rvbar_el2",        CPENC (3,4,C12,C0,1),    F_REG_READ), >>> -  SR_CORE ("rvbar_el3",        CPENC (3,6,C12,C0,1),    F_REG_READ), >>> -  SR_CORE ("rmr_el1",        CPENC (3,0,C12,C0,2),    0), >>> -  SR_CORE ("rmr_el2",        CPENC (3,4,C12,C0,2),    0), >>> -  SR_CORE ("rmr_el3",        CPENC (3,6,C12,C0,2),    0), >>> -  SR_CORE ("isr_el1",        CPENC (3,0,C12,C1,0),    F_REG_READ), >>> -  SR_RAS  ("disr_el1",        CPENC (3,0,C12,C1,1),    0), >>> -  SR_RAS  ("vdisr_el2",        CPENC (3,4,C12,C1,1),    0), >>> -  SR_CORE ("contextidr_el1",    CPENC (3,0,C13,C0,1),    0), >>> -  SR_V8_1A ("contextidr_el2",    CPENC (3,4,C13,C0,1),    0), >>> -  SR_V8_1A ("contextidr_el12",    CPENC (3,5,C13,C0,1),    0), >>> -  SR_RNG  ("rndr",        CPENC (3,3,C2,C4,0),    F_REG_READ), >>> -  SR_RNG  ("rndrrs",        CPENC (3,3,C2,C4,1),    F_REG_READ), >>> -  SR_MEMTAG ("tco",        CPENC (3,3,C4,C2,7),    0), >>> -  SR_MEMTAG ("tfsre0_el1",    CPENC (3,0,C5,C6,1),    0), >>> -  SR_MEMTAG ("tfsr_el1",    CPENC (3,0,C5,C6,0),    0), >>> -  SR_MEMTAG ("tfsr_el2",    CPENC (3,4,C5,C6,0),    0), >>> -  SR_MEMTAG ("tfsr_el3",    CPENC (3,6,C5,C6,0),    0), >>> -  SR_MEMTAG ("tfsr_el12",    CPENC (3,5,C5,C6,0),    0), >>> -  SR_MEMTAG ("rgsr_el1",    CPENC (3,0,C1,C0,5),    0), >>> -  SR_MEMTAG ("gcr_el1",        CPENC (3,0,C1,C0,6),    0), >>> -  SR_MEMTAG ("gmid_el1",    CPENC (3,1,C0,C0,4),    F_REG_READ), >>> -  SR_CORE ("tpidr_el0",        CPENC (3,3,C13,C0,2),    0), >>> -  SR_CORE ("tpidrro_el0",       CPENC (3,3,C13,C0,3),    0), >>> -  SR_CORE ("tpidr_el1",        CPENC (3,0,C13,C0,4),    0), >>> -  SR_CORE ("tpidr_el2",        CPENC (3,4,C13,C0,2),    0), >>> -  SR_CORE ("tpidr_el3",        CPENC (3,6,C13,C0,2),    0), >>> -  SR_SCXTNUM ("scxtnum_el0",    CPENC (3,3,C13,C0,7),    0), >>> -  SR_SCXTNUM ("scxtnum_el1",    CPENC (3,0,C13,C0,7),    0), >>> -  SR_SCXTNUM ("scxtnum_el2",    CPENC (3,4,C13,C0,7),    0), >>> -  SR_SCXTNUM ("scxtnum_el12",   CPENC (3,5,C13,C0,7),    0), >>> -  SR_SCXTNUM ("scxtnum_el3",    CPENC (3,6,C13,C0,7),    0), >>> -  SR_CORE ("teecr32_el1",       CPENC (2,2,C0, C0,0),    0), /* See >>> section 3.9.7.1.  */ >>> -  SR_CORE ("cntfrq_el0",    CPENC (3,3,C14,C0,0),    0), >>> -  SR_CORE ("cntpct_el0",    CPENC (3,3,C14,C0,1),    F_REG_READ), >>> -  SR_CORE ("cntvct_el0",    CPENC (3,3,C14,C0,2),    F_REG_READ), >>> -  SR_CORE ("cntvoff_el2",       CPENC (3,4,C14,C0,3),    0), >>> -  SR_CORE ("cntkctl_el1",       CPENC (3,0,C14,C1,0),    0), >>> -  SR_V8_1A ("cntkctl_el12",    CPENC (3,5,C14,C1,0),    0), >>> -  SR_CORE ("cnthctl_el2",    CPENC (3,4,C14,C1,0),    0), >>> -  SR_CORE ("cntp_tval_el0",    CPENC (3,3,C14,C2,0),    0), >>> -  SR_V8_1A ("cntp_tval_el02",    CPENC (3,5,C14,C2,0),    0), >>> -  SR_CORE ("cntp_ctl_el0",      CPENC (3,3,C14,C2,1),    0), >>> -  SR_V8_1A ("cntp_ctl_el02",    CPENC (3,5,C14,C2,1),    0), >>> -  SR_CORE ("cntp_cval_el0",     CPENC (3,3,C14,C2,2),    0), >>> -  SR_V8_1A ("cntp_cval_el02",    CPENC (3,5,C14,C2,2),    0), >>> -  SR_CORE ("cntv_tval_el0",     CPENC (3,3,C14,C3,0),    0), >>> -  SR_V8_1A ("cntv_tval_el02",    CPENC (3,5,C14,C3,0),    0), >>> -  SR_CORE ("cntv_ctl_el0",      CPENC (3,3,C14,C3,1),    0), >>> -  SR_V8_1A ("cntv_ctl_el02",    CPENC (3,5,C14,C3,1),    0), >>> -  SR_CORE ("cntv_cval_el0",     CPENC (3,3,C14,C3,2),    0), >>> -  SR_V8_1A ("cntv_cval_el02",    CPENC (3,5,C14,C3,2),    0), >>> -  SR_CORE ("cnthp_tval_el2",    CPENC (3,4,C14,C2,0),    0), >>> -  SR_CORE ("cnthp_ctl_el2",    CPENC (3,4,C14,C2,1),    0), >>> -  SR_CORE ("cnthp_cval_el2",    CPENC (3,4,C14,C2,2),    0), >>> -  SR_CORE ("cntps_tval_el1",    CPENC (3,7,C14,C2,0),    0), >>> -  SR_CORE ("cntps_ctl_el1",    CPENC (3,7,C14,C2,1),    0), >>> -  SR_CORE ("cntps_cval_el1",    CPENC (3,7,C14,C2,2),    0), >>> -  SR_V8_1A ("cnthv_tval_el2",    CPENC (3,4,C14,C3,0),    0), >>> -  SR_V8_1A ("cnthv_ctl_el2",    CPENC (3,4,C14,C3,1),    0), >>> -  SR_V8_1A ("cnthv_cval_el2",    CPENC (3,4,C14,C3,2),    0), >>> -  SR_CORE ("dacr32_el2",    CPENC (3,4,C3,C0,0),    0), >>> -  SR_CORE ("ifsr32_el2",    CPENC (3,4,C5,C0,1),    0), >>> -  SR_CORE ("teehbr32_el1",    CPENC (2,2,C1,C0,0),    0), >>> -  SR_CORE ("sder32_el3",    CPENC (3,6,C1,C1,1),    0), >>> -  SR_CORE ("mdscr_el1",        CPENC (2,0,C0,C2,2),    0), >>> -  SR_CORE ("mdccsr_el0",    CPENC (2,3,C0,C1,0),    F_REG_READ), >>> -  SR_CORE ("mdccint_el1",       CPENC (2,0,C0,C2,0),    0), >>> -  SR_CORE ("dbgdtr_el0",    CPENC (2,3,C0,C4,0),    0), >>> -  SR_CORE ("dbgdtrrx_el0",    CPENC (2,3,C0,C5,0),    F_REG_READ), >>> -  SR_CORE ("dbgdtrtx_el0",    CPENC (2,3,C0,C5,0),    F_REG_WRITE), >>> -  SR_CORE ("osdtrrx_el1",    CPENC (2,0,C0,C0,2),    0), >>> -  SR_CORE ("osdtrtx_el1",    CPENC (2,0,C0,C3,2),    0), >>> -  SR_CORE ("oseccr_el1",    CPENC (2,0,C0,C6,2),    0), >>> -  SR_CORE ("dbgvcr32_el2",      CPENC (2,4,C0,C7,0),    0), >>> -  SR_CORE ("dbgbvr0_el1",       CPENC (2,0,C0,C0,4),    0), >>> -  SR_CORE ("dbgbvr1_el1",       CPENC (2,0,C0,C1,4),    0), >>> -  SR_CORE ("dbgbvr2_el1",       CPENC (2,0,C0,C2,4),    0), >>> -  SR_CORE ("dbgbvr3_el1",       CPENC (2,0,C0,C3,4),    0), >>> -  SR_CORE ("dbgbvr4_el1",       CPENC (2,0,C0,C4,4),    0), >>> -  SR_CORE ("dbgbvr5_el1",       CPENC (2,0,C0,C5,4),    0), >>> -  SR_CORE ("dbgbvr6_el1",       CPENC (2,0,C0,C6,4),    0), >>> -  SR_CORE ("dbgbvr7_el1",       CPENC (2,0,C0,C7,4),    0), >>> -  SR_CORE ("dbgbvr8_el1",       CPENC (2,0,C0,C8,4),    0), >>> -  SR_CORE ("dbgbvr9_el1",       CPENC (2,0,C0,C9,4),    0), >>> -  SR_CORE ("dbgbvr10_el1",      CPENC (2,0,C0,C10,4),    0), >>> -  SR_CORE ("dbgbvr11_el1",      CPENC (2,0,C0,C11,4),    0), >>> -  SR_CORE ("dbgbvr12_el1",      CPENC (2,0,C0,C12,4),    0), >>> -  SR_CORE ("dbgbvr13_el1",      CPENC (2,0,C0,C13,4),    0), >>> -  SR_CORE ("dbgbvr14_el1",      CPENC (2,0,C0,C14,4),    0), >>> -  SR_CORE ("dbgbvr15_el1",      CPENC (2,0,C0,C15,4),    0), >>> -  SR_CORE ("dbgbcr0_el1",       CPENC (2,0,C0,C0,5),    0), >>> -  SR_CORE ("dbgbcr1_el1",       CPENC (2,0,C0,C1,5),    0), >>> -  SR_CORE ("dbgbcr2_el1",       CPENC (2,0,C0,C2,5),    0), >>> -  SR_CORE ("dbgbcr3_el1",       CPENC (2,0,C0,C3,5),    0), >>> -  SR_CORE ("dbgbcr4_el1",       CPENC (2,0,C0,C4,5),    0), >>> -  SR_CORE ("dbgbcr5_el1",       CPENC (2,0,C0,C5,5),    0), >>> -  SR_CORE ("dbgbcr6_el1",       CPENC (2,0,C0,C6,5),    0), >>> -  SR_CORE ("dbgbcr7_el1",       CPENC (2,0,C0,C7,5),    0), >>> -  SR_CORE ("dbgbcr8_el1",       CPENC (2,0,C0,C8,5),    0), >>> -  SR_CORE ("dbgbcr9_el1",       CPENC (2,0,C0,C9,5),    0), >>> -  SR_CORE ("dbgbcr10_el1",      CPENC (2,0,C0,C10,5),    0), >>> -  SR_CORE ("dbgbcr11_el1",      CPENC (2,0,C0,C11,5),    0), >>> -  SR_CORE ("dbgbcr12_el1",      CPENC (2,0,C0,C12,5),    0), >>> -  SR_CORE ("dbgbcr13_el1",      CPENC (2,0,C0,C13,5),    0), >>> -  SR_CORE ("dbgbcr14_el1",      CPENC (2,0,C0,C14,5),    0), >>> -  SR_CORE ("dbgbcr15_el1",      CPENC (2,0,C0,C15,5),    0), >>> -  SR_CORE ("dbgwvr0_el1",       CPENC (2,0,C0,C0,6),    0), >>> -  SR_CORE ("dbgwvr1_el1",       CPENC (2,0,C0,C1,6),    0), >>> -  SR_CORE ("dbgwvr2_el1",       CPENC (2,0,C0,C2,6),    0), >>> -  SR_CORE ("dbgwvr3_el1",       CPENC (2,0,C0,C3,6),    0), >>> -  SR_CORE ("dbgwvr4_el1",       CPENC (2,0,C0,C4,6),    0), >>> -  SR_CORE ("dbgwvr5_el1",       CPENC (2,0,C0,C5,6),    0), >>> -  SR_CORE ("dbgwvr6_el1",       CPENC (2,0,C0,C6,6),    0), >>> -  SR_CORE ("dbgwvr7_el1",       CPENC (2,0,C0,C7,6),    0), >>> -  SR_CORE ("dbgwvr8_el1",       CPENC (2,0,C0,C8,6),    0), >>> -  SR_CORE ("dbgwvr9_el1",       CPENC (2,0,C0,C9,6),    0), >>> -  SR_CORE ("dbgwvr10_el1",      CPENC (2,0,C0,C10,6),    0), >>> -  SR_CORE ("dbgwvr11_el1",      CPENC (2,0,C0,C11,6),    0), >>> -  SR_CORE ("dbgwvr12_el1",      CPENC (2,0,C0,C12,6),    0), >>> -  SR_CORE ("dbgwvr13_el1",      CPENC (2,0,C0,C13,6),    0), >>> -  SR_CORE ("dbgwvr14_el1",      CPENC (2,0,C0,C14,6),    0), >>> -  SR_CORE ("dbgwvr15_el1",      CPENC (2,0,C0,C15,6),    0), >>> -  SR_CORE ("dbgwcr0_el1",       CPENC (2,0,C0,C0,7),    0), >>> -  SR_CORE ("dbgwcr1_el1",       CPENC (2,0,C0,C1,7),    0), >>> -  SR_CORE ("dbgwcr2_el1",       CPENC (2,0,C0,C2,7),    0), >>> -  SR_CORE ("dbgwcr3_el1",       CPENC (2,0,C0,C3,7),    0), >>> -  SR_CORE ("dbgwcr4_el1",       CPENC (2,0,C0,C4,7),    0), >>> -  SR_CORE ("dbgwcr5_el1",       CPENC (2,0,C0,C5,7),    0), >>> -  SR_CORE ("dbgwcr6_el1",       CPENC (2,0,C0,C6,7),    0), >>> -  SR_CORE ("dbgwcr7_el1",       CPENC (2,0,C0,C7,7),    0), >>> -  SR_CORE ("dbgwcr8_el1",       CPENC (2,0,C0,C8,7),    0), >>> -  SR_CORE ("dbgwcr9_el1",       CPENC (2,0,C0,C9,7),    0), >>> -  SR_CORE ("dbgwcr10_el1",      CPENC (2,0,C0,C10,7),    0), >>> -  SR_CORE ("dbgwcr11_el1",      CPENC (2,0,C0,C11,7),    0), >>> -  SR_CORE ("dbgwcr12_el1",      CPENC (2,0,C0,C12,7),    0), >>> -  SR_CORE ("dbgwcr13_el1",      CPENC (2,0,C0,C13,7),    0), >>> -  SR_CORE ("dbgwcr14_el1",      CPENC (2,0,C0,C14,7),    0), >>> -  SR_CORE ("dbgwcr15_el1",      CPENC (2,0,C0,C15,7),    0), >>> -  SR_CORE ("mdrar_el1",        CPENC (2,0,C1,C0,0),    F_REG_READ), >>> -  SR_CORE ("oslar_el1",        CPENC (2,0,C1,C0,4),    F_REG_WRITE), >>> -  SR_CORE ("oslsr_el1",        CPENC (2,0,C1,C1,4),    F_REG_READ), >>> -  SR_CORE ("osdlr_el1",        CPENC (2,0,C1,C3,4),    0), >>> -  SR_CORE ("dbgprcr_el1",       CPENC (2,0,C1,C4,4),    0), >>> -  SR_CORE ("dbgclaimset_el1",   CPENC (2,0,C7,C8,6),    0), >>> -  SR_CORE ("dbgclaimclr_el1",   CPENC (2,0,C7,C9,6),    0), >>> -  SR_CORE ("dbgauthstatus_el1", CPENC (2,0,C7,C14,6),    F_REG_READ), >>> -  SR_PROFILE ("pmblimitr_el1",    CPENC (3,0,C9,C10,0),    0), >>> -  SR_PROFILE ("pmbptr_el1",    CPENC (3,0,C9,C10,1),    0), >>> -  SR_PROFILE ("pmbsr_el1",    CPENC (3,0,C9,C10,3),    0), >>> -  SR_PROFILE ("pmbidr_el1",    CPENC (3,0,C9,C10,7),    F_REG_READ), >>> -  SR_PROFILE ("pmscr_el1",    CPENC (3,0,C9,C9,0),    0), >>> -  SR_PROFILE ("pmsicr_el1",    CPENC (3,0,C9,C9,2),    0), >>> -  SR_PROFILE ("pmsirr_el1",    CPENC (3,0,C9,C9,3),    0), >>> -  SR_PROFILE ("pmsfcr_el1",    CPENC (3,0,C9,C9,4),    0), >>> -  SR_PROFILE ("pmsevfr_el1",    CPENC (3,0,C9,C9,5),    0), >>> -  SR_PROFILE ("pmslatfr_el1",    CPENC (3,0,C9,C9,6),    0), >>> -  SR_PROFILE ("pmsidr_el1",    CPENC (3,0,C9,C9,7),    F_REG_READ), >>> -  SR_PROFILE ("pmscr_el2",    CPENC (3,4,C9,C9,0),    0), >>> -  SR_PROFILE ("pmscr_el12",    CPENC (3,5,C9,C9,0),    0), >>> -  SR_CORE ("pmcr_el0",        CPENC (3,3,C9,C12,0),    0), >>> -  SR_CORE ("pmcntenset_el0",    CPENC (3,3,C9,C12,1),    0), >>> -  SR_CORE ("pmcntenclr_el0",    CPENC (3,3,C9,C12,2),    0), >>> -  SR_CORE ("pmovsclr_el0",      CPENC (3,3,C9,C12,3),    0), >>> -  SR_CORE ("pmswinc_el0",       CPENC (3,3,C9,C12,4),    F_REG_WRITE), >>> -  SR_CORE ("pmselr_el0",    CPENC (3,3,C9,C12,5),    0), >>> -  SR_CORE ("pmceid0_el0",       CPENC (3,3,C9,C12,6),    F_REG_READ), >>> -  SR_CORE ("pmceid1_el0",       CPENC (3,3,C9,C12,7),    F_REG_READ), >>> -  SR_CORE ("pmccntr_el0",       CPENC (3,3,C9,C13,0),    0), >>> -  SR_CORE ("pmxevtyper_el0",    CPENC (3,3,C9,C13,1),    0), >>> -  SR_CORE ("pmxevcntr_el0",     CPENC (3,3,C9,C13,2),    0), >>> -  SR_CORE ("pmuserenr_el0",     CPENC (3,3,C9,C14,0),    0), >>> -  SR_CORE ("pmintenset_el1",    CPENC (3,0,C9,C14,1),    0), >>> -  SR_CORE ("pmintenclr_el1",    CPENC (3,0,C9,C14,2),    0), >>> -  SR_CORE ("pmovsset_el0",      CPENC (3,3,C9,C14,3),    0), >>> -  SR_CORE ("pmevcntr0_el0",     CPENC (3,3,C14,C8,0),    0), >>> -  SR_CORE ("pmevcntr1_el0",     CPENC (3,3,C14,C8,1),    0), >>> -  SR_CORE ("pmevcntr2_el0",     CPENC (3,3,C14,C8,2),    0), >>> -  SR_CORE ("pmevcntr3_el0",     CPENC (3,3,C14,C8,3),    0), >>> -  SR_CORE ("pmevcntr4_el0",     CPENC (3,3,C14,C8,4),    0), >>> -  SR_CORE ("pmevcntr5_el0",     CPENC (3,3,C14,C8,5),    0), >>> -  SR_CORE ("pmevcntr6_el0",     CPENC (3,3,C14,C8,6),    0), >>> -  SR_CORE ("pmevcntr7_el0",     CPENC (3,3,C14,C8,7),    0), >>> -  SR_CORE ("pmevcntr8_el0",     CPENC (3,3,C14,C9,0),    0), >>> -  SR_CORE ("pmevcntr9_el0",     CPENC (3,3,C14,C9,1),    0), >>> -  SR_CORE ("pmevcntr10_el0",    CPENC (3,3,C14,C9,2),    0), >>> -  SR_CORE ("pmevcntr11_el0",    CPENC (3,3,C14,C9,3),    0), >>> -  SR_CORE ("pmevcntr12_el0",    CPENC (3,3,C14,C9,4),    0), >>> -  SR_CORE ("pmevcntr13_el0",    CPENC (3,3,C14,C9,5),    0), >>> -  SR_CORE ("pmevcntr14_el0",    CPENC (3,3,C14,C9,6),    0), >>> -  SR_CORE ("pmevcntr15_el0",    CPENC (3,3,C14,C9,7),    0), >>> -  SR_CORE ("pmevcntr16_el0",    CPENC (3,3,C14,C10,0),    0), >>> -  SR_CORE ("pmevcntr17_el0",    CPENC (3,3,C14,C10,1),    0), >>> -  SR_CORE ("pmevcntr18_el0",    CPENC (3,3,C14,C10,2),    0), >>> -  SR_CORE ("pmevcntr19_el0",    CPENC (3,3,C14,C10,3),    0), >>> -  SR_CORE ("pmevcntr20_el0",    CPENC (3,3,C14,C10,4),    0), >>> -  SR_CORE ("pmevcntr21_el0",    CPENC (3,3,C14,C10,5),    0), >>> -  SR_CORE ("pmevcntr22_el0",    CPENC (3,3,C14,C10,6),    0), >>> -  SR_CORE ("pmevcntr23_el0",    CPENC (3,3,C14,C10,7),    0), >>> -  SR_CORE ("pmevcntr24_el0",    CPENC (3,3,C14,C11,0),    0), >>> -  SR_CORE ("pmevcntr25_el0",    CPENC (3,3,C14,C11,1),    0), >>> -  SR_CORE ("pmevcntr26_el0",    CPENC (3,3,C14,C11,2),    0), >>> -  SR_CORE ("pmevcntr27_el0",    CPENC (3,3,C14,C11,3),    0), >>> -  SR_CORE ("pmevcntr28_el0",    CPENC (3,3,C14,C11,4),    0), >>> -  SR_CORE ("pmevcntr29_el0",    CPENC (3,3,C14,C11,5),    0), >>> -  SR_CORE ("pmevcntr30_el0",    CPENC (3,3,C14,C11,6),    0), >>> -  SR_CORE ("pmevtyper0_el0",    CPENC (3,3,C14,C12,0),    0), >>> -  SR_CORE ("pmevtyper1_el0",    CPENC (3,3,C14,C12,1),    0), >>> -  SR_CORE ("pmevtyper2_el0",    CPENC (3,3,C14,C12,2),    0), >>> -  SR_CORE ("pmevtyper3_el0",    CPENC (3,3,C14,C12,3),    0), >>> -  SR_CORE ("pmevtyper4_el0",    CPENC (3,3,C14,C12,4),    0), >>> -  SR_CORE ("pmevtyper5_el0",    CPENC (3,3,C14,C12,5),    0), >>> -  SR_CORE ("pmevtyper6_el0",    CPENC (3,3,C14,C12,6),    0), >>> -  SR_CORE ("pmevtyper7_el0",    CPENC (3,3,C14,C12,7),    0), >>> -  SR_CORE ("pmevtyper8_el0",    CPENC (3,3,C14,C13,0),    0), >>> -  SR_CORE ("pmevtyper9_el0",    CPENC (3,3,C14,C13,1),    0), >>> -  SR_CORE ("pmevtyper10_el0",   CPENC (3,3,C14,C13,2),    0), >>> -  SR_CORE ("pmevtyper11_el0",   CPENC (3,3,C14,C13,3),    0), >>> -  SR_CORE ("pmevtyper12_el0",   CPENC (3,3,C14,C13,4),    0), >>> -  SR_CORE ("pmevtyper13_el0",   CPENC (3,3,C14,C13,5),    0), >>> -  SR_CORE ("pmevtyper14_el0",   CPENC (3,3,C14,C13,6),    0), >>> -  SR_CORE ("pmevtyper15_el0",   CPENC (3,3,C14,C13,7),    0), >>> -  SR_CORE ("pmevtyper16_el0",   CPENC (3,3,C14,C14,0),    0), >>> -  SR_CORE ("pmevtyper17_el0",   CPENC (3,3,C14,C14,1),    0), >>> -  SR_CORE ("pmevtyper18_el0",   CPENC (3,3,C14,C14,2),    0), >>> -  SR_CORE ("pmevtyper19_el0",   CPENC (3,3,C14,C14,3),    0), >>> -  SR_CORE ("pmevtyper20_el0",   CPENC (3,3,C14,C14,4),    0), >>> -  SR_CORE ("pmevtyper21_el0",   CPENC (3,3,C14,C14,5),    0), >>> -  SR_CORE ("pmevtyper22_el0",   CPENC (3,3,C14,C14,6),    0), >>> -  SR_CORE ("pmevtyper23_el0",   CPENC (3,3,C14,C14,7),    0), >>> -  SR_CORE ("pmevtyper24_el0",   CPENC (3,3,C14,C15,0),    0), >>> -  SR_CORE ("pmevtyper25_el0",   CPENC (3,3,C14,C15,1),    0), >>> -  SR_CORE ("pmevtyper26_el0",   CPENC (3,3,C14,C15,2),    0), >>> -  SR_CORE ("pmevtyper27_el0",   CPENC (3,3,C14,C15,3),    0), >>> -  SR_CORE ("pmevtyper28_el0",   CPENC (3,3,C14,C15,4),    0), >>> -  SR_CORE ("pmevtyper29_el0",   CPENC (3,3,C14,C15,5),    0), >>> -  SR_CORE ("pmevtyper30_el0",   CPENC (3,3,C14,C15,6),    0), >>> -  SR_CORE ("pmccfiltr_el0",     CPENC (3,3,C14,C15,7),    0), >>> - >>> -  SR_V8_4A ("dit",        CPEN_ (3,C2,5),        0), >>> -  SR_V8_4A ("trfcr_el1",        CPENC (3,0,C1,C2,1),    0), >>> -  SR_V8_4A ("pmmir_el1",        CPENC (3,0,C9,C14,6),    F_REG_READ), >>> -  SR_V8_4A ("trfcr_el2",        CPENC (3,4,C1,C2,1),    0), >>> -  SR_V8_4A ("vstcr_el2",        CPENC (3,4,C2,C6,2),    0), >>> -  SR_V8_4_A ("vsttbr_el2",    CPENC (3,4,C2,C6,0),    0), >>> -  SR_V8_4A ("cnthvs_tval_el2",    CPENC (3,4,C14,C4,0),    0), >>> -  SR_V8_4A ("cnthvs_cval_el2",    CPENC (3,4,C14,C4,2),    0), >>> -  SR_V8_4A ("cnthvs_ctl_el2",    CPENC (3,4,C14,C4,1),    0), >>> -  SR_V8_4A ("cnthps_tval_el2",    CPENC (3,4,C14,C5,0),    0), >>> -  SR_V8_4A ("cnthps_cval_el2",    CPENC (3,4,C14,C5,2),    0), >>> -  SR_V8_4A ("cnthps_ctl_el2",    CPENC (3,4,C14,C5,1),    0), >>> -  SR_V8_4A ("sder32_el2",    CPENC (3,4,C1,C3,1),    0), >>> -  SR_V8_4A ("vncr_el2",        CPENC (3,4,C2,C2,0),    0), >>> -  SR_V8_4A ("trfcr_el12",    CPENC (3,5,C1,C2,1),    0), >>> - >>> -  SR_CORE ("mpam0_el1",        CPENC (3,0,C10,C5,1),    0), >>> -  SR_CORE ("mpam1_el1",        CPENC (3,0,C10,C5,0),    0), >>> -  SR_CORE ("mpam1_el12",    CPENC (3,5,C10,C5,0),    0), >>> -  SR_CORE ("mpam2_el2",        CPENC (3,4,C10,C5,0),    0), >>> -  SR_CORE ("mpam3_el3",        CPENC (3,6,C10,C5,0),    0), >>> -  SR_CORE ("mpamhcr_el2",    CPENC (3,4,C10,C4,0),    0), >>> -  SR_CORE ("mpamidr_el1",    CPENC (3,0,C10,C4,4),    F_REG_READ), >>> -  SR_CORE ("mpamvpm0_el2",    CPENC (3,4,C10,C6,0),    0), >>> -  SR_CORE ("mpamvpm1_el2",    CPENC (3,4,C10,C6,1),    0), >>> -  SR_CORE ("mpamvpm2_el2",    CPENC (3,4,C10,C6,2),    0), >>> -  SR_CORE ("mpamvpm3_el2",    CPENC (3,4,C10,C6,3),    0), >>> -  SR_CORE ("mpamvpm4_el2",    CPENC (3,4,C10,C6,4),    0), >>> -  SR_CORE ("mpamvpm5_el2",    CPENC (3,4,C10,C6,5),    0), >>> -  SR_CORE ("mpamvpm6_el2",    CPENC (3,4,C10,C6,6),    0), >>> -  SR_CORE ("mpamvpm7_el2",    CPENC (3,4,C10,C6,7),    0), >>> -  SR_CORE ("mpamvpmv_el2",    CPENC (3,4,C10,C4,1),    0), >>> - >>> -  SR_V8R ("mpuir_el1",        CPENC (3,0,C0,C0,4),    F_REG_READ), >>> -  SR_V8R ("mpuir_el2",        CPENC (3,4,C0,C0,4),    F_REG_READ), >>> -  SR_V8R ("prbar_el1",        CPENC (3,0,C6,C8,0),    0), >>> -  SR_V8R ("prbar_el2",        CPENC (3,4,C6,C8,0),    0), >>> - >>> -#define ENC_BARLAR(x,n,lar) \ >>> -  CPENC (3, (x-1) << 2, C6, 8 | (n >> 1), ((n & 1) << 2) | lar) >>> - >>> -#define PRBARn_ELx(x,n) SR_V8R ("prbar" #n "_el" #x, ENC_BARLAR >>> (x,n,0), 0) >>> -#define PRLARn_ELx(x,n) SR_V8R ("prlar" #n "_el" #x, ENC_BARLAR >>> (x,n,1), 0) >>> - >>> -  SR_EXPAND_EL12 (PRBARn_ELx) >>> -  SR_V8R ("prenr_el1",        CPENC (3,0,C6,C1,1),    0), >>> -  SR_V8R ("prenr_el2",        CPENC (3,4,C6,C1,1),    0), >>> -  SR_V8R ("prlar_el1",        CPENC (3,0,C6,C8,1),    0), >>> -  SR_V8R ("prlar_el2",        CPENC (3,4,C6,C8,1),    0), >>> -  SR_EXPAND_EL12 (PRLARn_ELx) >>> -  SR_V8R ("prselr_el1",    CPENC (3,0,C6,C2,1),    0), >>> -  SR_V8R ("prselr_el2",    CPENC (3,4,C6,C2,1),    0), >>> -  SR_V8R ("vsctlr_el2",    CPENC (3,4,C2,C0,0),    0), >>> - >>> -  SR_CORE("trbbaser_el1",     CPENC (3,0,C9,C11,2),    0), >>> -  SR_CORE("trbidr_el1",     CPENC (3,0,C9,C11,7),    F_REG_READ), >>> -  SR_CORE("trblimitr_el1",     CPENC (3,0,C9,C11,0),    0), >>> -  SR_CORE("trbmar_el1",     CPENC (3,0,C9,C11,4),    0), >>> -  SR_CORE("trbptr_el1",     CPENC (3,0,C9,C11,1),    0), >>> -  SR_CORE("trbsr_el1",      CPENC (3,0,C9,C11,3),    0), >>> -  SR_CORE("trbtrg_el1",     CPENC (3,0,C9,C11,6),    0), >>> - >>> -  SR_CORE ("trcauthstatus", CPENC (2,1,C7,C14,6), F_REG_READ), >>> -  SR_CORE ("trccidr0",      CPENC (2,1,C7,C12,7), F_REG_READ), >>> -  SR_CORE ("trccidr1",      CPENC (2,1,C7,C13,7), F_REG_READ), >>> -  SR_CORE ("trccidr2",      CPENC (2,1,C7,C14,7), F_REG_READ), >>> -  SR_CORE ("trccidr3",      CPENC (2,1,C7,C15,7), F_REG_READ), >>> -  SR_CORE ("trcdevaff0",    CPENC (2,1,C7,C10,6), F_REG_READ), >>> -  SR_CORE ("trcdevaff1",    CPENC (2,1,C7,C11,6), F_REG_READ), >>> -  SR_CORE ("trcdevarch",    CPENC (2,1,C7,C15,6), F_REG_READ), >>> -  SR_CORE ("trcdevid",      CPENC (2,1,C7,C2,7),  F_REG_READ), >>> -  SR_CORE ("trcdevtype",    CPENC (2,1,C7,C3,7),  F_REG_READ), >>> -  SR_CORE ("trcidr0",       CPENC (2,1,C0,C8,7),  F_REG_READ), >>> -  SR_CORE ("trcidr1",       CPENC (2,1,C0,C9,7),  F_REG_READ), >>> -  SR_CORE ("trcidr2",       CPENC (2,1,C0,C10,7), F_REG_READ), >>> -  SR_CORE ("trcidr3",       CPENC (2,1,C0,C11,7), F_REG_READ), >>> -  SR_CORE ("trcidr4",       CPENC (2,1,C0,C12,7), F_REG_READ), >>> -  SR_CORE ("trcidr5",       CPENC (2,1,C0,C13,7), F_REG_READ), >>> -  SR_CORE ("trcidr6",       CPENC (2,1,C0,C14,7), F_REG_READ), >>> -  SR_CORE ("trcidr7",       CPENC (2,1,C0,C15,7), F_REG_READ), >>> -  SR_CORE ("trcidr8",       CPENC (2,1,C0,C0,6),  F_REG_READ), >>> -  SR_CORE ("trcidr9",       CPENC (2,1,C0,C1,6),  F_REG_READ), >>> -  SR_CORE ("trcidr10",      CPENC (2,1,C0,C2,6),  F_REG_READ), >>> -  SR_CORE ("trcidr11",      CPENC (2,1,C0,C3,6),  F_REG_READ), >>> -  SR_CORE ("trcidr12",      CPENC (2,1,C0,C4,6),  F_REG_READ), >>> -  SR_CORE ("trcidr13",      CPENC (2,1,C0,C5,6),  F_REG_READ), >>> -  SR_CORE ("trclsr",        CPENC (2,1,C7,C13,6), F_REG_READ), >>> -  SR_CORE ("trcoslsr",      CPENC (2,1,C1,C1,4),  F_REG_READ), >>> -  SR_CORE ("trcpdsr",       CPENC (2,1,C1,C5,4),  F_REG_READ), >>> -  SR_CORE ("trcpidr0",      CPENC (2,1,C7,C8,7),  F_REG_READ), >>> -  SR_CORE ("trcpidr1",      CPENC (2,1,C7,C9,7),  F_REG_READ), >>> -  SR_CORE ("trcpidr2",      CPENC (2,1,C7,C10,7), F_REG_READ), >>> -  SR_CORE ("trcpidr3",      CPENC (2,1,C7,C11,7), F_REG_READ), >>> -  SR_CORE ("trcpidr4",      CPENC (2,1,C7,C4,7),  F_REG_READ), >>> -  SR_CORE ("trcpidr5",      CPENC (2,1,C7,C5,7),  F_REG_READ), >>> -  SR_CORE ("trcpidr6",      CPENC (2,1,C7,C6,7),  F_REG_READ), >>> -  SR_CORE ("trcpidr7",      CPENC (2,1,C7,C7,7),  F_REG_READ), >>> -  SR_CORE ("trcstatr",      CPENC (2,1,C0,C3,0),  F_REG_READ), >>> -  SR_CORE ("trcacatr0",     CPENC (2,1,C2,C0,2),  0), >>> -  SR_CORE ("trcacatr1",     CPENC (2,1,C2,C2,2),  0), >>> -  SR_CORE ("trcacatr2",     CPENC (2,1,C2,C4,2),  0), >>> -  SR_CORE ("trcacatr3",     CPENC (2,1,C2,C6,2),  0), >>> -  SR_CORE ("trcacatr4",     CPENC (2,1,C2,C8,2),  0), >>> -  SR_CORE ("trcacatr5",     CPENC (2,1,C2,C10,2), 0), >>> -  SR_CORE ("trcacatr6",     CPENC (2,1,C2,C12,2), 0), >>> -  SR_CORE ("trcacatr7",     CPENC (2,1,C2,C14,2), 0), >>> -  SR_CORE ("trcacatr8",     CPENC (2,1,C2,C0,3),  0), >>> -  SR_CORE ("trcacatr9",     CPENC (2,1,C2,C2,3),  0), >>> -  SR_CORE ("trcacatr10",    CPENC (2,1,C2,C4,3),  0), >>> -  SR_CORE ("trcacatr11",    CPENC (2,1,C2,C6,3),  0), >>> -  SR_CORE ("trcacatr12",    CPENC (2,1,C2,C8,3),  0), >>> -  SR_CORE ("trcacatr13",    CPENC (2,1,C2,C10,3), 0), >>> -  SR_CORE ("trcacatr14",    CPENC (2,1,C2,C12,3), 0), >>> -  SR_CORE ("trcacatr15",    CPENC (2,1,C2,C14,3), 0), >>> -  SR_CORE ("trcacvr0",      CPENC (2,1,C2,C0,0),  0), >>> -  SR_CORE ("trcacvr1",      CPENC (2,1,C2,C2,0),  0), >>> -  SR_CORE ("trcacvr2",      CPENC (2,1,C2,C4,0),  0), >>> -  SR_CORE ("trcacvr3",      CPENC (2,1,C2,C6,0),  0), >>> -  SR_CORE ("trcacvr4",      CPENC (2,1,C2,C8,0),  0), >>> -  SR_CORE ("trcacvr5",      CPENC (2,1,C2,C10,0), 0), >>> -  SR_CORE ("trcacvr6",      CPENC (2,1,C2,C12,0), 0), >>> -  SR_CORE ("trcacvr7",      CPENC (2,1,C2,C14,0), 0), >>> -  SR_CORE ("trcacvr8",      CPENC (2,1,C2,C0,1),  0), >>> -  SR_CORE ("trcacvr9",      CPENC (2,1,C2,C2,1),  0), >>> -  SR_CORE ("trcacvr10",     CPENC (2,1,C2,C4,1),  0), >>> -  SR_CORE ("trcacvr11",     CPENC (2,1,C2,C6,1),  0), >>> -  SR_CORE ("trcacvr12",     CPENC (2,1,C2,C8,1),  0), >>> -  SR_CORE ("trcacvr13",     CPENC (2,1,C2,C10,1), 0), >>> -  SR_CORE ("trcacvr14",     CPENC (2,1,C2,C12,1), 0), >>> -  SR_CORE ("trcacvr15",     CPENC (2,1,C2,C14,1), 0), >>> -  SR_CORE ("trcauxctlr",    CPENC (2,1,C0,C6,0),  0), >>> -  SR_CORE ("trcbbctlr",     CPENC (2,1,C0,C15,0), 0), >>> -  SR_CORE ("trcccctlr",     CPENC (2,1,C0,C14,0), 0), >>> -  SR_CORE ("trccidcctlr0",  CPENC (2,1,C3,C0,2),  0), >>> -  SR_CORE ("trccidcctlr1",  CPENC (2,1,C3,C1,2),  0), >>> -  SR_CORE ("trccidcvr0",    CPENC (2,1,C3,C0,0),  0), >>> -  SR_CORE ("trccidcvr1",    CPENC (2,1,C3,C2,0),  0), >>> -  SR_CORE ("trccidcvr2",    CPENC (2,1,C3,C4,0),  0), >>> -  SR_CORE ("trccidcvr3",    CPENC (2,1,C3,C6,0),  0), >>> -  SR_CORE ("trccidcvr4",    CPENC (2,1,C3,C8,0),  0), >>> -  SR_CORE ("trccidcvr5",    CPENC (2,1,C3,C10,0), 0), >>> -  SR_CORE ("trccidcvr6",    CPENC (2,1,C3,C12,0), 0), >>> -  SR_CORE ("trccidcvr7",    CPENC (2,1,C3,C14,0), 0), >>> -  SR_CORE ("trcclaimclr",   CPENC (2,1,C7,C9,6),  0), >>> -  SR_CORE ("trcclaimset",   CPENC (2,1,C7,C8,6),  0), >>> -  SR_CORE ("trccntctlr0",   CPENC (2,1,C0,C4,5),  0), >>> -  SR_CORE ("trccntctlr1",   CPENC (2,1,C0,C5,5),  0), >>> -  SR_CORE ("trccntctlr2",   CPENC (2,1,C0,C6,5),  0), >>> -  SR_CORE ("trccntctlr3",   CPENC (2,1,C0,C7,5),  0), >>> -  SR_CORE ("trccntrldvr0",  CPENC (2,1,C0,C0,5),  0), >>> -  SR_CORE ("trccntrldvr1",  CPENC (2,1,C0,C1,5),  0), >>> -  SR_CORE ("trccntrldvr2",  CPENC (2,1,C0,C2,5),  0), >>> -  SR_CORE ("trccntrldvr3",  CPENC (2,1,C0,C3,5),  0), >>> -  SR_CORE ("trccntvr0",     CPENC (2,1,C0,C8,5),  0), >>> -  SR_CORE ("trccntvr1",     CPENC (2,1,C0,C9,5),  0), >>> -  SR_CORE ("trccntvr2",     CPENC (2,1,C0,C10,5), 0), >>> -  SR_CORE ("trccntvr3",     CPENC (2,1,C0,C11,5), 0), >>> -  SR_CORE ("trcconfigr",    CPENC (2,1,C0,C4,0),  0), >>> -  SR_CORE ("trcdvcmr0",     CPENC (2,1,C2,C0,6),  0), >>> -  SR_CORE ("trcdvcmr1",     CPENC (2,1,C2,C4,6),  0), >>> -  SR_CORE ("trcdvcmr2",     CPENC (2,1,C2,C8,6),  0), >>> -  SR_CORE ("trcdvcmr3",     CPENC (2,1,C2,C12,6), 0), >>> -  SR_CORE ("trcdvcmr4",     CPENC (2,1,C2,C0,7),  0), >>> -  SR_CORE ("trcdvcmr5",     CPENC (2,1,C2,C4,7),  0), >>> -  SR_CORE ("trcdvcmr6",     CPENC (2,1,C2,C8,7),  0), >>> -  SR_CORE ("trcdvcmr7",     CPENC (2,1,C2,C12,7), 0), >>> -  SR_CORE ("trcdvcvr0",     CPENC (2,1,C2,C0,4),  0), >>> -  SR_CORE ("trcdvcvr1",     CPENC (2,1,C2,C4,4),  0), >>> -  SR_CORE ("trcdvcvr2",     CPENC (2,1,C2,C8,4),  0), >>> -  SR_CORE ("trcdvcvr3",     CPENC (2,1,C2,C12,4), 0), >>> -  SR_CORE ("trcdvcvr4",     CPENC (2,1,C2,C0,5),  0), >>> -  SR_CORE ("trcdvcvr5",     CPENC (2,1,C2,C4,5),  0), >>> -  SR_CORE ("trcdvcvr6",     CPENC (2,1,C2,C8,5),  0), >>> -  SR_CORE ("trcdvcvr7",     CPENC (2,1,C2,C12,5), 0), >>> -  SR_CORE ("trceventctl0r", CPENC (2,1,C0,C8,0),  0), >>> -  SR_CORE ("trceventctl1r", CPENC (2,1,C0,C9,0),  0), >>> -  SR_CORE ("trcextinselr0", CPENC (2,1,C0,C8,4),  0), >>> -  SR_CORE ("trcextinselr",  CPENC (2,1,C0,C8,4),  F_REG_ALIAS), >>> -  SR_CORE ("trcextinselr1", CPENC (2,1,C0,C9,4),  0), >>> -  SR_CORE ("trcextinselr2", CPENC (2,1,C0,C10,4), 0), >>> -  SR_CORE ("trcextinselr3", CPENC (2,1,C0,C11,4), 0), >>> -  SR_CORE ("trcimspec0",    CPENC (2,1,C0,C0,7),  0), >>> -  SR_CORE ("trcimspec1",    CPENC (2,1,C0,C1,7),  0), >>> -  SR_CORE ("trcimspec2",    CPENC (2,1,C0,C2,7),  0), >>> -  SR_CORE ("trcimspec3",    CPENC (2,1,C0,C3,7),  0), >>> -  SR_CORE ("trcimspec4",    CPENC (2,1,C0,C4,7),  0), >>> -  SR_CORE ("trcimspec5",    CPENC (2,1,C0,C5,7),  0), >>> -  SR_CORE ("trcimspec6",    CPENC (2,1,C0,C6,7),  0), >>> -  SR_CORE ("trcimspec7",    CPENC (2,1,C0,C7,7),  0), >>> -  SR_CORE ("trcitctrl",     CPENC (2,1,C7,C0,4),  0), >>> -  SR_CORE ("trcpdcr",       CPENC (2,1,C1,C4,4),  0), >>> -  SR_CORE ("trcprgctlr",    CPENC (2,1,C0,C1,0),  0), >>> -  SR_CORE ("trcprocselr",   CPENC (2,1,C0,C2,0),  0), >>> -  SR_CORE ("trcqctlr",      CPENC (2,1,C0,C1,1),  0), >>> -  SR_CORE ("trcrsr",        CPENC (2,1,C0,C10,0), 0), >>> -  SR_CORE ("trcrsctlr2",    CPENC (2,1,C1,C2,0),  0), >>> -  SR_CORE ("trcrsctlr3",    CPENC (2,1,C1,C3,0),  0), >>> -  SR_CORE ("trcrsctlr4",    CPENC (2,1,C1,C4,0),  0), >>> -  SR_CORE ("trcrsctlr5",    CPENC (2,1,C1,C5,0),  0), >>> -  SR_CORE ("trcrsctlr6",    CPENC (2,1,C1,C6,0),  0), >>> -  SR_CORE ("trcrsctlr7",    CPENC (2,1,C1,C7,0),  0), >>> -  SR_CORE ("trcrsctlr8",    CPENC (2,1,C1,C8,0),  0), >>> -  SR_CORE ("trcrsctlr9",    CPENC (2,1,C1,C9,0),  0), >>> -  SR_CORE ("trcrsctlr10",   CPENC (2,1,C1,C10,0), 0), >>> -  SR_CORE ("trcrsctlr11",   CPENC (2,1,C1,C11,0), 0), >>> -  SR_CORE ("trcrsctlr12",   CPENC (2,1,C1,C12,0), 0), >>> -  SR_CORE ("trcrsctlr13",   CPENC (2,1,C1,C13,0), 0), >>> -  SR_CORE ("trcrsctlr14",   CPENC (2,1,C1,C14,0), 0), >>> -  SR_CORE ("trcrsctlr15",   CPENC (2,1,C1,C15,0), 0), >>> -  SR_CORE ("trcrsctlr16",   CPENC (2,1,C1,C0,1),  0), >>> -  SR_CORE ("trcrsctlr17",   CPENC (2,1,C1,C1,1),  0), >>> -  SR_CORE ("trcrsctlr18",   CPENC (2,1,C1,C2,1),  0), >>> -  SR_CORE ("trcrsctlr19",   CPENC (2,1,C1,C3,1),  0), >>> -  SR_CORE ("trcrsctlr20",   CPENC (2,1,C1,C4,1),  0), >>> -  SR_CORE ("trcrsctlr21",   CPENC (2,1,C1,C5,1),  0), >>> -  SR_CORE ("trcrsctlr22",   CPENC (2,1,C1,C6,1),  0), >>> -  SR_CORE ("trcrsctlr23",   CPENC (2,1,C1,C7,1),  0), >>> -  SR_CORE ("trcrsctlr24",   CPENC (2,1,C1,C8,1),  0), >>> -  SR_CORE ("trcrsctlr25",   CPENC (2,1,C1,C9,1),  0), >>> -  SR_CORE ("trcrsctlr26",   CPENC (2,1,C1,C10,1), 0), >>> -  SR_CORE ("trcrsctlr27",   CPENC (2,1,C1,C11,1), 0), >>> -  SR_CORE ("trcrsctlr28",   CPENC (2,1,C1,C12,1), 0), >>> -  SR_CORE ("trcrsctlr29",   CPENC (2,1,C1,C13,1), 0), >>> -  SR_CORE ("trcrsctlr30",   CPENC (2,1,C1,C14,1), 0), >>> -  SR_CORE ("trcrsctlr31",   CPENC (2,1,C1,C15,1), 0), >>> -  SR_CORE ("trcseqevr0",    CPENC (2,1,C0,C0,4),  0), >>> -  SR_CORE ("trcseqevr1",    CPENC (2,1,C0,C1,4),  0), >>> -  SR_CORE ("trcseqevr2",    CPENC (2,1,C0,C2,4),  0), >>> -  SR_CORE ("trcseqrstevr",  CPENC (2,1,C0,C6,4),  0), >>> -  SR_CORE ("trcseqstr",     CPENC (2,1,C0,C7,4),  0), >>> -  SR_CORE ("trcssccr0",     CPENC (2,1,C1,C0,2),  0), >>> -  SR_CORE ("trcssccr1",     CPENC (2,1,C1,C1,2),  0), >>> -  SR_CORE ("trcssccr2",     CPENC (2,1,C1,C2,2),  0), >>> -  SR_CORE ("trcssccr3",     CPENC (2,1,C1,C3,2),  0), >>> -  SR_CORE ("trcssccr4",     CPENC (2,1,C1,C4,2),  0), >>> -  SR_CORE ("trcssccr5",     CPENC (2,1,C1,C5,2),  0), >>> -  SR_CORE ("trcssccr6",     CPENC (2,1,C1,C6,2),  0), >>> -  SR_CORE ("trcssccr7",     CPENC (2,1,C1,C7,2),  0), >>> -  SR_CORE ("trcsscsr0",     CPENC (2,1,C1,C8,2),  0), >>> -  SR_CORE ("trcsscsr1",     CPENC (2,1,C1,C9,2),  0), >>> -  SR_CORE ("trcsscsr2",     CPENC (2,1,C1,C10,2), 0), >>> -  SR_CORE ("trcsscsr3",     CPENC (2,1,C1,C11,2), 0), >>> -  SR_CORE ("trcsscsr4",     CPENC (2,1,C1,C12,2), 0), >>> -  SR_CORE ("trcsscsr5",     CPENC (2,1,C1,C13,2), 0), >>> -  SR_CORE ("trcsscsr6",     CPENC (2,1,C1,C14,2), 0), >>> -  SR_CORE ("trcsscsr7",     CPENC (2,1,C1,C15,2), 0), >>> -  SR_CORE ("trcsspcicr0",   CPENC (2,1,C1,C0,3),  0), >>> -  SR_CORE ("trcsspcicr1",   CPENC (2,1,C1,C1,3),  0), >>> -  SR_CORE ("trcsspcicr2",   CPENC (2,1,C1,C2,3),  0), >>> -  SR_CORE ("trcsspcicr3",   CPENC (2,1,C1,C3,3),  0), >>> -  SR_CORE ("trcsspcicr4",   CPENC (2,1,C1,C4,3),  0), >>> -  SR_CORE ("trcsspcicr5",   CPENC (2,1,C1,C5,3),  0), >>> -  SR_CORE ("trcsspcicr6",   CPENC (2,1,C1,C6,3),  0), >>> -  SR_CORE ("trcsspcicr7",   CPENC (2,1,C1,C7,3),  0), >>> -  SR_CORE ("trcstallctlr",  CPENC (2,1,C0,C11,0), 0), >>> -  SR_CORE ("trcsyncpr",     CPENC (2,1,C0,C13,0), 0), >>> -  SR_CORE ("trctraceidr",   CPENC (2,1,C0,C0,1),  0), >>> -  SR_CORE ("trctsctlr",     CPENC (2,1,C0,C12,0), 0), >>> -  SR_CORE ("trcvdarcctlr",  CPENC (2,1,C0,C10,2), 0), >>> -  SR_CORE ("trcvdctlr",     CPENC (2,1,C0,C8,2),  0), >>> -  SR_CORE ("trcvdsacctlr",  CPENC (2,1,C0,C9,2),  0), >>> -  SR_CORE ("trcvictlr",     CPENC (2,1,C0,C0,2),  0), >>> -  SR_CORE ("trcviiectlr",   CPENC (2,1,C0,C1,2),  0), >>> -  SR_CORE ("trcvipcssctlr", CPENC (2,1,C0,C3,2),  0), >>> -  SR_CORE ("trcvissctlr",   CPENC (2,1,C0,C2,2),  0), >>> -  SR_CORE ("trcvmidcctlr0", CPENC (2,1,C3,C2,2),  0), >>> -  SR_CORE ("trcvmidcctlr1", CPENC (2,1,C3,C3,2),  0), >>> -  SR_CORE ("trcvmidcvr0",   CPENC (2,1,C3,C0,1),  0), >>> -  SR_CORE ("trcvmidcvr1",   CPENC (2,1,C3,C2,1),  0), >>> -  SR_CORE ("trcvmidcvr2",   CPENC (2,1,C3,C4,1),  0), >>> -  SR_CORE ("trcvmidcvr3",   CPENC (2,1,C3,C6,1),  0), >>> -  SR_CORE ("trcvmidcvr4",   CPENC (2,1,C3,C8,1),  0), >>> -  SR_CORE ("trcvmidcvr5",   CPENC (2,1,C3,C10,1), 0), >>> -  SR_CORE ("trcvmidcvr6",   CPENC (2,1,C3,C12,1), 0), >>> -  SR_CORE ("trcvmidcvr7",   CPENC (2,1,C3,C14,1), 0), >>> -  SR_CORE ("trclar",        CPENC (2,1,C7,C12,6), F_REG_WRITE), >>> -  SR_CORE ("trcoslar",      CPENC (2,1,C1,C0,4),  F_REG_WRITE), >>> - >>> -  SR_CORE ("csrcr_el0",     CPENC (2,3,C8,C0,0),  0), >>> -  SR_CORE ("csrptr_el0",    CPENC (2,3,C8,C0,1),  0), >>> -  SR_CORE ("csridr_el0",    CPENC (2,3,C8,C0,2),  F_REG_READ), >>> -  SR_CORE ("csrptridx_el0", CPENC (2,3,C8,C0,3),  F_REG_READ), >>> -  SR_CORE ("csrcr_el1",     CPENC (2,0,C8,C0,0),  0), >>> -  SR_CORE ("csrcr_el12",    CPENC (2,5,C8,C0,0),  0), >>> -  SR_CORE ("csrptr_el1",    CPENC (2,0,C8,C0,1),  0), >>> -  SR_CORE ("csrptr_el12",   CPENC (2,5,C8,C0,1),  0), >>> -  SR_CORE ("csrptridx_el1", CPENC (2,0,C8,C0,3),  F_REG_READ), >>> -  SR_CORE ("csrcr_el2",     CPENC (2,4,C8,C0,0),  0), >>> -  SR_CORE ("csrptr_el2",    CPENC (2,4,C8,C0,1),  0), >>> -  SR_CORE ("csrptridx_el2", CPENC (2,4,C8,C0,3),  F_REG_READ), >>> - >>> -  SR_LOR ("lorid_el1",      CPENC (3,0,C10,C4,7),  F_REG_READ), >>> -  SR_LOR ("lorc_el1",       CPENC (3,0,C10,C4,3),  0), >>> -  SR_LOR ("lorea_el1",      CPENC (3,0,C10,C4,1),  0), >>> -  SR_LOR ("lorn_el1",       CPENC (3,0,C10,C4,2),  0), >>> -  SR_LOR ("lorsa_el1",      CPENC (3,0,C10,C4,0),  0), >>> - >>> -  SR_CORE ("icc_ctlr_el3",  CPENC (3,6,C12,C12,4), 0), >>> -  SR_CORE ("icc_sre_el1",   CPENC (3,0,C12,C12,5), 0), >>> -  SR_CORE ("icc_sre_el2",   CPENC (3,4,C12,C9,5),  0), >>> -  SR_CORE ("icc_sre_el3",   CPENC (3,6,C12,C12,5), 0), >>> -  SR_CORE ("ich_vtr_el2",   CPENC (3,4,C12,C11,1), F_REG_READ), >>> - >>> -  SR_CORE ("brbcr_el1",     CPENC (2,1,C9,C0,0),  0), >>> -  SR_CORE ("brbcr_el12",    CPENC (2,5,C9,C0,0),  0), >>> -  SR_CORE ("brbfcr_el1",    CPENC (2,1,C9,C0,1),  0), >>> -  SR_CORE ("brbts_el1",     CPENC (2,1,C9,C0,2),  0), >>> -  SR_CORE ("brbinfinj_el1", CPENC (2,1,C9,C1,0),  0), >>> -  SR_CORE ("brbsrcinj_el1", CPENC (2,1,C9,C1,1),  0), >>> -  SR_CORE ("brbtgtinj_el1", CPENC (2,1,C9,C1,2),  0), >>> -  SR_CORE ("brbidr0_el1",   CPENC (2,1,C9,C2,0),  F_REG_READ), >>> -  SR_CORE ("brbcr_el2",     CPENC (2,4,C9,C0,0),  0), >>> -  SR_CORE ("brbsrc0_el1",   CPENC (2,1,C8,C0,1),  F_REG_READ), >>> -  SR_CORE ("brbsrc1_el1",   CPENC (2,1,C8,C1,1),  F_REG_READ), >>> -  SR_CORE ("brbsrc2_el1",   CPENC (2,1,C8,C2,1),  F_REG_READ), >>> -  SR_CORE ("brbsrc3_el1",   CPENC (2,1,C8,C3,1),  F_REG_READ), >>> -  SR_CORE ("brbsrc4_el1",   CPENC (2,1,C8,C4,1),  F_REG_READ), >>> -  SR_CORE ("brbsrc5_el1",   CPENC (2,1,C8,C5,1),  F_REG_READ), >>> -  SR_CORE ("brbsrc6_el1",   CPENC (2,1,C8,C6,1),  F_REG_READ), >>> -  SR_CORE ("brbsrc7_el1",   CPENC (2,1,C8,C7,1),  F_REG_READ), >>> -  SR_CORE ("brbsrc8_el1",   CPENC (2,1,C8,C8,1),  F_REG_READ), >>> -  SR_CORE ("brbsrc9_el1",   CPENC (2,1,C8,C9,1),  F_REG_READ), >>> -  SR_CORE ("brbsrc10_el1",  CPENC (2,1,C8,C10,1), F_REG_READ), >>> -  SR_CORE ("brbsrc11_el1",  CPENC (2,1,C8,C11,1), F_REG_READ), >>> -  SR_CORE ("brbsrc12_el1",  CPENC (2,1,C8,C12,1), F_REG_READ), >>> -  SR_CORE ("brbsrc13_el1",  CPENC (2,1,C8,C13,1), F_REG_READ), >>> -  SR_CORE ("brbsrc14_el1",  CPENC (2,1,C8,C14,1), F_REG_READ), >>> -  SR_CORE ("brbsrc15_el1",  CPENC (2,1,C8,C15,1), F_REG_READ), >>> -  SR_CORE ("brbsrc16_el1",  CPENC (2,1,C8,C0,5),  F_REG_READ), >>> -  SR_CORE ("brbsrc17_el1",  CPENC (2,1,C8,C1,5),  F_REG_READ), >>> -  SR_CORE ("brbsrc18_el1",  CPENC (2,1,C8,C2,5),  F_REG_READ), >>> -  SR_CORE ("brbsrc19_el1",  CPENC (2,1,C8,C3,5),  F_REG_READ), >>> -  SR_CORE ("brbsrc20_el1",  CPENC (2,1,C8,C4,5),  F_REG_READ), >>> -  SR_CORE ("brbsrc21_el1",  CPENC (2,1,C8,C5,5),  F_REG_READ), >>> -  SR_CORE ("brbsrc22_el1",  CPENC (2,1,C8,C6,5),  F_REG_READ), >>> -  SR_CORE ("brbsrc23_el1",  CPENC (2,1,C8,C7,5),  F_REG_READ), >>> -  SR_CORE ("brbsrc24_el1",  CPENC (2,1,C8,C8,5),  F_REG_READ), >>> -  SR_CORE ("brbsrc25_el1",  CPENC (2,1,C8,C9,5),  F_REG_READ), >>> -  SR_CORE ("brbsrc26_el1",  CPENC (2,1,C8,C10,5), F_REG_READ), >>> -  SR_CORE ("brbsrc27_el1",  CPENC (2,1,C8,C11,5), F_REG_READ), >>> -  SR_CORE ("brbsrc28_el1",  CPENC (2,1,C8,C12,5), F_REG_READ), >>> -  SR_CORE ("brbsrc29_el1",  CPENC (2,1,C8,C13,5), F_REG_READ), >>> -  SR_CORE ("brbsrc30_el1",  CPENC (2,1,C8,C14,5), F_REG_READ), >>> -  SR_CORE ("brbsrc31_el1",  CPENC (2,1,C8,C15,5), F_REG_READ), >>> -  SR_CORE ("brbtgt0_el1",   CPENC (2,1,C8,C0,2),  F_REG_READ), >>> -  SR_CORE ("brbtgt1_el1",   CPENC (2,1,C8,C1,2),  F_REG_READ), >>> -  SR_CORE ("brbtgt2_el1",   CPENC (2,1,C8,C2,2),  F_REG_READ), >>> -  SR_CORE ("brbtgt3_el1",   CPENC (2,1,C8,C3,2),  F_REG_READ), >>> -  SR_CORE ("brbtgt4_el1",   CPENC (2,1,C8,C4,2),  F_REG_READ), >>> -  SR_CORE ("brbtgt5_el1",   CPENC (2,1,C8,C5,2),  F_REG_READ), >>> -  SR_CORE ("brbtgt6_el1",   CPENC (2,1,C8,C6,2),  F_REG_READ), >>> -  SR_CORE ("brbtgt7_el1",   CPENC (2,1,C8,C7,2),  F_REG_READ), >>> -  SR_CORE ("brbtgt8_el1",   CPENC (2,1,C8,C8,2),  F_REG_READ), >>> -  SR_CORE ("brbtgt9_el1",   CPENC (2,1,C8,C9,2),  F_REG_READ), >>> -  SR_CORE ("brbtgt10_el1",  CPENC (2,1,C8,C10,2), F_REG_READ), >>> -  SR_CORE ("brbtgt11_el1",  CPENC (2,1,C8,C11,2), F_REG_READ), >>> -  SR_CORE ("brbtgt12_el1",  CPENC (2,1,C8,C12,2), F_REG_READ), >>> -  SR_CORE ("brbtgt13_el1",  CPENC (2,1,C8,C13,2), F_REG_READ), >>> -  SR_CORE ("brbtgt14_el1",  CPENC (2,1,C8,C14,2), F_REG_READ), >>> -  SR_CORE ("brbtgt15_el1",  CPENC (2,1,C8,C15,2), F_REG_READ), >>> -  SR_CORE ("brbtgt16_el1",  CPENC (2,1,C8,C0,6),  F_REG_READ), >>> -  SR_CORE ("brbtgt17_el1",  CPENC (2,1,C8,C1,6),  F_REG_READ), >>> -  SR_CORE ("brbtgt18_el1",  CPENC (2,1,C8,C2,6),  F_REG_READ), >>> -  SR_CORE ("brbtgt19_el1",  CPENC (2,1,C8,C3,6),  F_REG_READ), >>> -  SR_CORE ("brbtgt20_el1",  CPENC (2,1,C8,C4,6),  F_REG_READ), >>> -  SR_CORE ("brbtgt21_el1",  CPENC (2,1,C8,C5,6),  F_REG_READ), >>> -  SR_CORE ("brbtgt22_el1",  CPENC (2,1,C8,C6,6),  F_REG_READ), >>> -  SR_CORE ("brbtgt23_el1",  CPENC (2,1,C8,C7,6),  F_REG_READ), >>> -  SR_CORE ("brbtgt24_el1",  CPENC (2,1,C8,C8,6),  F_REG_READ), >>> -  SR_CORE ("brbtgt25_el1",  CPENC (2,1,C8,C9,6),  F_REG_READ), >>> -  SR_CORE ("brbtgt26_el1",  CPENC (2,1,C8,C10,6), F_REG_READ), >>> -  SR_CORE ("brbtgt27_el1",  CPENC (2,1,C8,C11,6), F_REG_READ), >>> -  SR_CORE ("brbtgt28_el1",  CPENC (2,1,C8,C12,6), F_REG_READ), >>> -  SR_CORE ("brbtgt29_el1",  CPENC (2,1,C8,C13,6), F_REG_READ), >>> -  SR_CORE ("brbtgt30_el1",  CPENC (2,1,C8,C14,6), F_REG_READ), >>> -  SR_CORE ("brbtgt31_el1",  CPENC (2,1,C8,C15,6), F_REG_READ), >>> -  SR_CORE ("brbinf0_el1",   CPENC (2,1,C8,C0,0),  F_REG_READ), >>> -  SR_CORE ("brbinf1_el1",   CPENC (2,1,C8,C1,0),  F_REG_READ), >>> -  SR_CORE ("brbinf2_el1",   CPENC (2,1,C8,C2,0),  F_REG_READ), >>> -  SR_CORE ("brbinf3_el1",   CPENC (2,1,C8,C3,0),  F_REG_READ), >>> -  SR_CORE ("brbinf4_el1",   CPENC (2,1,C8,C4,0),  F_REG_READ), >>> -  SR_CORE ("brbinf5_el1",   CPENC (2,1,C8,C5,0),  F_REG_READ), >>> -  SR_CORE ("brbinf6_el1",   CPENC (2,1,C8,C6,0),  F_REG_READ), >>> -  SR_CORE ("brbinf7_el1",   CPENC (2,1,C8,C7,0),  F_REG_READ), >>> -  SR_CORE ("brbinf8_el1",   CPENC (2,1,C8,C8,0),  F_REG_READ), >>> -  SR_CORE ("brbinf9_el1",   CPENC (2,1,C8,C9,0),  F_REG_READ), >>> -  SR_CORE ("brbinf10_el1",  CPENC (2,1,C8,C10,0), F_REG_READ), >>> -  SR_CORE ("brbinf11_el1",  CPENC (2,1,C8,C11,0), F_REG_READ), >>> -  SR_CORE ("brbinf12_el1",  CPENC (2,1,C8,C12,0), F_REG_READ), >>> -  SR_CORE ("brbinf13_el1",  CPENC (2,1,C8,C13,0), F_REG_READ), >>> -  SR_CORE ("brbinf14_el1",  CPENC (2,1,C8,C14,0), F_REG_READ), >>> -  SR_CORE ("brbinf15_el1",  CPENC (2,1,C8,C15,0), F_REG_READ), >>> -  SR_CORE ("brbinf16_el1",  CPENC (2,1,C8,C0,4),  F_REG_READ), >>> -  SR_CORE ("brbinf17_el1",  CPENC (2,1,C8,C1,4),  F_REG_READ), >>> -  SR_CORE ("brbinf18_el1",  CPENC (2,1,C8,C2,4),  F_REG_READ), >>> -  SR_CORE ("brbinf19_el1",  CPENC (2,1,C8,C3,4),  F_REG_READ), >>> -  SR_CORE ("brbinf20_el1",  CPENC (2,1,C8,C4,4),  F_REG_READ), >>> -  SR_CORE ("brbinf21_el1",  CPENC (2,1,C8,C5,4),  F_REG_READ), >>> -  SR_CORE ("brbinf22_el1",  CPENC (2,1,C8,C6,4),  F_REG_READ), >>> -  SR_CORE ("brbinf23_el1",  CPENC (2,1,C8,C7,4),  F_REG_READ), >>> -  SR_CORE ("brbinf24_el1",  CPENC (2,1,C8,C8,4),  F_REG_READ), >>> -  SR_CORE ("brbinf25_el1",  CPENC (2,1,C8,C9,4),  F_REG_READ), >>> -  SR_CORE ("brbinf26_el1",  CPENC (2,1,C8,C10,4), F_REG_READ), >>> -  SR_CORE ("brbinf27_el1",  CPENC (2,1,C8,C11,4), F_REG_READ), >>> -  SR_CORE ("brbinf28_el1",  CPENC (2,1,C8,C12,4), F_REG_READ), >>> -  SR_CORE ("brbinf29_el1",  CPENC (2,1,C8,C13,4), F_REG_READ), >>> -  SR_CORE ("brbinf30_el1",  CPENC (2,1,C8,C14,4), F_REG_READ), >>> -  SR_CORE ("brbinf31_el1",  CPENC (2,1,C8,C15,4), F_REG_READ), >>> - >>> -  SR_CORE ("accdata_el1",   CPENC (3,0,C13,C0,5), 0), >>> - >>> -  SR_CORE ("mfar_el3",      CPENC (3,6,C6,C0,5), 0), >>> -  SR_CORE ("gpccr_el3",     CPENC (3,6,C2,C1,6), 0), >>> -  SR_CORE ("gptbr_el3",     CPENC (3,6,C2,C1,4), 0), >>> - >>> -  SR_CORE ("mecidr_el2",    CPENC (3,4,C10,C8,7),  F_REG_READ), >>> -  SR_CORE ("mecid_p0_el2",  CPENC (3,4,C10,C8,0),  0), >>> -  SR_CORE ("mecid_a0_el2",  CPENC (3,4,C10,C8,1),  0), >>> -  SR_CORE ("mecid_p1_el2",  CPENC (3,4,C10,C8,2),  0), >>> -  SR_CORE ("mecid_a1_el2",  CPENC (3,4,C10,C8,3),  0), >>> -  SR_CORE ("vmecid_p_el2",  CPENC (3,4,C10,C9,0),  0), >>> -  SR_CORE ("vmecid_a_el2",  CPENC (3,4,C10,C9,1),  0), >>> -  SR_CORE ("mecid_rl_a_el3",CPENC (3,6,C10,C10,1), 0), >>> - >>> -  SR_SME ("svcr",             CPENC (3,3,C4,C2,2),  0), >>> -  SR_SME ("id_aa64smfr0_el1", CPENC (3,0,C0,C4,5),  F_REG_READ), >>> -  SR_SME ("smcr_el1",         CPENC (3,0,C1,C2,6),  0), >>> -  SR_SME ("smcr_el12",        CPENC (3,5,C1,C2,6),  0), >>> -  SR_SME ("smcr_el2",         CPENC (3,4,C1,C2,6),  0), >>> -  SR_SME ("smcr_el3",         CPENC (3,6,C1,C2,6),  0), >>> -  SR_SME ("smpri_el1",        CPENC (3,0,C1,C2,4),  0), >>> -  SR_SME ("smprimap_el2",     CPENC (3,4,C1,C2,5),  0), >>> -  SR_SME ("smidr_el1",        CPENC (3,1,C0,C0,6),  F_REG_READ), >>> -  SR_SME ("tpidr2_el0",       CPENC (3,3,C13,C0,5), 0), >>> -  SR_SME ("mpamsm_el1",       CPENC (3,0,C10,C5,3), 0), >>> - >>> -  SR_AMU ("amcr_el0",           CPENC (3,3,C13,C2,0),   0), >>> -  SR_AMU ("amcfgr_el0",         CPENC (3,3,C13,C2,1),   F_REG_READ), >>> -  SR_AMU ("amcgcr_el0",         CPENC (3,3,C13,C2,2),   F_REG_READ), >>> -  SR_AMU ("amuserenr_el0",      CPENC (3,3,C13,C2,3),   0), >>> -  SR_AMU ("amcntenclr0_el0",    CPENC (3,3,C13,C2,4),   0), >>> -  SR_AMU ("amcntenset0_el0",    CPENC (3,3,C13,C2,5),   0), >>> -  SR_AMU ("amcntenclr1_el0",    CPENC (3,3,C13,C3,0),   0), >>> -  SR_AMU ("amcntenset1_el0",    CPENC (3,3,C13,C3,1),   0), >>> -  SR_AMU ("amevcntr00_el0",     CPENC (3,3,C13,C4,0),   0), >>> -  SR_AMU ("amevcntr01_el0",     CPENC (3,3,C13,C4,1),   0), >>> -  SR_AMU ("amevcntr02_el0",     CPENC (3,3,C13,C4,2),   0), >>> -  SR_AMU ("amevcntr03_el0",     CPENC (3,3,C13,C4,3),   0), >>> -  SR_AMU ("amevtyper00_el0",    CPENC (3,3,C13,C6,0),   F_REG_READ), >>> -  SR_AMU ("amevtyper01_el0",    CPENC (3,3,C13,C6,1),   F_REG_READ), >>> -  SR_AMU ("amevtyper02_el0",    CPENC (3,3,C13,C6,2),   F_REG_READ), >>> -  SR_AMU ("amevtyper03_el0",    CPENC (3,3,C13,C6,3),   F_REG_READ), >>> -  SR_AMU ("amevcntr10_el0",     CPENC (3,3,C13,C12,0),  0), >>> -  SR_AMU ("amevcntr11_el0",     CPENC (3,3,C13,C12,1),  0), >>> -  SR_AMU ("amevcntr12_el0",     CPENC (3,3,C13,C12,2),  0), >>> -  SR_AMU ("amevcntr13_el0",     CPENC (3,3,C13,C12,3),  0), >>> -  SR_AMU ("amevcntr14_el0",     CPENC (3,3,C13,C12,4),  0), >>> -  SR_AMU ("amevcntr15_el0",     CPENC (3,3,C13,C12,5),  0), >>> -  SR_AMU ("amevcntr16_el0",     CPENC (3,3,C13,C12,6),  0), >>> -  SR_AMU ("amevcntr17_el0",     CPENC (3,3,C13,C12,7),  0), >>> -  SR_AMU ("amevcntr18_el0",     CPENC (3,3,C13,C13,0),  0), >>> -  SR_AMU ("amevcntr19_el0",     CPENC (3,3,C13,C13,1),  0), >>> -  SR_AMU ("amevcntr110_el0",    CPENC (3,3,C13,C13,2),  0), >>> -  SR_AMU ("amevcntr111_el0",    CPENC (3,3,C13,C13,3),  0), >>> -  SR_AMU ("amevcntr112_el0",    CPENC (3,3,C13,C13,4),  0), >>> -  SR_AMU ("amevcntr113_el0",    CPENC (3,3,C13,C13,5),  0), >>> -  SR_AMU ("amevcntr114_el0",    CPENC (3,3,C13,C13,6),  0), >>> -  SR_AMU ("amevcntr115_el0",    CPENC (3,3,C13,C13,7),  0), >>> -  SR_AMU ("amevtyper10_el0",    CPENC (3,3,C13,C14,0),  0), >>> -  SR_AMU ("amevtyper11_el0",    CPENC (3,3,C13,C14,1),  0), >>> -  SR_AMU ("amevtyper12_el0",    CPENC (3,3,C13,C14,2),  0), >>> -  SR_AMU ("amevtyper13_el0",    CPENC (3,3,C13,C14,3),  0), >>> -  SR_AMU ("amevtyper14_el0",    CPENC (3,3,C13,C14,4),  0), >>> -  SR_AMU ("amevtyper15_el0",    CPENC (3,3,C13,C14,5),  0), >>> -  SR_AMU ("amevtyper16_el0",    CPENC (3,3,C13,C14,6),  0), >>> -  SR_AMU ("amevtyper17_el0",    CPENC (3,3,C13,C14,7),  0), >>> -  SR_AMU ("amevtyper18_el0",    CPENC (3,3,C13,C15,0),  0), >>> -  SR_AMU ("amevtyper19_el0",    CPENC (3,3,C13,C15,1),  0), >>> -  SR_AMU ("amevtyper110_el0",   CPENC (3,3,C13,C15,2),  0), >>> -  SR_AMU ("amevtyper111_el0",   CPENC (3,3,C13,C15,3),  0), >>> -  SR_AMU ("amevtyper112_el0",   CPENC (3,3,C13,C15,4),  0), >>> -  SR_AMU ("amevtyper113_el0",   CPENC (3,3,C13,C15,5),  0), >>> -  SR_AMU ("amevtyper114_el0",   CPENC (3,3,C13,C15,6),  0), >>> -  SR_AMU ("amevtyper115_el0",   CPENC (3,3,C13,C15,7),  0), >>> - >>> -  SR_GIC ("icc_pmr_el1",        CPENC (3,0,C4,C6,0),    0), >>> -  SR_GIC ("icc_iar0_el1",       CPENC (3,0,C12,C8,0),   F_REG_READ), >>> -  SR_GIC ("icc_eoir0_el1",      CPENC (3,0,C12,C8,1),   F_REG_WRITE), >>> -  SR_GIC ("icc_hppir0_el1",     CPENC (3,0,C12,C8,2),   F_REG_READ), >>> -  SR_GIC ("icc_bpr0_el1",       CPENC (3,0,C12,C8,3),   0), >>> -  SR_GIC ("icc_ap0r0_el1",      CPENC (3,0,C12,C8,4),   0), >>> -  SR_GIC ("icc_ap0r1_el1",      CPENC (3,0,C12,C8,5),   0), >>> -  SR_GIC ("icc_ap0r2_el1",      CPENC (3,0,C12,C8,6),   0), >>> -  SR_GIC ("icc_ap0r3_el1",      CPENC (3,0,C12,C8,7),   0), >>> -  SR_GIC ("icc_ap1r0_el1",      CPENC (3,0,C12,C9,0),   0), >>> -  SR_GIC ("icc_ap1r1_el1",      CPENC (3,0,C12,C9,1),   0), >>> -  SR_GIC ("icc_ap1r2_el1",      CPENC (3,0,C12,C9,2),   0), >>> -  SR_GIC ("icc_ap1r3_el1",      CPENC (3,0,C12,C9,3),   0), >>> -  SR_GIC ("icc_dir_el1",        CPENC (3,0,C12,C11,1),  F_REG_WRITE), >>> -  SR_GIC ("icc_rpr_el1",        CPENC (3,0,C12,C11,3),  F_REG_READ), >>> -  SR_GIC ("icc_sgi1r_el1",      CPENC (3,0,C12,C11,5),  F_REG_WRITE), >>> -  SR_GIC ("icc_asgi1r_el1",     CPENC (3,0,C12,C11,6),  F_REG_WRITE), >>> -  SR_GIC ("icc_sgi0r_el1",      CPENC (3,0,C12,C11,7),  F_REG_WRITE), >>> -  SR_GIC ("icc_iar1_el1",       CPENC (3,0,C12,C12,0),  F_REG_READ), >>> -  SR_GIC ("icc_eoir1_el1",      CPENC (3,0,C12,C12,1),  F_REG_WRITE), >>> -  SR_GIC ("icc_hppir1_el1",     CPENC (3,0,C12,C12,2),  F_REG_READ), >>> -  SR_GIC ("icc_bpr1_el1",       CPENC (3,0,C12,C12,3),  0), >>> -  SR_GIC ("icc_ctlr_el1",       CPENC (3,0,C12,C12,4),  0), >>> -  SR_GIC ("icc_igrpen0_el1",    CPENC (3,0,C12,C12,6),  0), >>> -  SR_GIC ("icc_igrpen1_el1",    CPENC (3,0,C12,C12,7),  0), >>> -  SR_GIC ("ich_ap0r0_el2",      CPENC (3,4,C12,C8,0),   0), >>> -  SR_GIC ("ich_ap0r1_el2",      CPENC (3,4,C12,C8,1),   0), >>> -  SR_GIC ("ich_ap0r2_el2",      CPENC (3,4,C12,C8,2),   0), >>> -  SR_GIC ("ich_ap0r3_el2",      CPENC (3,4,C12,C8,3),   0), >>> -  SR_GIC ("ich_ap1r0_el2",      CPENC (3,4,C12,C9,0),   0), >>> -  SR_GIC ("ich_ap1r1_el2",      CPENC (3,4,C12,C9,1),   0), >>> -  SR_GIC ("ich_ap1r2_el2",      CPENC (3,4,C12,C9,2),   0), >>> -  SR_GIC ("ich_ap1r3_el2",      CPENC (3,4,C12,C9,3),   0), >>> -  SR_GIC ("ich_hcr_el2",        CPENC (3,4,C12,C11,0),  0), >>> -  SR_GIC ("ich_misr_el2",       CPENC (3,4,C12,C11,2),  F_REG_READ), >>> -  SR_GIC ("ich_eisr_el2",       CPENC (3,4,C12,C11,3),  F_REG_READ), >>> -  SR_GIC ("ich_elrsr_el2",      CPENC (3,4,C12,C11,5),  F_REG_READ), >>> -  SR_GIC ("ich_vmcr_el2",       CPENC (3,4,C12,C11,7),  0), >>> -  SR_GIC ("ich_lr0_el2",        CPENC (3,4,C12,C12,0),  0), >>> -  SR_GIC ("ich_lr1_el2",        CPENC (3,4,C12,C12,1),  0), >>> -  SR_GIC ("ich_lr2_el2",        CPENC (3,4,C12,C12,2),  0), >>> -  SR_GIC ("ich_lr3_el2",        CPENC (3,4,C12,C12,3),  0), >>> -  SR_GIC ("ich_lr4_el2",        CPENC (3,4,C12,C12,4),  0), >>> -  SR_GIC ("ich_lr5_el2",        CPENC (3,4,C12,C12,5),  0), >>> -  SR_GIC ("ich_lr6_el2",        CPENC (3,4,C12,C12,6),  0), >>> -  SR_GIC ("ich_lr7_el2",        CPENC (3,4,C12,C12,7),  0), >>> -  SR_GIC ("ich_lr8_el2",        CPENC (3,4,C12,C13,0),  0), >>> -  SR_GIC ("ich_lr9_el2",        CPENC (3,4,C12,C13,1),  0), >>> -  SR_GIC ("ich_lr10_el2",       CPENC (3,4,C12,C13,2),  0), >>> -  SR_GIC ("ich_lr11_el2",       CPENC (3,4,C12,C13,3),  0), >>> -  SR_GIC ("ich_lr12_el2",       CPENC (3,4,C12,C13,4),  0), >>> -  SR_GIC ("ich_lr13_el2",       CPENC (3,4,C12,C13,5),  0), >>> -  SR_GIC ("ich_lr14_el2",       CPENC (3,4,C12,C13,6),  0), >>> -  SR_GIC ("ich_lr15_el2",       CPENC (3,4,C12,C13,7),  0), >>> -  SR_GIC ("icc_igrpen1_el3",    CPENC (3,6,C12,C12,7),  0), >>> - >>> -  SR_V8_6A ("amcg1idr_el0",      CPENC (3,3,C13,C2,6),   F_REG_READ), >>> -  SR_V8_6A ("cntpctss_el0",      CPENC (3,3,C14,C0,5),   F_REG_READ), >>> -  SR_V8_6A ("cntvctss_el0",      CPENC (3,3,C14,C0,6),   F_REG_READ), >>> -  SR_V8_6A ("hfgrtr_el2",        CPENC (3,4,C1,C1,4),    0), >>> -  SR_V8_6A ("hfgwtr_el2",        CPENC (3,4,C1,C1,5),    0), >>> -  SR_V8_6A ("hfgitr_el2",        CPENC (3,4,C1,C1,6),    0), >>> -  SR_V8_6A ("hdfgrtr_el2",       CPENC (3,4,C3,C1,4),    0), >>> -  SR_V8_6A ("hdfgwtr_el2",       CPENC (3,4,C3,C1,5),    0), >>> -  SR_V8_6A ("hafgrtr_el2",       CPENC (3,4,C3,C1,6),    0), >>> -  SR_V8_6A ("amevcntvoff00_el2", CPENC (3,4,C13,C8,0),   0), >>> -  SR_V8_6A ("amevcntvoff01_el2", CPENC (3,4,C13,C8,1),   0), >>> -  SR_V8_6A ("amevcntvoff02_el2", CPENC (3,4,C13,C8,2),   0), >>> -  SR_V8_6A ("amevcntvoff03_el2", CPENC (3,4,C13,C8,3),   0), >>> -  SR_V8_6A ("amevcntvoff04_el2", CPENC (3,4,C13,C8,4),   0), >>> -  SR_V8_6A ("amevcntvoff05_el2", CPENC (3,4,C13,C8,5),   0), >>> -  SR_V8_6A ("amevcntvoff06_el2", CPENC (3,4,C13,C8,6),   0), >>> -  SR_V8_6A ("amevcntvoff07_el2", CPENC (3,4,C13,C8,7),   0), >>> -  SR_V8_6A ("amevcntvoff08_el2", CPENC (3,4,C13,C9,0),   0), >>> -  SR_V8_6A ("amevcntvoff09_el2", CPENC (3,4,C13,C9,1),   0), >>> -  SR_V8_6A ("amevcntvoff010_el2", CPENC (3,4,C13,C9,2),  0), >>> -  SR_V8_6A ("amevcntvoff011_el2", CPENC (3,4,C13,C9,3),  0), >>> -  SR_V8_6A ("amevcntvoff012_el2", CPENC (3,4,C13,C9,4),  0), >>> -  SR_V8_6A ("amevcntvoff013_el2", CPENC (3,4,C13,C9,5),  0), >>> -  SR_V8_6A ("amevcntvoff014_el2", CPENC (3,4,C13,C9,6),  0), >>> -  SR_V8_6A ("amevcntvoff015_el2", CPENC (3,4,C13,C9,7),  0), >>> -  SR_V8_6A ("amevcntvoff10_el2", CPENC (3,4,C13,C10,0),  0), >>> -  SR_V8_6A ("amevcntvoff11_el2", CPENC (3,4,C13,C10,1),  0), >>> -  SR_V8_6A ("amevcntvoff12_el2", CPENC (3,4,C13,C10,2),  0), >>> -  SR_V8_6A ("amevcntvoff13_el2", CPENC (3,4,C13,C10,3),  0), >>> -  SR_V8_6A ("amevcntvoff14_el2", CPENC (3,4,C13,C10,4),  0), >>> -  SR_V8_6A ("amevcntvoff15_el2", CPENC (3,4,C13,C10,5),  0), >>> -  SR_V8_6A ("amevcntvoff16_el2", CPENC (3,4,C13,C10,6),  0), >>> -  SR_V8_6A ("amevcntvoff17_el2", CPENC (3,4,C13,C10,7),  0), >>> -  SR_V8_6A ("amevcntvoff18_el2", CPENC (3,4,C13,C11,0),  0), >>> -  SR_V8_6A ("amevcntvoff19_el2", CPENC (3,4,C13,C11,1),  0), >>> -  SR_V8_6A ("amevcntvoff110_el2", CPENC (3,4,C13,C11,2), 0), >>> -  SR_V8_6A ("amevcntvoff111_el2", CPENC (3,4,C13,C11,3), 0), >>> -  SR_V8_6A ("amevcntvoff112_el2", CPENC (3,4,C13,C11,4), 0), >>> -  SR_V8_6A ("amevcntvoff113_el2", CPENC (3,4,C13,C11,5), 0), >>> -  SR_V8_6A ("amevcntvoff114_el2", CPENC (3,4,C13,C11,6), 0), >>> -  SR_V8_6A ("amevcntvoff115_el2", CPENC (3,4,C13,C11,7), 0), >>> -  SR_V8_6A ("cntpoff_el2",       CPENC (3,4,C14,C0,6),   0), >>> - >>> -  SR_V8_7A ("pmsnevfr_el1",      CPENC (3,0,C9,C9,1),    0), >>> -  SR_V8_7A ("hcrx_el2",          CPENC (3,4,C1,C2,2),    0), >>> - >>> -  SR_V8_8A ("allint",            CPENC (3,0,C4,C3,0),    0), >>> -  SR_V8_8A ("icc_nmiar1_el1",    CPENC (3,0,C12,C9,5),   F_REG_READ), >>> - >>> +  #define SYSREG(name, encoding, flags, features) \ >>> +    { name, encoding, flags, features }, >>> +  #include "aarch64-sys-regs.def" >>>     { 0, CPENC (0,0,0,0,0), 0, AARCH64_NO_FEATURES } >>> +  #undef SYSREG >>>   }; >>>   bool >>> @@ -5758,22 +4710,22 @@ aarch64_sys_reg_alias_p (const uint32_t >>> reg_flags) >>>      0b011010 (0x1a).  */ >>>   const aarch64_sys_reg aarch64_pstatefields [] = >>>   { >>> -  SR_CORE ("spsel",      0x05,    F_REG_MAX_VALUE (1)), >>> -  SR_CORE ("daifset",      0x1e,    F_REG_MAX_VALUE (15)), >>> -  SR_CORE ("daifclr",      0x1f,    F_REG_MAX_VALUE (15)), >>> -  SR_PAN  ("pan",      0x04, F_REG_MAX_VALUE (1)), >>> -  SR_V8_2A ("uao",      0x03, F_REG_MAX_VALUE (1)), >>> -  SR_SSBS ("ssbs",      0x19, F_REG_MAX_VALUE (1)), >>> -  SR_V8_4A ("dit",      0x1a,    F_REG_MAX_VALUE (1)), >>> -  SR_MEMTAG ("tco",      0x1c,    F_REG_MAX_VALUE (1)), >>> -  SR_SME  ("svcrsm",      0x1b, PSTATE_ENCODE_CRM_AND_IMM(0x2,0x1) >>> -                | F_REG_MAX_VALUE (1)), >>> -  SR_SME  ("svcrza",      0x1b, PSTATE_ENCODE_CRM_AND_IMM(0x4,0x1) >>> -                | F_REG_MAX_VALUE (1)), >>> -  SR_SME  ("svcrsmza",      0x1b, PSTATE_ENCODE_CRM_AND_IMM(0x6,0x1) >>> -                | F_REG_MAX_VALUE (1)), >>> -  SR_V8_8A ("allint",      0x08,    F_REG_MAX_VALUE (1)), >>> -  { 0,      CPENC (0,0,0,0,0), 0, AARCH64_NO_FEATURES }, >>> +  { "spsel",    0x05, F_REG_MAX_VALUE (1), AARCH64_NO_FEATURES }, >>> +  { "daifset",    0x1e, F_REG_MAX_VALUE (15), AARCH64_NO_FEATURES }, >>> +  { "daifclr",    0x1f, F_REG_MAX_VALUE (15), AARCH64_NO_FEATURES }, >>> +  { "pan",    0x04, F_REG_MAX_VALUE (1) | F_ARCHEXT, AARCH64_FEATURE >>> (PAN) }, >>> +  { "uao",    0x03, F_REG_MAX_VALUE (1) | F_ARCHEXT, AARCH64_FEATURE >>> (V8_2A) }, >>> +  { "ssbs",    0x19, F_REG_MAX_VALUE (1) | F_ARCHEXT, >>> AARCH64_FEATURE (SSBS) }, >>> +  { "dit",    0x1a, F_REG_MAX_VALUE (1) | F_ARCHEXT, AARCH64_FEATURE >>> (V8_4A) }, >>> +  { "tco",    0x1c, F_REG_MAX_VALUE (1) | F_ARCHEXT, AARCH64_FEATURE >>> (MEMTAG) }, >>> +  { "svcrsm",    0x1b, PSTATE_ENCODE_CRM_AND_IMM (0x2,0x1) | >>> F_REG_MAX_VALUE (1) >>> +              | F_ARCHEXT, AARCH64_FEATURE (SME) }, >>> +  { "svcrza",    0x1b, PSTATE_ENCODE_CRM_AND_IMM (0x4,0x1) | >>> F_REG_MAX_VALUE (1) >>> +              | F_ARCHEXT, AARCH64_FEATURE (SME) }, >>> +  { "svcrsmza",    0x1b, PSTATE_ENCODE_CRM_AND_IMM (0x6,0x1) | >>> F_REG_MAX_VALUE (1) >>> +              | F_ARCHEXT, AARCH64_FEATURE (SME) }, >>> +  { "allint",    0x08, F_REG_MAX_VALUE (1) | F_ARCHEXT, >>> AARCH64_FEATURE (V8_8A) }, >>> +  { 0,    CPENC (0,0,0,0,0), 0, AARCH64_NO_FEATURES }, >>>   }; >>>   bool >>> diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def >>> new file mode 100644 >>> index 00000000000..f8e733b6807 >>> --- /dev/null >>> +++ b/opcodes/aarch64-sys-regs.def >>> @@ -0,0 +1,1060 @@ >>> +/* aarch64-system-regs.def -- AArch64 opcode support. >>> +   Copyright (C) 2009-2023 Free Software Foundation, Inc. >>> +   Contributed by ARM Ltd. >>> + >>> +   This file is part of the GNU opcodes library. >>> + >>> +   This library is free software; you can redistribute it and/or modify >>> +   it under the terms of the GNU General Public License as published by >>> +   the Free Software Foundation; either version 3, or (at your option) >>> +   any later version. >>> + >>> +   It is distributed in the hope that it will be useful, but WITHOUT >>> +   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY >>> +   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public >>> +   License for more details. >>> + >>> +   You should have received a copy of the GNU General Public License >>> +   along with this program; see the file COPYING3.  If not, >>> +   see .  */ >>> + >>> +/* Array of system registers and their associated arch features. >>> + >>> +   Before using #include to read this file, define a macro: >>> + >>> +     SYSREG (name, encoding, flags, features) >>> + >>> +  The NAME is the system register name, as recognized by the >>> +  assembler.  ENCODING provides the necessary information for the >>> binary >>> +  encoding of the system register.  The FLAGS field is a bitmask of >>> +  relevant behavior information pertaining to the particular register. >>> +  For example: is it read/write-only? does it alias another register? >>> +  The FEATURES field maps onto ISA flags and specifies the >>> architectural >>> +  feature requirements of the system register.  */ >>> + >>> +  SYSREG ("accdata_el1",    CPENC (3,0,13,0,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("actlr_el1",        CPENC (3,0,1,0,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("actlr_el2",        CPENC (3,4,1,0,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("actlr_el3",        CPENC (3,6,1,0,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("afsr0_el1",        CPENC (3,0,5,1,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("afsr0_el12",        CPENC (3,5,5,1,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("afsr0_el2",        CPENC (3,4,5,1,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("afsr0_el3",        CPENC (3,6,5,1,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("afsr1_el1",        CPENC (3,0,5,1,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("afsr1_el12",        CPENC (3,5,5,1,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("afsr1_el2",        CPENC (3,4,5,1,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("afsr1_el3",        CPENC (3,6,5,1,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("aidr_el1",        CPENC (3,1,0,0,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("allint",        CPENC (3,0,4,3,0),    F_ARCHEXT, >>> AARCH64_FEATURE (V8_8A)) >>> +  SYSREG ("amair_el1",        CPENC (3,0,10,3,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("amair_el12",        CPENC (3,5,10,3,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("amair_el2",        CPENC (3,4,10,3,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("amair_el3",        CPENC (3,6,10,3,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("amcfgr_el0",        CPENC (3,3,13,2,1), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amcg1idr_el0",    CPENC (3,3,13,2,6), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amcgcr_el0",        CPENC (3,3,13,2,2), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amcntenclr0_el0",    CPENC (3,3,13,2,4), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amcntenclr1_el0",    CPENC (3,3,13,3,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amcntenset0_el0",    CPENC (3,3,13,2,5), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amcntenset1_el0",    CPENC (3,3,13,3,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amcr_el0",        CPENC (3,3,13,2,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntr00_el0",    CPENC (3,3,13,4,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntr01_el0",    CPENC (3,3,13,4,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntr02_el0",    CPENC (3,3,13,4,2), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntr03_el0",    CPENC (3,3,13,4,3), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntr10_el0",    CPENC (3,3,13,12,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntr110_el0",    CPENC (3,3,13,13,2), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntr111_el0",    CPENC (3,3,13,13,3), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntr112_el0",    CPENC (3,3,13,13,4), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntr113_el0",    CPENC (3,3,13,13,5), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntr114_el0",    CPENC (3,3,13,13,6), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntr115_el0",    CPENC (3,3,13,13,7), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntr11_el0",    CPENC (3,3,13,12,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntr12_el0",    CPENC (3,3,13,12,2), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntr13_el0",    CPENC (3,3,13,12,3), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntr14_el0",    CPENC (3,3,13,12,4), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntr15_el0",    CPENC (3,3,13,12,5), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntr16_el0",    CPENC (3,3,13,12,6), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntr17_el0",    CPENC (3,3,13,12,7), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntr18_el0",    CPENC (3,3,13,13,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntr19_el0",    CPENC (3,3,13,13,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevcntvoff00_el2",    CPENC (3,4,13,8,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff010_el2",    CPENC (3,4,13,9,2), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff011_el2",    CPENC (3,4,13,9,3), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff012_el2",    CPENC (3,4,13,9,4), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff013_el2",    CPENC (3,4,13,9,5), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff014_el2",    CPENC (3,4,13,9,6), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff015_el2",    CPENC (3,4,13,9,7), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff01_el2",    CPENC (3,4,13,8,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff02_el2",    CPENC (3,4,13,8,2), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff03_el2",    CPENC (3,4,13,8,3), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff04_el2",    CPENC (3,4,13,8,4), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff05_el2",    CPENC (3,4,13,8,5), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff06_el2",    CPENC (3,4,13,8,6), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff07_el2",    CPENC (3,4,13,8,7), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff08_el2",    CPENC (3,4,13,9,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff09_el2",    CPENC (3,4,13,9,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff10_el2",    CPENC (3,4,13,10,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff110_el2",    CPENC (3,4,13,11,2), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff111_el2",    CPENC (3,4,13,11,3), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff112_el2",    CPENC (3,4,13,11,4), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff113_el2",    CPENC (3,4,13,11,5), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff114_el2",    CPENC (3,4,13,11,6), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff115_el2",    CPENC (3,4,13,11,7), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff11_el2",    CPENC (3,4,13,10,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff12_el2",    CPENC (3,4,13,10,2), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff13_el2",    CPENC (3,4,13,10,3), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff14_el2",    CPENC (3,4,13,10,4), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff15_el2",    CPENC (3,4,13,10,5), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff16_el2",    CPENC (3,4,13,10,6), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff17_el2",    CPENC (3,4,13,10,7), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff18_el2",    CPENC (3,4,13,11,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevcntvoff19_el2",    CPENC (3,4,13,11,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("amevtyper00_el0",    CPENC (3,3,13,6,0), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevtyper01_el0",    CPENC (3,3,13,6,1), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevtyper02_el0",    CPENC (3,3,13,6,2), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevtyper03_el0",    CPENC (3,3,13,6,3), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevtyper10_el0",    CPENC (3,3,13,14,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevtyper110_el0",    CPENC (3,3,13,15,2), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevtyper111_el0",    CPENC (3,3,13,15,3), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevtyper112_el0",    CPENC (3,3,13,15,4), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevtyper113_el0",    CPENC (3,3,13,15,5), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevtyper114_el0",    CPENC (3,3,13,15,6), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevtyper115_el0",    CPENC (3,3,13,15,7), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevtyper11_el0",    CPENC (3,3,13,14,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevtyper12_el0",    CPENC (3,3,13,14,2), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevtyper13_el0",    CPENC (3,3,13,14,3), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevtyper14_el0",    CPENC (3,3,13,14,4), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevtyper15_el0",    CPENC (3,3,13,14,5), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevtyper16_el0",    CPENC (3,3,13,14,6), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevtyper17_el0",    CPENC (3,3,13,14,7), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevtyper18_el0",    CPENC (3,3,13,15,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amevtyper19_el0",    CPENC (3,3,13,15,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("amuserenr_el0",    CPENC (3,3,13,2,3), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("apdakeyhi_el1",    CPENC (3,0,2,2,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_3A)) >>> +  SYSREG ("apdakeylo_el1",    CPENC (3,0,2,2,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_3A)) >>> +  SYSREG ("apdbkeyhi_el1",    CPENC (3,0,2,2,3), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_3A)) >>> +  SYSREG ("apdbkeylo_el1",    CPENC (3,0,2,2,2), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_3A)) >>> +  SYSREG ("apgakeyhi_el1",    CPENC (3,0,2,3,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_3A)) >>> +  SYSREG ("apgakeylo_el1",    CPENC (3,0,2,3,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_3A)) >>> +  SYSREG ("apiakeyhi_el1",    CPENC (3,0,2,1,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_3A)) >>> +  SYSREG ("apiakeylo_el1",    CPENC (3,0,2,1,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_3A)) >>> +  SYSREG ("apibkeyhi_el1",    CPENC (3,0,2,1,3), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_3A)) >>> +  SYSREG ("apibkeylo_el1",    CPENC (3,0,2,1,2), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_3A)) >>> +  SYSREG ("brbcr_el1",        CPENC (2,1,9,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbcr_el12",        CPENC (2,5,9,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbcr_el2",        CPENC (2,4,9,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbfcr_el1",        CPENC (2,1,9,0,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbidr0_el1",    CPENC (2,1,9,2,0),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf0_el1",    CPENC (2,1,8,0,0),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf10_el1",    CPENC (2,1,8,10,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf11_el1",    CPENC (2,1,8,11,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf12_el1",    CPENC (2,1,8,12,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf13_el1",    CPENC (2,1,8,13,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf14_el1",    CPENC (2,1,8,14,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf15_el1",    CPENC (2,1,8,15,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf16_el1",    CPENC (2,1,8,0,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf17_el1",    CPENC (2,1,8,1,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf18_el1",    CPENC (2,1,8,2,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf19_el1",    CPENC (2,1,8,3,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf1_el1",    CPENC (2,1,8,1,0),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf20_el1",    CPENC (2,1,8,4,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf21_el1",    CPENC (2,1,8,5,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf22_el1",    CPENC (2,1,8,6,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf23_el1",    CPENC (2,1,8,7,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf24_el1",    CPENC (2,1,8,8,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf25_el1",    CPENC (2,1,8,9,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf26_el1",    CPENC (2,1,8,10,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf27_el1",    CPENC (2,1,8,11,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf28_el1",    CPENC (2,1,8,12,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf29_el1",    CPENC (2,1,8,13,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf2_el1",    CPENC (2,1,8,2,0),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf30_el1",    CPENC (2,1,8,14,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf31_el1",    CPENC (2,1,8,15,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf3_el1",    CPENC (2,1,8,3,0),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf4_el1",    CPENC (2,1,8,4,0),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf5_el1",    CPENC (2,1,8,5,0),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf6_el1",    CPENC (2,1,8,6,0),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf7_el1",    CPENC (2,1,8,7,0),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf8_el1",    CPENC (2,1,8,8,0),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinf9_el1",    CPENC (2,1,8,9,0),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbinfinj_el1",    CPENC (2,1,9,1,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc0_el1",    CPENC (2,1,8,0,1),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc10_el1",    CPENC (2,1,8,10,1), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc11_el1",    CPENC (2,1,8,11,1), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc12_el1",    CPENC (2,1,8,12,1), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc13_el1",    CPENC (2,1,8,13,1), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc14_el1",    CPENC (2,1,8,14,1), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc15_el1",    CPENC (2,1,8,15,1), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc16_el1",    CPENC (2,1,8,0,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc17_el1",    CPENC (2,1,8,1,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc18_el1",    CPENC (2,1,8,2,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc19_el1",    CPENC (2,1,8,3,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc1_el1",    CPENC (2,1,8,1,1),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc20_el1",    CPENC (2,1,8,4,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc21_el1",    CPENC (2,1,8,5,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc22_el1",    CPENC (2,1,8,6,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc23_el1",    CPENC (2,1,8,7,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc24_el1",    CPENC (2,1,8,8,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc25_el1",    CPENC (2,1,8,9,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc26_el1",    CPENC (2,1,8,10,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc27_el1",    CPENC (2,1,8,11,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc28_el1",    CPENC (2,1,8,12,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc29_el1",    CPENC (2,1,8,13,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc2_el1",    CPENC (2,1,8,2,1),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc30_el1",    CPENC (2,1,8,14,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc31_el1",    CPENC (2,1,8,15,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc3_el1",    CPENC (2,1,8,3,1),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc4_el1",    CPENC (2,1,8,4,1),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc5_el1",    CPENC (2,1,8,5,1),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc6_el1",    CPENC (2,1,8,6,1),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc7_el1",    CPENC (2,1,8,7,1),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc8_el1",    CPENC (2,1,8,8,1),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrc9_el1",    CPENC (2,1,8,9,1),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbsrcinj_el1",    CPENC (2,1,9,1,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt0_el1",    CPENC (2,1,8,0,2),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt10_el1",    CPENC (2,1,8,10,2), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt11_el1",    CPENC (2,1,8,11,2), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt12_el1",    CPENC (2,1,8,12,2), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt13_el1",    CPENC (2,1,8,13,2), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt14_el1",    CPENC (2,1,8,14,2), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt15_el1",    CPENC (2,1,8,15,2), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt16_el1",    CPENC (2,1,8,0,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt17_el1",    CPENC (2,1,8,1,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt18_el1",    CPENC (2,1,8,2,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt19_el1",    CPENC (2,1,8,3,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt1_el1",    CPENC (2,1,8,1,2),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt20_el1",    CPENC (2,1,8,4,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt21_el1",    CPENC (2,1,8,5,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt22_el1",    CPENC (2,1,8,6,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt23_el1",    CPENC (2,1,8,7,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt24_el1",    CPENC (2,1,8,8,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt25_el1",    CPENC (2,1,8,9,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt26_el1",    CPENC (2,1,8,10,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt27_el1",    CPENC (2,1,8,11,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt28_el1",    CPENC (2,1,8,12,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt29_el1",    CPENC (2,1,8,13,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt2_el1",    CPENC (2,1,8,2,2),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt30_el1",    CPENC (2,1,8,14,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt31_el1",    CPENC (2,1,8,15,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt3_el1",    CPENC (2,1,8,3,2),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt4_el1",    CPENC (2,1,8,4,2),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt5_el1",    CPENC (2,1,8,5,2),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt6_el1",    CPENC (2,1,8,6,2),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt7_el1",    CPENC (2,1,8,7,2),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt8_el1",    CPENC (2,1,8,8,2),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgt9_el1",    CPENC (2,1,8,9,2),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbtgtinj_el1",    CPENC (2,1,9,1,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("brbts_el1",        CPENC (2,1,9,0,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ccsidr2_el1",    CPENC (3,1,0,0,2), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (V8_3A)) >>> +  SYSREG ("ccsidr_el1",        CPENC (3,1,0,0,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("clidr_el1",        CPENC (3,1,0,0,1), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("cntfrq_el0",        CPENC (3,3,14,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("cnthctl_el2",    CPENC (3,4,14,1,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("cnthp_ctl_el2",    CPENC (3,4,14,2,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("cnthp_cval_el2",    CPENC (3,4,14,2,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("cnthp_tval_el2",    CPENC (3,4,14,2,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("cnthps_ctl_el2",    CPENC (3,4,14,5,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("cnthps_cval_el2",    CPENC (3,4,14,5,2), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("cnthps_tval_el2",    CPENC (3,4,14,5,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("cnthv_ctl_el2",    CPENC (3,4,14,3,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("cnthv_cval_el2",    CPENC (3,4,14,3,2), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("cnthv_tval_el2",    CPENC (3,4,14,3,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("cnthvs_ctl_el2",    CPENC (3,4,14,4,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("cnthvs_cval_el2",    CPENC (3,4,14,4,2), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("cnthvs_tval_el2",    CPENC (3,4,14,4,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("cntkctl_el1",    CPENC (3,0,14,1,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("cntkctl_el12",    CPENC (3,5,14,1,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("cntp_ctl_el0",    CPENC (3,3,14,2,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("cntp_ctl_el02",    CPENC (3,5,14,2,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("cntp_cval_el0",    CPENC (3,3,14,2,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("cntp_cval_el02",    CPENC (3,5,14,2,2), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("cntp_tval_el0",    CPENC (3,3,14,2,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("cntp_tval_el02",    CPENC (3,5,14,2,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("cntpct_el0",        CPENC (3,3,14,0,1), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("cntpctss_el0",    CPENC (3,3,14,0,5), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("cntpoff_el2",    CPENC (3,4,14,0,6),    F_ARCHEXT, >>> AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("cntps_ctl_el1",    CPENC (3,7,14,2,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("cntps_cval_el1",    CPENC (3,7,14,2,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("cntps_tval_el1",    CPENC (3,7,14,2,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("cntv_ctl_el0",    CPENC (3,3,14,3,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("cntv_ctl_el02",    CPENC (3,5,14,3,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("cntv_cval_el0",    CPENC (3,3,14,3,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("cntv_cval_el02",    CPENC (3,5,14,3,2), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("cntv_tval_el0",    CPENC (3,3,14,3,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("cntv_tval_el02",    CPENC (3,5,14,3,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("cntvct_el0",        CPENC (3,3,14,0,2), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("cntvctss_el0",    CPENC (3,3,14,0,6), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("cntvoff_el2",    CPENC (3,4,14,0,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("contextidr_el1",    CPENC (3,0,13,0,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("contextidr_el12",    CPENC (3,5,13,0,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("contextidr_el2",    CPENC (3,4,13,0,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("cpacr_el1",        CPENC (3,0,1,0,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("cpacr_el12",        CPENC (3,5,1,0,2), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("cptr_el2",        CPENC (3,4,1,1,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("cptr_el3",        CPENC (3,6,1,1,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("csrcr_el0",        CPENC (2,3,8,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("csrcr_el1",        CPENC (2,0,8,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("csrcr_el12",        CPENC (2,5,8,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("csrcr_el2",        CPENC (2,4,8,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("csridr_el0",        CPENC (2,3,8,0,2), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("csrptr_el0",        CPENC (2,3,8,0,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("csrptr_el1",        CPENC (2,0,8,0,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("csrptr_el12",    CPENC (2,5,8,0,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("csrptr_el2",        CPENC (2,4,8,0,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("csrptridx_el0",    CPENC (2,3,8,0,3), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("csrptridx_el1",    CPENC (2,0,8,0,3), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("csrptridx_el2",    CPENC (2,4,8,0,3), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("csselr_el1",        CPENC (3,2,0,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ctr_el0",        CPENC (3,3,0,0,1),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("currentel",        CPENC (3,0,4,2,2), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("dacr32_el2",        CPENC (3,4,3,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("daif",        CPENC (3,3,4,2,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgauthstatus_el1",    CPENC (2,0,7,14,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbcr0_el1",    CPENC (2,0,0,0,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbcr10_el1",    CPENC (2,0,0,10,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbcr11_el1",    CPENC (2,0,0,11,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbcr12_el1",    CPENC (2,0,0,12,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbcr13_el1",    CPENC (2,0,0,13,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbcr14_el1",    CPENC (2,0,0,14,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbcr15_el1",    CPENC (2,0,0,15,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbcr1_el1",    CPENC (2,0,0,1,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbcr2_el1",    CPENC (2,0,0,2,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbcr3_el1",    CPENC (2,0,0,3,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbcr4_el1",    CPENC (2,0,0,4,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbcr5_el1",    CPENC (2,0,0,5,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbcr6_el1",    CPENC (2,0,0,6,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbcr7_el1",    CPENC (2,0,0,7,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbcr8_el1",    CPENC (2,0,0,8,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbcr9_el1",    CPENC (2,0,0,9,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbvr0_el1",    CPENC (2,0,0,0,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbvr10_el1",    CPENC (2,0,0,10,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbvr11_el1",    CPENC (2,0,0,11,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbvr12_el1",    CPENC (2,0,0,12,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbvr13_el1",    CPENC (2,0,0,13,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbvr14_el1",    CPENC (2,0,0,14,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbvr15_el1",    CPENC (2,0,0,15,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbvr1_el1",    CPENC (2,0,0,1,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbvr2_el1",    CPENC (2,0,0,2,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbvr3_el1",    CPENC (2,0,0,3,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbvr4_el1",    CPENC (2,0,0,4,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbvr5_el1",    CPENC (2,0,0,5,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbvr6_el1",    CPENC (2,0,0,6,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbvr7_el1",    CPENC (2,0,0,7,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbvr8_el1",    CPENC (2,0,0,8,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgbvr9_el1",    CPENC (2,0,0,9,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgclaimclr_el1",    CPENC (2,0,7,9,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgclaimset_el1",    CPENC (2,0,7,8,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgdtr_el0",        CPENC (2,3,0,4,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgdtrrx_el0",    CPENC (2,3,0,5,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgdtrtx_el0",    CPENC (2,3,0,5,0), >>> F_REG_WRITE,        AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgprcr_el1",    CPENC (2,0,1,4,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgvcr32_el2",    CPENC (2,4,0,7,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwcr0_el1",    CPENC (2,0,0,0,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwcr10_el1",    CPENC (2,0,0,10,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwcr11_el1",    CPENC (2,0,0,11,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwcr12_el1",    CPENC (2,0,0,12,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwcr13_el1",    CPENC (2,0,0,13,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwcr14_el1",    CPENC (2,0,0,14,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwcr15_el1",    CPENC (2,0,0,15,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwcr1_el1",    CPENC (2,0,0,1,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwcr2_el1",    CPENC (2,0,0,2,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwcr3_el1",    CPENC (2,0,0,3,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwcr4_el1",    CPENC (2,0,0,4,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwcr5_el1",    CPENC (2,0,0,5,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwcr6_el1",    CPENC (2,0,0,6,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwcr7_el1",    CPENC (2,0,0,7,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwcr8_el1",    CPENC (2,0,0,8,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwcr9_el1",    CPENC (2,0,0,9,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwvr0_el1",    CPENC (2,0,0,0,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwvr10_el1",    CPENC (2,0,0,10,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwvr11_el1",    CPENC (2,0,0,11,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwvr12_el1",    CPENC (2,0,0,12,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwvr13_el1",    CPENC (2,0,0,13,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwvr14_el1",    CPENC (2,0,0,14,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwvr15_el1",    CPENC (2,0,0,15,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwvr1_el1",    CPENC (2,0,0,1,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwvr2_el1",    CPENC (2,0,0,2,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwvr3_el1",    CPENC (2,0,0,3,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwvr4_el1",    CPENC (2,0,0,4,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwvr5_el1",    CPENC (2,0,0,5,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwvr6_el1",    CPENC (2,0,0,6,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwvr7_el1",    CPENC (2,0,0,7,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwvr8_el1",    CPENC (2,0,0,8,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dbgwvr9_el1",    CPENC (2,0,0,9,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dczid_el0",        CPENC (3,3,0,0,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("disr_el1",        CPENC (3,0,12,1,1), >>> F_ARCHEXT,        AARCH64_FEATURE (RAS)) >>> +  SYSREG ("dit",        CPENC (3,3,4,2,5),    F_ARCHEXT, >>> AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("dlr_el0",        CPENC (3,3,4,5,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("dspsr_el0",        CPENC (3,3,4,5,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("elr_el1",        CPENC (3,0,4,0,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("elr_el12",        CPENC (3,5,4,0,1),    F_ARCHEXT, >>> AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("elr_el2",        CPENC (3,4,4,0,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("elr_el3",        CPENC (3,6,4,0,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("erridr_el1",        CPENC (3,0,5,3,0), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (RAS)) >>> +  SYSREG ("errselr_el1",    CPENC (3,0,5,3,1),    F_ARCHEXT, >>> AARCH64_FEATURE (RAS)) >>> +  SYSREG ("erxaddr_el1",    CPENC (3,0,5,4,3),    F_ARCHEXT, >>> AARCH64_FEATURE (RAS)) >>> +  SYSREG ("erxctlr_el1",    CPENC (3,0,5,4,1),    F_ARCHEXT, >>> AARCH64_FEATURE (RAS)) >>> +  SYSREG ("erxfr_el1",        CPENC (3,0,5,4,0), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (RAS)) >>> +  SYSREG ("erxmisc0_el1",    CPENC (3,0,5,5,0),    F_ARCHEXT, >>> AARCH64_FEATURE (RAS)) >>> +  SYSREG ("erxmisc1_el1",    CPENC (3,0,5,5,1),    F_ARCHEXT, >>> AARCH64_FEATURE (RAS)) >>> +  SYSREG ("erxmisc2_el1",    CPENC (3,0,5,5,2),    F_ARCHEXT, >>> AARCH64_FEATURE (RAS)) >>> +  SYSREG ("erxmisc3_el1",    CPENC (3,0,5,5,3),    F_ARCHEXT, >>> AARCH64_FEATURE (RAS)) >>> +  SYSREG ("erxpfgcdn_el1",    CPENC (3,0,5,4,6), >>> F_ARCHEXT,        AARCH64_FEATURE (RAS)) >>> +  SYSREG ("erxpfgctl_el1",    CPENC (3,0,5,4,5), >>> F_ARCHEXT,        AARCH64_FEATURE (RAS)) >>> +  SYSREG ("erxpfgf_el1",    CPENC (3,0,5,4,4), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (RAS)) >>> +  SYSREG ("erxstatus_el1",    CPENC (3,0,5,4,2), >>> F_ARCHEXT,        AARCH64_FEATURE (RAS)) >>> +  SYSREG ("esr_el1",        CPENC (3,0,5,2,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("esr_el12",        CPENC (3,5,5,2,0),    F_ARCHEXT, >>> AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("esr_el2",        CPENC (3,4,5,2,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("esr_el3",        CPENC (3,6,5,2,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("far_el1",        CPENC (3,0,6,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("far_el12",        CPENC (3,5,6,0,0),    F_ARCHEXT, >>> AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("far_el2",        CPENC (3,4,6,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("far_el3",        CPENC (3,6,6,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("fpcr",        CPENC (3,3,4,4,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("fpexc32_el2",    CPENC (3,4,5,3,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("fpsr",        CPENC (3,3,4,4,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("gcr_el1",        CPENC (3,0,1,0,6),    F_ARCHEXT, >>> AARCH64_FEATURE (MEMTAG)) >>> +  SYSREG ("gmid_el1",        CPENC (3,1,0,0,4), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (MEMTAG)) >>> +  SYSREG ("gpccr_el3",        CPENC (3,6,2,1,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("gptbr_el3",        CPENC (3,6,2,1,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("hacr_el2",        CPENC (3,4,1,1,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("hafgrtr_el2",    CPENC (3,4,3,1,6),    F_ARCHEXT, >>> AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("hcr_el2",        CPENC (3,4,1,1,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("hcrx_el2",        CPENC (3,4,1,2,2),    F_ARCHEXT, >>> AARCH64_FEATURE (V8_7A)) >>> +  SYSREG ("hdfgrtr_el2",    CPENC (3,4,3,1,4),    F_ARCHEXT, >>> AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("hdfgwtr_el2",    CPENC (3,4,3,1,5),    F_ARCHEXT, >>> AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("hfgitr_el2",        CPENC (3,4,1,1,6), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("hfgrtr_el2",        CPENC (3,4,1,1,4), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("hfgwtr_el2",        CPENC (3,4,1,1,5), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_6A)) >>> +  SYSREG ("hpfar_el2",        CPENC (3,4,6,0,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("hstr_el2",        CPENC (3,4,1,1,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_ap0r0_el1",    CPENC (3,0,12,8,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_ap0r1_el1",    CPENC (3,0,12,8,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_ap0r2_el1",    CPENC (3,0,12,8,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_ap0r3_el1",    CPENC (3,0,12,8,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_ap1r0_el1",    CPENC (3,0,12,9,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_ap1r1_el1",    CPENC (3,0,12,9,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_ap1r2_el1",    CPENC (3,0,12,9,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_ap1r3_el1",    CPENC (3,0,12,9,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_asgi1r_el1",    CPENC (3,0,12,11,6), >>> F_REG_WRITE,        AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_bpr0_el1",    CPENC (3,0,12,8,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_bpr1_el1",    CPENC (3,0,12,12,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_ctlr_el1",    CPENC (3,0,12,12,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_ctlr_el3",    CPENC (3,6,12,12,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_dir_el1",    CPENC (3,0,12,11,1), >>> F_REG_WRITE,        AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_eoir0_el1",    CPENC (3,0,12,8,1), >>> F_REG_WRITE,        AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_eoir1_el1",    CPENC (3,0,12,12,1), >>> F_REG_WRITE,        AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_hppir0_el1",    CPENC (3,0,12,8,2), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_hppir1_el1",    CPENC (3,0,12,12,2), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_iar0_el1",    CPENC (3,0,12,8,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_iar1_el1",    CPENC (3,0,12,12,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_igrpen0_el1",    CPENC (3,0,12,12,6), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_igrpen1_el1",    CPENC (3,0,12,12,7), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_igrpen1_el3",    CPENC (3,6,12,12,7), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_nmiar1_el1",    CPENC (3,0,12,9,5), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (V8_8A)) >>> +  SYSREG ("icc_pmr_el1",    CPENC (3,0,4,6,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_rpr_el1",    CPENC (3,0,12,11,3), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_sgi0r_el1",    CPENC (3,0,12,11,7), >>> F_REG_WRITE,        AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_sgi1r_el1",    CPENC (3,0,12,11,5), >>> F_REG_WRITE,        AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_sre_el1",    CPENC (3,0,12,12,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_sre_el2",    CPENC (3,4,12,9,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("icc_sre_el3",    CPENC (3,6,12,12,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_ap0r0_el2",    CPENC (3,4,12,8,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_ap0r1_el2",    CPENC (3,4,12,8,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_ap0r2_el2",    CPENC (3,4,12,8,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_ap0r3_el2",    CPENC (3,4,12,8,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_ap1r0_el2",    CPENC (3,4,12,9,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_ap1r1_el2",    CPENC (3,4,12,9,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_ap1r2_el2",    CPENC (3,4,12,9,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_ap1r3_el2",    CPENC (3,4,12,9,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_eisr_el2",    CPENC (3,4,12,11,3), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_elrsr_el2",    CPENC (3,4,12,11,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_hcr_el2",    CPENC (3,4,12,11,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_lr0_el2",    CPENC (3,4,12,12,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_lr10_el2",    CPENC (3,4,12,13,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_lr11_el2",    CPENC (3,4,12,13,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_lr12_el2",    CPENC (3,4,12,13,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_lr13_el2",    CPENC (3,4,12,13,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_lr14_el2",    CPENC (3,4,12,13,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_lr15_el2",    CPENC (3,4,12,13,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_lr1_el2",    CPENC (3,4,12,12,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_lr2_el2",    CPENC (3,4,12,12,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_lr3_el2",    CPENC (3,4,12,12,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_lr4_el2",    CPENC (3,4,12,12,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_lr5_el2",    CPENC (3,4,12,12,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_lr6_el2",    CPENC (3,4,12,12,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_lr7_el2",    CPENC (3,4,12,12,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_lr8_el2",    CPENC (3,4,12,13,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_lr9_el2",    CPENC (3,4,12,13,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_misr_el2",    CPENC (3,4,12,11,2), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_vmcr_el2",    CPENC (3,4,12,11,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ich_vtr_el2",    CPENC (3,4,12,11,1), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_aa64afr0_el1",    CPENC (3,0,0,5,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_aa64afr1_el1",    CPENC (3,0,0,5,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_aa64dfr0_el1",    CPENC (3,0,0,5,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_aa64dfr1_el1",    CPENC (3,0,0,5,1), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_aa64isar0_el1",    CPENC (3,0,0,6,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_aa64isar1_el1",    CPENC (3,0,0,6,1), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_aa64isar2_el1",    CPENC (3,0,0,6,2), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_aa64mmfr0_el1",    CPENC (3,0,0,7,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_aa64mmfr1_el1",    CPENC (3,0,0,7,1), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_aa64mmfr2_el1",    CPENC (3,0,0,7,2), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_aa64pfr0_el1",    CPENC (3,0,0,4,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_aa64pfr1_el1",    CPENC (3,0,0,4,1), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_aa64smfr0_el1",    CPENC (3,0,0,4,5), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (SME)) >>> +  SYSREG ("id_aa64zfr0_el1",    CPENC (3,0,0,4,4), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (SVE)) >>> +  SYSREG ("id_afr0_el1",    CPENC (3,0,0,1,3),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("id_dfr0_el1",    CPENC (3,0,0,1,2),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("id_dfr1_el1",    CPENC (3,0,0,3,5),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("id_isar0_el1",    CPENC (3,0,0,2,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_isar1_el1",    CPENC (3,0,0,2,1), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_isar2_el1",    CPENC (3,0,0,2,2), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_isar3_el1",    CPENC (3,0,0,2,3), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_isar4_el1",    CPENC (3,0,0,2,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_isar5_el1",    CPENC (3,0,0,2,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_isar6_el1",    CPENC (3,0,0,2,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_mmfr0_el1",    CPENC (3,0,0,1,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_mmfr1_el1",    CPENC (3,0,0,1,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_mmfr2_el1",    CPENC (3,0,0,1,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_mmfr3_el1",    CPENC (3,0,0,1,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_mmfr4_el1",    CPENC (3,0,0,2,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_mmfr5_el1",    CPENC (3,0,0,3,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("id_pfr0_el1",    CPENC (3,0,0,1,0),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("id_pfr1_el1",    CPENC (3,0,0,1,1),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("id_pfr2_el1",    CPENC (3,0,0,3,4), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (ID_PFR2)) >>> +  SYSREG ("ifsr32_el2",        CPENC (3,4,5,0,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("isr_el1",        CPENC (3,0,12,1,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("lorc_el1",        CPENC (3,0,10,4,3), >>> F_ARCHEXT,        AARCH64_FEATURE (LOR)) >>> +  SYSREG ("lorea_el1",        CPENC (3,0,10,4,1), >>> F_ARCHEXT,        AARCH64_FEATURE (LOR)) >>> +  SYSREG ("lorid_el1",        CPENC (3,0,10,4,7), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (LOR)) >>> +  SYSREG ("lorn_el1",        CPENC (3,0,10,4,2), >>> F_ARCHEXT,        AARCH64_FEATURE (LOR)) >>> +  SYSREG ("lorsa_el1",        CPENC (3,0,10,4,0), >>> F_ARCHEXT,        AARCH64_FEATURE (LOR)) >>> +  SYSREG ("mair_el1",        CPENC (3,0,10,2,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mair_el12",        CPENC (3,5,10,2,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("mair_el2",        CPENC (3,4,10,2,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mair_el3",        CPENC (3,6,10,2,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mdccint_el1",    CPENC (2,0,0,2,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mdccsr_el0",        CPENC (2,3,0,1,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("mdcr_el2",        CPENC (3,4,1,1,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mdcr_el3",        CPENC (3,6,1,3,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mdrar_el1",        CPENC (2,0,1,0,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("mdscr_el1",        CPENC (2,0,0,2,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mecid_a0_el2",    CPENC (3,4,10,8,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mecid_a1_el2",    CPENC (3,4,10,8,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mecid_p0_el2",    CPENC (3,4,10,8,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mecid_p1_el2",    CPENC (3,4,10,8,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mecid_rl_a_el3",    CPENC (3,6,10,10,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mecidr_el2",        CPENC (3,4,10,8,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("mfar_el3",        CPENC (3,6,6,0,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("midr_el1",        CPENC (3,0,0,0,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("mpam0_el1",        CPENC (3,0,10,5,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mpam1_el1",        CPENC (3,0,10,5,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mpam1_el12",        CPENC (3,5,10,5,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mpam2_el2",        CPENC (3,4,10,5,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mpam3_el3",        CPENC (3,6,10,5,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mpamhcr_el2",    CPENC (3,4,10,4,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mpamidr_el1",    CPENC (3,0,10,4,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("mpamsm_el1",        CPENC (3,0,10,5,3), >>> F_ARCHEXT,        AARCH64_FEATURE (SME)) >>> +  SYSREG ("mpamvpm0_el2",    CPENC (3,4,10,6,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mpamvpm1_el2",    CPENC (3,4,10,6,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mpamvpm2_el2",    CPENC (3,4,10,6,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mpamvpm3_el2",    CPENC (3,4,10,6,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mpamvpm4_el2",    CPENC (3,4,10,6,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mpamvpm5_el2",    CPENC (3,4,10,6,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mpamvpm6_el2",    CPENC (3,4,10,6,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mpamvpm7_el2",    CPENC (3,4,10,6,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mpamvpmv_el2",    CPENC (3,4,10,4,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("mpidr_el1",        CPENC (3,0,0,0,5), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("mpuir_el1",        CPENC (3,0,0,0,4), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (V8R)) >>> +  SYSREG ("mpuir_el2",        CPENC (3,4,0,0,4), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (V8R)) >>> +  SYSREG ("mvfr0_el1",        CPENC (3,0,0,3,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("mvfr1_el1",        CPENC (3,0,0,3,1), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("mvfr2_el1",        CPENC (3,0,0,3,2), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("nzcv",        CPENC (3,3,4,2,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("osdlr_el1",        CPENC (2,0,1,3,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("osdtrrx_el1",    CPENC (2,0,0,0,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("osdtrtx_el1",    CPENC (2,0,0,3,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("oseccr_el1",        CPENC (2,0,0,6,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("oslar_el1",        CPENC (2,0,1,0,4), >>> F_REG_WRITE,        AARCH64_NO_FEATURES) >>> +  SYSREG ("oslsr_el1",        CPENC (2,0,1,1,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("pan",        CPENC (3,0,4,2,3),    F_ARCHEXT, >>> AARCH64_FEATURE (PAN)) >>> +  SYSREG ("par_el1",        CPENC (3,0,7,4,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmbidr_el1",        CPENC (3,0,9,10,7), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (PROFILE)) >>> +  SYSREG ("pmblimitr_el1",    CPENC (3,0,9,10,0), >>> F_ARCHEXT,        AARCH64_FEATURE (PROFILE)) >>> +  SYSREG ("pmbptr_el1",        CPENC (3,0,9,10,1), >>> F_ARCHEXT,        AARCH64_FEATURE (PROFILE)) >>> +  SYSREG ("pmbsr_el1",        CPENC (3,0,9,10,3), >>> F_ARCHEXT,        AARCH64_FEATURE (PROFILE)) >>> +  SYSREG ("pmccfiltr_el0",    CPENC (3,3,14,15,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmccntr_el0",    CPENC (3,3,9,13,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmceid0_el0",    CPENC (3,3,9,12,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("pmceid1_el0",    CPENC (3,3,9,12,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("pmcntenclr_el0",    CPENC (3,3,9,12,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmcntenset_el0",    CPENC (3,3,9,12,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmcr_el0",        CPENC (3,3,9,12,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr0_el0",    CPENC (3,3,14,8,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr10_el0",    CPENC (3,3,14,9,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr11_el0",    CPENC (3,3,14,9,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr12_el0",    CPENC (3,3,14,9,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr13_el0",    CPENC (3,3,14,9,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr14_el0",    CPENC (3,3,14,9,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr15_el0",    CPENC (3,3,14,9,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr16_el0",    CPENC (3,3,14,10,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr17_el0",    CPENC (3,3,14,10,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr18_el0",    CPENC (3,3,14,10,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr19_el0",    CPENC (3,3,14,10,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr1_el0",    CPENC (3,3,14,8,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr20_el0",    CPENC (3,3,14,10,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr21_el0",    CPENC (3,3,14,10,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr22_el0",    CPENC (3,3,14,10,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr23_el0",    CPENC (3,3,14,10,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr24_el0",    CPENC (3,3,14,11,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr25_el0",    CPENC (3,3,14,11,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr26_el0",    CPENC (3,3,14,11,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr27_el0",    CPENC (3,3,14,11,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr28_el0",    CPENC (3,3,14,11,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr29_el0",    CPENC (3,3,14,11,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr2_el0",    CPENC (3,3,14,8,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr30_el0",    CPENC (3,3,14,11,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr3_el0",    CPENC (3,3,14,8,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr4_el0",    CPENC (3,3,14,8,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr5_el0",    CPENC (3,3,14,8,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr6_el0",    CPENC (3,3,14,8,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr7_el0",    CPENC (3,3,14,8,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr8_el0",    CPENC (3,3,14,9,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevcntr9_el0",    CPENC (3,3,14,9,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper0_el0",    CPENC (3,3,14,12,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper10_el0",    CPENC (3,3,14,13,2), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper11_el0",    CPENC (3,3,14,13,3), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper12_el0",    CPENC (3,3,14,13,4), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper13_el0",    CPENC (3,3,14,13,5), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper14_el0",    CPENC (3,3,14,13,6), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper15_el0",    CPENC (3,3,14,13,7), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper16_el0",    CPENC (3,3,14,14,0), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper17_el0",    CPENC (3,3,14,14,1), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper18_el0",    CPENC (3,3,14,14,2), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper19_el0",    CPENC (3,3,14,14,3), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper1_el0",    CPENC (3,3,14,12,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper20_el0",    CPENC (3,3,14,14,4), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper21_el0",    CPENC (3,3,14,14,5), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper22_el0",    CPENC (3,3,14,14,6), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper23_el0",    CPENC (3,3,14,14,7), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper24_el0",    CPENC (3,3,14,15,0), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper25_el0",    CPENC (3,3,14,15,1), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper26_el0",    CPENC (3,3,14,15,2), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper27_el0",    CPENC (3,3,14,15,3), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper28_el0",    CPENC (3,3,14,15,4), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper29_el0",    CPENC (3,3,14,15,5), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper2_el0",    CPENC (3,3,14,12,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper30_el0",    CPENC (3,3,14,15,6), >>> 0,            AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper3_el0",    CPENC (3,3,14,12,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper4_el0",    CPENC (3,3,14,12,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper5_el0",    CPENC (3,3,14,12,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper6_el0",    CPENC (3,3,14,12,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper7_el0",    CPENC (3,3,14,12,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper8_el0",    CPENC (3,3,14,13,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmevtyper9_el0",    CPENC (3,3,14,13,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmintenclr_el1",    CPENC (3,0,9,14,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmintenset_el1",    CPENC (3,0,9,14,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmmir_el1",        CPENC (3,0,9,14,6), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("pmovsclr_el0",    CPENC (3,3,9,12,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmovsset_el0",    CPENC (3,3,9,14,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmscr_el1",        CPENC (3,0,9,9,0), >>> F_ARCHEXT,        AARCH64_FEATURE (PROFILE)) >>> +  SYSREG ("pmscr_el12",        CPENC (3,5,9,9,0), >>> F_ARCHEXT,        AARCH64_FEATURE (PROFILE)) >>> +  SYSREG ("pmscr_el2",        CPENC (3,4,9,9,0), >>> F_ARCHEXT,        AARCH64_FEATURE (PROFILE)) >>> +  SYSREG ("pmselr_el0",        CPENC (3,3,9,12,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmsevfr_el1",    CPENC (3,0,9,9,5),    F_ARCHEXT, >>> AARCH64_FEATURE (PROFILE)) >>> +  SYSREG ("pmsfcr_el1",        CPENC (3,0,9,9,4), >>> F_ARCHEXT,        AARCH64_FEATURE (PROFILE)) >>> +  SYSREG ("pmsicr_el1",        CPENC (3,0,9,9,2), >>> F_ARCHEXT,        AARCH64_FEATURE (PROFILE)) >>> +  SYSREG ("pmsidr_el1",        CPENC (3,0,9,9,7), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (PROFILE)) >>> +  SYSREG ("pmsirr_el1",        CPENC (3,0,9,9,3), >>> F_ARCHEXT,        AARCH64_FEATURE (PROFILE)) >>> +  SYSREG ("pmslatfr_el1",    CPENC (3,0,9,9,6),    F_ARCHEXT, >>> AARCH64_FEATURE (PROFILE)) >>> +  SYSREG ("pmsnevfr_el1",    CPENC (3,0,9,9,1),    F_ARCHEXT, >>> AARCH64_FEATURE (V8_7A)) >>> +  SYSREG ("pmswinc_el0",    CPENC (3,3,9,12,4), >>> F_REG_WRITE,        AARCH64_NO_FEATURES) >>> +  SYSREG ("pmuserenr_el0",    CPENC (3,3,9,14,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmxevcntr_el0",    CPENC (3,3,9,13,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("pmxevtyper_el0",    CPENC (3,3,9,13,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("prbar10_el1",    CPENC (3,0,6,13,0),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar10_el2",    CPENC (3,4,6,13,0),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar11_el1",    CPENC (3,0,6,13,4),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar11_el2",    CPENC (3,4,6,13,4),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar12_el1",    CPENC (3,0,6,14,0),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar12_el2",    CPENC (3,4,6,14,0),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar13_el1",    CPENC (3,0,6,14,4),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar13_el2",    CPENC (3,4,6,14,4),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar14_el1",    CPENC (3,0,6,15,0),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar14_el2",    CPENC (3,4,6,15,0),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar15_el1",    CPENC (3,0,6,15,4),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar15_el2",    CPENC (3,4,6,15,4),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar1_el1",        CPENC (3,0,6,8,4), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar1_el2",        CPENC (3,4,6,8,4), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar2_el1",        CPENC (3,0,6,9,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar2_el2",        CPENC (3,4,6,9,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar3_el1",        CPENC (3,0,6,9,4), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar3_el2",        CPENC (3,4,6,9,4), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar4_el1",        CPENC (3,0,6,10,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar4_el2",        CPENC (3,4,6,10,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar5_el1",        CPENC (3,0,6,10,4), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar5_el2",        CPENC (3,4,6,10,4), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar6_el1",        CPENC (3,0,6,11,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar6_el2",        CPENC (3,4,6,11,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar7_el1",        CPENC (3,0,6,11,4), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar7_el2",        CPENC (3,4,6,11,4), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar8_el1",        CPENC (3,0,6,12,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar8_el2",        CPENC (3,4,6,12,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar9_el1",        CPENC (3,0,6,12,4), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar9_el2",        CPENC (3,4,6,12,4), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar_el1",        CPENC (3,0,6,8,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prbar_el2",        CPENC (3,4,6,8,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prenr_el1",        CPENC (3,0,6,1,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prenr_el2",        CPENC (3,4,6,1,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar10_el1",    CPENC (3,0,6,13,1),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar10_el2",    CPENC (3,4,6,13,1),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar11_el1",    CPENC (3,0,6,13,5),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar11_el2",    CPENC (3,4,6,13,5),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar12_el1",    CPENC (3,0,6,14,1),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar12_el2",    CPENC (3,4,6,14,1),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar13_el1",    CPENC (3,0,6,14,5),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar13_el2",    CPENC (3,4,6,14,5),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar14_el1",    CPENC (3,0,6,15,1),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar14_el2",    CPENC (3,4,6,15,1),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar15_el1",    CPENC (3,0,6,15,5),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar15_el2",    CPENC (3,4,6,15,5),    F_ARCHEXT, >>> AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar1_el1",        CPENC (3,0,6,8,5), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar1_el2",        CPENC (3,4,6,8,5), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar2_el1",        CPENC (3,0,6,9,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar2_el2",        CPENC (3,4,6,9,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar3_el1",        CPENC (3,0,6,9,5), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar3_el2",        CPENC (3,4,6,9,5), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar4_el1",        CPENC (3,0,6,10,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar4_el2",        CPENC (3,4,6,10,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar5_el1",        CPENC (3,0,6,10,5), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar5_el2",        CPENC (3,4,6,10,5), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar6_el1",        CPENC (3,0,6,11,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar6_el2",        CPENC (3,4,6,11,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar7_el1",        CPENC (3,0,6,11,5), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar7_el2",        CPENC (3,4,6,11,5), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar8_el1",        CPENC (3,0,6,12,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar8_el2",        CPENC (3,4,6,12,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar9_el1",        CPENC (3,0,6,12,5), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar9_el2",        CPENC (3,4,6,12,5), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar_el1",        CPENC (3,0,6,8,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prlar_el2",        CPENC (3,4,6,8,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prselr_el1",        CPENC (3,0,6,2,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("prselr_el2",        CPENC (3,4,6,2,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("revidr_el1",        CPENC (3,0,0,0,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("rgsr_el1",        CPENC (3,0,1,0,5),    F_ARCHEXT, >>> AARCH64_FEATURE (MEMTAG)) >>> +  SYSREG ("rmr_el1",        CPENC (3,0,12,0,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("rmr_el2",        CPENC (3,4,12,0,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("rmr_el3",        CPENC (3,6,12,0,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("rndr",        CPENC (3,3,2,4,0), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (RNG)) >>> +  SYSREG ("rndrrs",        CPENC (3,3,2,4,1), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (RNG)) >>> +  SYSREG ("rvbar_el1",        CPENC (3,0,12,0,1), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("rvbar_el2",        CPENC (3,4,12,0,1), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("rvbar_el3",        CPENC (3,6,12,0,1), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("scr_el3",        CPENC (3,6,1,1,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("sctlr_el1",        CPENC (3,0,1,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("sctlr_el12",        CPENC (3,5,1,0,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("sctlr_el2",        CPENC (3,4,1,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("sctlr_el3",        CPENC (3,6,1,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("scxtnum_el0",    CPENC (3,3,13,0,7),    F_ARCHEXT, >>> AARCH64_FEATURE (SCXTNUM)) >>> +  SYSREG ("scxtnum_el1",    CPENC (3,0,13,0,7),    F_ARCHEXT, >>> AARCH64_FEATURE (SCXTNUM)) >>> +  SYSREG ("scxtnum_el12",    CPENC (3,5,13,0,7), >>> F_ARCHEXT,        AARCH64_FEATURE (SCXTNUM)) >>> +  SYSREG ("scxtnum_el2",    CPENC (3,4,13,0,7),    F_ARCHEXT, >>> AARCH64_FEATURE (SCXTNUM)) >>> +  SYSREG ("scxtnum_el3",    CPENC (3,6,13,0,7),    F_ARCHEXT, >>> AARCH64_FEATURE (SCXTNUM)) >>> +  SYSREG ("sder32_el2",        CPENC (3,4,1,3,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("sder32_el3",        CPENC (3,6,1,1,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("smcr_el1",        CPENC (3,0,1,2,6),    F_ARCHEXT, >>> AARCH64_FEATURE (SME)) >>> +  SYSREG ("smcr_el12",        CPENC (3,5,1,2,6), >>> F_ARCHEXT,        AARCH64_FEATURE (SME)) >>> +  SYSREG ("smcr_el2",        CPENC (3,4,1,2,6),    F_ARCHEXT, >>> AARCH64_FEATURE (SME)) >>> +  SYSREG ("smcr_el3",        CPENC (3,6,1,2,6),    F_ARCHEXT, >>> AARCH64_FEATURE (SME)) >>> +  SYSREG ("smidr_el1",        CPENC (3,1,0,0,6), >>> F_REG_READ|F_ARCHEXT,    AARCH64_FEATURE (SME)) >>> +  SYSREG ("smpri_el1",        CPENC (3,0,1,2,4), >>> F_ARCHEXT,        AARCH64_FEATURE (SME)) >>> +  SYSREG ("smprimap_el2",    CPENC (3,4,1,2,5),    F_ARCHEXT, >>> AARCH64_FEATURE (SME)) >>> +  SYSREG ("sp_el0",        CPENC (3,0,4,1,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("sp_el1",        CPENC (3,4,4,1,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("sp_el2",        CPENC (3,6,4,1,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("spsel",        CPENC (3,0,4,2,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("spsr_abt",        CPENC (3,4,4,3,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("spsr_el1",        CPENC (3,0,4,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("spsr_el12",        CPENC (3,5,4,0,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("spsr_el2",        CPENC (3,4,4,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("spsr_el3",        CPENC (3,6,4,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("spsr_fiq",        CPENC (3,4,4,3,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("spsr_hyp",        CPENC (3,4,4,0,0), >>> F_DEPRECATED,        AARCH64_NO_FEATURES) >>> +  SYSREG ("spsr_irq",        CPENC (3,4,4,3,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("spsr_svc",        CPENC (3,0,4,0,0), >>> F_DEPRECATED,        AARCH64_NO_FEATURES) >>> +  SYSREG ("spsr_und",        CPENC (3,4,4,3,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ssbs",        CPENC (3,3,4,2,6),    F_ARCHEXT, >>> AARCH64_FEATURE (SSBS)) >>> +  SYSREG ("svcr",        CPENC (3,3,4,2,2),    F_ARCHEXT, >>> AARCH64_FEATURE (SME)) >>> +  SYSREG ("tco",        CPENC (3,3,4,2,7),    F_ARCHEXT, >>> AARCH64_FEATURE (MEMTAG)) >>> +  SYSREG ("tcr_el1",        CPENC (3,0,2,0,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("tcr_el12",        CPENC (3,5,2,0,2),    F_ARCHEXT, >>> AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("tcr_el2",        CPENC (3,4,2,0,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("tcr_el3",        CPENC (3,6,2,0,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("teecr32_el1",    CPENC (2,2,0,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("teehbr32_el1",    CPENC (2,2,1,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("tfsr_el1",        CPENC (3,0,5,6,0),    F_ARCHEXT, >>> AARCH64_FEATURE (MEMTAG)) >>> +  SYSREG ("tfsr_el12",        CPENC (3,5,5,6,0), >>> F_ARCHEXT,        AARCH64_FEATURE (MEMTAG)) >>> +  SYSREG ("tfsr_el2",        CPENC (3,4,5,6,0),    F_ARCHEXT, >>> AARCH64_FEATURE (MEMTAG)) >>> +  SYSREG ("tfsr_el3",        CPENC (3,6,5,6,0),    F_ARCHEXT, >>> AARCH64_FEATURE (MEMTAG)) >>> +  SYSREG ("tfsre0_el1",        CPENC (3,0,5,6,1), >>> F_ARCHEXT,        AARCH64_FEATURE (MEMTAG)) >>> +  SYSREG ("tpidr2_el0",        CPENC (3,3,13,0,5), >>> F_ARCHEXT,        AARCH64_FEATURE (SME)) >>> +  SYSREG ("tpidr_el0",        CPENC (3,3,13,0,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("tpidr_el1",        CPENC (3,0,13,0,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("tpidr_el2",        CPENC (3,4,13,0,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("tpidr_el3",        CPENC (3,6,13,0,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("tpidrro_el0",    CPENC (3,3,13,0,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trbbaser_el1",    CPENC (3,0,9,11,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trbidr_el1",        CPENC (3,0,9,11,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trblimitr_el1",    CPENC (3,0,9,11,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trbmar_el1",        CPENC (3,0,9,11,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trbptr_el1",        CPENC (3,0,9,11,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trbsr_el1",        CPENC (3,0,9,11,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trbtrg_el1",        CPENC (3,0,9,11,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacatr0",        CPENC (2,1,2,0,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacatr1",        CPENC (2,1,2,2,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacatr10",        CPENC (2,1,2,4,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacatr11",        CPENC (2,1,2,6,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacatr12",        CPENC (2,1,2,8,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacatr13",        CPENC (2,1,2,10,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacatr14",        CPENC (2,1,2,12,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacatr15",        CPENC (2,1,2,14,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacatr2",        CPENC (2,1,2,4,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacatr3",        CPENC (2,1,2,6,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacatr4",        CPENC (2,1,2,8,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacatr5",        CPENC (2,1,2,10,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacatr6",        CPENC (2,1,2,12,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacatr7",        CPENC (2,1,2,14,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacatr8",        CPENC (2,1,2,0,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacatr9",        CPENC (2,1,2,2,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacvr0",        CPENC (2,1,2,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacvr1",        CPENC (2,1,2,2,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacvr10",        CPENC (2,1,2,4,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacvr11",        CPENC (2,1,2,6,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacvr12",        CPENC (2,1,2,8,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacvr13",        CPENC (2,1,2,10,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacvr14",        CPENC (2,1,2,12,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacvr15",        CPENC (2,1,2,14,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacvr2",        CPENC (2,1,2,4,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacvr3",        CPENC (2,1,2,6,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacvr4",        CPENC (2,1,2,8,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacvr5",        CPENC (2,1,2,10,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacvr6",        CPENC (2,1,2,12,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacvr7",        CPENC (2,1,2,14,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacvr8",        CPENC (2,1,2,0,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcacvr9",        CPENC (2,1,2,2,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcauthstatus",    CPENC (2,1,7,14,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcauxctlr",        CPENC (2,1,0,6,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcbbctlr",        CPENC (2,1,0,15,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcccctlr",        CPENC (2,1,0,14,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccidcctlr0",    CPENC (2,1,3,0,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccidcctlr1",    CPENC (2,1,3,1,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccidcvr0",        CPENC (2,1,3,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccidcvr1",        CPENC (2,1,3,2,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccidcvr2",        CPENC (2,1,3,4,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccidcvr3",        CPENC (2,1,3,6,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccidcvr4",        CPENC (2,1,3,8,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccidcvr5",        CPENC (2,1,3,10,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccidcvr6",        CPENC (2,1,3,12,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccidcvr7",        CPENC (2,1,3,14,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccidr0",        CPENC (2,1,7,12,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trccidr1",        CPENC (2,1,7,13,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trccidr2",        CPENC (2,1,7,14,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trccidr3",        CPENC (2,1,7,15,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcclaimclr",    CPENC (2,1,7,9,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcclaimset",    CPENC (2,1,7,8,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccntctlr0",    CPENC (2,1,0,4,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccntctlr1",    CPENC (2,1,0,5,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccntctlr2",    CPENC (2,1,0,6,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccntctlr3",    CPENC (2,1,0,7,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccntrldvr0",    CPENC (2,1,0,0,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccntrldvr1",    CPENC (2,1,0,1,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccntrldvr2",    CPENC (2,1,0,2,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccntrldvr3",    CPENC (2,1,0,3,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccntvr0",        CPENC (2,1,0,8,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccntvr1",        CPENC (2,1,0,9,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccntvr2",        CPENC (2,1,0,10,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trccntvr3",        CPENC (2,1,0,11,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcconfigr",        CPENC (2,1,0,4,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdevaff0",        CPENC (2,1,7,10,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdevaff1",        CPENC (2,1,7,11,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdevarch",        CPENC (2,1,7,15,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdevid",        CPENC (2,1,7,2,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdevtype",        CPENC (2,1,7,3,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdvcmr0",        CPENC (2,1,2,0,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdvcmr1",        CPENC (2,1,2,4,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdvcmr2",        CPENC (2,1,2,8,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdvcmr3",        CPENC (2,1,2,12,6),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdvcmr4",        CPENC (2,1,2,0,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdvcmr5",        CPENC (2,1,2,4,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdvcmr6",        CPENC (2,1,2,8,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdvcmr7",        CPENC (2,1,2,12,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdvcvr0",        CPENC (2,1,2,0,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdvcvr1",        CPENC (2,1,2,4,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdvcvr2",        CPENC (2,1,2,8,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdvcvr3",        CPENC (2,1,2,12,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdvcvr4",        CPENC (2,1,2,0,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdvcvr5",        CPENC (2,1,2,4,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdvcvr6",        CPENC (2,1,2,8,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcdvcvr7",        CPENC (2,1,2,12,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trceventctl0r",    CPENC (2,1,0,8,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trceventctl1r",    CPENC (2,1,0,9,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcextinselr",    CPENC (2,1,0,8,4), >>> F_REG_ALIAS,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcextinselr0",    CPENC (2,1,0,8,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcextinselr1",    CPENC (2,1,0,9,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcextinselr2",    CPENC (2,1,0,10,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcextinselr3",    CPENC (2,1,0,11,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcidr0",        CPENC (2,1,0,8,7),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcidr1",        CPENC (2,1,0,9,7),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcidr10",        CPENC (2,1,0,2,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcidr11",        CPENC (2,1,0,3,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcidr12",        CPENC (2,1,0,4,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcidr13",        CPENC (2,1,0,5,6), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcidr2",        CPENC (2,1,0,10,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcidr3",        CPENC (2,1,0,11,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcidr4",        CPENC (2,1,0,12,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcidr5",        CPENC (2,1,0,13,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcidr6",        CPENC (2,1,0,14,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcidr7",        CPENC (2,1,0,15,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcidr8",        CPENC (2,1,0,0,6),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcidr9",        CPENC (2,1,0,1,6),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcimspec0",        CPENC (2,1,0,0,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcimspec1",        CPENC (2,1,0,1,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcimspec2",        CPENC (2,1,0,2,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcimspec3",        CPENC (2,1,0,3,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcimspec4",        CPENC (2,1,0,4,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcimspec5",        CPENC (2,1,0,5,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcimspec6",        CPENC (2,1,0,6,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcimspec7",        CPENC (2,1,0,7,7),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcitctrl",        CPENC (2,1,7,0,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trclar",        CPENC (2,1,7,12,6), >>> F_REG_WRITE,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trclsr",        CPENC (2,1,7,13,6),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcoslar",        CPENC (2,1,1,0,4), >>> F_REG_WRITE,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcoslsr",        CPENC (2,1,1,1,4), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcpdcr",        CPENC (2,1,1,4,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcpdsr",        CPENC (2,1,1,5,4),    F_REG_READ, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcpidr0",        CPENC (2,1,7,8,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcpidr1",        CPENC (2,1,7,9,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcpidr2",        CPENC (2,1,7,10,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcpidr3",        CPENC (2,1,7,11,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcpidr4",        CPENC (2,1,7,4,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcpidr5",        CPENC (2,1,7,5,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcpidr6",        CPENC (2,1,7,6,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcpidr7",        CPENC (2,1,7,7,7), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcprgctlr",        CPENC (2,1,0,1,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcprocselr",    CPENC (2,1,0,2,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcqctlr",        CPENC (2,1,0,1,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr10",    CPENC (2,1,1,10,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr11",    CPENC (2,1,1,11,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr12",    CPENC (2,1,1,12,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr13",    CPENC (2,1,1,13,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr14",    CPENC (2,1,1,14,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr15",    CPENC (2,1,1,15,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr16",    CPENC (2,1,1,0,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr17",    CPENC (2,1,1,1,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr18",    CPENC (2,1,1,2,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr19",    CPENC (2,1,1,3,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr2",        CPENC (2,1,1,2,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr20",    CPENC (2,1,1,4,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr21",    CPENC (2,1,1,5,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr22",    CPENC (2,1,1,6,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr23",    CPENC (2,1,1,7,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr24",    CPENC (2,1,1,8,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr25",    CPENC (2,1,1,9,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr26",    CPENC (2,1,1,10,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr27",    CPENC (2,1,1,11,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr28",    CPENC (2,1,1,12,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr29",    CPENC (2,1,1,13,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr3",        CPENC (2,1,1,3,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr30",    CPENC (2,1,1,14,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr31",    CPENC (2,1,1,15,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr4",        CPENC (2,1,1,4,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr5",        CPENC (2,1,1,5,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr6",        CPENC (2,1,1,6,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr7",        CPENC (2,1,1,7,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr8",        CPENC (2,1,1,8,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsctlr9",        CPENC (2,1,1,9,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcrsr",        CPENC (2,1,0,10,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcseqevr0",        CPENC (2,1,0,0,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcseqevr1",        CPENC (2,1,0,1,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcseqevr2",        CPENC (2,1,0,2,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcseqrstevr",    CPENC (2,1,0,6,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcseqstr",        CPENC (2,1,0,7,4),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcssccr0",        CPENC (2,1,1,0,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcssccr1",        CPENC (2,1,1,1,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcssccr2",        CPENC (2,1,1,2,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcssccr3",        CPENC (2,1,1,3,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcssccr4",        CPENC (2,1,1,4,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcssccr5",        CPENC (2,1,1,5,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcssccr6",        CPENC (2,1,1,6,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcssccr7",        CPENC (2,1,1,7,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcsscsr0",        CPENC (2,1,1,8,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcsscsr1",        CPENC (2,1,1,9,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcsscsr2",        CPENC (2,1,1,10,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcsscsr3",        CPENC (2,1,1,11,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcsscsr4",        CPENC (2,1,1,12,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcsscsr5",        CPENC (2,1,1,13,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcsscsr6",        CPENC (2,1,1,14,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcsscsr7",        CPENC (2,1,1,15,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcsspcicr0",    CPENC (2,1,1,0,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcsspcicr1",    CPENC (2,1,1,1,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcsspcicr2",    CPENC (2,1,1,2,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcsspcicr3",    CPENC (2,1,1,3,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcsspcicr4",    CPENC (2,1,1,4,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcsspcicr5",    CPENC (2,1,1,5,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcsspcicr6",    CPENC (2,1,1,6,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcsspcicr7",    CPENC (2,1,1,7,3),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcstallctlr",    CPENC (2,1,0,11,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcstatr",        CPENC (2,1,0,3,0), >>> F_REG_READ,        AARCH64_NO_FEATURES) >>> +  SYSREG ("trcsyncpr",        CPENC (2,1,0,13,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trctraceidr",    CPENC (2,1,0,0,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trctsctlr",        CPENC (2,1,0,12,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcvdarcctlr",    CPENC (2,1,0,10,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcvdctlr",        CPENC (2,1,0,8,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcvdsacctlr",    CPENC (2,1,0,9,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcvictlr",        CPENC (2,1,0,0,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcviiectlr",    CPENC (2,1,0,1,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcvipcssctlr",    CPENC (2,1,0,3,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcvissctlr",    CPENC (2,1,0,2,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcvmidcctlr0",    CPENC (2,1,3,2,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcvmidcctlr1",    CPENC (2,1,3,3,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcvmidcvr0",    CPENC (2,1,3,0,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcvmidcvr1",    CPENC (2,1,3,2,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcvmidcvr2",    CPENC (2,1,3,4,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcvmidcvr3",    CPENC (2,1,3,6,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcvmidcvr4",    CPENC (2,1,3,8,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcvmidcvr5",    CPENC (2,1,3,10,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcvmidcvr6",    CPENC (2,1,3,12,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trcvmidcvr7",    CPENC (2,1,3,14,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("trfcr_el1",        CPENC (3,0,1,2,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("trfcr_el12",        CPENC (3,5,1,2,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("trfcr_el2",        CPENC (3,4,1,2,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("ttbr0_el1",        CPENC (3,0,2,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ttbr0_el12",        CPENC (3,5,2,0,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("ttbr0_el2",        CPENC (3,4,2,0,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8A)) >>> +  SYSREG ("ttbr0_el3",        CPENC (3,6,2,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ttbr1_el1",        CPENC (3,0,2,0,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("ttbr1_el12",        CPENC (3,5,2,0,1), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("ttbr1_el2",        CPENC (3,4,2,0,1), >>> F_ARCHEXT,        AARCH64_FEATURES (2, V8A, V8_1A)) >>> +  SYSREG ("uao",        CPENC (3,0,4,2,4),    F_ARCHEXT, >>> AARCH64_FEATURE (V8_2A)) >>> +  SYSREG ("vbar_el1",        CPENC (3,0,12,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("vbar_el12",        CPENC (3,5,12,0,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_1A)) >>> +  SYSREG ("vbar_el2",        CPENC (3,4,12,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("vbar_el3",        CPENC (3,6,12,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("vdisr_el2",        CPENC (3,4,12,1,1), >>> F_ARCHEXT,        AARCH64_FEATURE (RAS)) >>> +  SYSREG ("vmecid_a_el2",    CPENC (3,4,10,9,1),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("vmecid_p_el2",    CPENC (3,4,10,9,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("vmpidr_el2",        CPENC (3,4,0,0,5),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("vncr_el2",        CPENC (3,4,2,2,0),    F_ARCHEXT, >>> AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("vpidr_el2",        CPENC (3,4,0,0,0),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("vsctlr_el2",        CPENC (3,4,2,0,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8R)) >>> +  SYSREG ("vsesr_el2",        CPENC (3,4,5,2,3), >>> F_ARCHEXT,        AARCH64_FEATURE (RAS)) >>> +  SYSREG ("vstcr_el2",        CPENC (3,4,2,6,2), >>> F_ARCHEXT,        AARCH64_FEATURE (V8_4A)) >>> +  SYSREG ("vsttbr_el2",        CPENC (3,4,2,6,0), >>> F_ARCHEXT,        AARCH64_FEATURES (2, V8A, V8_4A)) >>> +  SYSREG ("vtcr_el2",        CPENC (3,4,2,1,2),    0, >>> AARCH64_NO_FEATURES) >>> +  SYSREG ("vttbr_el2",        CPENC (3,4,2,1,0), >>> F_ARCHEXT,        AARCH64_FEATURE (V8A)) >>> +  SYSREG ("zcr_el1",        CPENC (3,0,1,2,0),    F_ARCHEXT, >>> AARCH64_FEATURE (SVE)) >>> +  SYSREG ("zcr_el12",        CPENC (3,5,1,2,0),    F_ARCHEXT, >>> AARCH64_FEATURE (SVE)) >>> +  SYSREG ("zcr_el2",        CPENC (3,4,1,2,0),    F_ARCHEXT, >>> AARCH64_FEATURE (SVE)) >>> +  SYSREG ("zcr_el3",        CPENC (3,6,1,2,0),    F_ARCHEXT, >>> AARCH64_FEATURE (SVE)) >>> \ No newline at end of file >>