Linker overlay pages strategy [Q]

Linker overlay pages strategy [Q]

[Timothy Wall]

I'm trying to figure out the best way to handle a processor's dual
address space as it relates to the linker and script files.  Fortunately

I don't have to do compatibility with the other vendor's linker scripts,

but there are a few options I need to include.  First is being able to
specify separate allocations for load-time and run-time addresses of
sections, and second, being able to map into two overlapping addrss
spaces.

Most links for this target (TIC54X) specify memory regions for PROG
(usually ROM) and DATA (maybe on-chip, maybe not), these usually get
designated pages 0 and 1, respectively.

Some sections may be designated to have a different "run time"
allocation, which may be on the same or a different page.  e.g.

MEMORY
{
    PAGE 0: PROG: ORIGIN 0x0000 LENGTH 0xFF00
   PAGE 1: DATA: ORIGIN 0x0080 LENGTH 0xFF80
}

SECTIONS
{
    .text: load = PROG, run = 0x800
    .cinit: load = PROG, run = DATA
}

So what this does is effectively allocate two sections per section.  The

text section is expected to be relocated before running (so all
relocations are done for the "run" address).
Note that the memory "pages" have overlapping address space.

So for the first item, I can link each section in twice.
The overlay functions more or less provide the second item, though I'd
prefer to keep the semantics closer to the above example (which
represents putting sections into two memory areas which happen to have
the same address) rather than using the OVERLAY semantics (which puts
more than one section into the same address).

Any comments, ideas, references?  Please CC twall@tiac.net, as I am not
subscribed to the list.

Thanks
Tim Wall

Re: Linker overlay pages strategy [Q]

[Ian Lance Taylor]

   Date: Thu, 19 Aug 1999 22:37:23 -0400
   From: Timothy Wall <twall@tiac.net>

   I'm trying to figure out the best way to handle a processor's dual
   address space as it relates to the linker and script files.  Fortunately
   I don't have to do compatibility with the other vendor's linker scripts,
   but there are a few options I need to include.  First is being able to
   specify separate allocations for load-time and run-time addresses of
   sections, and second, being able to map into two overlapping addrss
   spaces.

Separate load and run time addresses are normally handled via the AT
modifier in the linker script.

The linker does nothing to stop you from mapping into overlapping
address spaces.

   Some sections may be designated to have a different "run time"
   allocation, which may be on the same or a different page.  e.g.

   MEMORY
   {
       PAGE 0: PROG: ORIGIN 0x0000 LENGTH 0xFF00
      PAGE 1: DATA: ORIGIN 0x0080 LENGTH 0xFF80
   }

   SECTIONS
   {
       .text: load = PROG, run = 0x800
       .cinit: load = PROG, run = DATA
   }

   So what this does is effectively allocate two sections per section.  The
   text section is expected to be relocated before running (so all
   relocations are done for the "run" address).

You just need to use the AT modifier for the .text section.  Do
something like
    .text 0x800 : AT (0) { *(.text) }
or
    .text : AT (0) { *(.text) } > PROG

   Note that the memory "pages" have overlapping address space.

I don't think the linker will care.

Note that you don't have to use MEMORY regions.  If you find them
inconvenient, just specify the addresses directly.  The main advantage
of MEMORY regions is that they cause the linker to warn when you
overflow memory.

Ian