From: Andrew Haley <aph@pasanda.cygnus.co.uk>
To: ian@zembu.com
Cc: gavin@cygnus.com, binutils@sourceware.cygnus.com
Subject: Re: MIPS opcodes patch: change move from andu to or
Date: Mon, 25 Oct 1999 10:39:00 -0000 [thread overview]
Message-ID: <19991025173905.17950.qmail@pasanda.cygnus.co.uk> (raw)
In-Reply-To: <19991025173112.5003.qmail@daffy.airs.com>
> Date: 25 Oct 1999 13:31:12 -0400
> From: Ian Lance Taylor <ian@zembu.com>
>
> Date: Mon, 25 Oct 1999 11:19:28 -0400 (EDT)
> From: Gavin Romig-Koch <gavin@cygnus.com>
>
> OK to commit?
>
> For opcodes:
> * mips-opc.c (move): Use "or" rather than "addu" or "daddu".
>
> We deliberately chose ``addu'' and ``daddu'' rather than ``or''
> because several MIPS chips have two pipelined addition units but only
> one pipelined logical unit. Those chips can move two pairs of
> registers around at once if we use ``addu'', but they can only move
> one pair if we use ``or''.
Aha! That's a *very* good reason. I'll add a comment, if that's OK
with you.
> Is there any reason we should use ``or''? Your comment mentions
> something about ``gcc -mips3 -gp32''; can't we fix gcc?
Yeah. The problem is that -mgp32 is supposed to generate 32-bit code,
but any move insns get converted into "dadd". I don't really think
that this is important, since the insns will have the same effect, but
it looks rather odd.
I suppose that we could change gcc to ouput "or" insns for 32-bit
moves, but that would degrade performance in the case that you
describe.
Andrew.
next prev parent reply other threads:[~1999-10-25 10:39 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
1999-10-25 8:21 Gavin Romig-Koch
1999-10-25 10:31 ` Ian Lance Taylor
1999-10-25 10:39 ` Andrew Haley [this message]
1999-10-25 12:50 ` Gavin Romig-Koch
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