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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id j10-20020a05600c190a00b00418a9961c47sm40323411wmq.47.2024.04.28.23.55.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 28 Apr 2024 23:55:29 -0700 (PDT) Message-ID: <1ba314a7-94e4-4fc9-9598-3581bd48f516@suse.com> Date: Mon, 29 Apr 2024 08:55:31 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1] RISC-V: Add support for Zimop extension Content-Language: en-US To: Xiao Zeng Cc: kito.cheng@gmail.com, palmer@dabbelt.com, nelson@rivosinc.com, zhengyu@eswincomputing.com, binutils@sourceware.org References: <20240425101602.90429-1-zengxiao@eswincomputing.com> From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20240425101602.90429-1-zengxiao@eswincomputing.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3030.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 25.04.2024 12:16, Xiao Zeng wrote: > This implements the Zimop (May-Be-Operations) extension, as of version 1.0. > > See > What about C.MOP.? It's in the spec, but missing from this patch without any word on why that would be the case? Jan > bfd/ChangeLog: > > * elfxx-riscv.c (riscv_multi_subset_supports): Handle zimop > (riscv_multi_subset_supports_ext): Ditto. > > gas/ChangeLog: > > * NEWS: Updated. > * testsuite/gas/riscv/march-help.l: Ditto. > * testsuite/gas/riscv/zimop.d: New test. > * testsuite/gas/riscv/zimop.s: New test. > > include/ChangeLog: > > * opcode/riscv-opc.h (MATCH_MOP_R_0): Define. > (MASK_MOP_R_0): Ditto. > (MATCH_MOP_R_1): Ditto. > (MASK_MOP_R_1): Ditto. > (MATCH_MOP_R_2): Ditto. > (MASK_MOP_R_2): Ditto. > (MATCH_MOP_R_3): Ditto. > (MASK_MOP_R_3): Ditto. > (MATCH_MOP_R_4): Ditto. > (MASK_MOP_R_4): Ditto. > (MATCH_MOP_R_5): Ditto. > (MASK_MOP_R_5): Ditto. > (MATCH_MOP_R_6): Ditto. > (MASK_MOP_R_6): Ditto. > (MATCH_MOP_R_7): Ditto. > (MASK_MOP_R_7): Ditto. > (MATCH_MOP_R_8): Ditto. > (MASK_MOP_R_8): Ditto. > (MATCH_MOP_R_9): Ditto. > (MASK_MOP_R_9): Ditto. > (MATCH_MOP_R_10): Ditto. > (MASK_MOP_R_10): Ditto. > (MATCH_MOP_R_11): Ditto. > (MASK_MOP_R_11): Ditto. > (MATCH_MOP_R_12): Ditto. > (MASK_MOP_R_12): Ditto. > (MATCH_MOP_R_13): Ditto. > (MASK_MOP_R_13): Ditto. > (MATCH_MOP_R_14): Ditto. > (MASK_MOP_R_14): Ditto. > (MATCH_MOP_R_15): Ditto. > (MASK_MOP_R_15): Ditto. > (MATCH_MOP_R_16): Ditto. > (MASK_MOP_R_16): Ditto. > (MATCH_MOP_R_17): Ditto. > (MASK_MOP_R_17): Ditto. > (MATCH_MOP_R_18): Ditto. > (MASK_MOP_R_18): Ditto. > (MATCH_MOP_R_19): Ditto. > (MASK_MOP_R_19): Ditto. > (MATCH_MOP_R_20): Ditto. > (MASK_MOP_R_20): Ditto. > (MATCH_MOP_R_21): Ditto. > (MASK_MOP_R_21): Ditto. > (MATCH_MOP_R_22): Ditto. > (MASK_MOP_R_22): Ditto. > (MATCH_MOP_R_23): Ditto. > (MASK_MOP_R_23): Ditto. > (MATCH_MOP_R_24): Ditto. > (MASK_MOP_R_24): Ditto. > (MATCH_MOP_R_25): Ditto. > (MASK_MOP_R_25): Ditto. > (MATCH_MOP_R_26): Ditto. > (MASK_MOP_R_26): Ditto. > (MATCH_MOP_R_27): Ditto. > (MASK_MOP_R_27): Ditto. > (MATCH_MOP_R_28): Ditto. > (MASK_MOP_R_28): Ditto. > (MATCH_MOP_R_29): Ditto. > (MASK_MOP_R_29): Ditto. > (MATCH_MOP_R_30): Ditto. > (MASK_MOP_R_30): Ditto. > (MATCH_MOP_R_31): Ditto. > (MASK_MOP_R_31): Ditto. > (MATCH_MOP_RR_0): Ditto. > (MASK_MOP_RR_0): Ditto. > (MATCH_MOP_RR_1): Ditto. > (MASK_MOP_RR_1): Ditto. > (MATCH_MOP_RR_2): Ditto. > (MASK_MOP_RR_2): Ditto. > (MATCH_MOP_RR_3): Ditto. > (MASK_MOP_RR_3): Ditto. > (MATCH_MOP_RR_4): Ditto. > (MASK_MOP_RR_4): Ditto. > (MATCH_MOP_RR_5): Ditto. > (MASK_MOP_RR_5): Ditto. > (MATCH_MOP_RR_6): Ditto. > (MASK_MOP_RR_6): Ditto. > (MATCH_MOP_RR_7): Ditto. > (MASK_MOP_RR_7): Ditto. > (DECLARE_INSN): New declarations for zimop. > * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZIMOP. > > opcodes/ChangeLog: > > * riscv-opc.c: Add Zimop instructions. > --- > bfd/elfxx-riscv.c | 5 ++ > gas/NEWS | 2 + > gas/testsuite/gas/riscv/march-help.l | 1 + > gas/testsuite/gas/riscv/zimop.d | 48 +++++++++++ > gas/testsuite/gas/riscv/zimop.s | 43 ++++++++++ > include/opcode/riscv-opc.h | 122 +++++++++++++++++++++++++++ > include/opcode/riscv.h | 1 + > opcodes/riscv-opc.c | 42 +++++++++ > 8 files changed, 264 insertions(+) > create mode 100644 gas/testsuite/gas/riscv/zimop.d > create mode 100644 gas/testsuite/gas/riscv/zimop.s > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index b08e44577b8..e471acda72b 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -1348,6 +1348,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = > {"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, > {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, > + {"zimop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zabha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > @@ -2515,6 +2516,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, > || riscv_subset_supports (rps, "zca"))); > case INSN_CLASS_ZIHINTPAUSE: > return riscv_subset_supports (rps, "zihintpause"); > + case INSN_CLASS_ZIMOP: > + return riscv_subset_supports (rps, "zimop"); > case INSN_CLASS_M: > return riscv_subset_supports (rps, "m"); > case INSN_CLASS_ZMMUL: > @@ -2741,6 +2744,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, > return _("c' or `zca"); > case INSN_CLASS_ZIHINTPAUSE: > return "zihintpause"; > + case INSN_CLASS_ZIMOP: > + return "zimop"; > case INSN_CLASS_M: > return "m"; > case INSN_CLASS_ZMMUL: > diff --git a/gas/NEWS b/gas/NEWS > index cb58ca8fb8d..f13b1020d3e 100644 > --- a/gas/NEWS > +++ b/gas/NEWS > @@ -1,5 +1,7 @@ > -*- text -*- > > +* Add support for RISC-V Zimop extension with version 1.0. > + > * Support the NF feature in Intel APX. > > * Remove KEYLOCKER and SHA promotions from EVEX MAP4. > diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l > index e45221e5ed8..723f934b997 100644 > --- a/gas/testsuite/gas/riscv/march-help.l > +++ b/gas/testsuite/gas/riscv/march-help.l > @@ -19,6 +19,7 @@ All available -march extensions for RISC-V: > zihintntl 1.0 > zihintpause 2.0 > zihpm 2.0 > + zimop 1.0 > zmmul 1.0 > zabha 1.0 > zawrs 1.0 > diff --git a/gas/testsuite/gas/riscv/zimop.d b/gas/testsuite/gas/riscv/zimop.d > new file mode 100644 > index 00000000000..becb72ca650 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zimop.d > @@ -0,0 +1,48 @@ > +#as: -march=rv64i_zimop > +#objdump: -d > + > +.*:[ ]+file format .* > + > +Disassembly of section .text: > + > +0+000 : > +[ ]+[0-9a-f]+:[ ]+81c5c573[ ]+mop.r.0[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+81d5c573[ ]+mop.r.1[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+81e5c573[ ]+mop.r.2[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+81f5c573[ ]+mop.r.3[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+85c5c573[ ]+mop.r.4[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+85d5c573[ ]+mop.r.5[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+85e5c573[ ]+mop.r.6[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+85f5c573[ ]+mop.r.7[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+89c5c573[ ]+mop.r.8[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+89d5c573[ ]+mop.r.9[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+89e5c573[ ]+mop.r.10[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+89f5c573[ ]+mop.r.11[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+8dc5c573[ ]+mop.r.12[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+8dd5c573[ ]+mop.r.13[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+8de5c573[ ]+mop.r.14[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+8df5c573[ ]+mop.r.15[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c1c5c573[ ]+mop.r.16[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c1d5c573[ ]+mop.r.17[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c1e5c573[ ]+mop.r.18[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c1f5c573[ ]+mop.r.19[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c5c5c573[ ]+mop.r.20[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c5d5c573[ ]+mop.r.21[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c5e5c573[ ]+mop.r.22[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c5f5c573[ ]+mop.r.23[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c9c5c573[ ]+mop.r.24[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c9d5c573[ ]+mop.r.25[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c9e5c573[ ]+mop.r.26[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c9f5c573[ ]+mop.r.27[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+cdc5c573[ ]+mop.r.28[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+cdd5c573[ ]+mop.r.29[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+cde5c573[ ]+mop.r.30[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+cdf5c573[ ]+mop.r.31[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+82c5c573[ ]+mop.rr.0[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+86c5c573[ ]+mop.rr.1[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+8ac5c573[ ]+mop.rr.2[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+8ec5c573[ ]+mop.rr.3[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+c2c5c573[ ]+mop.rr.4[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+c6c5c573[ ]+mop.rr.5[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+cac5c573[ ]+mop.rr.6[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+cec5c573[ ]+mop.rr.7[ ]+a0,a1,a2 > diff --git a/gas/testsuite/gas/riscv/zimop.s b/gas/testsuite/gas/riscv/zimop.s > new file mode 100644 > index 00000000000..d244c1fb0fb > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zimop.s > @@ -0,0 +1,43 @@ > +target: > + # mop.r.n > + mop.r.0 a0, a1 > + mop.r.1 a0, a1 > + mop.r.2 a0, a1 > + mop.r.3 a0, a1 > + mop.r.4 a0, a1 > + mop.r.5 a0, a1 > + mop.r.6 a0, a1 > + mop.r.7 a0, a1 > + mop.r.8 a0, a1 > + mop.r.9 a0, a1 > + mop.r.10 a0, a1 > + mop.r.11 a0, a1 > + mop.r.12 a0, a1 > + mop.r.13 a0, a1 > + mop.r.14 a0, a1 > + mop.r.15 a0, a1 > + mop.r.16 a0, a1 > + mop.r.17 a0, a1 > + mop.r.18 a0, a1 > + mop.r.19 a0, a1 > + mop.r.20 a0, a1 > + mop.r.21 a0, a1 > + mop.r.22 a0, a1 > + mop.r.23 a0, a1 > + mop.r.24 a0, a1 > + mop.r.25 a0, a1 > + mop.r.26 a0, a1 > + mop.r.27 a0, a1 > + mop.r.28 a0, a1 > + mop.r.29 a0, a1 > + mop.r.30 a0, a1 > + mop.r.31 a0, a1 > + # mop.rr.n > + mop.rr.0 a0, a1, a2 > + mop.rr.1 a0, a1, a2 > + mop.rr.2 a0, a1, a2 > + mop.rr.3 a0, a1, a2 > + mop.rr.4 a0, a1, a2 > + mop.rr.5 a0, a1, a2 > + mop.rr.6 a0, a1, a2 > + mop.rr.7 a0, a1, a2 > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h > index ae14e14d427..a6d7e4b24e2 100644 > --- a/include/opcode/riscv-opc.h > +++ b/include/opcode/riscv-opc.h > @@ -2360,6 +2360,87 @@ > #define MASK_C_NTL_S1 0xffff > #define MATCH_C_NTL_ALL 0x9016 > #define MASK_C_NTL_ALL 0xffff > +/* Zimop instructions. */ > +#define MATCH_MOP_R_0 0x81c04073 > +#define MASK_MOP_R_0 0xfff0707f > +#define MATCH_MOP_R_1 0x81d04073 > +#define MASK_MOP_R_1 0xfff0707f > +#define MATCH_MOP_R_2 0x81e04073 > +#define MASK_MOP_R_2 0xfff0707f > +#define MATCH_MOP_R_3 0x81f04073 > +#define MASK_MOP_R_3 0xfff0707f > +#define MATCH_MOP_R_4 0x85c04073 > +#define MASK_MOP_R_4 0xfff0707f > +#define MATCH_MOP_R_5 0x85d04073 > +#define MASK_MOP_R_5 0xfff0707f > +#define MATCH_MOP_R_6 0x85e04073 > +#define MASK_MOP_R_6 0xfff0707f > +#define MATCH_MOP_R_7 0x85f04073 > +#define MASK_MOP_R_7 0xfff0707f > +#define MATCH_MOP_R_8 0x89c04073 > +#define MASK_MOP_R_8 0xfff0707f > +#define MATCH_MOP_R_9 0x89d04073 > +#define MASK_MOP_R_9 0xfff0707f > +#define MATCH_MOP_R_10 0x89e04073 > +#define MASK_MOP_R_10 0xfff0707f > +#define MATCH_MOP_R_11 0x89f04073 > +#define MASK_MOP_R_11 0xfff0707f > +#define MATCH_MOP_R_12 0x8dc04073 > +#define MASK_MOP_R_12 0xfff0707f > +#define MATCH_MOP_R_13 0x8dd04073 > +#define MASK_MOP_R_13 0xfff0707f > +#define MATCH_MOP_R_14 0x8de04073 > +#define MASK_MOP_R_14 0xfff0707f > +#define MATCH_MOP_R_15 0x8df04073 > +#define MASK_MOP_R_15 0xfff0707f > +#define MATCH_MOP_R_16 0xc1c04073 > +#define MASK_MOP_R_16 0xfff0707f > +#define MATCH_MOP_R_17 0xc1d04073 > +#define MASK_MOP_R_17 0xfff0707f > +#define MATCH_MOP_R_18 0xc1e04073 > +#define MASK_MOP_R_18 0xfff0707f > +#define MATCH_MOP_R_19 0xc1f04073 > +#define MASK_MOP_R_19 0xfff0707f > +#define MATCH_MOP_R_20 0xc5c04073 > +#define MASK_MOP_R_20 0xfff0707f > +#define MATCH_MOP_R_21 0xc5d04073 > +#define MASK_MOP_R_21 0xfff0707f > +#define MATCH_MOP_R_22 0xc5e04073 > +#define MASK_MOP_R_22 0xfff0707f > +#define MATCH_MOP_R_23 0xc5f04073 > +#define MASK_MOP_R_23 0xfff0707f > +#define MATCH_MOP_R_24 0xc9c04073 > +#define MASK_MOP_R_24 0xfff0707f > +#define MATCH_MOP_R_25 0xc9d04073 > +#define MASK_MOP_R_25 0xfff0707f > +#define MATCH_MOP_R_26 0xc9e04073 > +#define MASK_MOP_R_26 0xfff0707f > +#define MATCH_MOP_R_27 0xc9f04073 > +#define MASK_MOP_R_27 0xfff0707f > +#define MATCH_MOP_R_28 0xcdc04073 > +#define MASK_MOP_R_28 0xfff0707f > +#define MATCH_MOP_R_29 0xcdd04073 > +#define MASK_MOP_R_29 0xfff0707f > +#define MATCH_MOP_R_30 0xcde04073 > +#define MASK_MOP_R_30 0xfff0707f > +#define MATCH_MOP_R_31 0xcdf04073 > +#define MASK_MOP_R_31 0xfff0707f > +#define MATCH_MOP_RR_0 0x82004073 > +#define MASK_MOP_RR_0 0xfe00707f > +#define MATCH_MOP_RR_1 0x86004073 > +#define MASK_MOP_RR_1 0xfe00707f > +#define MATCH_MOP_RR_2 0x8a004073 > +#define MASK_MOP_RR_2 0xfe00707f > +#define MATCH_MOP_RR_3 0x8e004073 > +#define MASK_MOP_RR_3 0xfe00707f > +#define MATCH_MOP_RR_4 0xc2004073 > +#define MASK_MOP_RR_4 0xfe00707f > +#define MATCH_MOP_RR_5 0xc6004073 > +#define MASK_MOP_RR_5 0xfe00707f > +#define MATCH_MOP_RR_6 0xca004073 > +#define MASK_MOP_RR_6 0xfe00707f > +#define MATCH_MOP_RR_7 0xce004073 > +#define MASK_MOP_RR_7 0xfe00707f > /* Zawrs instructions. */ > #define MATCH_WRS_NTO 0x00d00073 > #define MASK_WRS_NTO 0xffffffff > @@ -3909,6 +3990,47 @@ DECLARE_INSN(c_ntl_p1, MATCH_C_NTL_P1, MASK_C_NTL_P1) > DECLARE_INSN(c_ntl_pall, MATCH_C_NTL_PALL, MASK_C_NTL_PALL) > DECLARE_INSN(c_ntl_s1, MATCH_C_NTL_S1, MASK_C_NTL_S1) > DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL) > +/* Zimop instructions. */ > +DECLARE_INSN(MOP_R_0, MATCH_MOP_R_0, MASK_MOP_R_0) > +DECLARE_INSN(MOP_R_1, MATCH_MOP_R_1, MASK_MOP_R_1) > +DECLARE_INSN(MOP_R_2, MATCH_MOP_R_2, MASK_MOP_R_2) > +DECLARE_INSN(MOP_R_3, MATCH_MOP_R_3, MASK_MOP_R_3) > +DECLARE_INSN(MOP_R_4, MATCH_MOP_R_4, MASK_MOP_R_4) > +DECLARE_INSN(MOP_R_5, MATCH_MOP_R_5, MASK_MOP_R_5) > +DECLARE_INSN(MOP_R_6, MATCH_MOP_R_6, MASK_MOP_R_6) > +DECLARE_INSN(MOP_R_7, MATCH_MOP_R_7, MASK_MOP_R_7) > +DECLARE_INSN(MOP_R_8, MATCH_MOP_R_8, MASK_MOP_R_8) > +DECLARE_INSN(MOP_R_9, MATCH_MOP_R_9, MASK_MOP_R_9) > +DECLARE_INSN(MOP_R_10, MATCH_MOP_R_10, MASK_MOP_R_10) > +DECLARE_INSN(MOP_R_11, MATCH_MOP_R_11, MASK_MOP_R_11) > +DECLARE_INSN(MOP_R_12, MATCH_MOP_R_12, MASK_MOP_R_12) > +DECLARE_INSN(MOP_R_13, MATCH_MOP_R_13, MASK_MOP_R_13) > +DECLARE_INSN(MOP_R_14, MATCH_MOP_R_14, MASK_MOP_R_14) > +DECLARE_INSN(MOP_R_15, MATCH_MOP_R_15, MASK_MOP_R_15) > +DECLARE_INSN(MOP_R_16, MATCH_MOP_R_16, MASK_MOP_R_16) > +DECLARE_INSN(MOP_R_17, MATCH_MOP_R_17, MASK_MOP_R_17) > +DECLARE_INSN(MOP_R_18, MATCH_MOP_R_18, MASK_MOP_R_18) > +DECLARE_INSN(MOP_R_19, MATCH_MOP_R_19, MASK_MOP_R_19) > +DECLARE_INSN(MOP_R_20, MATCH_MOP_R_20, MASK_MOP_R_20) > +DECLARE_INSN(MOP_R_21, MATCH_MOP_R_21, MASK_MOP_R_21) > +DECLARE_INSN(MOP_R_22, MATCH_MOP_R_22, MASK_MOP_R_22) > +DECLARE_INSN(MOP_R_23, MATCH_MOP_R_23, MASK_MOP_R_23) > +DECLARE_INSN(MOP_R_24, MATCH_MOP_R_24, MASK_MOP_R_24) > +DECLARE_INSN(MOP_R_25, MATCH_MOP_R_25, MASK_MOP_R_25) > +DECLARE_INSN(MOP_R_26, MATCH_MOP_R_26, MASK_MOP_R_26) > +DECLARE_INSN(MOP_R_27, MATCH_MOP_R_27, MASK_MOP_R_27) > +DECLARE_INSN(MOP_R_28, MATCH_MOP_R_28, MASK_MOP_R_28) > +DECLARE_INSN(MOP_R_29, MATCH_MOP_R_29, MASK_MOP_R_29) > +DECLARE_INSN(MOP_R_30, MATCH_MOP_R_30, MASK_MOP_R_30) > +DECLARE_INSN(MOP_R_31, MATCH_MOP_R_31, MASK_MOP_R_31) > +DECLARE_INSN(MOP_RR_0, MATCH_MOP_RR_0, MASK_MOP_RR_0) > +DECLARE_INSN(MOP_RR_1, MATCH_MOP_RR_1, MASK_MOP_RR_1) > +DECLARE_INSN(MOP_RR_2, MATCH_MOP_RR_2, MASK_MOP_RR_2) > +DECLARE_INSN(MOP_RR_3, MATCH_MOP_RR_3, MASK_MOP_RR_3) > +DECLARE_INSN(MOP_RR_4, MATCH_MOP_RR_4, MASK_MOP_RR_4) > +DECLARE_INSN(MOP_RR_5, MATCH_MOP_RR_5, MASK_MOP_RR_5) > +DECLARE_INSN(MOP_RR_6, MATCH_MOP_RR_6, MASK_MOP_RR_6) > +DECLARE_INSN(MOP_RR_7, MATCH_MOP_RR_7, MASK_MOP_RR_7) > /* Zawrs instructions. */ > DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) > DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h > index d967b78f706..2434810c26e 100644 > --- a/include/opcode/riscv.h > +++ b/include/opcode/riscv.h > @@ -435,6 +435,7 @@ enum riscv_insn_class > INSN_CLASS_ZIHINTNTL, > INSN_CLASS_ZIHINTNTL_AND_C, > INSN_CLASS_ZIHINTPAUSE, > + INSN_CLASS_ZIMOP, > INSN_CLASS_ZMMUL, > INSN_CLASS_ZAWRS, > INSN_CLASS_F_INX, > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index 38a4624da7e..f78ca18a6ee 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -1085,6 +1085,48 @@ const struct riscv_opcode riscv_opcodes[] = > {"czero.eqz", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 }, > {"czero.nez", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 }, > > +/* Zimop instructions. */ > +{"mop.r.0", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_0, MASK_MOP_R_0, match_opcode, 0 }, > +{"mop.r.1", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_1, MASK_MOP_R_1, match_opcode, 0 }, > +{"mop.r.2", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_2, MASK_MOP_R_2, match_opcode, 0 }, > +{"mop.r.3", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_3, MASK_MOP_R_3, match_opcode, 0 }, > +{"mop.r.4", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_4, MASK_MOP_R_4, match_opcode, 0 }, > +{"mop.r.5", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_5, MASK_MOP_R_5, match_opcode, 0 }, > +{"mop.r.6", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_6, MASK_MOP_R_6, match_opcode, 0 }, > +{"mop.r.7", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_7, MASK_MOP_R_7, match_opcode, 0 }, > +{"mop.r.8", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_8, MASK_MOP_R_8, match_opcode, 0 }, > +{"mop.r.9", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_9, MASK_MOP_R_9, match_opcode, 0 }, > +{"mop.r.10", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_10, MASK_MOP_R_10, match_opcode, 0 }, > +{"mop.r.11", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_11, MASK_MOP_R_11, match_opcode, 0 }, > +{"mop.r.12", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_12, MASK_MOP_R_12, match_opcode, 0 }, > +{"mop.r.13", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_13, MASK_MOP_R_13, match_opcode, 0 }, > +{"mop.r.14", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_14, MASK_MOP_R_14, match_opcode, 0 }, > +{"mop.r.15", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_15, MASK_MOP_R_15, match_opcode, 0 }, > +{"mop.r.16", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_16, MASK_MOP_R_16, match_opcode, 0 }, > +{"mop.r.17", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_17, MASK_MOP_R_17, match_opcode, 0 }, > +{"mop.r.18", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_18, MASK_MOP_R_18, match_opcode, 0 }, > +{"mop.r.19", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_19, MASK_MOP_R_19, match_opcode, 0 }, > +{"mop.r.20", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_20, MASK_MOP_R_20, match_opcode, 0 }, > +{"mop.r.21", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_21, MASK_MOP_R_21, match_opcode, 0 }, > +{"mop.r.22", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_22, MASK_MOP_R_22, match_opcode, 0 }, > +{"mop.r.23", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_23, MASK_MOP_R_23, match_opcode, 0 }, > +{"mop.r.24", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_24, MASK_MOP_R_24, match_opcode, 0 }, > +{"mop.r.25", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_25, MASK_MOP_R_25, match_opcode, 0 }, > +{"mop.r.26", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_26, MASK_MOP_R_26, match_opcode, 0 }, > +{"mop.r.27", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_27, MASK_MOP_R_27, match_opcode, 0 }, > +{"mop.r.28", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_28, MASK_MOP_R_28, match_opcode, 0 }, > +{"mop.r.29", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_29, MASK_MOP_R_29, match_opcode, 0 }, > +{"mop.r.30", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_30, MASK_MOP_R_30, match_opcode, 0 }, > +{"mop.r.31", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_31, MASK_MOP_R_31, match_opcode, 0 }, > +{"mop.rr.0", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_0, MASK_MOP_RR_0, match_opcode, 0 }, > +{"mop.rr.1", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_1, MASK_MOP_RR_1, match_opcode, 0 }, > +{"mop.rr.2", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_2, MASK_MOP_RR_2, match_opcode, 0 }, > +{"mop.rr.3", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_3, MASK_MOP_RR_3, match_opcode, 0 }, > +{"mop.rr.4", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_4, MASK_MOP_RR_4, match_opcode, 0 }, > +{"mop.rr.5", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_5, MASK_MOP_RR_5, match_opcode, 0 }, > +{"mop.rr.6", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_6, MASK_MOP_RR_6, match_opcode, 0 }, > +{"mop.rr.7", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_7, MASK_MOP_RR_7, match_opcode, 0 }, > + > /* Zawrs instructions. */ > {"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 }, > {"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 },