From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id F283E38A8161 for ; Sat, 8 Oct 2022 04:34:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org F283E38A8161 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 4A01D300089; Sat, 8 Oct 2022 04:34:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1665203690; bh=OfTXO/GYtxPCVIkUKCq6YQ0agUAtY6pn9V8Hg+dAPtA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=LdMP2403qMqfEVNYcd4zZaykiL8DGNrfSGGVUnlIebVSbMLfVHozJBcM/D3F4gTGr in+0kQpLSB+7V/q56HkbE2itxAuY4NP5GKXaghpwIqakdjkympT76wvA+FkkOMe7IY UgGIy6Fx9JR149BUT76pwrzZFo5pAaHIyHRFffd0= From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 2/5] opcodes/riscv-dis.c: Tidying with spacing Date: Sat, 8 Oct 2022 04:34:24 +0000 Message-Id: <1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Before changing the core disassembler, we take care of minor code clarity issues and improve readability. This commit takes care of improper spacing for code clarity. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Tidying with spacing. --- opcodes/riscv-dis.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 2d1faf26eb3..088d0d91080 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -715,7 +715,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) } /* If arch has the Zfinx extension, replace FPR with GPR. */ - if(riscv_subset_supports (&riscv_rps_dis, "zfinx")) + if (riscv_subset_supports (&riscv_rps_dis, "zfinx")) riscv_fpr_names = riscv_gpr_names; for (; op->name; op++) -- 2.34.1