* Patch to add -mfp32 support to MIPS gas
@ 2001-07-19 12:46 Richard Sandiford
2001-07-19 16:11 ` Thiemo Seufer
0 siblings, 1 reply; 20+ messages in thread
From: Richard Sandiford @ 2001-07-19 12:46 UTC (permalink / raw)
To: binutils
At the moment, MIPS gas uses:
ISA_HAS_64BIT_REGS (mips_opts.isa)
to decide what size the registers are and:
bfd_arch_bits_per_address (stdoutput) == 32
|| ! ISA_HAS_64BIT_REGS (mips_opts.isa)
to decide what size addresses are. That isn't as fine grain as GCC, which
allows the sizes of the FPRs and GPRs to be selected independently. GAS
already has a -mgp32 switch, but it doesn't affect the size of address
calculations; they will still be done using 64-bit instructions if a 64-bit
ISA is selected.
The patch below adds macros that give the size of GPRs, FPRs and addresses,
and tries to retrofit them to the rest of tc-mips.c. It also adds the
options -mfp32 and -mfp64, and documents -m[fg]p* in the usage printout.
The changes are mostly routine. Two things that needed special attention:
- The current code checks "bfd_arch_bits_per_address (stdoutput)" when
deciding whether the set instructions ("sle", etc.) should use 32-bit
or 64-bit instructions. That seems rather strange, and is inconsistent
with usage elsewhere, where "bfd_arch_bits_per_address" only affects
address calculations. The patch changes it to use 32-bit instructions
if GPRs are 32-bits wide, and 64-bit instructions otherwise.
- The LI_DD handler assumes that it can construct constants in a GPR
first and then copy it to an FPR. That doesn't work if the FPRs are
wider than the GPRs, so the patch forces floating-point constants
into memory under these conditions.
I've included 8 new test cases, hopefully testing each of the macros
whose code has been touched. They test the pattern of options:
{,-mgp32}{,-mfp32}{,-KPIC}
The testcases without a -mgp32 or -mfp32 option behaved the same before the
patch as they do after it. The patch introduces no regressions in the
existing test cases (tested with mips-elf).
Is this the right thing to do? Is it OK to apply?
Richard
[gas/ChangeLog]
* tc-mips.c (mips_fp32): New static variable.
(md_long_opts): Add -mfp32 and -mfp64.
(md_parse_option): Handle them.
(md_show_usage): Show usage for -mfp32, -mfp64, -mgp32 and -mgp64.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): New macros.
(HAVE_64BIT_GPRS, HAVE_64BIT_FPRS): New macros, inverse of the above.
(HAVE_32BIT_ADDRESSES): New macro.
(load_register): Use HAVE_32BIT_GPRS to determine the register width.
(load_address): Use HAVE_32BIT_ADDRESSES to determine the address size.
(s_cprestore, s_cpadd): Likewise.
(macro): Use HAVE_32BIT_GPRS to determine the width of registers
used in branch and M_LI_D macros. Use HAVE_32BIT_FPRS to determine
the width registers used in M_LI_DD macros. Use HAVE_32BIT_ADDRESSES
to determine the width of addresses in load, store and jump macros.
(macro2): Use HAVE_32BIT_GPRS to determine the width of registers
used in set instructions; do not check the address size for them.
Use HAVE_32BIT_ADDRESSES to determine the width of addresses in
unaligned load and store macros.
(mips_ip): Use the new macros to check the width of a register when
processing float constants. Force a constant into memory if it is
destined for an FPR and the FPRs are wider than the GPRs. Warn about
odd FPR numbers if HAVE_32BIT_FPRS.
[gas/testsuite/ChangeLog]
* gas/mips/mips-gp(32|64)-fp(32|64)(|-pic): New testcases.
Index: tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.51
diff -u -p -d -r1.51 tc-mips.c
--- tc-mips.c 2001/07/04 12:32:07 1.51
+++ tc-mips.c 2001/07/19 18:37:14
@@ -229,6 +229,9 @@ static int mips_32bitmode = 0;
/* True if -mgp32 was passed. */
static int mips_gp32 = 0;
+/* True if -mfp32 was passed. */
+static int mips_fp32 = 0;
+
/* Some ISA's have delay slots for instructions which read or write
from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
Return true if instructions marked INSN_LOAD_COPROC_DELAY,
@@ -251,6 +254,18 @@ static int mips_gp32 = 0;
|| (ISA) == ISA_MIPS64 \
)
+#define HAVE_32BIT_GPRS \
+ (mips_gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
+
+#define HAVE_32BIT_FPRS \
+ (mips_fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
+
+#define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
+#define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
+
+#define HAVE_32BIT_ADDRESSES \
+ (HAVE_32BIT_GPRS || bfd_arch_bits_per_address (stdoutput) == 32)
+
/* Whether the processor uses hardware interlocks to protect
reads from the HI and LO registers, and thus does not
require nops to be inserted. */
@@ -3008,9 +3023,9 @@ load_register (counter, reg, ep, dbl)
|| ! ep->X_unsigned
|| sizeof (ep->X_add_number) > 4
|| (ep->X_add_number & 0x80000000) == 0))
- || ((! ISA_HAS_64BIT_REGS (mips_opts.isa) || ! dbl)
+ || ((HAVE_32BIT_GPRS || ! dbl)
&& (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
- || (! ISA_HAS_64BIT_REGS (mips_opts.isa)
+ || (HAVE_32BIT_GPRS
&& ! dbl
&& ((ep->X_add_number &~ (offsetT) 0xffffffff)
== ~ (offsetT) 0xffffffff)))
@@ -3027,7 +3042,7 @@ load_register (counter, reg, ep, dbl)
/* The value is larger than 32 bits. */
- if (! ISA_HAS_64BIT_REGS (mips_opts.isa))
+ if (HAVE_32BIT_GPRS)
{
as_bad (_("Number larger than 32 bits"));
macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
@@ -3269,9 +3284,7 @@ load_address (counter, reg, ep)
{
frag_grow (20);
macro_build ((char *) NULL, counter, ep,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL);
p = frag_var (rs_machine_dependent, 8, 0,
RELAX_ENCODE (4, 8, 0, 4, 0,
@@ -3282,9 +3295,7 @@ load_address (counter, reg, ep)
if (p != NULL)
p += 4;
macro_build (p, counter, ep,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
}
else if (mips_pic == SVR4_PIC && ! mips_big_got)
@@ -3302,18 +3313,14 @@ load_address (counter, reg, ep)
ep->X_add_number = 0;
frag_grow (20);
macro_build ((char *) NULL, counter, ep,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP);
macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
p = frag_var (rs_machine_dependent, 4, 0,
RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
ep->X_add_symbol, (offsetT) 0, (char *) NULL);
macro_build (p, counter, ep,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
if (ex.X_add_number != 0)
{
@@ -3321,9 +3328,7 @@ load_address (counter, reg, ep)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
ex.X_op = O_constant;
macro_build ((char *) NULL, counter, &ex,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
}
}
@@ -3352,14 +3357,10 @@ load_address (counter, reg, ep)
macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
(int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, counter, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", reg, reg, GP);
macro_build ((char *) NULL, counter, ep,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
p = frag_var (rs_machine_dependent, 12 + off, 0,
RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
@@ -3375,17 +3376,13 @@ load_address (counter, reg, ep)
p += 4;
}
macro_build (p, counter, ep,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP);
p += 4;
macro_build (p, counter, (expressionS *) NULL, "nop", "");
p += 4;
macro_build (p, counter, ep,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
if (ex.X_add_number != 0)
{
@@ -3393,9 +3390,7 @@ load_address (counter, reg, ep)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
ex.X_op = O_constant;
macro_build ((char *) NULL, counter, &ex,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
}
}
@@ -3405,9 +3400,7 @@ load_address (counter, reg, ep)
addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
*/
macro_build ((char *) NULL, counter, ep,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL);
}
else
@@ -3614,7 +3607,7 @@ macro (ip)
case M_BGT_I:
/* check for > max integer */
maxnum = 0x7fffffff;
- if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4)
+ if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
{
maxnum <<= 16;
maxnum |= 0xffff;
@@ -3623,7 +3616,7 @@ macro (ip)
}
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number >= maxnum
- && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4))
+ && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
{
do_false:
/* result is always false */
@@ -3667,7 +3660,7 @@ macro (ip)
return;
}
maxnum = 0x7fffffff;
- if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4)
+ if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
{
maxnum <<= 16;
maxnum |= 0xffff;
@@ -3677,7 +3670,7 @@ macro (ip)
maxnum = - maxnum - 1;
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number <= maxnum
- && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4))
+ && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
{
do_true:
/* result is always true */
@@ -3714,7 +3707,7 @@ macro (ip)
likely = 1;
case M_BGTU_I:
if (sreg == 0
- || (! ISA_HAS_64BIT_REGS (mips_opts.isa)
+ || (HAVE_32BIT_GPRS
&& imm_expr.X_op == O_constant
&& imm_expr.X_add_number == 0xffffffff))
goto do_false;
@@ -3810,7 +3803,7 @@ macro (ip)
likely = 1;
case M_BLE_I:
maxnum = 0x7fffffff;
- if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4)
+ if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
{
maxnum <<= 16;
maxnum |= 0xffff;
@@ -3819,7 +3812,7 @@ macro (ip)
}
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number >= maxnum
- && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4))
+ && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
goto do_true;
if (imm_expr.X_op != O_constant)
as_bad (_("Unsupported large constant"));
@@ -3872,7 +3865,7 @@ macro (ip)
likely = 1;
case M_BLEU_I:
if (sreg == 0
- || (! ISA_HAS_64BIT_REGS (mips_opts.isa)
+ || (HAVE_32BIT_GPRS
&& imm_expr.X_op == O_constant
&& imm_expr.X_add_number == 0xffffffff))
goto do_true;
@@ -4170,9 +4163,7 @@ macro (ip)
macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
treg, (int) BFD_RELOC_PCREL_HI16_S);
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16);
return;
}
@@ -4213,9 +4204,7 @@ macro (ip)
{
frag_grow (20);
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL);
p = frag_var (rs_machine_dependent, 8, 0,
RELAX_ENCODE (4, 8, 0, 4, 0,
@@ -4227,9 +4216,7 @@ macro (ip)
if (p != NULL)
p += 4;
macro_build (p, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
}
else if (mips_pic == SVR4_PIC && ! mips_big_got)
@@ -4300,9 +4287,7 @@ macro (ip)
p += 4;
}
macro_build (p, &icnt, &expr1,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
/* FIXME: If breg == 0, and the next instruction uses
$tempreg, then if this variant case is used an extra
@@ -4314,9 +4299,7 @@ macro (ip)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
"nop", "");
macro_build ((char *) NULL, &icnt, &expr1,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
(void) frag_var (rs_machine_dependent, 0, 0,
RELAX_ENCODE (0, 0, -12, -4, 0, 0),
@@ -4341,9 +4324,7 @@ macro (ip)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
"nop", "");
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", treg, AT, breg);
breg = 0;
tempreg = treg;
@@ -4358,14 +4339,10 @@ macro (ip)
mips_optimize = hold_mips_optimize;
macro_build ((char *) NULL, &icnt, &expr1,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", AT, AT, (int) BFD_RELOC_LO16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", tempreg, tempreg, AT);
(void) frag_var (rs_machine_dependent, 0, 0,
RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
@@ -4435,9 +4412,7 @@ macro (ip)
macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
tempreg, lui_reloc_type);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", tempreg, tempreg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
dbl ? "ld" : "lw",
@@ -4473,9 +4448,7 @@ macro (ip)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
"nop", "");
macro_build ((char *) NULL, &icnt, &expr1,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
@@ -4508,9 +4481,7 @@ macro (ip)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
"nop", "");
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", treg, AT, breg);
dreg = treg;
adj = 8;
@@ -4524,14 +4495,10 @@ macro (ip)
mips_optimize = hold_mips_optimize;
macro_build ((char *) NULL, &icnt, &expr1,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", AT, AT, (int) BFD_RELOC_LO16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", dreg, dreg, AT);
p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
@@ -4563,9 +4530,7 @@ macro (ip)
macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
p += 4;
macro_build (p, &icnt, &expr1,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
/* FIXME: If add_number is 0, and there was no base
register, the external symbol case ended with a load,
@@ -4583,9 +4548,7 @@ macro (ip)
macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
p += 4;
macro_build (p, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", treg, AT, breg);
p += 4;
tempreg = treg;
@@ -4597,15 +4560,11 @@ macro (ip)
macro_build_lui (p, &icnt, &expr1, AT);
p += 4;
macro_build (p, &icnt, &expr1,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", AT, AT, (int) BFD_RELOC_LO16);
p += 4;
macro_build (p, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", tempreg, tempreg, AT);
p += 4;
}
@@ -4616,9 +4575,7 @@ macro (ip)
addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
*/
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL);
}
else
@@ -4626,9 +4583,7 @@ macro (ip)
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", treg, tempreg, breg);
if (! used_at)
@@ -4670,9 +4625,7 @@ macro (ip)
{
expr1.X_add_number = mips_cprestore_offset;
macro_build ((char *) NULL, &icnt, &expr1,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg);
}
}
@@ -4713,9 +4666,7 @@ macro (ip)
if (! mips_big_got)
{
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_CALL16, GP);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
@@ -4736,14 +4687,10 @@ macro (ip)
macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
@@ -4759,9 +4706,7 @@ macro (ip)
p += 4;
}
macro_build (p, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_GOT16, GP);
p += 4;
@@ -4769,9 +4714,7 @@ macro (ip)
p += 4;
}
macro_build (p, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", PIC_CALL_REG, PIC_CALL_REG,
(int) BFD_RELOC_LO16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
@@ -4785,9 +4728,7 @@ macro (ip)
"nop", "");
expr1.X_add_number = mips_cprestore_offset;
macro_build ((char *) NULL, &icnt, &expr1,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", GP, (int) BFD_RELOC_LO16,
mips_frame_reg);
}
@@ -5042,9 +4983,7 @@ macro (ip)
{
frag_grow (28);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", tempreg, breg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
treg, (int) BFD_RELOC_MIPS_GPREL, tempreg);
@@ -5057,9 +4996,7 @@ macro (ip)
if (p != NULL)
p += 4;
macro_build (p, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", tempreg, tempreg, breg);
if (p != NULL)
p += 4;
@@ -5092,9 +5029,7 @@ macro (ip)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
frag_grow (20);
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
p = frag_var (rs_machine_dependent, 4, 0,
@@ -5102,15 +5037,11 @@ macro (ip)
offset_expr.X_add_symbol, (offsetT) 0,
(char *) NULL);
macro_build (p, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", tempreg, tempreg, breg);
macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
(int) BFD_RELOC_LO16, tempreg);
@@ -5149,14 +5080,10 @@ macro (ip)
macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", tempreg, tempreg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
tempreg);
p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
@@ -5168,23 +5095,17 @@ macro (ip)
p += 4;
}
macro_build (p, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
p += 4;
macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
p += 4;
macro_build (p, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", tempreg, tempreg, breg);
macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
(int) BFD_RELOC_LO16, tempreg);
@@ -5207,9 +5128,7 @@ macro (ip)
else
{
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", tempreg, breg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
treg, (int) BFD_RELOC_MIPS_GPREL, tempreg);
@@ -5253,13 +5172,13 @@ macro (ip)
}
case M_LI_D:
- /* If we have a constant in IMM_EXPR, then in mips3 mode it is
- the entire value, and in mips1 mode it is the high order 32
- bits of the value and the low order 32 bits are either zero
- or in offset_expr. */
+ /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
+ wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
+ order 32 bits of the value and the low order 32 bits are either
+ zero or in OFFSET_EXPR. */
if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
{
- if (ISA_HAS_64BIT_REGS (mips_opts.isa))
+ if (HAVE_64BIT_GPRS)
load_register (&icnt, treg, &imm_expr, 1);
else
{
@@ -5303,9 +5222,7 @@ macro (ip)
else if (mips_pic == SVR4_PIC)
{
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
}
else if (mips_pic == EMBEDDED_PIC)
@@ -5313,9 +5230,7 @@ macro (ip)
/* For embedded PIC we pick up the entire address off $gp in
a single instruction. */
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL);
offset_expr.X_op = O_constant;
offset_expr.X_add_number = 0;
@@ -5324,7 +5239,7 @@ macro (ip)
abort ();
/* Now we load the register(s). */
- if (ISA_HAS_64BIT_REGS (mips_opts.isa))
+ if (HAVE_64BIT_GPRS)
macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
treg, (int) BFD_RELOC_LO16, AT);
else
@@ -5349,16 +5264,20 @@ macro (ip)
break;
case M_LI_DD:
- /* If we have a constant in IMM_EXPR, then in mips3 mode it is
- the entire value, and in mips1 mode it is the high order 32
- bits of the value and the low order 32 bits are either zero
- or in offset_expr. */
+ /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
+ wide, IMM_EXPR is the entire value and the GPRs are known to be 64
+ bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
+ the value and the low order 32 bits are either zero or in
+ OFFSET_EXPR. */
if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
{
- load_register (&icnt, AT, &imm_expr, ISA_HAS_64BIT_REGS (mips_opts.isa));
- if (ISA_HAS_64BIT_REGS (mips_opts.isa))
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- "dmtc1", "t,S", AT, treg);
+ load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
+ if (HAVE_64BIT_FPRS)
+ {
+ assert (HAVE_64BIT_GPRS);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
+ "dmtc1", "t,S", AT, treg);
+ }
else
{
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
@@ -5397,9 +5316,7 @@ macro (ip)
assert (strcmp (s, RDATA_SECTION_NAME) == 0);
if (mips_pic == SVR4_PIC)
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
else
{
@@ -5503,7 +5420,7 @@ macro (ip)
goto ldd_std;
case M_LD_AB:
- if (ISA_HAS_64BIT_REGS (mips_opts.isa))
+ if (HAVE_64BIT_GPRS)
{
s = "ld";
goto ld;
@@ -5514,7 +5431,7 @@ macro (ip)
goto ldd_std;
case M_SD_AB:
- if (ISA_HAS_64BIT_REGS (mips_opts.isa))
+ if (HAVE_64BIT_GPRS)
{
s = "sd";
goto st;
@@ -5576,9 +5493,7 @@ macro (ip)
{
frag_grow (36);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, breg, GP);
tempreg = AT;
off = 4;
@@ -5634,9 +5549,7 @@ macro (ip)
if (breg != 0)
{
macro_build (p, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, breg, AT);
if (p != NULL)
p += 4;
@@ -5683,16 +5596,12 @@ macro (ip)
off = 4;
frag_grow (24 + off);
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, breg, AT);
/* Itbl support may require additional care here. */
macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
@@ -5752,21 +5661,15 @@ macro (ip)
macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
AT, (int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, AT, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, breg, AT);
/* Itbl support may require additional care here. */
macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
@@ -5796,9 +5699,7 @@ macro (ip)
p += 4;
}
macro_build (p, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
p += 4;
macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
@@ -5806,9 +5707,7 @@ macro (ip)
if (breg != 0)
{
macro_build (p, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, breg, AT);
p += 4;
}
@@ -5847,9 +5746,7 @@ macro (ip)
else
{
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, breg, GP);
tempreg = AT;
used_at = 1;
@@ -5879,8 +5776,7 @@ macro (ip)
case M_SD_OB:
s = "sw";
sd_ob:
- assert (bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa));
+ assert (HAVE_32BIT_ADDRESSES);
macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
(int) BFD_RELOC_LO16, breg);
offset_expr.X_add_number += 4;
@@ -6174,9 +6070,7 @@ macro2 (ip)
{
imm_expr.X_add_number = -imm_expr.X_add_number;
macro_build ((char *) NULL, &icnt, &imm_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_GPRS ? "addiu" : "daddiu",
"t,r,j", dreg, sreg,
(int) BFD_RELOC_LO16);
used_at = 0;
@@ -6327,9 +6221,7 @@ macro2 (ip)
as_warn (_("Instruction %s: result is always true"),
ip->insn_mo->name);
macro_build ((char *) NULL, &icnt, &expr1,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_GPRS ? "addiu" : "daddiu",
"t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
return;
}
@@ -6347,9 +6239,7 @@ macro2 (ip)
{
imm_expr.X_add_number = -imm_expr.X_add_number;
macro_build ((char *) NULL, &icnt, &imm_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_GPRS ? "addiu" : "daddiu",
"t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
used_at = 0;
}
@@ -6516,9 +6406,7 @@ macro2 (ip)
load_address (&icnt, AT, &offset_expr);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, AT, breg);
if (! target_big_endian)
expr1.X_add_number = off;
@@ -6539,9 +6427,7 @@ macro2 (ip)
load_address (&icnt, AT, &offset_expr);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, AT, breg);
if (target_big_endian)
expr1.X_add_number = 0;
@@ -6613,9 +6499,7 @@ macro2 (ip)
load_address (&icnt, AT, &offset_expr);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, AT, breg);
if (! target_big_endian)
expr1.X_add_number = off;
@@ -6635,9 +6519,7 @@ macro2 (ip)
load_address (&icnt, AT, &offset_expr);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, AT, breg);
if (! target_big_endian)
expr1.X_add_number = 0;
@@ -7496,7 +7378,7 @@ mips_ip (str, ip)
as_bad (_("Invalid float register number (%d)"), regno);
if ((regno & 1) != 0
- && ! ISA_HAS_64BIT_REGS (mips_opts.isa)
+ && HAVE_32BIT_FPRS
&& ! (strcmp (str, "mtc1") == 0
|| strcmp (str, "mfc1") == 0
|| strcmp (str, "lwc1") == 0
@@ -7570,6 +7452,7 @@ mips_ip (str, ip)
case 'l':
{
int f64;
+ int using_gprs;
char *save_in;
char *err;
unsigned char temp[8];
@@ -7603,9 +7486,15 @@ mips_ip (str, ip)
.lit4 inline easily; we need to put .lit8
somewhere in the data segment, and using .lit8
permits the linker to eventually combine identical
- .lit8 entries). */
+ .lit8 entries).
+ The code below needs to know whether the target register
+ is 32 or 64 bits wide. It relies on the fact 'f' and
+ 'F' are used with GPR-based instructions and 'l' and
+ 'L' are used with FPR-based instructions. */
+
f64 = *args == 'F' || *args == 'L';
+ using_gprs = *args == 'F' || *args == 'f';
save_in = input_line_pointer;
input_line_pointer = s;
@@ -7638,18 +7527,24 @@ mips_ip (str, ip)
}
else if (length > 4
&& ! mips_disable_float_construction
+ /* Constants can only be constructed in GPRs and
+ copied to FPRs if the GPRs are at least as wide
+ as the FPRs. Force the constant into memory if
+ we are using 64-bit FPRs but the GPRs are only
+ 32 bits wide. */
+ && (using_gprs
+ || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
&& ((temp[0] == 0 && temp[1] == 0)
|| (temp[2] == 0 && temp[3] == 0))
&& ((temp[4] == 0 && temp[5] == 0)
|| (temp[6] == 0 && temp[7] == 0)))
{
- /* The value is simple enough to load with a
- couple of instructions. In mips1 mode, set
- imm_expr to the high order 32 bits and
- offset_expr to the low order 32 bits.
- Otherwise, set imm_expr to the entire 64 bit
- constant. */
- if (! ISA_HAS_64BIT_REGS (mips_opts.isa))
+ /* The value is simple enough to load with a couple of
+ instructions. If using 32-bit registers, set
+ imm_expr to the high order 32 bits and offset_expr to
+ the low order 32 bits. Otherwise, set imm_expr to
+ the entire 64 bit constant. */
+ if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
{
imm_expr.X_op = O_constant;
offset_expr.X_op = O_constant;
@@ -7820,7 +7715,7 @@ mips_ip (str, ip)
&& imm_expr.X_op == O_constant)
|| (more
&& imm_expr.X_add_number < 0
- && ISA_HAS_64BIT_REGS (mips_opts.isa)
+ && HAVE_64BIT_GPRS
&& imm_expr.X_unsigned
&& sizeof (imm_expr.X_add_number) <= 4))
{
@@ -8945,6 +8840,10 @@ struct option md_longopts[] =
{"march", required_argument, NULL, OPTION_MARCH},
#define OPTION_MTUNE (OPTION_MD_BASE + 32)
{"mtune", required_argument, NULL, OPTION_MTUNE},
+#define OPTION_FP32 (OPTION_MD_BASE + 33)
+ {"mfp32", no_argument, NULL, OPTION_FP32},
+#define OPTION_FP64 (OPTION_MD_BASE + 34)
+ {"mfp64", no_argument, NULL, OPTION_FP64},
#ifdef OBJ_ELF
#define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
#define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
@@ -9247,6 +9146,14 @@ md_parse_option (c, arg)
#endif
break;
+ case OPTION_FP32:
+ mips_fp32 = 1;
+ break;
+
+ case OPTION_FP64:
+ mips_fp32 = 0;
+ break;
+
case OPTION_MABI:
if (strcmp (arg, "32") == 0
|| strcmp (arg, "n32") == 0
@@ -9369,6 +9276,10 @@ MIPS options:\n\
-mips16 generate mips16 instructions\n\
-no-mips16 do not generate mips16 instructions\n"));
fprintf (stream, _("\
+-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
+-mgp64 has no effect, but is accepted for symmetry\n\
+-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
+-mfp64 has no effect, but is accepted for symmetry\n\
-O0 remove unneeded NOPs, do not swap branches\n\
-O remove unneeded NOPs and swap branches\n\
-n warn about NOPs generated from macros\n\
@@ -10546,9 +10457,7 @@ s_cprestore (ignore)
ex.X_add_number = mips_cprestore_offset;
macro_build ((char *) NULL, &icnt, &ex,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "sw" : "sd"),
+ HAVE_32BIT_ADDRESSES ? "sw" : "sd",
"t,o(b)", GP, (int) BFD_RELOC_LO16, SP);
demand_empty_rest_of_line ();
@@ -10614,9 +10523,7 @@ s_cpadd (ignore)
/* Add $gp to the register named as an argument. */
reg = tc_get_register (0);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", reg, reg, GP);
demand_empty_rest_of_line ();
Index: mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.14
diff -u -p -d -r1.14 mips.exp
--- mips.exp 2001/06/09 06:25:55 1.14
+++ mips.exp 2001/07/19 19:06:33
@@ -119,6 +119,11 @@ if { [istarget mips*-*-*] } then {
run_list_test "illegal" ""
+ run_dump_test "mips-gp32-fp32"
+ run_dump_test "mips-gp32-fp64"
+ run_dump_test "mips-gp64-fp32"
+ run_dump_test "mips-gp64-fp64"
+
if $svr4pic {
# Make sure that -mcpu=FOO and -mFOO are equivalent. Assemble a file
# containing 4650-specific instructions with -m4650 and -mcpu=4650,
@@ -131,6 +136,11 @@ if { [istarget mips*-*-*] } then {
run_dump_test "elf_e_flags3"
run_dump_test "elf_e_flags4"
+ run_dump_test "mips-gp32-fp32-pic"
+ run_dump_test "mips-gp32-fp64-pic"
+ run_dump_test "mips-gp64-fp32-pic"
+ run_dump_test "mips-gp64-fp64-pic"
+
if [istarget mips*el-*-*] {
run_dump_test "elfel-rel"
} {
--- /dev/null Tue Nov 14 21:44:43 2000
+++ mips-gp32-fp32-pic.s Thu Jul 19 18:24:15 2001
@@ -0,0 +1,139 @@
+
+ .sdata
+shared: .4byte 11
+
+ .data
+ .size unshared,16
+unshared:
+ .4byte 1
+ .4byte 2
+ .4byte 3
+ .4byte 4
+
+ .text
+ .ent func
+func:
+ .set mips4
+ .set noreorder
+ .cpload $25 # 0000 lui gp,hi(_gp_disp)
+ # 0004 addiu gp,gp,lo(_gp_disp)
+ # 0008 addu gp,gp,t9
+ .set reorder
+ .cprestore 8 # 000c sw gp,8(sp)
+ .cpadd $4 # 0010 addu a0,a0,gp
+ li $4, 0x12345678 # 0014 lui a0,0x1234
+ # 0018 ori a0,a0,0x5678
+ la $4, shared # 001c lw a0,got(.sdata)(gp)
+ # 0020 nop
+ # 0024 addiu a0,a0,lo(shared)
+ la $4, unshared # 0028 lw a0,got(.data)(gp)
+ # 002c nop
+ # 0030 addiu a0,a0,lo(unshared)
+ la $4, end # 0034 lw a0,got(.text)(gp)
+ # 0038 nop
+ # 003c addiu a0,a0,lo(end)
+ j end # 0040 b end
+ # 0044 nop
+ jal end # 0048 lw t9,got(.text)(gp)
+ # 004c nop
+ # 0050 addiu t9,t9,lo(end)
+ # 0054 jalr t9
+ # 0058 nop
+ # 005c lw gp,8(sp)
+ lw $4, shared # 0060 lw a0,got(.sdata)(gp)
+ # 0064 nop
+ # 0068 addiu a0,a0,lo(shared)
+ # 006c lw a0,(a0)
+ lw $4, unshared # 0070 lw a0,got(.data)(gp)
+ # 0074 nop
+ # 0078 addiu a0,a0,lo(unshared)
+ # 007c lw a0,(a0)
+ lw $4, end # 0080 lw a0,got(.text)(gp)
+ # 0084 nop
+ # 0088 addiu a0,a0,lo(end)
+ # 008c lw a0,(a0)
+ ld $4, shared # 0090 lw at,got(.sdata)(gp)
+ # 0094 nop
+ # 0098 lw a0,lo(shared)(at)
+ # 009c lw a1,lo(shared)+4(at)
+ ld $4, unshared # 00a0 lw at,got(.data)(gp)
+ # 00a4 nop
+ # 00a8 lw a0,lo(unshared)(at)
+ # 00ac lw a1,lo(unshared)+4(at)
+ ld $4, end # 00b0 lw at,got(.text)(gp)
+ # 00b4 nop
+ # 00b8 lw a0,lo(end)(at)
+ # 00bc lw a1,lo(end)+4(at)
+ sw $4, shared # 00c0 lw at,got(.sdata)(gp)
+ # 00c4 nop
+ # 00c8 addiu at,at,lo(shared)
+ # 00cc sw a0,0(at)
+ sw $4, unshared # 00d0 lw at,got(.data)(gp)
+ # 00d4 nop
+ # 00d8 addiu at,at,lo(unshared)
+ # 00dc sw a0,0(at)
+ sd $4, shared # 00e0 lw at,got(.sdata)(gp)
+ # 00e4 nop
+ # 00e8 sw a0,lo(shared)(at)
+ # 00ec sw a1,lo(shared)+4(at)
+ sd $4, unshared # 00f0 lw at,got(.data)(gp)
+ # 00f4 nop
+ # 00f8 sw a0,lo(unshared)(at)
+ # 00fc sw a1,lo(unshared)+4(at)
+ ulh $4, unshared # 0100 lw at,got(.data)(gp)
+ # 0104 nop
+ # 0108 addiu at,at,lo(unshared)
+ # 010c lb a0,0(at)
+ # 0110 lbu at,1(at)
+ # 0114 sll a0,a0,8
+ # 0118 or a0,a0,at
+ ush $4, unshared # 011c lw at,got(.data)(gp)
+ # 0120 nop
+ # 0124 addiu at,at,lo(unshared)
+ # 0128 sb a0,0(at)
+ # 012c srl a0,a0,8
+ # 0130 sb a0,1(at)
+ # 0134 lbu at,0(at)
+ # 0138 sll a0,a0,8
+ # 013c or a0,a0,at
+ ulw $4, unshared # 0140 lw at,got(.data)(gp)
+ # 0144 nop
+ # 0148 addiu at,at,lo(unshared)
+ # 014c lwl a0,0(at)
+ # 0150 lwr a0,3(at)
+ usw $4, unshared # 0154 lw at,got(.data)(gp)
+ # 0158 nop
+ # 015c addiu at,at,lo(unshared)
+ # 0160 swl a0,0(at)
+ # 0164 swr a0,3(at)
+ li.d $4, 1.0 # 0168 lui a0,0x3ff0
+ # 016c move a1,zero
+ li.d $4, 1.9 # 0170 lw at,got(.rodata)(gp)
+ # 0174 lw a0,lo(F1.9)(at)
+ # 0178 lw a1,lo(F1.9)+4(at)
+ li.d $f0, 1.0 # 017c lui at,0x3ff0
+ # 0180 mtc1 at,$f1
+ # 0184 mtc1 zero,$f0
+ li.d $f0, 1.9 # 0188 lw at,got(.rodata)(gp)
+ # 018c ldc1 $f0,lo(L1.9)(at)
+ seq $4, $5, -100 # 0190 addiu a0,a1,100
+ # 0194 sltiu a0,a0,1
+ sne $4, $5, -100 # 0198 addiu a0,a1,100
+ # 019c sltu a0,zero,a0
+
+# Not available in 32-bit mode
+# dla $4, shared
+# dla $4, unshared
+# uld $4, unshared
+# usd $4, unshared
+
+# Should produce warnings given -mgp32
+# bgt $4, 0x7fffffff, end
+# bgtu $4, 0xffffffff, end
+# ble $4, 0x7fffffff, end
+# bleu $4, 0xffffffff, end
+
+# Should produce warnings given -mfp32
+# add.d $f1, $f2, $f3
+
+end:
--- /dev/null Tue Nov 14 21:44:43 2000
+++ mips-gp32-fp32-pic.d Thu Jul 19 19:24:27 2001
@@ -0,0 +1,111 @@
+#objdump: --prefix-addresses -d -mmips:8000
+#as: -march=8000 -mgp32 -mfp32 -KPIC
+#name: MIPS -mgp32 -mfp32 (SVR4 PIC)
+
+.*: +file format.*
+
+Disassembly of section .text:
+0+000 <[^>]*> lui gp,0x0
+0+004 <[^>]*> addiu gp,gp,0
+0+008 <[^>]*> addu gp,gp,t9
+0+00c <[^>]*> sw gp,8\(sp\)
+0+010 <[^>]*> addu a0,a0,gp
+0+014 <[^>]*> lui a0,0x1234
+0+018 <[^>]*> ori a0,a0,0x5678
+0+01c <[^>]*> lw a0,0\(gp\)
+0+020 <[^>]*> nop
+0+024 <[^>]*> addiu a0,a0,0
+0+028 <[^>]*> lw a0,0\(gp\)
+0+02c <[^>]*> nop
+0+030 <[^>]*> addiu a0,a0,0
+0+034 <[^>]*> lw a0,0\(gp\)
+0+038 <[^>]*> nop
+0+03c <[^>]*> addiu a0,a0,416
+0+040 <[^>]*> b 0+1a0 <[^>]*>
+0+044 <[^>]*> nop
+0+048 <[^>]*> lw t9,0\(gp\)
+0+04c <[^>]*> nop
+0+050 <[^>]*> addiu t9,t9,416
+0+054 <[^>]*> jalr t9
+0+058 <[^>]*> nop
+0+05c <[^>]*> lw gp,8\(sp\)
+0+060 <[^>]*> lw a0,0\(gp\)
+0+064 <[^>]*> nop
+0+068 <[^>]*> addiu a0,a0,0
+0+06c <[^>]*> lw a0,0\(a0\)
+0+070 <[^>]*> lw a0,0\(gp\)
+0+074 <[^>]*> nop
+0+078 <[^>]*> addiu a0,a0,0
+0+07c <[^>]*> lw a0,0\(a0\)
+0+080 <[^>]*> lw a0,0\(gp\)
+0+084 <[^>]*> nop
+0+088 <[^>]*> addiu a0,a0,416
+0+08c <[^>]*> lw a0,0\(a0\)
+0+090 <[^>]*> lw at,0\(gp\)
+0+094 <[^>]*> nop
+0+098 <[^>]*> lw a0,0\(at\)
+0+09c <[^>]*> lw a1,4\(at\)
+0+0a0 <[^>]*> lw at,0\(gp\)
+0+0a4 <[^>]*> nop
+0+0a8 <[^>]*> lw a0,0\(at\)
+0+0ac <[^>]*> lw a1,4\(at\)
+0+0b0 <[^>]*> lw at,0\(gp\)
+0+0b4 <[^>]*> nop
+0+0b8 <[^>]*> lw a0,416\(at\)
+0+0bc <[^>]*> lw a1,420\(at\)
+0+0c0 <[^>]*> lw at,0\(gp\)
+0+0c4 <[^>]*> nop
+0+0c8 <[^>]*> addiu at,at,0
+0+0cc <[^>]*> sw a0,0\(at\)
+0+0d0 <[^>]*> lw at,0\(gp\)
+0+0d4 <[^>]*> nop
+0+0d8 <[^>]*> addiu at,at,0
+0+0dc <[^>]*> sw a0,0\(at\)
+0+0e0 <[^>]*> lw at,0\(gp\)
+0+0e4 <[^>]*> nop
+0+0e8 <[^>]*> sw a0,0\(at\)
+0+0ec <[^>]*> sw a1,4\(at\)
+0+0f0 <[^>]*> lw at,0\(gp\)
+0+0f4 <[^>]*> nop
+0+0f8 <[^>]*> sw a0,0\(at\)
+0+0fc <[^>]*> sw a1,4\(at\)
+0+100 <[^>]*> lw at,0\(gp\)
+0+104 <[^>]*> nop
+0+108 <[^>]*> addiu at,at,0
+0+10c <[^>]*> lb a0,0\(at\)
+0+110 <[^>]*> lbu at,1\(at\)
+0+114 <[^>]*> sll a0,a0,0x8
+0+118 <[^>]*> or a0,a0,at
+0+11c <[^>]*> lw at,0\(gp\)
+0+120 <[^>]*> nop
+0+124 <[^>]*> addiu at,at,0
+0+128 <[^>]*> sb a0,1\(at\)
+0+12c <[^>]*> srl a0,a0,0x8
+0+130 <[^>]*> sb a0,0\(at\)
+0+134 <[^>]*> lbu at,1\(at\)
+0+138 <[^>]*> sll a0,a0,0x8
+0+13c <[^>]*> or a0,a0,at
+0+140 <[^>]*> lw at,0\(gp\)
+0+144 <[^>]*> nop
+0+148 <[^>]*> addiu at,at,0
+0+14c <[^>]*> lwl a0,0\(at\)
+0+150 <[^>]*> lwr a0,3\(at\)
+0+154 <[^>]*> lw at,0\(gp\)
+0+158 <[^>]*> nop
+0+15c <[^>]*> addiu at,at,0
+0+160 <[^>]*> swl a0,0\(at\)
+0+164 <[^>]*> swr a0,3\(at\)
+0+168 <[^>]*> lui a0,0x3ff0
+0+16c <[^>]*> move a1,zero
+0+170 <[^>]*> lw at,0\(gp\)
+0+174 <[^>]*> lw a0,0\(at\)
+0+178 <[^>]*> lw a1,4\(at\)
+0+17c <[^>]*> lui at,0x3ff0
+0+180 <[^>]*> mtc1 at,\$f1
+0+184 <[^>]*> mtc1 zero,\$f0
+0+188 <[^>]*> lw at,0\(gp\)
+0+18c <[^>]*> ldc1 \$f0,8\(at\)
+0+190 <[^>]*> addiu a0,a1,100
+0+194 <[^>]*> sltiu a0,a0,1
+0+198 <[^>]*> addiu a0,a1,100
+0+19c <[^>]*> sltu a0,zero,a0
--- /dev/null Tue Nov 14 21:44:43 2000
+++ mips-gp32-fp32.s Thu Jul 19 19:09:16 2001
@@ -0,0 +1,98 @@
+
+ .sdata
+shared: .4byte 11
+
+ .data
+ .size unshared,16
+unshared:
+ .4byte 1
+ .4byte 2
+ .4byte 3
+ .4byte 4
+
+ .text
+func:
+ .set noreorder
+ .set mips4
+ li $4, 0x12345678 # 0000 lui a0,0x1234
+ # 0004 ori a0,a0,0x5678
+ la $4, shared # 0008 addiu a0,gp,shared
+ la $4, unshared # 000c lui a0,hi(unshared)
+ # 0010 addiu a0,a0,lo(unshared)
+ la $4, end # 0014 lui a0,hi(end)
+ # 0018 addiu a0,a0,lo(end)
+ j end # 001c j end
+ jal end # 0020 jal end
+ lw $4, shared # 0024 lw a0,shared(gp)
+ lw $4, unshared # 0028 lui a0,hi(unshared)
+ # 002c lw a0,lo(unshared)(a0)
+ lw $4, end # 0030 lui a0,hi(end)
+ # 0034 lw a0,lo(end)(a0)
+ ld $4, shared # 0038 lw a0,shared(gp)
+ # 003c lw a1,shared+4(gp)
+ ld $4, unshared # 0040 lui at,hi(unshared)
+ # 0044 lw a0,lo(unshared)(at)
+ # 0048 lw a1,lo(unshared)+4(at)
+ ld $4, end # 004c lui at,hi(end)
+ # 0050 lw a0,lo(end)(at)
+ # 0054 lw a1,lo(end)+4(at)
+ sw $4, shared # 0058 sw a0,shared(gp)
+ sw $4, unshared # 005c lui at,hi(unshared)
+ # 0060 sw a0,lo(unshared)(at)
+ sd $4, shared # 0064 sw a0,shared(gp)
+ # 0068 sw a1,shared+4(gp)
+ sd $4, unshared # 006c lui at,hi(unshared)
+ # 0070 sw a0,lo(unshared)(at)
+ # 0074 sw a1,lo(unshared)+4(at)
+ ulh $4, unshared # 0078 lui at,hi(unshared)
+ # 007c addiu at,at,lo(unshared)
+ # 0080 lb a0,0(at)
+ # 0084 lbu at,1(at)
+ # 0088 sll a0,a0,8
+ # 008c or a0,a0,at
+ ush $4, unshared # 0090 lui at,hi(unshared)
+ # 0094 addiu at,at,lo(unshared)
+ # 0098 sb a0,1(at)
+ # 009c srl a0,a0,8
+ # 00a0 sb a0,0(at)
+ # 00a4 lbu at,1(at)
+ # 00a8 sll a0,a0,8
+ # 00ac or a0,a0,at
+ ulw $4, unshared # 00b0 lui at,hi(unshared)
+ # 00b4 addiu at,at,lo(unshared)
+ # 00b8 lwl a0,0(at)
+ # 00bc lwr a0,3(at)
+ usw $4, unshared # 00c0 lui at,hi(unshared)
+ # 00c4 addiu at,at,lo(unshared)
+ # 00c8 swl a0,0(at)
+ # 00cc swr a0,3(at)
+ li.d $4, 1.0 # 00d0 lui a0,0x3ff0
+ # 00d4 move a1,zero
+ li.d $4, 1.9 # 00d8 lui at,hi(F1.9)
+ # 00dc lw a0,lo(F1.9)(at)
+ # 00e0 lw a1,lo(F1.9)+4(at)
+ li.d $f0, 1.0 # 00e4 lui at,0x3ff0
+ # 00e8 mtc1 at,$f1
+ # 00ec mtc1 zero,$f0
+ li.d $f0, 1.9 # 00f0 ldc1 $f0,L1.9(gp)
+ seq $4, $5, -100 # 00f4 addiu a0,a1,100
+ # 00f8 sltiu a0,a0,1
+ sne $4, $5, -100 # 00fc addiu a0,a1,100
+ # 0100 sltu a0,zero,a0
+
+# Not available in 32-bit mode
+# dla $4, shared
+# dla $4, unshared
+# uld $4, unshared
+# usd $4, unshared
+
+# Should produce warnings given -mgp32
+# bgt $4, 0x7fffffff, end
+# bgtu $4, 0xffffffff, end
+# ble $4, 0x7fffffff, end
+# bleu $4, 0xffffffff, end
+
+# Should produce warnings given -mfp32
+# add.d $f1, $f2, $f3
+
+end:
--- /dev/null Tue Nov 14 21:44:43 2000
+++ mips-gp32-fp32.d Thu Jul 19 19:24:27 2001
@@ -0,0 +1,72 @@
+#objdump: --prefix-addresses -d -mmips:8000
+#as: -march=8000 -mgp32 -mfp32
+#name: MIPS -mgp32 -mfp32
+
+.*: +file format.*
+
+Disassembly of section .text:
+0+000 <[^>]*> lui a0,0x1234
+0+004 <[^>]*> ori a0,a0,0x5678
+0+008 <[^>]*> addiu a0,gp,-16384
+0+00c <[^>]*> lui a0,0x0
+0+010 <[^>]*> addiu a0,a0,0
+0+014 <[^>]*> lui a0,0x0
+0+018 <[^>]*> addiu a0,a0,260
+0+01c <[^>]*> j 0+104 <[^>]*>
+0+020 <[^>]*> jal 0+104 <[^>]*>
+0+024 <[^>]*> lw a0,-16384\(gp\)
+0+028 <[^>]*> lui a0,0x0
+0+02c <[^>]*> lw a0,0\(a0\)
+0+030 <[^>]*> lui a0,0x0
+0+034 <[^>]*> lw a0,260\(a0\)
+0+038 <[^>]*> lw a0,-16384\(gp\)
+0+03c <[^>]*> lw a1,-16380\(gp\)
+0+040 <[^>]*> lui at,0x0
+0+044 <[^>]*> lw a0,0\(at\)
+0+048 <[^>]*> lw a1,4\(at\)
+0+04c <[^>]*> lui at,0x0
+0+050 <[^>]*> lw a0,260\(at\)
+0+054 <[^>]*> lw a1,264\(at\)
+0+058 <[^>]*> sw a0,-16384\(gp\)
+0+05c <[^>]*> lui at,0x0
+0+060 <[^>]*> sw a0,0\(at\)
+0+064 <[^>]*> sw a0,-16384\(gp\)
+0+068 <[^>]*> sw a1,-16380\(gp\)
+0+06c <[^>]*> lui at,0x0
+0+070 <[^>]*> sw a0,0\(at\)
+0+074 <[^>]*> sw a1,4\(at\)
+0+078 <[^>]*> lui at,0x0
+0+07c <[^>]*> addiu at,at,0
+0+080 <[^>]*> lb a0,0\(at\)
+0+084 <[^>]*> lbu at,1\(at\)
+0+088 <[^>]*> sll a0,a0,0x8
+0+08c <[^>]*> or a0,a0,at
+0+090 <[^>]*> lui at,0x0
+0+094 <[^>]*> addiu at,at,0
+0+098 <[^>]*> sb a0,1\(at\)
+0+09c <[^>]*> srl a0,a0,0x8
+0+0a0 <[^>]*> sb a0,0\(at\)
+0+0a4 <[^>]*> lbu at,1\(at\)
+0+0a8 <[^>]*> sll a0,a0,0x8
+0+0ac <[^>]*> or a0,a0,at
+0+0b0 <[^>]*> lui at,0x0
+0+0b4 <[^>]*> addiu at,at,0
+0+0b8 <[^>]*> lwl a0,0\(at\)
+0+0bc <[^>]*> lwr a0,3\(at\)
+0+0c0 <[^>]*> lui at,0x0
+0+0c4 <[^>]*> addiu at,at,0
+0+0c8 <[^>]*> swl a0,0\(at\)
+0+0cc <[^>]*> swr a0,3\(at\)
+0+0d0 <[^>]*> lui a0,0x3ff0
+0+0d4 <[^>]*> move a1,zero
+0+0d8 <[^>]*> lui at,0x0
+0+0dc <[^>]*> lw a0,0\(at\)
+0+0e0 <[^>]*> lw a1,4\(at\)
+0+0e4 <[^>]*> lui at,0x3ff0
+0+0e8 <[^>]*> mtc1 at,\$f1
+0+0ec <[^>]*> mtc1 zero,\$f0
+0+0f0 <[^>]*> ldc1 \$f0,-16384\(gp\)
+0+0f4 <[^>]*> addiu a0,a1,100
+0+0f8 <[^>]*> sltiu a0,a0,1
+0+0fc <[^>]*> addiu a0,a1,100
+0+100 <[^>]*> sltu a0,zero,a0
--- /dev/null Tue Nov 14 21:44:43 2000
+++ mips-gp32-fp64-pic.s Thu Jul 19 18:24:25 2001
@@ -0,0 +1,138 @@
+
+ .sdata
+shared: .4byte 11
+
+ .data
+ .size unshared,16
+unshared:
+ .4byte 1
+ .4byte 2
+ .4byte 3
+ .4byte 4
+
+ .text
+ .ent func
+func:
+ .set mips4
+ .set noreorder
+ .cpload $25 # 0000 lui gp,hi(_gp_disp)
+ # 0004 addiu gp,gp,lo(_gp_disp)
+ # 0008 addu gp,gp,t9
+ .set reorder
+ .cprestore 8 # 000c sw gp,8(sp)
+ .cpadd $4 # 0010 addu a0,a0,gp
+ li $4, 0x12345678 # 0014 lui a0,0x1234
+ # 0018 ori a0,a0,0x5678
+ la $4, shared # 001c lw a0,got(.sdata)(gp)
+ # 0020 nop
+ # 0024 addiu a0,a0,lo(shared)
+ la $4, unshared # 0028 lw a0,got(.data)(gp)
+ # 002c nop
+ # 0030 addiu a0,a0,lo(unshared)
+ la $4, end # 0034 lw a0,got(.text)(gp)
+ # 0038 nop
+ # 003c addiu a0,a0,lo(end)
+ j end # 0040 b end
+ # 0044 nop
+ jal end # 0048 lw t9,got(.text)(gp)
+ # 004c nop
+ # 0050 addiu t9,t9,lo(end)
+ # 0054 jalr t9
+ # 0058 nop
+ # 005c lw gp,8(sp)
+ lw $4, shared # 0060 lw a0,got(.sdata)(gp)
+ # 0064 nop
+ # 0068 addiu a0,a0,lo(shared)
+ # 006c lw a0,(a0)
+ lw $4, unshared # 0070 lw a0,got(.data)(gp)
+ # 0074 nop
+ # 0078 addiu a0,a0,lo(unshared)
+ # 007c lw a0,(a0)
+ lw $4, end # 0080 lw a0,got(.text)(gp)
+ # 0084 nop
+ # 0088 addiu a0,a0,lo(end)
+ # 008c lw a0,(a0)
+ ld $4, shared # 0090 lw at,got(.sdata)(gp)
+ # 0094 nop
+ # 0098 lw a0,lo(shared)(at)
+ # 009c lw a1,lo(shared)+4(at)
+ ld $4, unshared # 00a0 lw at,got(.data)(gp)
+ # 00a4 nop
+ # 00a8 lw a0,lo(unshared)(at)
+ # 00ac lw a1,lo(unshared)+4(at)
+ ld $4, end # 00b0 lw at,got(.text)(gp)
+ # 00b4 nop
+ # 00b8 lw a0,lo(end)(at)
+ # 00bc lw a1,lo(end)+4(at)
+ sw $4, shared # 00c0 lw at,got(.sdata)(gp)
+ # 00c4 nop
+ # 00c8 addiu at,at,lo(shared)
+ # 00cc sw a0,0(at)
+ sw $4, unshared # 00d0 lw at,got(.data)(gp)
+ # 00d4 nop
+ # 00d8 addiu at,at,lo(unshared)
+ # 00dc sw a0,0(at)
+ sd $4, shared # 00e0 lw at,got(.sdata)(gp)
+ # 00e4 nop
+ # 00e8 sw a0,lo(shared)(at)
+ # 00ec sw a1,lo(shared)+4(at)
+ sd $4, unshared # 00f0 lw at,got(.data)(gp)
+ # 00f4 nop
+ # 00f8 sw a0,lo(unshared)(at)
+ # 00fc sw a1,lo(unshared)+4(at)
+ ulh $4, unshared # 0100 lw at,got(.data)(gp)
+ # 0104 nop
+ # 0108 addiu at,at,lo(unshared)
+ # 010c lb a0,0(at)
+ # 0110 lbu at,1(at)
+ # 0114 sll a0,a0,8
+ # 0118 or a0,a0,at
+ ush $4, unshared # 011c lw at,got(.data)(gp)
+ # 0120 nop
+ # 0124 addiu at,at,lo(unshared)
+ # 0128 sb a0,0(at)
+ # 012c srl a0,a0,8
+ # 0130 sb a0,1(at)
+ # 0134 lbu at,0(at)
+ # 0138 sll a0,a0,8
+ # 013c or a0,a0,at
+ ulw $4, unshared # 0140 lw at,got(.data)(gp)
+ # 0144 nop
+ # 0148 addiu at,at,lo(unshared)
+ # 014c lwl a0,0(at)
+ # 0150 lwr a0,3(at)
+ usw $4, unshared # 0154 lw at,got(.data)(gp)
+ # 0158 nop
+ # 015c addiu at,at,lo(unshared)
+ # 0160 swl a0,0(at)
+ # 0164 swr a0,3(at)
+ li.d $4, 1.0 # 0168 lui a0,0x3ff0
+ # 016c move a1,zero
+ li.d $4, 1.9 # 0170 lw at,got(.rodata)(gp)
+ # 0174 lw a0,lo(F1.9)(at)
+ # 0178 lw a1,lo(F1.9)+4(at)
+ li.d $f0, 1.0 # 017c lw at,got(.rodata)(gp)
+ # 0180 ldc1 $f0,lo(L1.0)(at)
+ li.d $f0, 1.9 # 0184 lw at,got(.rodata)(gp)
+ # 0188 ldc1 $f0,lo(L1.9)(at)
+ seq $4, $5, -100 # 018c addiu a0,a1,100
+ # 0190 sltiu a0,a0,1
+ sne $4, $5, -100 # 0194 addiu a0,a1,100
+ # 0198 sltu a0,zero,a0
+
+# Not available in 32-bit mode
+# dla $4, shared
+# dla $4, unshared
+# uld $4, unshared
+# usd $4, unshared
+
+# Should produce warnings given -mgp32
+# bgt $4, 0x7fffffff, end
+# bgtu $4, 0xffffffff, end
+# ble $4, 0x7fffffff, end
+# bleu $4, 0xffffffff, end
+
+# Should produce warnings given -mfp32
+ add.d $f1, $f2, $f3 # 019c add.d $f1,$f2,$f3
+
+end:
--- /dev/null Tue Nov 14 21:44:43 2000
+++ mips-gp32-fp64-pic.d Thu Jul 19 19:24:28 2001
@@ -0,0 +1,111 @@
+#objdump: --prefix-addresses -d -mmips:8000
+#as: -march=8000 -mgp32 -KPIC
+#name: MIPS -mgp32 -mfp64 (SVR4 PIC)
+
+.*: +file format.*
+
+Disassembly of section .text:
+0+000 <[^>]*> lui gp,0x0
+0+004 <[^>]*> addiu gp,gp,0
+0+008 <[^>]*> addu gp,gp,t9
+0+00c <[^>]*> sw gp,8\(sp\)
+0+010 <[^>]*> addu a0,a0,gp
+0+014 <[^>]*> lui a0,0x1234
+0+018 <[^>]*> ori a0,a0,0x5678
+0+01c <[^>]*> lw a0,0\(gp\)
+0+020 <[^>]*> nop
+0+024 <[^>]*> addiu a0,a0,0
+0+028 <[^>]*> lw a0,0\(gp\)
+0+02c <[^>]*> nop
+0+030 <[^>]*> addiu a0,a0,0
+0+034 <[^>]*> lw a0,0\(gp\)
+0+038 <[^>]*> nop
+0+03c <[^>]*> addiu a0,a0,416
+0+040 <[^>]*> b 0+1a0 <[^>]*>
+0+044 <[^>]*> nop
+0+048 <[^>]*> lw t9,0\(gp\)
+0+04c <[^>]*> nop
+0+050 <[^>]*> addiu t9,t9,416
+0+054 <[^>]*> jalr t9
+0+058 <[^>]*> nop
+0+05c <[^>]*> lw gp,8\(sp\)
+0+060 <[^>]*> lw a0,0\(gp\)
+0+064 <[^>]*> nop
+0+068 <[^>]*> addiu a0,a0,0
+0+06c <[^>]*> lw a0,0\(a0\)
+0+070 <[^>]*> lw a0,0\(gp\)
+0+074 <[^>]*> nop
+0+078 <[^>]*> addiu a0,a0,0
+0+07c <[^>]*> lw a0,0\(a0\)
+0+080 <[^>]*> lw a0,0\(gp\)
+0+084 <[^>]*> nop
+0+088 <[^>]*> addiu a0,a0,416
+0+08c <[^>]*> lw a0,0\(a0\)
+0+090 <[^>]*> lw at,0\(gp\)
+0+094 <[^>]*> nop
+0+098 <[^>]*> lw a0,0\(at\)
+0+09c <[^>]*> lw a1,4\(at\)
+0+0a0 <[^>]*> lw at,0\(gp\)
+0+0a4 <[^>]*> nop
+0+0a8 <[^>]*> lw a0,0\(at\)
+0+0ac <[^>]*> lw a1,4\(at\)
+0+0b0 <[^>]*> lw at,0\(gp\)
+0+0b4 <[^>]*> nop
+0+0b8 <[^>]*> lw a0,416\(at\)
+0+0bc <[^>]*> lw a1,420\(at\)
+0+0c0 <[^>]*> lw at,0\(gp\)
+0+0c4 <[^>]*> nop
+0+0c8 <[^>]*> addiu at,at,0
+0+0cc <[^>]*> sw a0,0\(at\)
+0+0d0 <[^>]*> lw at,0\(gp\)
+0+0d4 <[^>]*> nop
+0+0d8 <[^>]*> addiu at,at,0
+0+0dc <[^>]*> sw a0,0\(at\)
+0+0e0 <[^>]*> lw at,0\(gp\)
+0+0e4 <[^>]*> nop
+0+0e8 <[^>]*> sw a0,0\(at\)
+0+0ec <[^>]*> sw a1,4\(at\)
+0+0f0 <[^>]*> lw at,0\(gp\)
+0+0f4 <[^>]*> nop
+0+0f8 <[^>]*> sw a0,0\(at\)
+0+0fc <[^>]*> sw a1,4\(at\)
+0+100 <[^>]*> lw at,0\(gp\)
+0+104 <[^>]*> nop
+0+108 <[^>]*> addiu at,at,0
+0+10c <[^>]*> lb a0,0\(at\)
+0+110 <[^>]*> lbu at,1\(at\)
+0+114 <[^>]*> sll a0,a0,0x8
+0+118 <[^>]*> or a0,a0,at
+0+11c <[^>]*> lw at,0\(gp\)
+0+120 <[^>]*> nop
+0+124 <[^>]*> addiu at,at,0
+0+128 <[^>]*> sb a0,1\(at\)
+0+12c <[^>]*> srl a0,a0,0x8
+0+130 <[^>]*> sb a0,0\(at\)
+0+134 <[^>]*> lbu at,1\(at\)
+0+138 <[^>]*> sll a0,a0,0x8
+0+13c <[^>]*> or a0,a0,at
+0+140 <[^>]*> lw at,0\(gp\)
+0+144 <[^>]*> nop
+0+148 <[^>]*> addiu at,at,0
+0+14c <[^>]*> lwl a0,0\(at\)
+0+150 <[^>]*> lwr a0,3\(at\)
+0+154 <[^>]*> lw at,0\(gp\)
+0+158 <[^>]*> nop
+0+15c <[^>]*> addiu at,at,0
+0+160 <[^>]*> swl a0,0\(at\)
+0+164 <[^>]*> swr a0,3\(at\)
+0+168 <[^>]*> lui a0,0x3ff0
+0+16c <[^>]*> move a1,zero
+0+170 <[^>]*> lw at,0\(gp\)
+0+174 <[^>]*> lw a0,0\(at\)
+0+178 <[^>]*> lw a1,4\(at\)
+0+17c <[^>]*> lw at,0\(gp\)
+0+180 <[^>]*> ldc1 \$f0,8\(at\)
+0+184 <[^>]*> lw at,0\(gp\)
+0+188 <[^>]*> ldc1 \$f0,16\(at\)
+0+18c <[^>]*> addiu a0,a1,100
+0+190 <[^>]*> sltiu a0,a0,1
+0+194 <[^>]*> addiu a0,a1,100
+0+198 <[^>]*> sltu a0,zero,a0
+0+19c <[^>]*> add.d \$f1,\$f2,\$f3
--- /dev/null Tue Nov 14 21:44:43 2000
+++ mips-gp32-fp64.s Thu Jul 19 19:09:05 2001
@@ -0,0 +1,95 @@
+
+ .sdata
+shared: .4byte 11
+
+ .data
+ .size unshared,16
+unshared:
+ .4byte 1
+ .4byte 2
+ .4byte 3
+ .4byte 4
+
+ .text
+func:
+ .set noreorder
+ .set mips4
+ li $4, 0x12345678 # 0000 lui a0,0x1234
+ # 0004 ori a0,a0,0x5678
+ la $4, shared # 0008 addiu a0,gp,shared
+ la $4, unshared # 000c lui a0,hi(unshared)
+ # 0010 addiu a0,a0,lo(unshared)
+ la $4, end # 0014 lui a0,hi(end)
+ # 0018 addiu a0,a0,lo(end)
+ j end # 001c j end
+ jal end # 0020 jal end
+ lw $4, shared # 0024 lw a0,shared(gp)
+ lw $4, unshared # 0028 lui a0,hi(unshared)
+ # 002c lw a0,lo(unshared)(a0)
+ lw $4, end # 0030 lui a0,hi(end)
+ # 0034 lw a0,lo(end)(a0)
+ ld $4, shared # 0038 lw a0,shared(gp)
+ # 003c lw a1,shared+4(gp)
+ ld $4, unshared # 0040 lui at,hi(unshared)
+ # 0044 lw a0,lo(unshared)(at)
+ # 0048 lw a1,lo(unshared)+4(at)
+ ld $4, end # 004c lui at,hi(end)
+ # 0050 lw a0,lo(end)(at)
+ # 0054 lw a1,lo(end)+4(at)
+ sw $4, shared # 0058 sw a0,shared(gp)
+ sw $4, unshared # 005c lui at,hi(unshared)
+ # 0060 sw a0,lo(unshared)(at)
+ sd $4, shared # 0064 sw a0,shared(gp)
+ # 0068 sw a1,shared+4(gp)
+ sd $4, unshared # 006c lui at,hi(unshared)
+ # 0070 sw a0,lo(unshared)(at)
+ # 0074 sw a1,lo(unshared)+4(at)
+ ulh $4, unshared # 0078 lui at,hi(unshared)
+ # 007c addiu at,at,lo(unshared)
+ # 0080 lb a0,0(at)
+ # 0084 lbu at,1(at)
+ # 0088 sll a0,a0,8
+ # 008c or a0,a0,at
+ ush $4, unshared # 0090 lui at,hi(unshared)
+ # 0094 addiu at,at,lo(unshared)
+ # 0098 sb a0,1(at)
+ # 009c srl a0,a0,8
+ # 00a0 sb a0,0(at)
+ # 00a4 lbu at,1(at)
+ # 00a8 sll a0,a0,8
+ # 00ac or a0,a0,at
+ ulw $4, unshared # 00b0 lui at,hi(unshared)
+ # 00b4 addiu at,at,lo(unshared)
+ # 00b8 lwl a0,0(at)
+ # 00bc lwr a0,3(at)
+ usw $4, unshared # 00c0 lui at,hi(unshared)
+ # 00c4 addiu at,at,lo(unshared)
+ # 00c8 swl a0,0(at)
+ # 00cc swr a0,3(at)
+ li.d $4, 1.0 # 00d0 lui a0,0x3ff0
+ # 00d4 move a1,zero
+ li.d $4, 1.9 # 00d8 lui at,hi(F1.9)
+ # 00dc lw a0,lo(F1.9)(at)
+ # 00e0 lw a1,lo(F1.9)+4(at)
+ li.d $f0, 1.0 # 00e4 ldc1 $f0,L1.0(gp)
+ li.d $f0, 1.9 # 00e8 ldc1 $f0,L1.9(gp)
+ seq $4, $5, -100 # 00ec addiu a0,a1,100
+ # 00f0 sltiu a0,a0,1
+ sne $4, $5, -100 # 00f4 addiu a0,a1,100
+ # 00f8 sltu a0,zero,a0
+
+# Not available in 32-bit mode
+# dla $4, shared
+# dla $4, unshared
+# uld $4, unshared
+# usd $4, unshared
+
+# Should produce warnings given -mgp32
+# bgt $4, 0x7fffffff, end
+# bgtu $4, 0xffffffff, end
+# ble $4, 0x7fffffff, end
+# bleu $4, 0xffffffff, end
+
+ add.d $f1, $f2, $f3 # 00fc add.d $f1,$f2,$f3
+
+end:
--- /dev/null Tue Nov 14 21:44:43 2000
+++ mips-gp32-fp64.d Thu Jul 19 19:24:27 2001
@@ -0,0 +1,71 @@
+#objdump: --prefix-addresses -d -mmips:8000
+#as: -march=8000 -mgp32
+#name: MIPS -mgp32 -mfp64
+
+.*: +file format.*
+
+Disassembly of section .text:
+0+000 <[^>]*> lui a0,0x1234
+0+004 <[^>]*> ori a0,a0,0x5678
+0+008 <[^>]*> addiu a0,gp,-16384
+0+00c <[^>]*> lui a0,0x0
+0+010 <[^>]*> addiu a0,a0,0
+0+014 <[^>]*> lui a0,0x0
+0+018 <[^>]*> addiu a0,a0,256
+0+01c <[^>]*> j 0+100 <[^>]*>
+0+020 <[^>]*> jal 0+100 <[^>]*>
+0+024 <[^>]*> lw a0,-16384\(gp\)
+0+028 <[^>]*> lui a0,0x0
+0+02c <[^>]*> lw a0,0\(a0\)
+0+030 <[^>]*> lui a0,0x0
+0+034 <[^>]*> lw a0,256\(a0\)
+0+038 <[^>]*> lw a0,-16384\(gp\)
+0+03c <[^>]*> lw a1,-16380\(gp\)
+0+040 <[^>]*> lui at,0x0
+0+044 <[^>]*> lw a0,0\(at\)
+0+048 <[^>]*> lw a1,4\(at\)
+0+04c <[^>]*> lui at,0x0
+0+050 <[^>]*> lw a0,256\(at\)
+0+054 <[^>]*> lw a1,260\(at\)
+0+058 <[^>]*> sw a0,-16384\(gp\)
+0+05c <[^>]*> lui at,0x0
+0+060 <[^>]*> sw a0,0\(at\)
+0+064 <[^>]*> sw a0,-16384\(gp\)
+0+068 <[^>]*> sw a1,-16380\(gp\)
+0+06c <[^>]*> lui at,0x0
+0+070 <[^>]*> sw a0,0\(at\)
+0+074 <[^>]*> sw a1,4\(at\)
+0+078 <[^>]*> lui at,0x0
+0+07c <[^>]*> addiu at,at,0
+0+080 <[^>]*> lb a0,0\(at\)
+0+084 <[^>]*> lbu at,1\(at\)
+0+088 <[^>]*> sll a0,a0,0x8
+0+08c <[^>]*> or a0,a0,at
+0+090 <[^>]*> lui at,0x0
+0+094 <[^>]*> addiu at,at,0
+0+098 <[^>]*> sb a0,1\(at\)
+0+09c <[^>]*> srl a0,a0,0x8
+0+0a0 <[^>]*> sb a0,0\(at\)
+0+0a4 <[^>]*> lbu at,1\(at\)
+0+0a8 <[^>]*> sll a0,a0,0x8
+0+0ac <[^>]*> or a0,a0,at
+0+0b0 <[^>]*> lui at,0x0
+0+0b4 <[^>]*> addiu at,at,0
+0+0b8 <[^>]*> lwl a0,0\(at\)
+0+0bc <[^>]*> lwr a0,3\(at\)
+0+0c0 <[^>]*> lui at,0x0
+0+0c4 <[^>]*> addiu at,at,0
+0+0c8 <[^>]*> swl a0,0\(at\)
+0+0cc <[^>]*> swr a0,3\(at\)
+0+0d0 <[^>]*> lui a0,0x3ff0
+0+0d4 <[^>]*> move a1,zero
+0+0d8 <[^>]*> lui at,0x0
+0+0dc <[^>]*> lw a0,0\(at\)
+0+0e0 <[^>]*> lw a1,4\(at\)
+0+0e4 <[^>]*> ldc1 \$f0,-16384\(gp\)
+0+0e8 <[^>]*> ldc1 \$f0,-16376\(gp\)
+0+0ec <[^>]*> addiu a0,a1,100
+0+0f0 <[^>]*> sltiu a0,a0,1
+0+0f4 <[^>]*> addiu a0,a1,100
+0+0f8 <[^>]*> sltu a0,zero,a0
+0+0fc <[^>]*> add.d \$f1,\$f2,\$f3
--- /dev/null Tue Nov 14 21:44:43 2000
+++ mips-gp64-fp32-pic.s Thu Jul 19 18:20:17 2001
@@ -0,0 +1,162 @@
+
+ .sdata
+shared: .4byte 11
+
+ .data
+ .size unshared,16
+unshared:
+ .4byte 1
+ .4byte 2
+ .4byte 3
+ .4byte 4
+
+ .text
+ .ent func
+func:
+ .set mips4
+ .set noreorder
+ .cpload $25 # 0000 lui gp,hi(_gp_disp)
+ # 0004 addiu gp,gp,lo(_gp_disp)
+ # 0008 addu gp,gp,t9
+ .set reorder
+ .cprestore 8 # 000c sd gp,8(sp)
+ .cpadd $4 # 0010 daddu a0,a0,gp
+ li $4, 0x12345678 # 0014 lui a0,0x1234
+ # 0018 ori a0,a0,0x5678
+ la $4, shared # 001c lw a0,got(.sdata)(gp)
+ # 0020 nop
+ # 0024 daddiu a0,a0,lo(shared)
+ la $4, unshared # 0028 lw a0,got(.data)(gp)
+ # 002c nop
+ # 0030 daddiu a0,a0,lo(unshared)
+ la $4, end # 0034 lw a0,got(.text)(gp)
+ # 0038 nop
+ # 003c daddiu a0,a0,lo(end)
+ j end # 0040 b end
+ # 0044 nop
+ jal end # 0048 ld t9,got(.text)(gp)
+ # 004c nop
+ # 0050 daddiu t9,t9,lo(end)
+ # 0054 jalr t9
+ # 0058 nop
+ # 005c ld gp,8(sp)
+ lw $4, shared # 0060 ld a0,got(.sdata)(gp)
+ # 0064 nop
+ # 0068 daddiu a0,a0,lo(shared)
+ # 006c lw a0,(a0)
+ lw $4, unshared # 0070 ld a0,got(.data)(gp)
+ # 0074 nop
+ # 0078 daddiu a0,a0,lo(unshared)
+ # 007c lw a0,(a0)
+ lw $4, end # 0080 ld a0,got(.text)(gp)
+ # 0084 nop
+ # 0088 daddiu a0,a0,lo(end)
+ # 008c lw a0,(a0)
+ ld $4, shared # 0090 ld a0,got(.sdata)(gp)
+ # 0094 nop
+ # 0098 daddiu a0,a0,lo(shared)
+ # 009c ld a0,(a0)
+ ld $4, unshared # 00a0 ld a0,got(.data)(gp)
+ # 00a4 nop
+ # 00a8 daddiu a0,a0,lo(unshared)
+ # 00ac ld a0,(a0)
+ ld $4, end # 00b0 ld a0,got(.text)(gp)
+ # 00b4 nop
+ # 00b8 daddiu a0,a0,lo(end)
+ # 00bc ld a0,(a0)
+ sw $4, shared # 00c0 ld at,got(.sdata)(gp)
+ # 00c4 nop
+ # 00c8 daddiu at,at,lo(shared)
+ # 00cc sw a0,0(at)
+ sw $4, unshared # 00d0 ld at,got(.data)(gp)
+ # 00d4 nop
+ # 00d8 daddiu at,at,lo(unshared)
+ # 00dc sw a0,0(at)
+ sd $4, shared # 00e0 ld at,got(.sdata)(gp)
+ # 00e4 nop
+ # 00e8 daddiu at,at,lo(shared)
+ # 00ec sd a0,(at)
+ sd $4, unshared # 00f0 ld at,got(.data)(gp)
+ # 00f4 nop
+ # 00f8 daddiu at,at,lo(unshared)
+ # 00fc sd a0,(at)
+ ulh $4, unshared # 0100 ld at,got(.data)(gp)
+ # 0104 nop
+ # 0108 daddiu at,at,lo(unshared)
+ # 010c lb a0,0(at)
+ # 0110 lbu at,1(at)
+ # 0114 sll a0,a0,8
+ # 0118 or a0,a0,at
+ ush $4, unshared # 011c ld at,got(.data)(gp)
+ # 0120 nop
+ # 0124 daddiu at,at,lo(unshared)
+ # 0128 sb a0,0(at)
+ # 012c srl a0,a0,8
+ # 0130 sb a0,1(at)
+ # 0134 lbu at,0(at)
+ # 0138 sll a0,a0,8
+ # 013c or a0,a0,at
+ ulw $4, unshared # 0140 ld at,got(.data)(gp)
+ # 0144 nop
+ # 0148 daddiu at,at,lo(unshared)
+ # 014c lwl a0,0(at)
+ # 0150 lwr a0,3(at)
+ usw $4, unshared # 0154 ld at,got(.data)(gp)
+ # 0158 nop
+ # 015c daddiu at,at,lo(unshared)
+ # 0160 swl a0,0(at)
+ # 0164 swr a0,3(at)
+ li.d $4, 1.0 # 0168 li a0,0xffc0
+ # 016c dsll32 a0,a0,14
+ li.d $4, 1.9 # 0170 ld at,got(.rodata)(gp)
+ # 0174 ld a0,lo(F1.9)(at)
+ li.d $f0, 1.0 # 0178 lui at,0x3ff0
+ # 017c mtc1 at,$f1
+ # 0180 mtc1 zero,$f0
+ li.d $f0, 1.9 # 0184 ld at,got(.rodata)(gp)
+ # 0188 ldc1 $f0,lo(L1.9)(at)
+ seq $4, $5, -100 # 018c daddiu a0,a1,100
+ # 0190 sltiu a0,a0,1
+ sne $4, $5, -100 # 0194 daddiu a0,a1,100
+ # 0198 sltu a0,zero,a0
+
+ dla $4, shared # 019c ld a0,got(.sdata)(gp)
+ # 01a0 nop
+ # 01a4 daddiu a0,a0,lo(shared)
+ dla $4, unshared # 01a8 ld a0,got(.data)(gp)
+ # 01ac nop
+ # 01b0 daddiu a0,a0,lo(unshared)
+ uld $4, unshared # 01b4 ld at,got(.data)(gp)
+ # 01b8 nop
+ # 01bc daddiu at,at,lo(unshared)
+ # 01c0 ldl a0,0(at)
+ # 01c4 ldr a0,7(at)
+ usd $4, unshared # 01c8 ld at,got(.data)(gp)
+ # 01cc nop
+ # 01d0 daddiu at,at,lo(unshared)
+ # 01d4 sdl a0,0(at)
+ # 01d8 sdr a0,7(at)
+
+ bgt $4, 0x7fffffff, end # 01dc lui at,0x8000
+ # 01e0 slt at,a0,at
+ # 01e4 beqz at,end
+ # 01e8 nop
+ bgtu $4, 0xffffffff, end # 01ec li at,0x8000
+ # 01f0 dsll at,at,17
+ # 01f4 sltu at,a0,at
+ # 01f8 beqz at,end
+ # 01fc nop
+ ble $4, 0x7fffffff, end # 0200 lui at,0x8000
+ # 0204 slt at,a0,at
+ # 0208 bnez at,end
+ # 020c nop
+ bleu $4, 0xffffffff, end # 0210 li at,0x8000
+ # 0214 dsll at,at,17
+ # 0218 sltu at,a0,at
+ # 021c bnez at,end
+ # 0220 nop
+
+# Should produce warnings given -mfp32
+# add.d $f1, $f2, $f3
+
+end:
--- /dev/null Tue Nov 14 21:44:43 2000
+++ mips-gp64-fp32-pic.d Thu Jul 19 19:24:28 2001
@@ -0,0 +1,144 @@
+#objdump: --prefix-addresses -d -mmips:8000
+#as: -march=8000 -mfp32 -KPIC
+#name: MIPS -mgp64 -mfp32 (SVR4 PIC)
+
+.*: +file format.*
+
+Disassembly of section .text:
+0+000 <[^>]*> lui gp,0x0
+0+004 <[^>]*> addiu gp,gp,0
+0+008 <[^>]*> addu gp,gp,t9
+0+00c <[^>]*> sd gp,8\(sp\)
+0+010 <[^>]*> daddu a0,a0,gp
+0+014 <[^>]*> lui a0,0x1234
+0+018 <[^>]*> ori a0,a0,0x5678
+0+01c <[^>]*> lw a0,0\(gp\)
+0+020 <[^>]*> nop
+0+024 <[^>]*> daddiu a0,a0,0
+0+028 <[^>]*> lw a0,0\(gp\)
+0+02c <[^>]*> nop
+0+030 <[^>]*> daddiu a0,a0,0
+0+034 <[^>]*> lw a0,0\(gp\)
+0+038 <[^>]*> nop
+0+03c <[^>]*> daddiu a0,a0,548
+0+040 <[^>]*> b 0+224 <[^>]*>
+0+044 <[^>]*> nop
+0+048 <[^>]*> ld t9,0\(gp\)
+0+04c <[^>]*> nop
+0+050 <[^>]*> daddiu t9,t9,548
+0+054 <[^>]*> jalr t9
+0+058 <[^>]*> nop
+0+05c <[^>]*> ld gp,8\(sp\)
+0+060 <[^>]*> ld a0,0\(gp\)
+0+064 <[^>]*> nop
+0+068 <[^>]*> daddiu a0,a0,0
+0+06c <[^>]*> lw a0,0\(a0\)
+0+070 <[^>]*> ld a0,0\(gp\)
+0+074 <[^>]*> nop
+0+078 <[^>]*> daddiu a0,a0,0
+0+07c <[^>]*> lw a0,0\(a0\)
+0+080 <[^>]*> ld a0,0\(gp\)
+0+084 <[^>]*> nop
+0+088 <[^>]*> daddiu a0,a0,548
+0+08c <[^>]*> lw a0,0\(a0\)
+0+090 <[^>]*> ld a0,0\(gp\)
+0+094 <[^>]*> nop
+0+098 <[^>]*> daddiu a0,a0,0
+0+09c <[^>]*> ld a0,0\(a0\)
+0+0a0 <[^>]*> ld a0,0\(gp\)
+0+0a4 <[^>]*> nop
+0+0a8 <[^>]*> daddiu a0,a0,0
+0+0ac <[^>]*> ld a0,0\(a0\)
+0+0b0 <[^>]*> ld a0,0\(gp\)
+0+0b4 <[^>]*> nop
+0+0b8 <[^>]*> daddiu a0,a0,548
+0+0bc <[^>]*> ld a0,0\(a0\)
+0+0c0 <[^>]*> ld at,0\(gp\)
+0+0c4 <[^>]*> nop
+0+0c8 <[^>]*> daddiu at,at,0
+0+0cc <[^>]*> sw a0,0\(at\)
+0+0d0 <[^>]*> ld at,0\(gp\)
+0+0d4 <[^>]*> nop
+0+0d8 <[^>]*> daddiu at,at,0
+0+0dc <[^>]*> sw a0,0\(at\)
+0+0e0 <[^>]*> ld at,0\(gp\)
+0+0e4 <[^>]*> nop
+0+0e8 <[^>]*> daddiu at,at,0
+0+0ec <[^>]*> sd a0,0\(at\)
+0+0f0 <[^>]*> ld at,0\(gp\)
+0+0f4 <[^>]*> nop
+0+0f8 <[^>]*> daddiu at,at,0
+0+0fc <[^>]*> sd a0,0\(at\)
+0+100 <[^>]*> ld at,0\(gp\)
+0+104 <[^>]*> nop
+0+108 <[^>]*> daddiu at,at,0
+0+10c <[^>]*> lb a0,0\(at\)
+0+110 <[^>]*> lbu at,1\(at\)
+0+114 <[^>]*> sll a0,a0,0x8
+0+118 <[^>]*> or a0,a0,at
+0+11c <[^>]*> ld at,0\(gp\)
+0+120 <[^>]*> nop
+0+124 <[^>]*> daddiu at,at,0
+0+128 <[^>]*> sb a0,1\(at\)
+0+12c <[^>]*> srl a0,a0,0x8
+0+130 <[^>]*> sb a0,0\(at\)
+0+134 <[^>]*> lbu at,1\(at\)
+0+138 <[^>]*> sll a0,a0,0x8
+0+13c <[^>]*> or a0,a0,at
+0+140 <[^>]*> ld at,0\(gp\)
+0+144 <[^>]*> nop
+0+148 <[^>]*> daddiu at,at,0
+0+14c <[^>]*> lwl a0,0\(at\)
+0+150 <[^>]*> lwr a0,3\(at\)
+0+154 <[^>]*> ld at,0\(gp\)
+0+158 <[^>]*> nop
+0+15c <[^>]*> daddiu at,at,0
+0+160 <[^>]*> swl a0,0\(at\)
+0+164 <[^>]*> swr a0,3\(at\)
+0+168 <[^>]*> li a0,0xffc0
+0+16c <[^>]*> dsll32 a0,a0,0xe
+0+170 <[^>]*> ld at,0\(gp\)
+0+174 <[^>]*> ld a0,0\(at\)
+0+178 <[^>]*> lui at,0x3ff0
+0+17c <[^>]*> mtc1 at,\$f1
+0+180 <[^>]*> mtc1 zero,\$f0
+0+184 <[^>]*> ld at,0\(gp\)
+0+188 <[^>]*> ldc1 \$f0,8\(at\)
+0+18c <[^>]*> daddiu a0,a1,100
+0+190 <[^>]*> sltiu a0,a0,1
+0+194 <[^>]*> daddiu a0,a1,100
+0+198 <[^>]*> sltu a0,zero,a0
+0+19c <[^>]*> ld a0,0\(gp\)
+0+1a0 <[^>]*> nop
+0+1a4 <[^>]*> daddiu a0,a0,0
+0+1a8 <[^>]*> ld a0,0\(gp\)
+0+1ac <[^>]*> nop
+0+1b0 <[^>]*> daddiu a0,a0,0
+0+1b4 <[^>]*> ld at,0\(gp\)
+0+1b8 <[^>]*> nop
+0+1bc <[^>]*> daddiu at,at,0
+0+1c0 <[^>]*> ldl a0,0\(at\)
+0+1c4 <[^>]*> ldr a0,7\(at\)
+0+1c8 <[^>]*> ld at,0\(gp\)
+0+1cc <[^>]*> nop
+0+1d0 <[^>]*> daddiu at,at,0
+0+1d4 <[^>]*> sdl a0,0\(at\)
+0+1d8 <[^>]*> sdr a0,7\(at\)
+0+1dc <[^>]*> lui at,0x8000
+0+1e0 <[^>]*> slt at,a0,at
+0+1e4 <[^>]*> beqz at,0+224 <[^>]*>
+0+1e8 <[^>]*> nop
+0+1ec <[^>]*> li at,0x8000
+0+1f0 <[^>]*> dsll at,at,0x11
+0+1f4 <[^>]*> sltu at,a0,at
+0+1f8 <[^>]*> beqz at,0+224 <[^>]*>
+0+1fc <[^>]*> nop
+0+200 <[^>]*> lui at,0x8000
+0+204 <[^>]*> slt at,a0,at
+0+208 <[^>]*> bnez at,0+224 <[^>]*>
+0+20c <[^>]*> nop
+0+210 <[^>]*> li at,0x8000
+0+214 <[^>]*> dsll at,at,0x11
+0+218 <[^>]*> sltu at,a0,at
+0+21c <[^>]*> bnez at,0+224 <[^>]*>
+0+220 <[^>]*> nop
--- /dev/null Tue Nov 14 21:44:43 2000
+++ mips-gp64-fp32.s Thu Jul 19 19:23:40 2001
@@ -0,0 +1,106 @@
+
+ .sdata
+shared: .4byte 11
+
+ .data
+ .size unshared,16
+unshared:
+ .4byte 1
+ .4byte 2
+ .4byte 3
+ .4byte 4
+
+ .text
+func:
+ .set noreorder
+ .set mips4
+ li $4, 0x12345678 # 0000 lui a0,0x1234
+ # 0004 ori a0,a0,0x5678
+ la $4, shared # 0008 daddiu a0,gp,shared
+ la $4, unshared # 000c lui a0,hi(unshared)
+ # 0010 daddiu a0,a0,lo(unshared)
+ la $4, end # 0014 lui a0,hi(end)
+ # 0018 daddiu a0,a0,lo(end)
+ j end # 001c j end
+ jal end # 0020 jal end
+ lw $4, shared # 0024 lw a0,shared(gp)
+ lw $4, unshared # 0028 lui a0,hi(unshared)
+ # 002c lw a0,lo(unshared)(a0)
+ lw $4, end # 0030 lui a0,hi(end)
+ # 0034 lw a0,lo(end)(a0)
+ ld $4, shared # 0038 ld a0,shared(gp)
+ ld $4, unshared # 003c lui a0,hi(unshared)
+ # 0040 ld a0,lo(unshared)(a0)
+ ld $4, end # 0044 lui a0,hi(end)
+ # 0048 ld a0,lo(end)(a0)
+ sw $4, shared # 004c sw a0,shared(gp)
+ sw $4, unshared # 0050 lui at,hi(unshared)
+ # 0054 sw a0,lo(unshared)(at)
+ sd $4, shared # 0058 sd a0,shared(gp)
+ sd $4, unshared # 005c lui at,hi(unshared)
+ # 0060 sd a0,lo(unshared)(at)
+ ulh $4, unshared # 0064 lui at,hi(unshared)
+ # 0068 daddiu at,at,lo(unshared)
+ # 006c lb a0,0(at)
+ # 0070 lbu at,1(at)
+ # 0074 sll a0,a0,8
+ # 0078 or a0,a0,at
+ ush $4, unshared # 007c lui at,hi(unshared)
+ # 0080 daddiu at,at,lo(unshared)
+ # 0084 sb a0,1(at)
+ # 0088 srl a0,a0,8
+ # 008c sb a0,0(at)
+ # 0090 lbu at,1(at)
+ # 0094 sll a0,a0,8
+ # 0098 or a0,a0,at
+ ulw $4, unshared # 009c lui at,hi(unshared)
+ # 00a0 daddiu at,at,lo(unshared)
+ # 00a4 lwl a0,0(at)
+ # 00a8 lwr a0,3(at)
+ usw $4, unshared # 00ac lui at,hi(unshared)
+ # 00b0 daddiu at,at,lo(unshared)
+ # 00b4 swl a0,0(at)
+ # 00b8 swr a0,3(at)
+ li.d $4, 1.0 # 00bc li a0,0xffc0
+ # 00c0 dsll32 a0,a0,14 # giving 0x3ff00000...
+ li.d $4, 1.9 # 00c4 lui at,hi(F1.9)
+ # 00c8 ld a0,lo(F1.9)(at)
+ li.d $f0, 1.0 # 00cc lui at,0x3ff0
+ # 00d0 mtc1 at,$f1
+ # 00d4 mtc1 zero,$f0
+ li.d $f0, 1.9 # 00d8 ldc1 $f0,L1.9(gp)
+ seq $4, $5, -100 # 00dc daddiu a0,a1,100
+ # 00e0 sltiu a0,a0,1
+ sne $4, $5, -100 # 00e4 daddiu a0,a1,100
+ # 00e8 sltu a0,zero,a0
+ dla $4, shared # 00ec daddiu a0,gp,shared
+ dla $4, unshared # 00f0 lui a0,hi(unshared)
+ # 00f4 daddiu a0,a0,lo(unshared)
+ uld $4, unshared # 00f8 lui at,hi(unshared)
+ # 00fc daddiu at,at,lo(unshared)
+ # 0100 ldl a0,0(at)
+ # 0104 ldr a0,7(at)
+ usd $4, unshared # 0108 lui at,hi(unshared)
+ # 010c daddiu at,at,lo(unshared)
+ # 0110 sdl a0,0(at)
+ # 0114 sdr a0,7(at)
+
+ bgt $4, 0x7fffffff, end # 0118 lui at,0x8000
+ # 011c slt at,a0,at
+ # 0120 beqz at,end
+ bgtu $4, 0xffffffff, end # 0124 li at,0x8000
+ # 0128 dsll at,at,17
+ # 012c sltu at,a0,at
+ # 0130 beqz at,end
+ ble $4, 0x7fffffff, end # 0134 lui at,0x8000
+ # 0138 slt at,a0,at
+ # 013c bnez at,end
+ bleu $4, 0xffffffff, end # 0140 li at,0x8000
+ # 0144 dsll at,at,17
+ # 0148 sltu at,a0,at
+ # 014c bnez at,end
+
+# Should produce warnings given -mfp32
+# add.d $f1, $f2, $f3
+
+end:
--- /dev/null Tue Nov 14 21:44:43 2000
+++ mips-gp64-fp32.d Thu Jul 19 19:24:27 2001
@@ -0,0 +1,91 @@
+#objdump: --prefix-addresses -d -mmips:8000
+#as: -march=8000 -mfp32
+#name: MIPS -mgp64 -mfp32
+
+.*: +file format.*
+
+Disassembly of section .text:
+0+000 <[^>]*> lui a0,0x1234
+0+004 <[^>]*> ori a0,a0,0x5678
+0+008 <[^>]*> daddiu a0,gp,-16384
+0+00c <[^>]*> lui a0,0x0
+0+010 <[^>]*> daddiu a0,a0,0
+0+014 <[^>]*> lui a0,0x0
+0+018 <[^>]*> daddiu a0,a0,336
+0+01c <[^>]*> j 0+150 <[^>]*>
+0+020 <[^>]*> jal 0+150 <[^>]*>
+0+024 <[^>]*> lw a0,-16384\(gp\)
+0+028 <[^>]*> lui a0,0x0
+0+02c <[^>]*> lw a0,0\(a0\)
+0+030 <[^>]*> lui a0,0x0
+0+034 <[^>]*> lw a0,336\(a0\)
+0+038 <[^>]*> ld a0,-16384\(gp\)
+0+03c <[^>]*> lui a0,0x0
+0+040 <[^>]*> ld a0,0\(a0\)
+0+044 <[^>]*> lui a0,0x0
+0+048 <[^>]*> ld a0,336\(a0\)
+0+04c <[^>]*> sw a0,-16384\(gp\)
+0+050 <[^>]*> lui at,0x0
+0+054 <[^>]*> sw a0,0\(at\)
+0+058 <[^>]*> sd a0,-16384\(gp\)
+0+05c <[^>]*> lui at,0x0
+0+060 <[^>]*> sd a0,0\(at\)
+0+064 <[^>]*> lui at,0x0
+0+068 <[^>]*> daddiu at,at,0
+0+06c <[^>]*> lb a0,0\(at\)
+0+070 <[^>]*> lbu at,1\(at\)
+0+074 <[^>]*> sll a0,a0,0x8
+0+078 <[^>]*> or a0,a0,at
+0+07c <[^>]*> lui at,0x0
+0+080 <[^>]*> daddiu at,at,0
+0+084 <[^>]*> sb a0,1\(at\)
+0+088 <[^>]*> srl a0,a0,0x8
+0+08c <[^>]*> sb a0,0\(at\)
+0+090 <[^>]*> lbu at,1\(at\)
+0+094 <[^>]*> sll a0,a0,0x8
+0+098 <[^>]*> or a0,a0,at
+0+09c <[^>]*> lui at,0x0
+0+0a0 <[^>]*> daddiu at,at,0
+0+0a4 <[^>]*> lwl a0,0\(at\)
+0+0a8 <[^>]*> lwr a0,3\(at\)
+0+0ac <[^>]*> lui at,0x0
+0+0b0 <[^>]*> daddiu at,at,0
+0+0b4 <[^>]*> swl a0,0\(at\)
+0+0b8 <[^>]*> swr a0,3\(at\)
+0+0bc <[^>]*> li a0,0xffc0
+0+0c0 <[^>]*> dsll32 a0,a0,0xe
+0+0c4 <[^>]*> lui at,0x0
+0+0c8 <[^>]*> ld a0,0\(at\)
+0+0cc <[^>]*> lui at,0x3ff0
+0+0d0 <[^>]*> mtc1 at,\$f1
+0+0d4 <[^>]*> mtc1 zero,\$f0
+0+0d8 <[^>]*> ldc1 \$f0,-16384\(gp\)
+0+0dc <[^>]*> daddiu a0,a1,100
+0+0e0 <[^>]*> sltiu a0,a0,1
+0+0e4 <[^>]*> daddiu a0,a1,100
+0+0e8 <[^>]*> sltu a0,zero,a0
+0+0ec <[^>]*> daddiu a0,gp,-16384
+0+0f0 <[^>]*> lui a0,0x0
+0+0f4 <[^>]*> daddiu a0,a0,0
+0+0f8 <[^>]*> lui at,0x0
+0+0fc <[^>]*> daddiu at,at,0
+0+100 <[^>]*> ldl a0,0\(at\)
+0+104 <[^>]*> ldr a0,7\(at\)
+0+108 <[^>]*> lui at,0x0
+0+10c <[^>]*> daddiu at,at,0
+0+110 <[^>]*> sdl a0,0\(at\)
+0+114 <[^>]*> sdr a0,7\(at\)
+0+118 <[^>]*> lui at,0x8000
+0+11c <[^>]*> slt at,a0,at
+0+120 <[^>]*> beqz at,0+150 <[^>]*>
+0+124 <[^>]*> li at,0x8000
+0+128 <[^>]*> dsll at,at,0x11
+0+12c <[^>]*> sltu at,a0,at
+0+130 <[^>]*> beqz at,0+150 <[^>]*>
+0+134 <[^>]*> lui at,0x8000
+0+138 <[^>]*> slt at,a0,at
+0+13c <[^>]*> bnez at,0+150 <[^>]*>
+0+140 <[^>]*> li at,0x8000
+0+144 <[^>]*> dsll at,at,0x11
+0+148 <[^>]*> sltu at,a0,at
+0+14c <[^>]*> bnez at,0+150 <[^>]*>
--- /dev/null Tue Nov 14 21:44:43 2000
+++ mips-gp64-fp64-pic.s Thu Jul 19 18:23:28 2001
@@ -0,0 +1,161 @@
+
+ .sdata
+shared: .4byte 11
+
+ .data
+ .size unshared,16
+unshared:
+ .4byte 1
+ .4byte 2
+ .4byte 3
+ .4byte 4
+
+ .text
+ .ent func
+func:
+ .set mips4
+ .set noreorder
+ .cpload $25 # 0000 lui gp,hi(_gp_disp)
+ # 0004 addiu gp,gp,lo(_gp_disp)
+ # 0008 addu gp,gp,t9
+ .set reorder
+ .cprestore 8 # 000c sd gp,8(sp)
+ .cpadd $4 # 0010 daddu a0,a0,gp
+ li $4, 0x12345678 # 0014 lui a0,0x1234
+ # 0018 ori a0,a0,0x5678
+ la $4, shared # 001c lw a0,got(.sdata)(gp)
+ # 0020 nop
+ # 0024 daddiu a0,a0,lo(shared)
+ la $4, unshared # 0028 lw a0,got(.data)(gp)
+ # 002c nop
+ # 0030 daddiu a0,a0,lo(unshared)
+ la $4, end # 0034 lw a0,got(.text)(gp)
+ # 0038 nop
+ # 003c daddiu a0,a0,lo(end)
+ j end # 0040 b end
+ # 0044 nop
+ jal end # 0048 ld t9,got(.text)(gp)
+ # 004c nop
+ # 0050 daddiu t9,t9,lo(end)
+ # 0054 jalr t9
+ # 0058 nop
+ # 005c ld gp,8(sp)
+ lw $4, shared # 0060 ld a0,got(.sdata)(gp)
+ # 0064 nop
+ # 0068 daddiu a0,a0,lo(shared)
+ # 006c lw a0,(a0)
+ lw $4, unshared # 0070 ld a0,got(.data)(gp)
+ # 0074 nop
+ # 0078 daddiu a0,a0,lo(unshared)
+ # 007c lw a0,(a0)
+ lw $4, end # 0080 ld a0,got(.text)(gp)
+ # 0084 nop
+ # 0088 daddiu a0,a0,lo(end)
+ # 008c lw a0,(a0)
+ ld $4, shared # 0090 ld a0,got(.sdata)(gp)
+ # 0094 nop
+ # 0098 daddiu a0,a0,lo(shared)
+ # 009c ld a0,(a0)
+ ld $4, unshared # 00a0 ld a0,got(.data)(gp)
+ # 00a4 nop
+ # 00a8 daddiu a0,a0,lo(unshared)
+ # 00ac ld a0,(a0)
+ ld $4, end # 00b0 ld a0,got(.text)(gp)
+ # 00b4 nop
+ # 00b8 daddiu a0,a0,lo(end)
+ # 00bc ld a0,(a0)
+ sw $4, shared # 00c0 ld at,got(.sdata)(gp)
+ # 00c4 nop
+ # 00c8 daddiu at,at,lo(shared)
+ # 00cc sw a0,0(at)
+ sw $4, unshared # 00d0 ld at,got(.data)(gp)
+ # 00d4 nop
+ # 00d8 daddiu at,at,lo(unshared)
+ # 00dc sw a0,0(at)
+ sd $4, shared # 00e0 ld at,got(.sdata)(gp)
+ # 00e4 nop
+ # 00e8 daddiu at,at,lo(shared)
+ # 00ec sd a0,(at)
+ sd $4, unshared # 00f0 ld at,got(.data)(gp)
+ # 00f4 nop
+ # 00f8 daddiu at,at,lo(unshared)
+ # 00fc sd a0,(at)
+ ulh $4, unshared # 0100 ld at,got(.data)(gp)
+ # 0104 nop
+ # 0108 daddiu at,at,lo(unshared)
+ # 010c lb a0,0(at)
+ # 0110 lbu at,1(at)
+ # 0114 sll a0,a0,8
+ # 0118 or a0,a0,at
+ ush $4, unshared # 011c ld at,got(.data)(gp)
+ # 0120 nop
+ # 0124 daddiu at,at,lo(unshared)
+ # 0128 sb a0,0(at)
+ # 012c srl a0,a0,8
+ # 0130 sb a0,1(at)
+ # 0134 lbu at,0(at)
+ # 0138 sll a0,a0,8
+ # 013c or a0,a0,at
+ ulw $4, unshared # 0140 ld at,got(.data)(gp)
+ # 0144 nop
+ # 0148 daddiu at,at,lo(unshared)
+ # 014c lwl a0,0(at)
+ # 0150 lwr a0,3(at)
+ usw $4, unshared # 0154 ld at,got(.data)(gp)
+ # 0158 nop
+ # 015c daddiu at,at,lo(unshared)
+ # 0160 swl a0,0(at)
+ # 0164 swr a0,3(at)
+ li.d $4, 1.0 # 0168 li a0,0xffc0
+ # 016c dsll32 a0,a0,14
+ li.d $4, 1.9 # 0170 ld at,got(.rodata)(gp)
+ # 0174 ld a0,lo(F1.9)(at)
+ li.d $f0, 1.0 # 0178 li at,0xffc0
+ # 017c dsll32 at,at,14
+ # 0180 dmtc1 at,$f0
+ li.d $f0, 1.9 # 0184 ld at,got(.rodata)(gp)
+ # 0188 ldc1 $f0,lo(L1.9)(at)
+ seq $4, $5, -100 # 018c daddiu a0,a1,100
+ # 0190 sltiu a0,a0,1
+ sne $4, $5, -100 # 0194 daddiu a0,a1,100
+ # 0198 sltu a0,zero,a0
+
+ dla $4, shared # 019c ld a0,got(.sdata)(gp)
+ # 01a0 nop
+ # 01a4 daddiu a0,a0,lo(shared)
+ dla $4, unshared # 01a8 ld a0,got(.data)(gp)
+ # 01ac nop
+ # 01b0 daddiu a0,a0,lo(unshared)
+ uld $4, unshared # 01b4 ld at,got(.data)(gp)
+ # 01b8 nop
+ # 01bc daddiu at,at,lo(unshared)
+ # 01c0 ldl a0,0(at)
+ # 01c4 ldr a0,7(at)
+ usd $4, unshared # 01c8 ld at,got(.data)(gp)
+ # 01cc nop
+ # 01d0 daddiu at,at,lo(unshared)
+ # 01d4 sdl a0,0(at)
+ # 01d8 sdr a0,7(at)
+
+ bgt $4, 0x7fffffff, end # 01dc lui at,0x8000
+ # 01e0 slt at,a0,at
+ # 01e4 beqz at,end
+ # 01e8 nop
+ bgtu $4, 0xffffffff, end # 01ec li at,0x8000
+ # 01f0 dsll at,at,17
+ # 01f4 sltu at,a0,at
+ # 01f8 beqz at,end
+ # 01fc nop
+ ble $4, 0x7fffffff, end # 0200 lui at,0x8000
+ # 0204 slt at,a0,at
+ # 0208 bnez at,end
+ # 020c nop
+ bleu $4, 0xffffffff, end # 0210 li at,0x8000
+ # 0214 dsll at,at,17
+ # 0218 sltu at,a0,at
+ # 021c bnez at,end
+ # 0220 nop
+
+ add.d $f1, $f2, $f3 # 0224 add.d $f1,$f2,$f3
+
+end:
--- /dev/null Tue Nov 14 21:44:43 2000
+++ mips-gp64-fp64-pic.d Thu Jul 19 19:24:28 2001
@@ -0,0 +1,145 @@
+#objdump: --prefix-addresses -d -mmips:8000
+#as: -march=8000 -KPIC
+#name: MIPS -mgp64 -mfp64 (SVR4 PIC)
+
+.*: +file format.*
+
+Disassembly of section .text:
+0+000 <[^>]*> lui gp,0x0
+0+004 <[^>]*> addiu gp,gp,0
+0+008 <[^>]*> addu gp,gp,t9
+0+00c <[^>]*> sd gp,8\(sp\)
+0+010 <[^>]*> daddu a0,a0,gp
+0+014 <[^>]*> lui a0,0x1234
+0+018 <[^>]*> ori a0,a0,0x5678
+0+01c <[^>]*> lw a0,0\(gp\)
+0+020 <[^>]*> nop
+0+024 <[^>]*> daddiu a0,a0,0
+0+028 <[^>]*> lw a0,0\(gp\)
+0+02c <[^>]*> nop
+0+030 <[^>]*> daddiu a0,a0,0
+0+034 <[^>]*> lw a0,0\(gp\)
+0+038 <[^>]*> nop
+0+03c <[^>]*> daddiu a0,a0,552
+0+040 <[^>]*> b 0+228 <[^>]*>
+0+044 <[^>]*> nop
+0+048 <[^>]*> ld t9,0\(gp\)
+0+04c <[^>]*> nop
+0+050 <[^>]*> daddiu t9,t9,552
+0+054 <[^>]*> jalr t9
+0+058 <[^>]*> nop
+0+05c <[^>]*> ld gp,8\(sp\)
+0+060 <[^>]*> ld a0,0\(gp\)
+0+064 <[^>]*> nop
+0+068 <[^>]*> daddiu a0,a0,0
+0+06c <[^>]*> lw a0,0\(a0\)
+0+070 <[^>]*> ld a0,0\(gp\)
+0+074 <[^>]*> nop
+0+078 <[^>]*> daddiu a0,a0,0
+0+07c <[^>]*> lw a0,0\(a0\)
+0+080 <[^>]*> ld a0,0\(gp\)
+0+084 <[^>]*> nop
+0+088 <[^>]*> daddiu a0,a0,552
+0+08c <[^>]*> lw a0,0\(a0\)
+0+090 <[^>]*> ld a0,0\(gp\)
+0+094 <[^>]*> nop
+0+098 <[^>]*> daddiu a0,a0,0
+0+09c <[^>]*> ld a0,0\(a0\)
+0+0a0 <[^>]*> ld a0,0\(gp\)
+0+0a4 <[^>]*> nop
+0+0a8 <[^>]*> daddiu a0,a0,0
+0+0ac <[^>]*> ld a0,0\(a0\)
+0+0b0 <[^>]*> ld a0,0\(gp\)
+0+0b4 <[^>]*> nop
+0+0b8 <[^>]*> daddiu a0,a0,552
+0+0bc <[^>]*> ld a0,0\(a0\)
+0+0c0 <[^>]*> ld at,0\(gp\)
+0+0c4 <[^>]*> nop
+0+0c8 <[^>]*> daddiu at,at,0
+0+0cc <[^>]*> sw a0,0\(at\)
+0+0d0 <[^>]*> ld at,0\(gp\)
+0+0d4 <[^>]*> nop
+0+0d8 <[^>]*> daddiu at,at,0
+0+0dc <[^>]*> sw a0,0\(at\)
+0+0e0 <[^>]*> ld at,0\(gp\)
+0+0e4 <[^>]*> nop
+0+0e8 <[^>]*> daddiu at,at,0
+0+0ec <[^>]*> sd a0,0\(at\)
+0+0f0 <[^>]*> ld at,0\(gp\)
+0+0f4 <[^>]*> nop
+0+0f8 <[^>]*> daddiu at,at,0
+0+0fc <[^>]*> sd a0,0\(at\)
+0+100 <[^>]*> ld at,0\(gp\)
+0+104 <[^>]*> nop
+0+108 <[^>]*> daddiu at,at,0
+0+10c <[^>]*> lb a0,0\(at\)
+0+110 <[^>]*> lbu at,1\(at\)
+0+114 <[^>]*> sll a0,a0,0x8
+0+118 <[^>]*> or a0,a0,at
+0+11c <[^>]*> ld at,0\(gp\)
+0+120 <[^>]*> nop
+0+124 <[^>]*> daddiu at,at,0
+0+128 <[^>]*> sb a0,1\(at\)
+0+12c <[^>]*> srl a0,a0,0x8
+0+130 <[^>]*> sb a0,0\(at\)
+0+134 <[^>]*> lbu at,1\(at\)
+0+138 <[^>]*> sll a0,a0,0x8
+0+13c <[^>]*> or a0,a0,at
+0+140 <[^>]*> ld at,0\(gp\)
+0+144 <[^>]*> nop
+0+148 <[^>]*> daddiu at,at,0
+0+14c <[^>]*> lwl a0,0\(at\)
+0+150 <[^>]*> lwr a0,3\(at\)
+0+154 <[^>]*> ld at,0\(gp\)
+0+158 <[^>]*> nop
+0+15c <[^>]*> daddiu at,at,0
+0+160 <[^>]*> swl a0,0\(at\)
+0+164 <[^>]*> swr a0,3\(at\)
+0+168 <[^>]*> li a0,0xffc0
+0+16c <[^>]*> dsll32 a0,a0,0xe
+0+170 <[^>]*> ld at,0\(gp\)
+0+174 <[^>]*> ld a0,0\(at\)
+0+178 <[^>]*> li at,0xffc0
+0+17c <[^>]*> dsll32 at,at,0xe
+0+180 <[^>]*> dmtc1 at,\$f0
+0+184 <[^>]*> ld at,0\(gp\)
+0+188 <[^>]*> ldc1 \$f0,8\(at\)
+0+18c <[^>]*> daddiu a0,a1,100
+0+190 <[^>]*> sltiu a0,a0,1
+0+194 <[^>]*> daddiu a0,a1,100
+0+198 <[^>]*> sltu a0,zero,a0
+0+19c <[^>]*> ld a0,0\(gp\)
+0+1a0 <[^>]*> nop
+0+1a4 <[^>]*> daddiu a0,a0,0
+0+1a8 <[^>]*> ld a0,0\(gp\)
+0+1ac <[^>]*> nop
+0+1b0 <[^>]*> daddiu a0,a0,0
+0+1b4 <[^>]*> ld at,0\(gp\)
+0+1b8 <[^>]*> nop
+0+1bc <[^>]*> daddiu at,at,0
+0+1c0 <[^>]*> ldl a0,0\(at\)
+0+1c4 <[^>]*> ldr a0,7\(at\)
+0+1c8 <[^>]*> ld at,0\(gp\)
+0+1cc <[^>]*> nop
+0+1d0 <[^>]*> daddiu at,at,0
+0+1d4 <[^>]*> sdl a0,0\(at\)
+0+1d8 <[^>]*> sdr a0,7\(at\)
+0+1dc <[^>]*> lui at,0x8000
+0+1e0 <[^>]*> slt at,a0,at
+0+1e4 <[^>]*> beqz at,0+228 <[^>]*>
+0+1e8 <[^>]*> nop
+0+1ec <[^>]*> li at,0x8000
+0+1f0 <[^>]*> dsll at,at,0x11
+0+1f4 <[^>]*> sltu at,a0,at
+0+1f8 <[^>]*> beqz at,0+228 <[^>]*>
+0+1fc <[^>]*> nop
+0+200 <[^>]*> lui at,0x8000
+0+204 <[^>]*> slt at,a0,at
+0+208 <[^>]*> bnez at,0+228 <[^>]*>
+0+20c <[^>]*> nop
+0+210 <[^>]*> li at,0x8000
+0+214 <[^>]*> dsll at,at,0x11
+0+218 <[^>]*> sltu at,a0,at
+0+21c <[^>]*> bnez at,0+228 <[^>]*>
+0+220 <[^>]*> nop
+0+224 <[^>]*> add.d \$f1,\$f2,\$f3
--- /dev/null Tue Nov 14 21:44:43 2000
+++ mips-gp64-fp64.s Thu Jul 19 19:24:18 2001
@@ -0,0 +1,104 @@
+
+ .sdata
+shared: .4byte 11
+
+ .data
+ .size unshared,16
+unshared:
+ .4byte 1
+ .4byte 2
+ .4byte 3
+ .4byte 4
+
+ .text
+func:
+ .set noreorder
+ .set mips4
+ li $4, 0x12345678 # 0000 lui a0,0x1234
+ # 0004 ori a0,a0,0x5678
+ la $4, shared # 0008 daddiu a0,gp,shared
+ la $4, unshared # 000c lui a0,hi(unshared)
+ # 0010 daddiu a0,a0,lo(unshared)
+ la $4, end # 0014 lui a0,hi(end)
+ # 0018 daddiu a0,a0,lo(end)
+ j end # 001c j end
+ jal end # 0020 jal end
+ lw $4, shared # 0024 lw a0,shared(gp)
+ lw $4, unshared # 0028 lui a0,hi(unshared)
+ # 002c lw a0,lo(unshared)(a0)
+ lw $4, end # 0030 lui a0,hi(end)
+ # 0034 lw a0,lo(end)(a0)
+ ld $4, shared # 0038 ld a0,shared(gp)
+ ld $4, unshared # 003c lui a0,hi(unshared)
+ # 0040 ld a0,lo(unshared)(a0)
+ ld $4, end # 0044 lui a0,hi(end)
+ # 0048 ld a0,lo(end)(a0)
+ sw $4, shared # 004c sw a0,shared(gp)
+ sw $4, unshared # 0050 lui at,hi(unshared)
+ # 0054 sw a0,lo(unshared)(at)
+ sd $4, shared # 0058 sd a0,shared(gp)
+ sd $4, unshared # 005c lui at,hi(unshared)
+ # 0060 sd a0,lo(unshared)(at)
+ ulh $4, unshared # 0064 lui at,hi(unshared)
+ # 0068 daddiu at,at,lo(unshared)
+ # 006c lb a0,0(at)
+ # 0070 lbu at,1(at)
+ # 0074 sll a0,a0,8
+ # 0078 or a0,a0,at
+ ush $4, unshared # 007c lui at,hi(unshared)
+ # 0080 daddiu at,at,lo(unshared)
+ # 0084 sb a0,1(at)
+ # 0088 srl a0,a0,8
+ # 008c sb a0,0(at)
+ # 0090 lbu at,1(at)
+ # 0094 sll a0,a0,8
+ # 0098 or a0,a0,at
+ ulw $4, unshared # 009c lui at,hi(unshared)
+ # 00a0 daddiu at,at,lo(unshared)
+ # 00a4 lwl a0,0(at)
+ # 00a8 lwr a0,3(at)
+ usw $4, unshared # 00ac lui at,hi(unshared)
+ # 00b0 daddiu at,at,lo(unshared)
+ # 00b4 swl a0,0(at)
+ # 00b8 swr a0,3(at)
+ li.d $4, 1.0 # 00bc li a0,0xffc0
+ # 00c0 dsll32 a0,a0,14 # giving 0x3ff00000...
+ li.d $4, 1.9 # 00c4 lui at,hi(F1.9)
+ # 00c8 ld a0,lo(F1.9)(at)
+ li.d $f0, 1.0 # 00cc li at,0xffc0
+ # 00d0 dsll32 at,at,14
+ # 00d4 dmtc1 at,$f0
+ li.d $f0, 1.9 # 00d8 ldc1 $f0,L1.9(gp)
+ seq $4, $5, -100 # 00dc daddiu a0,a1,100
+ # 00e0 sltiu a0,a0,1
+ sne $4, $5, -100 # 00e4 daddiu a0,a1,100
+ # 00e8 sltu a0,zero,a0
+ dla $4, shared # 00ec daddiu a0,gp,shared
+ dla $4, unshared # 00f0 lui a0,hi(unshared)
+ # 00f4 daddiu a0,a0,lo(unshared)
+ uld $4, unshared # 00f8 lui at,hi(unshared)
+ # 00fc daddiu at,at,lo(unshared)
+ # 0100 ldl a0,0(at)
+ # 0104 ldr a0,7(at)
+ usd $4, unshared # 0108 lui at,hi(unshared)
+ # 010c daddiu at,at,lo(unshared)
+ # 0110 sdl a0,0(at)
+ # 0114 sdr a0,7(at)
+
+ bgt $4, 0x7fffffff, end # 0118 lui at,0x8000
+ # 011c slt at,a0,at
+ # 0120 beqz at,end
+ bgtu $4, 0xffffffff, end # 0124 li at,0x8000
+ # 0128 dsll at,at,17
+ # 012c sltu at,a0,at
+ # 0130 beqz at,end
+ ble $4, 0x7fffffff, end # 0134 lui at,0x8000
+ # 0138 slt at,a0,at
+ # 013c bnez at,end
+ bleu $4, 0xffffffff, end # 0140 li at,0x8000
+ # 0144 dsll at,at,17
+ # 0148 sltu at,a0,at
+ # 014c bnez at,end
+
+ add.d $f1, $f2, $f3 # 0150 add.d $f1,$f2,$f3
+end:
--- /dev/null Tue Nov 14 21:44:43 2000
+++ mips-gp64-fp64.d Thu Jul 19 19:24:27 2001
@@ -0,0 +1,92 @@
+#objdump: --prefix-addresses -d -mmips:8000
+#as: -march=8000
+#name: MIPS -mgp64 -mfp64
+
+.*: +file format.*
+
+Disassembly of section .text:
+0+000 <[^>]*> lui a0,0x1234
+0+004 <[^>]*> ori a0,a0,0x5678
+0+008 <[^>]*> daddiu a0,gp,-16384
+0+00c <[^>]*> lui a0,0x0
+0+010 <[^>]*> daddiu a0,a0,0
+0+014 <[^>]*> lui a0,0x0
+0+018 <[^>]*> daddiu a0,a0,340
+0+01c <[^>]*> j 0+154 <[^>]*>
+0+020 <[^>]*> jal 0+154 <[^>]*>
+0+024 <[^>]*> lw a0,-16384\(gp\)
+0+028 <[^>]*> lui a0,0x0
+0+02c <[^>]*> lw a0,0\(a0\)
+0+030 <[^>]*> lui a0,0x0
+0+034 <[^>]*> lw a0,340\(a0\)
+0+038 <[^>]*> ld a0,-16384\(gp\)
+0+03c <[^>]*> lui a0,0x0
+0+040 <[^>]*> ld a0,0\(a0\)
+0+044 <[^>]*> lui a0,0x0
+0+048 <[^>]*> ld a0,340\(a0\)
+0+04c <[^>]*> sw a0,-16384\(gp\)
+0+050 <[^>]*> lui at,0x0
+0+054 <[^>]*> sw a0,0\(at\)
+0+058 <[^>]*> sd a0,-16384\(gp\)
+0+05c <[^>]*> lui at,0x0
+0+060 <[^>]*> sd a0,0\(at\)
+0+064 <[^>]*> lui at,0x0
+0+068 <[^>]*> daddiu at,at,0
+0+06c <[^>]*> lb a0,0\(at\)
+0+070 <[^>]*> lbu at,1\(at\)
+0+074 <[^>]*> sll a0,a0,0x8
+0+078 <[^>]*> or a0,a0,at
+0+07c <[^>]*> lui at,0x0
+0+080 <[^>]*> daddiu at,at,0
+0+084 <[^>]*> sb a0,1\(at\)
+0+088 <[^>]*> srl a0,a0,0x8
+0+08c <[^>]*> sb a0,0\(at\)
+0+090 <[^>]*> lbu at,1\(at\)
+0+094 <[^>]*> sll a0,a0,0x8
+0+098 <[^>]*> or a0,a0,at
+0+09c <[^>]*> lui at,0x0
+0+0a0 <[^>]*> daddiu at,at,0
+0+0a4 <[^>]*> lwl a0,0\(at\)
+0+0a8 <[^>]*> lwr a0,3\(at\)
+0+0ac <[^>]*> lui at,0x0
+0+0b0 <[^>]*> daddiu at,at,0
+0+0b4 <[^>]*> swl a0,0\(at\)
+0+0b8 <[^>]*> swr a0,3\(at\)
+0+0bc <[^>]*> li a0,0xffc0
+0+0c0 <[^>]*> dsll32 a0,a0,0xe
+0+0c4 <[^>]*> lui at,0x0
+0+0c8 <[^>]*> ld a0,0\(at\)
+0+0cc <[^>]*> li at,0xffc0
+0+0d0 <[^>]*> dsll32 at,at,0xe
+0+0d4 <[^>]*> dmtc1 at,\$f0
+0+0d8 <[^>]*> ldc1 \$f0,-16384\(gp\)
+0+0dc <[^>]*> daddiu a0,a1,100
+0+0e0 <[^>]*> sltiu a0,a0,1
+0+0e4 <[^>]*> daddiu a0,a1,100
+0+0e8 <[^>]*> sltu a0,zero,a0
+0+0ec <[^>]*> daddiu a0,gp,-16384
+0+0f0 <[^>]*> lui a0,0x0
+0+0f4 <[^>]*> daddiu a0,a0,0
+0+0f8 <[^>]*> lui at,0x0
+0+0fc <[^>]*> daddiu at,at,0
+0+100 <[^>]*> ldl a0,0\(at\)
+0+104 <[^>]*> ldr a0,7\(at\)
+0+108 <[^>]*> lui at,0x0
+0+10c <[^>]*> daddiu at,at,0
+0+110 <[^>]*> sdl a0,0\(at\)
+0+114 <[^>]*> sdr a0,7\(at\)
+0+118 <[^>]*> lui at,0x8000
+0+11c <[^>]*> slt at,a0,at
+0+120 <[^>]*> beqz at,0+154 <[^>]*>
+0+124 <[^>]*> li at,0x8000
+0+128 <[^>]*> dsll at,at,0x11
+0+12c <[^>]*> sltu at,a0,at
+0+130 <[^>]*> beqz at,0+154 <[^>]*>
+0+134 <[^>]*> lui at,0x8000
+0+138 <[^>]*> slt at,a0,at
+0+13c <[^>]*> bnez at,0+154 <[^>]*>
+0+140 <[^>]*> li at,0x8000
+0+144 <[^>]*> dsll at,at,0x11
+0+148 <[^>]*> sltu at,a0,at
+0+14c <[^>]*> bnez at,0+154 <[^>]*>
+0+150 <[^>]*> add.d \$f1,\$f2,\$f3
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: Patch to add -mfp32 support to MIPS gas
2001-07-19 12:46 Patch to add -mfp32 support to MIPS gas Richard Sandiford
@ 2001-07-19 16:11 ` Thiemo Seufer
2001-07-20 0:20 ` Eric Christopher
2001-07-20 1:41 ` Richard Sandiford
0 siblings, 2 replies; 20+ messages in thread
From: Thiemo Seufer @ 2001-07-19 16:11 UTC (permalink / raw)
To: binutils
Richard Sandiford wrote:
>
> At the moment, MIPS gas uses:
>
> ISA_HAS_64BIT_REGS (mips_opts.isa)
>
> to decide what size the registers are and:
>
> bfd_arch_bits_per_address (stdoutput) == 32
> || ! ISA_HAS_64BIT_REGS (mips_opts.isa)
>
> to decide what size addresses are. That isn't as fine grain as GCC, which
> allows the sizes of the FPRs and GPRs to be selected independently.
Just curious: Who needs to set GPR/FPR sizes explicitly on MIPS?
It's usually a ABI property.
[snip]
> +#define HAVE_32BIT_GPRS \
> + (mips_gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
> +
> +#define HAVE_32BIT_FPRS \
> + (mips_fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
> +
> +#define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
> +#define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
> +
> +#define HAVE_32BIT_ADDRESSES \
> + (HAVE_32BIT_GPRS || bfd_arch_bits_per_address (stdoutput) == 32)
How is mips_32bitmode handled WRT this?
[snip]
> @@ -9247,6 +9146,14 @@ md_parse_option (c, arg)
> #endif
> break;
>
> + case OPTION_FP32:
> + mips_fp32 = 1;
> + break;
> +
> + case OPTION_FP64:
> + mips_fp32 = 0;
> + break;
Perhaps there should be some checking for consistency with ABI's
definitions then.
Thiemo
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: Patch to add -mfp32 support to MIPS gas
2001-07-19 16:11 ` Thiemo Seufer
@ 2001-07-20 0:20 ` Eric Christopher
2001-07-20 1:41 ` Richard Sandiford
1 sibling, 0 replies; 20+ messages in thread
From: Eric Christopher @ 2001-07-20 0:20 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: binutils
> Just curious: Who needs to set GPR/FPR sizes explicitly on MIPS?
> It's usually a ABI property.
>
I do actually. There are lots of times when someone will come up with a
chip variant that really is just a small variant, or a piece of software
that only wants to save the bottom 32 bits of registers and you'd like
to get it across to the tools that there really are only 32-bits in the
registers - even if the chip really has 64 bits.
-eric
--
I will not grease the monkey bars
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: Patch to add -mfp32 support to MIPS gas
2001-07-19 16:11 ` Thiemo Seufer
2001-07-20 0:20 ` Eric Christopher
@ 2001-07-20 1:41 ` Richard Sandiford
2001-07-20 12:17 ` Thiemo Seufer
1 sibling, 1 reply; 20+ messages in thread
From: Richard Sandiford @ 2001-07-20 1:41 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: binutils
Thanks for the feedback,
Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de> writes:
> Just curious: Who needs to set GPR/FPR sizes explicitly on MIPS?
> It's usually a ABI property.
Perhaps the -mabi switch should affect registers sizes too. Hopefully the
patch would make it easier for that to happen in the future.
> > +#define HAVE_32BIT_GPRS \
> > + (mips_gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
> > +
> > +#define HAVE_32BIT_FPRS \
> > + (mips_fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
> > +
> > +#define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
> > +#define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
> > +
> > +#define HAVE_32BIT_ADDRESSES \
> > + (HAVE_32BIT_GPRS || bfd_arch_bits_per_address (stdoutput) == 32)
>
> How is mips_32bitmode handled WRT this?
I'm not sure whether you mean "how does mips_32bitmode affect these macros?"
or "how do these macros affect mips_32bitmode?".
For the first, mips_32bitmode gets set if a 32-bit ISA and a 64-bit CPU are
specified on the command line. So if no 64-bit ISA is specified in the
source code, mips_32bitmode already implies HAVE_32BIT_GPRS and
HAVE_32BIT_FPRS.
If a 64-bit ISA *is* specified in the source code, GAS (before and after the
patch) will assume that registers are 64 bits wide while generating code for
that ISA. mips_32bitmode didn't have any effect before the patch, and
doesn't after it. -mgp32 is there for the case when you want GAS to assume
that registers are 32 bits wide even when handling a 64-bit ISA.
As to setting mips_32bitmode if -mgp32 or -mfp32 is specified. Well,
the code has this to say about -mgp32 setting mips_32bitmode:
/* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
flag in object files because to do so would make it
impossible to link with libraries compiled without "-gp32".
This is unnecessarily restrictive.
We could solve this problem by adding "-gp32" multilibs to
gcc, but to set this flag before gcc is built with such
multilibs will break too many systems. */
#if 0
mips_32bitmode = 1;
#endif
I thought the same argument would apply to -mfp32.
> Perhaps there should be some checking for consistency with ABI's
> definitions then.
If the chosen ABI does affect GAS's handling of registers in the future, I
agree it should check for consistency then. But I'd rather save ABI
handling for another day.
Richard
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: Patch to add -mfp32 support to MIPS gas
2001-07-20 1:41 ` Richard Sandiford
@ 2001-07-20 12:17 ` Thiemo Seufer
2001-07-23 10:00 ` Richard Sandiford
0 siblings, 1 reply; 20+ messages in thread
From: Thiemo Seufer @ 2001-07-20 12:17 UTC (permalink / raw)
To: binutils
Richard Sandiford wrote:
[snip]
> As to setting mips_32bitmode if -mgp32 or -mfp32 is specified. Well,
> the code has this to say about -mgp32 setting mips_32bitmode:
>
> /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
> flag in object files because to do so would make it
> impossible to link with libraries compiled without "-gp32".
> This is unnecessarily restrictive.
>
> We could solve this problem by adding "-gp32" multilibs to
> gcc, but to set this flag before gcc is built with such
> multilibs will break too many systems. */
> #if 0
> mips_32bitmode = 1;
> #endif
>
> I thought the same argument would apply to -mfp32.
Ok, that looks reasonable.
Another Question, what happens if somebody specifies
"-mips1 -mcpu=r10000 -mfp=64" ? AFAICS it sets mips_32bitmode
and uses 64bit FPR's, which creates bad ELF object files.
The -mgp* options avoid this trap by setting mips_64 accordingly.
I don't know what would be appropriate for -mfp* here.
Thiemo
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: Patch to add -mfp32 support to MIPS gas
2001-07-20 12:17 ` Thiemo Seufer
@ 2001-07-23 10:00 ` Richard Sandiford
2001-07-23 12:05 ` Thiemo Seufer
0 siblings, 1 reply; 20+ messages in thread
From: Richard Sandiford @ 2001-07-23 10:00 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: binutils
Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de> writes:
> Another Question, what happens if somebody specifies
> "-mips1 -mcpu=r10000 -mfp=64" ? AFAICS it sets mips_32bitmode
> and uses 64bit FPR's, which creates bad ELF object files.
Is your objection is that it's possible to silently link executables
assembled with -mfp32 with others assembled with -mfp64? There's no
separate ELF header bit to indicate the FPR size, so I don't see how
we can avoid that.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: Patch to add -mfp32 support to MIPS gas
2001-07-23 10:00 ` Richard Sandiford
@ 2001-07-23 12:05 ` Thiemo Seufer
2001-07-24 7:01 ` Richard Sandiford
0 siblings, 1 reply; 20+ messages in thread
From: Thiemo Seufer @ 2001-07-23 12:05 UTC (permalink / raw)
To: binutils
Richard Sandiford wrote:
> Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de> writes:
>
> > Another Question, what happens if somebody specifies
> > "-mips1 -mcpu=r10000 -mfp=64" ? AFAICS it sets mips_32bitmode
> > and uses 64bit FPR's, which creates bad ELF object files.
>
> Is your objection is that it's possible to silently link executables
> assembled with -mfp32 with others assembled with -mfp64?
Err, no, and it's not really a objection, I only see some
potential conflict:
mips_32bitmode sets the EF_MIPS_32BITMODE flag. As far as I
understood the ELF format this guarantees the execution system
that only 32bit wide regs are used. This leads to two questions:
- Does the flags meaning include fp regs? It's AFAIK not
explicitly stated, but since the flags use is to provide
backward compatibility, I assume yes.
- Do the toolchains of People using -mfp64 care about the
EF_MIPS_32BITMODE flag?
Thiemo
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: Patch to add -mfp32 support to MIPS gas
2001-07-23 12:05 ` Thiemo Seufer
@ 2001-07-24 7:01 ` Richard Sandiford
2001-07-24 13:37 ` Thiemo Seufer
0 siblings, 1 reply; 20+ messages in thread
From: Richard Sandiford @ 2001-07-24 7:01 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: binutils
Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de> writes:
> > Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de> writes:
> >
> > > Another Question, what happens if somebody specifies
> > > "-mips1 -mcpu=r10000 -mfp=64" ? AFAICS it sets mips_32bitmode
> > > and uses 64bit FPR's, which creates bad ELF object files.
Sorry, I should have read that more carefully. Those options will make GAS
use 32-bit FPRs. The patch was to provide a way of forcing registers to be
32 bits wide on a 64-bit ISA, but not the other way round. As for why...
The current behaviour of -mgp* options seems to be that -mgp32 forces GAS to
use 32-bit GPRs when a 64-bit ISA is selected (at least in some contexts).
Unless I'm missing something, -mgp64 is essentially a no-op in that it does
not force the use of 64-bit registers on a 32-bit ISA. I'm not sure it
would make sense for it to do so.
My patch duplicates that behaviour for -mfp* and FPRs. And again, I don't
think it makes sense for -mfp64 to force the use of 64-bit registers on a
32-bit ISA.
Which begs the question, why have -mfp64 at all?
I think I may have been unduly influenced by GCC here. When I looked at
macro-generating code in GAS, I saw that some code depended on the FPR size,
some depended on the GPR size, and some depended on the address size. But
it often wasn't explicitly stated which. It seemed a good idea to have
separate macros for each size, if only to make the code clearer. And once
those macros were in, it seemed natural enough to add GCC's -mfp* options to
GAS. I think you've convinced me that those options aren't so great after
all.
What I want is a way of making GAS use the 32-bit variants of macros when
the O32 ABI is used on a 64-bit ISA. Note that "gas -mips4 -mabi=32" will
currently generate the 64-bit versions of macros.
In your first reply, you said that register size ought to be affected by the
ABI. Would it be OK to make -mabi=32 imply that the registers are 32 bits
wide, regardless of the chosen CPU and ISA?
Richard
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: Patch to add -mfp32 support to MIPS gas
2001-07-24 7:01 ` Richard Sandiford
@ 2001-07-24 13:37 ` Thiemo Seufer
2001-07-25 8:00 ` Richard Sandiford
0 siblings, 1 reply; 20+ messages in thread
From: Thiemo Seufer @ 2001-07-24 13:37 UTC (permalink / raw)
To: binutils
Richard Sandiford wrote:
[snip]
> The current behaviour of -mgp* options seems to be that -mgp32 forces GAS to
> use 32-bit GPRs when a 64-bit ISA is selected (at least in some contexts).
> Unless I'm missing something, -mgp64 is essentially a no-op in that it does
> not force the use of 64-bit registers on a 32-bit ISA.
-gp64 sets the mips_64 flag and unsets mips_gp32, so it implies the
effect of -64, but without checking for compiled in 64bit support
first. This is likely to be another bug in the current CVS code.
This also means your desription of -mgp64 as "no effect but accepted for
symmetry" is misleading.
> I'm not sure it
> would make sense for it to do so.
Well, I don't see the sense of it either. I must admit I'm worried
about the subtle side effects of these options and how they are
intended to be used.
> My patch duplicates that behaviour for -mfp* and FPRs. And again, I don't
> think it makes sense for -mfp64 to force the use of 64-bit registers on a
> 32-bit ISA.
A 32bit MIPS chip with 64bit FP would be a really weird thing.
I think (hope) there does none exist.
> Which begs the question, why have -mfp64 at all?
To add the next question: Why have -mgp64 at all?
> I think I may have been unduly influenced by GCC here. When I looked at
> macro-generating code in GAS, I saw that some code depended on the FPR size,
> some depended on the GPR size, and some depended on the address size. But
> it often wasn't explicitly stated which. It seemed a good idea to have
> separate macros for each size, if only to make the code clearer.
It's surely a win to have one point in the code where such checks
are defined.
> And once
> those macros were in, it seemed natural enough to add GCC's -mfp* options to
> GAS. I think you've convinced me that those options aren't so great after
> all.
the *32 variants might be useful in contexts where ABI-conformance
isn't an issue, as Eric already explained. The problem with the
*64 variants is that they can't made to be simple inverses of *32,
so it's IMHO better to leave them out.
> What I want is a way of making GAS use the 32-bit variants of macros when
> the O32 ABI is used on a 64-bit ISA. Note that "gas -mips4 -mabi=32" will
> currently generate the 64-bit versions of macros.
>
> In your first reply, you said that register size ought to be affected by the
> ABI. Would it be OK to make -mabi=32 imply that the registers are 32 bits
> wide, regardless of the chosen CPU and ISA?
AFAICS yes, it should imply GPR=32 and FPR=32.
Thiemo
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: Patch to add -mfp32 support to MIPS gas
2001-07-24 13:37 ` Thiemo Seufer
@ 2001-07-25 8:00 ` Richard Sandiford
2001-07-26 4:30 ` Thiemo Seufer
2001-07-30 8:33 ` Eric Christopher
0 siblings, 2 replies; 20+ messages in thread
From: Richard Sandiford @ 2001-07-25 8:00 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: binutils
Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de> writes:
> -gp64 sets the mips_64 flag and unsets mips_gp32, so it implies the
> effect of -64, but without checking for compiled in 64bit support
> first. This is likely to be another bug in the current CVS code.
>
> This also means your desription of -mgp64 as "no effect but accepted for
> symmetry" is misleading.
OK.
> > Which begs the question, why have -mfp64 at all?
>
> To add the next question: Why have -mgp64 at all?
Indeed. I'd rather not remove it as part of this patch, but it would
be nice if someone who's used it could say what it's supposed to do.
> the *32 variants might be useful in contexts where ABI-conformance
> isn't an issue, as Eric already explained. The problem with the
> *64 variants is that they can't made to be simple inverses of *32,
> so it's IMHO better to leave them out.
OK.
> > What I want is a way of making GAS use the 32-bit variants of macros when
> > the O32 ABI is used on a 64-bit ISA. Note that "gas -mips4 -mabi=32" will
> > currently generate the 64-bit versions of macros.
> >
> > In your first reply, you said that register size ought to be affected by
> > the ABI. Would it be OK to make -mabi=32 imply that the registers are
> > 32 bits wide, regardless of the chosen CPU and ISA?
>
> AFAICS yes, it should imply GPR=32 and FPR=32.
OK, I've attached a revised patch below. I think it makes more sense than
the original (thanks again for the feedback). The new patch only adds
-mfp32, not -mfp64; it doesn't include -mgp64 in the usage printout; and it
uses 32-bit registers if -mabi=32 is given.
The test cases are the same as before, except that -EB should be passed to
the assembler, and that there's now an extra abi32 case. I haven't included
them again since they're rather big.
Tested on mips-elf. mipsel-elf and mips64-elf. OK to apply?
[gas/ChangeLog]
* tc-mips.c (mips_fp32, mips_32bit_abi): New static variables.
(md_long_opts): Add -mfp32 option.
(md_parse_option): Handle it. Set mips_32bit_abi given -mabi=32.
(md_show_usage): Show usage for -mfp32 and -mgp32.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): New macros.
(HAVE_64BIT_GPRS, HAVE_64BIT_FPRS): New macros, inverse of the above.
(HAVE_32BIT_ADDRESSES): New macro.
(load_register): Use HAVE_32BIT_GPRS to determine the register width.
(load_address): Use HAVE_32BIT_ADDRESSES to determine the address size.
(s_cprestore, s_cpadd): Likewise.
(macro): Use HAVE_32BIT_GPRS to determine the width of registers
used in branch and M_LI_D macros. Use HAVE_64BIT_FPRS to determine
the width registers used in M_LI_DD macros. Use HAVE_32BIT_ADDRESSES
to determine the width of addresses in load, store and jump macros.
(macro2): Use HAVE_32BIT_GPRS to determine the width of registers
used in set instructions; do not check the address size for them.
Use HAVE_32BIT_ADDRESSES to determine the width of addresses in
unaligned load and store macros.
(mips_ip): Use the new macros to check the width of a register when
processing float constants. Force a constant into memory if it is
destined for an FPR and the FPRs are wider than the GPRs. Warn about
odd FPR numbers if HAVE_32BIT_FPRS.
[gas/testsuite/ChangeLog]
* gas/mips/mips-gp32-fp32,
* gas/mips/mips-gp32-fp64,
* gas/mips/mips-gp64-fp32,
* gas/mips/mips-gp64-fp64,
* gas/mips/mips-abi32
* gas/mips/mips-gp32-fp32-pic,
* gas/mips/mips-gp32-fp64-pic,
* gas/mips/mips-gp64-fp32-pic,
* gas/mips/mips-gp64-fp64-pic,
* gas/mips/mips-abi32-pic: New testcases.
* gas/mips/mips.exp: Run them.
Index: config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.53
diff -u -p -d -r1.53 tc-mips.c
--- config/tc-mips.c 2001/07/23 13:03:40 1.53
+++ config/tc-mips.c 2001/07/25 14:29:28
@@ -229,6 +229,12 @@ static int mips_32bitmode = 0;
/* True if -mgp32 was passed. */
static int mips_gp32 = 0;
+/* True if -mfp32 was passed. */
+static int mips_fp32 = 0;
+
+/* True if the selected ABI is defined for 32-bit registers only. */
+static int mips_32bit_abi = 0;
+
/* Some ISA's have delay slots for instructions which read or write
from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
Return true if instructions marked INSN_LOAD_COPROC_DELAY,
@@ -251,6 +257,23 @@ static int mips_gp32 = 0;
|| (ISA) == ISA_MIPS64 \
)
+#define HAVE_32BIT_GPRS \
+ (mips_gp32 \
+ || mips_32bit_abi \
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
+
+#define HAVE_32BIT_FPRS \
+ (mips_fp32 \
+ || mips_32bit_abi \
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
+
+#define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
+#define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
+
+#define HAVE_32BIT_ADDRESSES \
+ (HAVE_32BIT_GPRS \
+ || bfd_arch_bits_per_address (stdoutput) == 32)
+
/* Whether the processor uses hardware interlocks to protect
reads from the HI and LO registers, and thus does not
require nops to be inserted. */
@@ -3008,9 +3031,9 @@ load_register (counter, reg, ep, dbl)
|| ! ep->X_unsigned
|| sizeof (ep->X_add_number) > 4
|| (ep->X_add_number & 0x80000000) == 0))
- || ((! ISA_HAS_64BIT_REGS (mips_opts.isa) || ! dbl)
+ || ((HAVE_32BIT_GPRS || ! dbl)
&& (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
- || (! ISA_HAS_64BIT_REGS (mips_opts.isa)
+ || (HAVE_32BIT_GPRS
&& ! dbl
&& ((ep->X_add_number &~ (offsetT) 0xffffffff)
== ~ (offsetT) 0xffffffff)))
@@ -3027,7 +3050,7 @@ load_register (counter, reg, ep, dbl)
/* The value is larger than 32 bits. */
- if (! ISA_HAS_64BIT_REGS (mips_opts.isa))
+ if (HAVE_32BIT_GPRS)
{
as_bad (_("Number larger than 32 bits"));
macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
@@ -3269,9 +3292,7 @@ load_address (counter, reg, ep)
{
frag_grow (20);
macro_build ((char *) NULL, counter, ep,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL);
p = frag_var (rs_machine_dependent, 8, 0,
RELAX_ENCODE (4, 8, 0, 4, 0,
@@ -3282,9 +3303,7 @@ load_address (counter, reg, ep)
if (p != NULL)
p += 4;
macro_build (p, counter, ep,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
}
else if (mips_pic == SVR4_PIC && ! mips_big_got)
@@ -3302,18 +3321,14 @@ load_address (counter, reg, ep)
ep->X_add_number = 0;
frag_grow (20);
macro_build ((char *) NULL, counter, ep,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP);
macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
p = frag_var (rs_machine_dependent, 4, 0,
RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
ep->X_add_symbol, (offsetT) 0, (char *) NULL);
macro_build (p, counter, ep,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
if (ex.X_add_number != 0)
{
@@ -3321,9 +3336,7 @@ load_address (counter, reg, ep)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
ex.X_op = O_constant;
macro_build ((char *) NULL, counter, &ex,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
}
}
@@ -3352,14 +3365,10 @@ load_address (counter, reg, ep)
macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
(int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, counter, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", reg, reg, GP);
macro_build ((char *) NULL, counter, ep,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
p = frag_var (rs_machine_dependent, 12 + off, 0,
RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
@@ -3375,17 +3384,13 @@ load_address (counter, reg, ep)
p += 4;
}
macro_build (p, counter, ep,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP);
p += 4;
macro_build (p, counter, (expressionS *) NULL, "nop", "");
p += 4;
macro_build (p, counter, ep,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
if (ex.X_add_number != 0)
{
@@ -3393,9 +3398,7 @@ load_address (counter, reg, ep)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
ex.X_op = O_constant;
macro_build ((char *) NULL, counter, &ex,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
}
}
@@ -3405,9 +3408,7 @@ load_address (counter, reg, ep)
addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
*/
macro_build ((char *) NULL, counter, ep,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL);
}
else
@@ -3614,7 +3615,7 @@ macro (ip)
case M_BGT_I:
/* check for > max integer */
maxnum = 0x7fffffff;
- if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4)
+ if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
{
maxnum <<= 16;
maxnum |= 0xffff;
@@ -3623,7 +3624,7 @@ macro (ip)
}
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number >= maxnum
- && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4))
+ && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
{
do_false:
/* result is always false */
@@ -3667,7 +3668,7 @@ macro (ip)
return;
}
maxnum = 0x7fffffff;
- if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4)
+ if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
{
maxnum <<= 16;
maxnum |= 0xffff;
@@ -3677,7 +3678,7 @@ macro (ip)
maxnum = - maxnum - 1;
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number <= maxnum
- && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4))
+ && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
{
do_true:
/* result is always true */
@@ -3714,7 +3715,7 @@ macro (ip)
likely = 1;
case M_BGTU_I:
if (sreg == 0
- || (! ISA_HAS_64BIT_REGS (mips_opts.isa)
+ || (HAVE_32BIT_GPRS
&& imm_expr.X_op == O_constant
&& imm_expr.X_add_number == 0xffffffff))
goto do_false;
@@ -3810,7 +3811,7 @@ macro (ip)
likely = 1;
case M_BLE_I:
maxnum = 0x7fffffff;
- if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4)
+ if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
{
maxnum <<= 16;
maxnum |= 0xffff;
@@ -3819,7 +3820,7 @@ macro (ip)
}
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number >= maxnum
- && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4))
+ && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
goto do_true;
if (imm_expr.X_op != O_constant)
as_bad (_("Unsupported large constant"));
@@ -3872,7 +3873,7 @@ macro (ip)
likely = 1;
case M_BLEU_I:
if (sreg == 0
- || (! ISA_HAS_64BIT_REGS (mips_opts.isa)
+ || (HAVE_32BIT_GPRS
&& imm_expr.X_op == O_constant
&& imm_expr.X_add_number == 0xffffffff))
goto do_true;
@@ -4170,9 +4171,7 @@ macro (ip)
macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
treg, (int) BFD_RELOC_PCREL_HI16_S);
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16);
return;
}
@@ -4213,9 +4212,7 @@ macro (ip)
{
frag_grow (20);
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL);
p = frag_var (rs_machine_dependent, 8, 0,
RELAX_ENCODE (4, 8, 0, 4, 0,
@@ -4227,9 +4224,7 @@ macro (ip)
if (p != NULL)
p += 4;
macro_build (p, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
}
else if (mips_pic == SVR4_PIC && ! mips_big_got)
@@ -4300,9 +4295,7 @@ macro (ip)
p += 4;
}
macro_build (p, &icnt, &expr1,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
/* FIXME: If breg == 0, and the next instruction uses
$tempreg, then if this variant case is used an extra
@@ -4314,9 +4307,7 @@ macro (ip)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
"nop", "");
macro_build ((char *) NULL, &icnt, &expr1,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
(void) frag_var (rs_machine_dependent, 0, 0,
RELAX_ENCODE (0, 0, -12, -4, 0, 0),
@@ -4341,9 +4332,7 @@ macro (ip)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
"nop", "");
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", treg, AT, breg);
breg = 0;
tempreg = treg;
@@ -4358,14 +4347,10 @@ macro (ip)
mips_optimize = hold_mips_optimize;
macro_build ((char *) NULL, &icnt, &expr1,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", AT, AT, (int) BFD_RELOC_LO16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", tempreg, tempreg, AT);
(void) frag_var (rs_machine_dependent, 0, 0,
RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
@@ -4435,9 +4420,7 @@ macro (ip)
macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
tempreg, lui_reloc_type);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", tempreg, tempreg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
dbl ? "ld" : "lw",
@@ -4473,9 +4456,7 @@ macro (ip)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
"nop", "");
macro_build ((char *) NULL, &icnt, &expr1,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
@@ -4508,9 +4489,7 @@ macro (ip)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
"nop", "");
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", treg, AT, breg);
dreg = treg;
adj = 8;
@@ -4524,14 +4503,10 @@ macro (ip)
mips_optimize = hold_mips_optimize;
macro_build ((char *) NULL, &icnt, &expr1,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", AT, AT, (int) BFD_RELOC_LO16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", dreg, dreg, AT);
p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
@@ -4563,9 +4538,7 @@ macro (ip)
macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
p += 4;
macro_build (p, &icnt, &expr1,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
/* FIXME: If add_number is 0, and there was no base
register, the external symbol case ended with a load,
@@ -4583,9 +4556,7 @@ macro (ip)
macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
p += 4;
macro_build (p, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", treg, AT, breg);
p += 4;
tempreg = treg;
@@ -4597,15 +4568,11 @@ macro (ip)
macro_build_lui (p, &icnt, &expr1, AT);
p += 4;
macro_build (p, &icnt, &expr1,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", AT, AT, (int) BFD_RELOC_LO16);
p += 4;
macro_build (p, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", tempreg, tempreg, AT);
p += 4;
}
@@ -4616,9 +4583,7 @@ macro (ip)
addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
*/
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL);
}
else
@@ -4626,9 +4591,7 @@ macro (ip)
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", treg, tempreg, breg);
if (! used_at)
@@ -4670,9 +4633,7 @@ macro (ip)
{
expr1.X_add_number = mips_cprestore_offset;
macro_build ((char *) NULL, &icnt, &expr1,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg);
}
}
@@ -4713,9 +4674,7 @@ macro (ip)
if (! mips_big_got)
{
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_CALL16, GP);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
@@ -4736,14 +4695,10 @@ macro (ip)
macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
@@ -4759,9 +4714,7 @@ macro (ip)
p += 4;
}
macro_build (p, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_GOT16, GP);
p += 4;
@@ -4769,9 +4722,7 @@ macro (ip)
p += 4;
}
macro_build (p, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", PIC_CALL_REG, PIC_CALL_REG,
(int) BFD_RELOC_LO16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
@@ -4785,9 +4736,7 @@ macro (ip)
"nop", "");
expr1.X_add_number = mips_cprestore_offset;
macro_build ((char *) NULL, &icnt, &expr1,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", GP, (int) BFD_RELOC_LO16,
mips_frame_reg);
}
@@ -5042,9 +4991,7 @@ macro (ip)
{
frag_grow (28);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", tempreg, breg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
treg, (int) BFD_RELOC_MIPS_GPREL, tempreg);
@@ -5057,9 +5004,7 @@ macro (ip)
if (p != NULL)
p += 4;
macro_build (p, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", tempreg, tempreg, breg);
if (p != NULL)
p += 4;
@@ -5092,9 +5037,7 @@ macro (ip)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
frag_grow (20);
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
p = frag_var (rs_machine_dependent, 4, 0,
@@ -5102,15 +5045,11 @@ macro (ip)
offset_expr.X_add_symbol, (offsetT) 0,
(char *) NULL);
macro_build (p, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", tempreg, tempreg, breg);
macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
(int) BFD_RELOC_LO16, tempreg);
@@ -5149,14 +5088,10 @@ macro (ip)
macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", tempreg, tempreg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
tempreg);
p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
@@ -5168,23 +5103,17 @@ macro (ip)
p += 4;
}
macro_build (p, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
p += 4;
macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
p += 4;
macro_build (p, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", tempreg, tempreg, breg);
macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
(int) BFD_RELOC_LO16, tempreg);
@@ -5207,9 +5136,7 @@ macro (ip)
else
{
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", tempreg, breg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
treg, (int) BFD_RELOC_MIPS_GPREL, tempreg);
@@ -5253,13 +5180,13 @@ macro (ip)
}
case M_LI_D:
- /* If we have a constant in IMM_EXPR, then in mips3 mode it is
- the entire value, and in mips1 mode it is the high order 32
- bits of the value and the low order 32 bits are either zero
- or in offset_expr. */
+ /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
+ wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
+ order 32 bits of the value and the low order 32 bits are either
+ zero or in OFFSET_EXPR. */
if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
{
- if (ISA_HAS_64BIT_REGS (mips_opts.isa))
+ if (HAVE_64BIT_GPRS)
load_register (&icnt, treg, &imm_expr, 1);
else
{
@@ -5303,9 +5230,7 @@ macro (ip)
else if (mips_pic == SVR4_PIC)
{
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
}
else if (mips_pic == EMBEDDED_PIC)
@@ -5313,9 +5238,7 @@ macro (ip)
/* For embedded PIC we pick up the entire address off $gp in
a single instruction. */
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
"t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL);
offset_expr.X_op = O_constant;
offset_expr.X_add_number = 0;
@@ -5324,7 +5247,7 @@ macro (ip)
abort ();
/* Now we load the register(s). */
- if (ISA_HAS_64BIT_REGS (mips_opts.isa))
+ if (HAVE_64BIT_GPRS)
macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
treg, (int) BFD_RELOC_LO16, AT);
else
@@ -5349,16 +5272,20 @@ macro (ip)
break;
case M_LI_DD:
- /* If we have a constant in IMM_EXPR, then in mips3 mode it is
- the entire value, and in mips1 mode it is the high order 32
- bits of the value and the low order 32 bits are either zero
- or in offset_expr. */
+ /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
+ wide, IMM_EXPR is the entire value and the GPRs are known to be 64
+ bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
+ the value and the low order 32 bits are either zero or in
+ OFFSET_EXPR. */
if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
{
- load_register (&icnt, AT, &imm_expr, ISA_HAS_64BIT_REGS (mips_opts.isa));
- if (ISA_HAS_64BIT_REGS (mips_opts.isa))
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- "dmtc1", "t,S", AT, treg);
+ load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
+ if (HAVE_64BIT_FPRS)
+ {
+ assert (HAVE_64BIT_GPRS);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
+ "dmtc1", "t,S", AT, treg);
+ }
else
{
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
@@ -5397,9 +5324,7 @@ macro (ip)
assert (strcmp (s, RDATA_SECTION_NAME) == 0);
if (mips_pic == SVR4_PIC)
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
else
{
@@ -5503,7 +5428,7 @@ macro (ip)
goto ldd_std;
case M_LD_AB:
- if (ISA_HAS_64BIT_REGS (mips_opts.isa))
+ if (HAVE_64BIT_GPRS)
{
s = "ld";
goto ld;
@@ -5514,7 +5439,7 @@ macro (ip)
goto ldd_std;
case M_SD_AB:
- if (ISA_HAS_64BIT_REGS (mips_opts.isa))
+ if (HAVE_64BIT_GPRS)
{
s = "sd";
goto st;
@@ -5576,9 +5501,7 @@ macro (ip)
{
frag_grow (36);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, breg, GP);
tempreg = AT;
off = 4;
@@ -5634,9 +5557,7 @@ macro (ip)
if (breg != 0)
{
macro_build (p, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, breg, AT);
if (p != NULL)
p += 4;
@@ -5683,16 +5604,12 @@ macro (ip)
off = 4;
frag_grow (24 + off);
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, breg, AT);
/* Itbl support may require additional care here. */
macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
@@ -5752,21 +5669,15 @@ macro (ip)
macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
AT, (int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, AT, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, breg, AT);
/* Itbl support may require additional care here. */
macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
@@ -5796,9 +5707,7 @@ macro (ip)
p += 4;
}
macro_build (p, &icnt, &offset_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "lw" : "ld"),
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
p += 4;
macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
@@ -5806,9 +5715,7 @@ macro (ip)
if (breg != 0)
{
macro_build (p, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, breg, AT);
p += 4;
}
@@ -5847,9 +5754,7 @@ macro (ip)
else
{
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, breg, GP);
tempreg = AT;
used_at = 1;
@@ -5879,8 +5784,7 @@ macro (ip)
case M_SD_OB:
s = "sw";
sd_ob:
- assert (bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa));
+ assert (HAVE_32BIT_ADDRESSES);
macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
(int) BFD_RELOC_LO16, breg);
offset_expr.X_add_number += 4;
@@ -6174,9 +6078,7 @@ macro2 (ip)
{
imm_expr.X_add_number = -imm_expr.X_add_number;
macro_build ((char *) NULL, &icnt, &imm_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_GPRS ? "addiu" : "daddiu",
"t,r,j", dreg, sreg,
(int) BFD_RELOC_LO16);
used_at = 0;
@@ -6327,9 +6229,7 @@ macro2 (ip)
as_warn (_("Instruction %s: result is always true"),
ip->insn_mo->name);
macro_build ((char *) NULL, &icnt, &expr1,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_GPRS ? "addiu" : "daddiu",
"t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
return;
}
@@ -6347,9 +6247,7 @@ macro2 (ip)
{
imm_expr.X_add_number = -imm_expr.X_add_number;
macro_build ((char *) NULL, &icnt, &imm_expr,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addiu" : "daddiu"),
+ HAVE_32BIT_GPRS ? "addiu" : "daddiu",
"t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
used_at = 0;
}
@@ -6516,9 +6414,7 @@ macro2 (ip)
load_address (&icnt, AT, &offset_expr);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, AT, breg);
if (! target_big_endian)
expr1.X_add_number = off;
@@ -6539,9 +6435,7 @@ macro2 (ip)
load_address (&icnt, AT, &offset_expr);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, AT, breg);
if (target_big_endian)
expr1.X_add_number = 0;
@@ -6613,9 +6507,7 @@ macro2 (ip)
load_address (&icnt, AT, &offset_expr);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, AT, breg);
if (! target_big_endian)
expr1.X_add_number = off;
@@ -6635,9 +6527,7 @@ macro2 (ip)
load_address (&icnt, AT, &offset_expr);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", AT, AT, breg);
if (! target_big_endian)
expr1.X_add_number = 0;
@@ -7496,7 +7386,7 @@ mips_ip (str, ip)
as_bad (_("Invalid float register number (%d)"), regno);
if ((regno & 1) != 0
- && ! ISA_HAS_64BIT_REGS (mips_opts.isa)
+ && HAVE_32BIT_FPRS
&& ! (strcmp (str, "mtc1") == 0
|| strcmp (str, "mfc1") == 0
|| strcmp (str, "lwc1") == 0
@@ -7570,6 +7460,7 @@ mips_ip (str, ip)
case 'l':
{
int f64;
+ int using_gprs;
char *save_in;
char *err;
unsigned char temp[8];
@@ -7603,9 +7494,15 @@ mips_ip (str, ip)
.lit4 inline easily; we need to put .lit8
somewhere in the data segment, and using .lit8
permits the linker to eventually combine identical
- .lit8 entries). */
+ .lit8 entries).
+
+ The code below needs to know whether the target register
+ is 32 or 64 bits wide. It relies on the fact 'f' and
+ 'F' are used with GPR-based instructions and 'l' and
+ 'L' are used with FPR-based instructions. */
f64 = *args == 'F' || *args == 'L';
+ using_gprs = *args == 'F' || *args == 'f';
save_in = input_line_pointer;
input_line_pointer = s;
@@ -7638,18 +7535,24 @@ mips_ip (str, ip)
}
else if (length > 4
&& ! mips_disable_float_construction
+ /* Constants can only be constructed in GPRs and
+ copied to FPRs if the GPRs are at least as wide
+ as the FPRs. Force the constant into memory if
+ we are using 64-bit FPRs but the GPRs are only
+ 32 bits wide. */
+ && (using_gprs
+ || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
&& ((temp[0] == 0 && temp[1] == 0)
|| (temp[2] == 0 && temp[3] == 0))
&& ((temp[4] == 0 && temp[5] == 0)
|| (temp[6] == 0 && temp[7] == 0)))
{
- /* The value is simple enough to load with a
- couple of instructions. In mips1 mode, set
- imm_expr to the high order 32 bits and
- offset_expr to the low order 32 bits.
- Otherwise, set imm_expr to the entire 64 bit
- constant. */
- if (! ISA_HAS_64BIT_REGS (mips_opts.isa))
+ /* The value is simple enough to load with a couple of
+ instructions. If using 32-bit registers, set
+ imm_expr to the high order 32 bits and offset_expr to
+ the low order 32 bits. Otherwise, set imm_expr to
+ the entire 64 bit constant. */
+ if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
{
imm_expr.X_op = O_constant;
offset_expr.X_op = O_constant;
@@ -7820,7 +7723,7 @@ mips_ip (str, ip)
&& imm_expr.X_op == O_constant)
|| (more
&& imm_expr.X_add_number < 0
- && ISA_HAS_64BIT_REGS (mips_opts.isa)
+ && HAVE_64BIT_GPRS
&& imm_expr.X_unsigned
&& sizeof (imm_expr.X_add_number) <= 4))
{
@@ -8945,6 +8848,8 @@ struct option md_longopts[] =
{"march", required_argument, NULL, OPTION_MARCH},
#define OPTION_MTUNE (OPTION_MD_BASE + 32)
{"mtune", required_argument, NULL, OPTION_MTUNE},
+#define OPTION_FP32 (OPTION_MD_BASE + 33)
+ {"mfp32", no_argument, NULL, OPTION_FP32},
#ifdef OBJ_ELF
#define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
#define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
@@ -9247,13 +9152,20 @@ md_parse_option (c, arg)
#endif
break;
+ case OPTION_FP32:
+ mips_fp32 = 1;
+ break;
+
case OPTION_MABI:
if (strcmp (arg, "32") == 0
|| strcmp (arg, "n32") == 0
|| strcmp (arg, "64") == 0
|| strcmp (arg, "o64") == 0
|| strcmp (arg, "eabi") == 0)
- mips_abi_string = arg;
+ {
+ mips_abi_string = arg;
+ mips_32bit_abi = (strcmp (arg, "32") == 0);
+ }
break;
case OPTION_M7000_HILO_FIX:
@@ -9369,6 +9281,8 @@ MIPS options:\n\
-mips16 generate mips16 instructions\n\
-no-mips16 do not generate mips16 instructions\n"));
fprintf (stream, _("\
+-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
+-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
-O0 remove unneeded NOPs, do not swap branches\n\
-O remove unneeded NOPs and swap branches\n\
-n warn about NOPs generated from macros\n\
@@ -10546,9 +10460,7 @@ s_cprestore (ignore)
ex.X_add_number = mips_cprestore_offset;
macro_build ((char *) NULL, &icnt, &ex,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "sw" : "sd"),
+ HAVE_32BIT_ADDRESSES ? "sw" : "sd",
"t,o(b)", GP, (int) BFD_RELOC_LO16, SP);
demand_empty_rest_of_line ();
@@ -10614,9 +10526,7 @@ s_cpadd (ignore)
/* Add $gp to the register named as an argument. */
reg = tc_get_register (0);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
+ HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", reg, reg, GP);
demand_empty_rest_of_line ();
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: Patch to add -mfp32 support to MIPS gas
2001-07-25 8:00 ` Richard Sandiford
@ 2001-07-26 4:30 ` Thiemo Seufer
2001-07-30 8:33 ` Eric Christopher
1 sibling, 0 replies; 20+ messages in thread
From: Thiemo Seufer @ 2001-07-26 4:30 UTC (permalink / raw)
To: binutils
Richard Sandiford wrote:
[snip]
> OK, I've attached a revised patch below. I think it makes more sense than
> the original (thanks again for the feedback). The new patch only adds
> -mfp32, not -mfp64; it doesn't include -mgp64 in the usage printout; and it
> uses 32-bit registers if -mabi=32 is given.
>
> The test cases are the same as before, except that -EB should be passed to
> the assembler, and that there's now an extra abi32 case. I haven't included
> them again since they're rather big.
>
> Tested on mips-elf. mipsel-elf and mips64-elf. OK to apply?
Looks good IMHO.
Thiemo
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: Patch to add -mfp32 support to MIPS gas
2001-07-25 8:00 ` Richard Sandiford
2001-07-26 4:30 ` Thiemo Seufer
@ 2001-07-30 8:33 ` Eric Christopher
2001-07-31 5:31 ` Richard Sandiford
1 sibling, 1 reply; 20+ messages in thread
From: Eric Christopher @ 2001-07-30 8:33 UTC (permalink / raw)
To: Richard Sandiford; +Cc: Thiemo Seufer, binutils
> Tested on mips-elf. mipsel-elf and mips64-elf. OK to apply?
>
I think they are ok, but since there was discussion I'll give everyone
until tomorrow to object :)
Actually, you can use this time to document the options and include it
in your final patch :)
-eric
>
> [gas/ChangeLog]
>
> * tc-mips.c (mips_fp32, mips_32bit_abi): New static variables.
> (md_long_opts): Add -mfp32 option.
> (md_parse_option): Handle it. Set mips_32bit_abi given -mabi=32.
> (md_show_usage): Show usage for -mfp32 and -mgp32.
> (HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): New macros.
> (HAVE_64BIT_GPRS, HAVE_64BIT_FPRS): New macros, inverse of the above.
> (HAVE_32BIT_ADDRESSES): New macro.
> (load_register): Use HAVE_32BIT_GPRS to determine the register width.
> (load_address): Use HAVE_32BIT_ADDRESSES to determine the address size.
> (s_cprestore, s_cpadd): Likewise.
> (macro): Use HAVE_32BIT_GPRS to determine the width of registers
> used in branch and M_LI_D macros. Use HAVE_64BIT_FPRS to determine
> the width registers used in M_LI_DD macros. Use HAVE_32BIT_ADDRESSES
> to determine the width of addresses in load, store and jump macros.
> (macro2): Use HAVE_32BIT_GPRS to determine the width of registers
> used in set instructions; do not check the address size for them.
> Use HAVE_32BIT_ADDRESSES to determine the width of addresses in
> unaligned load and store macros.
> (mips_ip): Use the new macros to check the width of a register when
> processing float constants. Force a constant into memory if it is
> destined for an FPR and the FPRs are wider than the GPRs. Warn about
> odd FPR numbers if HAVE_32BIT_FPRS.
>
> [gas/testsuite/ChangeLog]
>
> * gas/mips/mips-gp32-fp32,
> * gas/mips/mips-gp32-fp64,
> * gas/mips/mips-gp64-fp32,
> * gas/mips/mips-gp64-fp64,
> * gas/mips/mips-abi32
> * gas/mips/mips-gp32-fp32-pic,
> * gas/mips/mips-gp32-fp64-pic,
> * gas/mips/mips-gp64-fp32-pic,
> * gas/mips/mips-gp64-fp64-pic,
> * gas/mips/mips-abi32-pic: New testcases.
>
> * gas/mips/mips.exp: Run them.
>
--
Look out behind you!
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: Patch to add -mfp32 support to MIPS gas
2001-07-30 8:33 ` Eric Christopher
@ 2001-07-31 5:31 ` Richard Sandiford
2001-07-31 5:44 ` Eric Christopher
0 siblings, 1 reply; 20+ messages in thread
From: Richard Sandiford @ 2001-07-31 5:31 UTC (permalink / raw)
To: Eric Christopher; +Cc: Richard Sandiford, Thiemo Seufer, binutils
[-- Attachment #1: Type: text/plain, Size: 21 bytes --]
application/t-bzip2
[-- Attachment #2: bin00000.bin --]
[-- Type: application/x-bzip2, Size: 13292 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: Patch to add -mfp32 support to MIPS gas
2001-07-31 5:31 ` Richard Sandiford
@ 2001-07-31 5:44 ` Eric Christopher
2001-07-31 6:02 ` Richard Sandiford
0 siblings, 1 reply; 20+ messages in thread
From: Eric Christopher @ 2001-07-31 5:44 UTC (permalink / raw)
To: Richard Sandiford; +Cc: Thiemo Seufer, binutils
Since no one has any further objections...
Approved.
-eric
--
Look out behind you!
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: Patch to add -mfp32 support to MIPS gas
2001-07-31 5:44 ` Eric Christopher
@ 2001-07-31 6:02 ` Richard Sandiford
2001-07-31 9:02 ` Ian Lance Taylor
[not found] ` <mailpost.996584774.27152@postal.sibyte.com>
0 siblings, 2 replies; 20+ messages in thread
From: Richard Sandiford @ 2001-07-31 6:02 UTC (permalink / raw)
To: Eric Christopher; +Cc: Richard Sandiford, Thiemo Seufer, binutils
Eric Christopher <echristo@redhat.com> writes:
> Since no one has any further objections...
Sorry, I screwed up the mime stuff, so the text part didn't come through...
The patch below includes the documentation.
In the second patch, I failed to pick up on the fact that the way the "move"
instruction is expanded depends on mips_gp32. The patch below makes it
depend on HAVE_32BIT_GPRS instead, so that the 32-bit version gets used when
a 32-bit ABI is selected. I've added a move test to the testcases.
But, can anyone explain these entries in mips-opc.c:
{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, M1|G6 },/* or */
{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, M3 },/* daddu */
{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, M1 },/* addu */
{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, M1 },/* or */
The archives say that "addu" is preferred to "or" because some processors
have two addition units but only a single logic unit:
< http://sources.redhat.com/ml/binutils/1999-10/msg00132.html >
But why that last entry? And why not use "addu" for -mgp32 as well?
Richard
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: Patch to add -mfp32 support to MIPS gas
2001-07-31 6:02 ` Richard Sandiford
@ 2001-07-31 9:02 ` Ian Lance Taylor
[not found] ` <mailpost.996584774.27152@postal.sibyte.com>
1 sibling, 0 replies; 20+ messages in thread
From: Ian Lance Taylor @ 2001-07-31 9:02 UTC (permalink / raw)
To: Richard Sandiford; +Cc: Eric Christopher, Thiemo Seufer, binutils
Richard Sandiford <r.sandiford@redhat.com> writes:
> But, can anyone explain these entries in mips-opc.c:
>
> {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, M1|G6 },/* or */
> {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, M3 },/* daddu */
> {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, M1 },/* addu */
> {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, M1 },/* or */
>
> The archives say that "addu" is preferred to "or" because some processors
> have two addition units but only a single logic unit:
>
> < http://sources.redhat.com/ml/binutils/1999-10/msg00132.html >
>
> But why that last entry?
The last entry is there for the disassembler.
> And why not use "addu" for -mgp32 as well?
I don't know.
Ian
^ permalink raw reply [flat|nested] 20+ messages in thread
* MIPS pseudo-insns and Re: Patch to add -mfp32 support to MIPSgas
[not found] ` <mailpost.996584774.27152@postal.sibyte.com>
@ 2001-08-03 16:38 ` cgd
2001-08-03 19:02 ` MIPS pseudo-insns and Re: Patch to add -mfp32 support toMIPS gas cgd
0 siblings, 1 reply; 20+ messages in thread
From: cgd @ 2001-08-03 16:38 UTC (permalink / raw)
To: r.sandiford; +Cc: binutils, echristo
First, no good deed goes unpunished. For doing the good deed of
adding test cases... there are new test failures:
Test: Fails on:
MIPS -mgp32 -mfp32 (a) (b)
MIPS -mgp32 -mfp64 (a) (b)
MIPS -mgp64 -mfp32 (a) (b)
MIPS -mgp64 -mfp64 (a) (b)
MIPS -mabi=32 (a) (b)
MIPS -mgp32 -mfp32 (SVR4 PIC) (a)
MIPS -mgp32 -mfp64 (SVR4 PIC) (a)
MIPS -mgp64 -mfp32 (SVR4 PIC) (a)
MIPS -mgp64 -mfp64 (SVR4 PIC) (a)
MIPS -mabi=32 (SVR4 PIC) (a)
(a): mips-linux, mipsel-linux, mips64-linux, mips64el-linux
(b): mips-ecoff, mipsel-ecoff
I didn't spend any time looking into them, other fish to fry. I was
just boggled by the sheer amount of output generated by the little
script that i used to check for failures from my 10-target builds.
(mips-elf, mipsel-el, mips64-elf, mips64el-elf look OK, in case you're
wondering what else i tried. 8-)
r.sandiford@redhat.com ("Richard Sandiford") writes:
> In the second patch, I failed to pick up on the fact that the way the "move"
> instruction is expanded depends on mips_gp32. The patch below makes it
> depend on HAVE_32BIT_GPRS instead, so that the 32-bit version gets used when
> a 32-bit ABI is selected. I've added a move test to the testcases.
>
> But, can anyone explain these entries in mips-opc.c:
>
> {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, M1|G6 },/* or */
> {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, M3 },/* daddu */
> {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, M1 },/* addu */
> {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, M1 },/* or */
>
> The archives say that "addu" is preferred to "or" because some processors
> have two addition units but only a single logic unit:
>
> < http://sources.redhat.com/ml/binutils/1999-10/msg00132.html >
>
> But why that last entry? And why not use "addu" for -mgp32 as well?
I think the notion with the last entry is so that a correctly-shaped
'or' will disassemble to as 'move'.
Personally, I think that's a bug, since i think it'd be nice to be
able to go:
* assemble 1
* disassemble 1
* possibly trivial modifications to get syntax right
* assemble 2
* disassemble 2
and get the same output from the two different 'assemble' passes, and
get the same output from the two different 'disassemble' passes.
that would mean that in My Little World 'disassemble' shouldn't spit
out pseudo-ops names for instructions (if those could then be
re-assembled differently).
But it gets better than that!
We now have -mtune, so we can rationally decide based on the processor
type how to implement 'li' and 'move'!
Yes, it's a micro-optimization, but in terms of the actual work done
by the compiler and assembler it should be approximately free (and why
blow the cycles if you really can tune well).
To the above ends, i would:
(1) remove all entries for 'li' and 'move' in the current mips opcode
table and replace them with M_LI and M_MOVE entries respectively.
(That would alos allow the instructions to disassemble as their actual
instruction opcodes.)
(2) in M_LI and M_MOVE, use an equivalent of the existing algorithm
for picking instructions but in the case where CPUs are known to work
better one way or another, optimize.
What do people think of this? I'd be willing to do the work myself
if it's desired (unless somebody beats me to it; it seems like this
would be simple to do, and a nice project for a beginner).
chris
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: MIPS pseudo-insns and Re: Patch to add -mfp32 support toMIPS gas
2001-08-03 16:38 ` MIPS pseudo-insns and Re: Patch to add -mfp32 support to MIPSgas cgd
@ 2001-08-03 19:02 ` cgd
2001-08-04 16:45 ` MIPS pseudo-insns and Re: Patch to add -mfp32 support to MIPS gas H . J . Lu
0 siblings, 1 reply; 20+ messages in thread
From: cgd @ 2001-08-03 19:02 UTC (permalink / raw)
To: r.sandiford; +Cc: binutils, echristo
cgd@broadcom.com (Chris G. Demetriou) writes:
> First, no good deed goes unpunished. For doing the good deed of
> adding test cases... there are new test failures:
>
> Test: Fails on:
>
> MIPS -mgp32 -mfp32 (a) (b)
> MIPS -mgp32 -mfp64 (a) (b)
> MIPS -mgp64 -mfp32 (a) (b)
> MIPS -mgp64 -mfp64 (a) (b)
> MIPS -mabi=32 (a) (b)
> MIPS -mgp32 -mfp32 (SVR4 PIC) (a)
> MIPS -mgp32 -mfp64 (SVR4 PIC) (a)
> MIPS -mgp64 -mfp32 (SVR4 PIC) (a)
> MIPS -mgp64 -mfp64 (SVR4 PIC) (a)
> MIPS -mabi=32 (SVR4 PIC) (a)
>
> (a): mips-linux, mipsel-linux, mips64-linux, mips64el-linux
> (b): mips-ecoff, mipsel-ecoff
i found a little time to look into these. patches like the ones
below, but applied to all 10 of the tests rather than just 2, should
make the problems go away.
I don't really have time to fix them all, but thought you might want
the info...
(OK, the first hunk of each .d file's diff, and the number of 0's in
the second hunk are my personal style preference... but you get the
idea... 8-)
chris
Index: mips-gp32-fp32-pic.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips-gp32-fp32-pic.d,v
retrieving revision 1.1
diff -c -r1.1 mips-gp32-fp32-pic.d
*** mips-gp32-fp32-pic.d 2001/08/02 10:16:49 1.1
--- mips-gp32-fp32-pic.d 2001/08/04 00:54:57
***************
*** 6,12 ****
Disassembly of section .text:
! 0+000 <[^>]*>:
0: 3c1c0000 lui gp,0x0
4: 279c0000 addiu gp,gp,0
8: 0399e021 addu gp,gp,t9
--- 6,12 ----
Disassembly of section .text:
! 0+0000 <[^>]*>:
0: 3c1c0000 lui gp,0x0
4: 279c0000 addiu gp,gp,0
8: 0399e021 addu gp,gp,t9
***************
*** 112,114 ****
--- 112,117 ----
198: 24a40064 addiu a0,a1,100
19c: 0004202b sltu a0,zero,a0
1a0: 00a02025 move a0,a1
+
+ 0+01a4 <[^>]*>:
+ ...
Index: mips-gp32-fp32-pic.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips-gp32-fp32-pic.s,v
retrieving revision 1.1
diff -c -r1.1 mips-gp32-fp32-pic.s
*** mips-gp32-fp32-pic.s 2001/08/02 10:16:49 1.1
--- mips-gp32-fp32-pic.s 2001/08/04 00:54:58
***************
*** 137,140 ****
--- 137,145 ----
# Should produce warnings given -mfp32
# add.d $f1, $f2, $f3
+ .end func
+
end:
+
+ # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
Index: mips-gp32-fp32.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips-gp32-fp32.d,v
retrieving revision 1.1
diff -c -r1.1 mips-gp32-fp32.d
*** mips-gp32-fp32.d 2001/08/02 10:16:49 1.1
--- mips-gp32-fp32.d 2001/08/04 00:54:58
***************
*** 6,12 ****
Disassembly of section .text:
! 0+000 <[^>]*>:
0: 3c041234 lui a0,0x1234
4: 34845678 ori a0,a0,0x5678
8: 2784c000 addiu a0,gp,-16384
--- 6,12 ----
Disassembly of section .text:
! 0+0000 <[^>]*>:
0: 3c041234 lui a0,0x1234
4: 34845678 ori a0,a0,0x5678
8: 2784c000 addiu a0,gp,-16384
***************
*** 73,75 ****
--- 73,78 ----
fc: 24a40064 addiu a0,a1,100
100: 0004202b sltu a0,zero,a0
104: 00a02025 move a0,a1
+
+ 0+0108 <[^>]*>:
+ ...
Index: mips-gp32-fp32.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips-gp32-fp32.s,v
retrieving revision 1.1
diff -c -r1.1 mips-gp32-fp32.s
*** mips-gp32-fp32.s 2001/08/02 10:16:49 1.1
--- mips-gp32-fp32.s 2001/08/04 00:54:58
***************
*** 97,99 ****
--- 97,102 ----
# add.d $f1, $f2, $f3
end:
+
+ # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: MIPS pseudo-insns and Re: Patch to add -mfp32 support to MIPS gas
2001-08-03 19:02 ` MIPS pseudo-insns and Re: Patch to add -mfp32 support toMIPS gas cgd
@ 2001-08-04 16:45 ` H . J . Lu
2001-08-07 15:30 ` MIPS pseudo-insns and Re: Patch to add -mfp32 support toMIPS gas cgd
0 siblings, 1 reply; 20+ messages in thread
From: H . J . Lu @ 2001-08-04 16:45 UTC (permalink / raw)
To: cgd; +Cc: r.sandiford, binutils, echristo
On Fri, Aug 03, 2001 at 05:58:36PM -0700, cgd@broadcom.com wrote:
> cgd@broadcom.com (Chris G. Demetriou) writes:
> > First, no good deed goes unpunished. For doing the good deed of
> > adding test cases... there are new test failures:
> >
> > Test: Fails on:
> >
> > MIPS -mgp32 -mfp32 (a) (b)
> > MIPS -mgp32 -mfp64 (a) (b)
> > MIPS -mgp64 -mfp32 (a) (b)
> > MIPS -mgp64 -mfp64 (a) (b)
> > MIPS -mabi=32 (a) (b)
> > MIPS -mgp32 -mfp32 (SVR4 PIC) (a)
> > MIPS -mgp32 -mfp64 (SVR4 PIC) (a)
> > MIPS -mgp64 -mfp32 (SVR4 PIC) (a)
> > MIPS -mgp64 -mfp64 (SVR4 PIC) (a)
> > MIPS -mabi=32 (SVR4 PIC) (a)
> >
> > (a): mips-linux, mipsel-linux, mips64-linux, mips64el-linux
> > (b): mips-ecoff, mipsel-ecoff
>
> i found a little time to look into these. patches like the ones
> below, but applied to all 10 of the tests rather than just 2, should
> make the problems go away.
>
> I don't really have time to fix them all, but thought you might want
> the info...
>
Tested on mips-linux, mipsel-linux, mips64-linux and mips64el-linux. I will
check in this patch shortly.
Thanks.
H.J.
----
2001-08-04 H.J. Lu <hjl@gnu.org>
Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/e32-rel4.s: Removed.
* gas/mips/e32-rel4.d: Use elf-rel4.s.
* gas/mips/mips-abi32-pic.d: Add lines for objdump.
* gas/mips/mips-abi32.d: Likewise.
* gas/mips/mips-gp32-fp32-pic.d: Likewise.
* gas/mips/mips-gp32-fp32.d: Likewise.
* gas/mips/mips-gp32-fp64-pic.d: Likewise.
* gas/mips/mips-gp32-fp64.d: Likewise.
* gas/mips/mips-gp64-fp32-pic.d: Likewise.
* gas/mips/mips-gp64-fp32.d: Likewise.
* gas/mips/mips-gp64-fp64-pic.d: Likewise.
* gas/mips/mips-gp64-fp64.d: Likewise.
* gas/mips/mips-abi32-pic.s: Add space for objdump.
* gas/mips/mips-abi32.s: Likewise.
* gas/mips/mips-gp32-fp32-pic.s: Likewise.
* gas/mips/mips-gp32-fp32.s: Likewise.
* gas/mips/mips-gp32-fp64-pic.s: Likewise.
* gas/mips/mips-gp32-fp64.s: Likewise.
* gas/mips/mips-gp64-fp32-pic.s: Likewise.
* gas/mips/mips-gp64-fp32.s: Likewise.
* gas/mips/mips-gp64-fp64-pic.s: Likewise.
* gas/mips/mips-gp64-fp64.s: Likewise.
* gas/mips/mips-abi32-pic.s: Add the missing .end.
* gas/mips/mips-gp32-fp32-pic.s: Likewise.
* gas/mips/mips-gp32-fp64-pic.s: Likewise.
* gas/mips/mips-gp64-fp32-pic.s: Likewise.
* gas/mips/mips-gp64-fp64-pic.s: Likewise.
* gas/mips/mips.exp: Use the same rel4 test for litte endian.
Index: gas/mips/e32-rel4.d
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/e32-rel4.d,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 e32-rel4.d
--- gas/mips/e32-rel4.d 2001/08/04 00:04:04 1.1.1.1
+++ gas/mips/e32-rel4.d 2001/08/04 23:41:00
@@ -1,5 +1,6 @@
#objdump: --prefix-addresses -dr
#name: MIPS ELF reloc 4
+#source: elf-rel4.s
.*: +file format.*
Index: gas/mips/e32-rel4.s
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/e32-rel4.s,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 e32-rel4.s
--- gas/mips/e32-rel4.s 2001/08/04 00:04:04 1.1.1.1
+++ gas/mips/e32-rel4.s 2001/08/04 23:41:14
@@ -1,12 +0,0 @@
-
- .section .sdata
- .global a
- .4byte 1
-a: .4byte 2
-
- .section .text
- la $4,a
- la $4,a+4
- la $4,a+8
- la $4,a+12
-
Index: gas/mips/mips-abi32-pic.d
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips-abi32-pic.d,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips-abi32-pic.d
--- gas/mips/mips-abi32-pic.d 2001/08/03 15:41:17 1.1.1.1
+++ gas/mips/mips-abi32-pic.d 2001/08/04 23:41:00
@@ -112,3 +112,6 @@ Disassembly of section .text:
198: 24a40064 addiu a0,a1,100
19c: 0004202b sltu a0,zero,a0
1a0: 00a02025 move a0,a1
+
+0+01a4 <[^>]*>:
+ ...
Index: gas/mips/mips-abi32-pic.s
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips-abi32-pic.s,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips-abi32-pic.s
--- gas/mips/mips-abi32-pic.s 2001/08/03 15:41:17 1.1.1.1
+++ gas/mips/mips-abi32-pic.s 2001/08/04 23:41:00
@@ -137,4 +137,9 @@ func:
# Should produce warnings given -mfp32
# add.d $f1, $f2, $f3
+ .end func
+
end:
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
Index: gas/mips/mips-abi32.d
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips-abi32.d,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips-abi32.d
--- gas/mips/mips-abi32.d 2001/08/03 15:41:17 1.1.1.1
+++ gas/mips/mips-abi32.d 2001/08/04 23:41:00
@@ -73,3 +73,6 @@ Disassembly of section .text:
fc: 24a40064 addiu a0,a1,100
100: 0004202b sltu a0,zero,a0
104: 00a02025 move a0,a1
+
+0+0108 <[^>]*>:
+ ...
Index: gas/mips/mips-abi32.s
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips-abi32.s,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips-abi32.s
--- gas/mips/mips-abi32.s 2001/08/03 15:41:17 1.1.1.1
+++ gas/mips/mips-abi32.s 2001/08/04 23:41:00
@@ -97,3 +97,6 @@ func:
# add.d $f1, $f2, $f3
end:
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
Index: gas/mips/mips-gp32-fp32-pic.d
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips-gp32-fp32-pic.d,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips-gp32-fp32-pic.d
--- gas/mips/mips-gp32-fp32-pic.d 2001/08/03 15:41:17 1.1.1.1
+++ gas/mips/mips-gp32-fp32-pic.d 2001/08/04 23:41:00
@@ -112,3 +112,6 @@ Disassembly of section .text:
198: 24a40064 addiu a0,a1,100
19c: 0004202b sltu a0,zero,a0
1a0: 00a02025 move a0,a1
+
+0+01a4 <[^>]*>:
+ ...
Index: gas/mips/mips-gp32-fp32-pic.s
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips-gp32-fp32-pic.s,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips-gp32-fp32-pic.s
--- gas/mips/mips-gp32-fp32-pic.s 2001/08/03 15:41:17 1.1.1.1
+++ gas/mips/mips-gp32-fp32-pic.s 2001/08/04 23:41:00
@@ -137,4 +137,9 @@ func:
# Should produce warnings given -mfp32
# add.d $f1, $f2, $f3
+ .end func
+
end:
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
Index: gas/mips/mips-gp32-fp32.d
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips-gp32-fp32.d,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips-gp32-fp32.d
--- gas/mips/mips-gp32-fp32.d 2001/08/03 15:41:17 1.1.1.1
+++ gas/mips/mips-gp32-fp32.d 2001/08/04 23:43:02
@@ -73,3 +73,6 @@ Disassembly of section .text:
fc: 24a40064 addiu a0,a1,100
100: 0004202b sltu a0,zero,a0
104: 00a02025 move a0,a1
+
+0+0108 <[^>]*>:
+ ...
Index: gas/mips/mips-gp32-fp32.s
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips-gp32-fp32.s,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips-gp32-fp32.s
--- gas/mips/mips-gp32-fp32.s 2001/08/03 15:41:17 1.1.1.1
+++ gas/mips/mips-gp32-fp32.s 2001/08/04 23:41:00
@@ -97,3 +97,6 @@ func:
# add.d $f1, $f2, $f3
end:
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
Index: gas/mips/mips-gp32-fp64-pic.d
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips-gp32-fp64-pic.d,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips-gp32-fp64-pic.d
--- gas/mips/mips-gp32-fp64-pic.d 2001/08/03 15:41:17 1.1.1.1
+++ gas/mips/mips-gp32-fp64-pic.d 2001/08/04 23:41:00
@@ -112,3 +112,6 @@ Disassembly of section .text:
198: 0004202b sltu a0,zero,a0
19c: 00a02025 move a0,a1
1a0: 46231040 add.d \$f1,\$f2,\$f3
+
+0+01a4 <[^>]*>:
+ ...
Index: gas/mips/mips-gp32-fp64-pic.s
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips-gp32-fp64-pic.s,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips-gp32-fp64-pic.s
--- gas/mips/mips-gp32-fp64-pic.s 2001/08/03 15:41:17 1.1.1.1
+++ gas/mips/mips-gp32-fp64-pic.s 2001/08/04 23:41:00
@@ -136,4 +136,8 @@ func:
# Should produce warnings given -mfp32
add.d $f1, $f2, $f3 # 01a0 add.d $f1,$f2,$f3
+ .end func
end:
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
Index: gas/mips/mips-gp32-fp64.d
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips-gp32-fp64.d,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips-gp32-fp64.d
--- gas/mips/mips-gp32-fp64.d 2001/08/03 15:41:17 1.1.1.1
+++ gas/mips/mips-gp32-fp64.d 2001/08/04 23:41:00
@@ -72,3 +72,6 @@ Disassembly of section .text:
f8: 0004202b sltu a0,zero,a0
fc: 00a02025 move a0,a1
100: 46231040 add.d \$f1,\$f2,\$f3
+
+0+0104 <[^>]*>:
+ ...
Index: gas/mips/mips-gp32-fp64.s
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips-gp32-fp64.s,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips-gp32-fp64.s
--- gas/mips/mips-gp32-fp64.s 2001/08/03 15:41:17 1.1.1.1
+++ gas/mips/mips-gp32-fp64.s 2001/08/04 23:41:00
@@ -94,3 +94,6 @@ func:
add.d $f1, $f2, $f3 # 0100 add.d $f1,$f2,$f3
end:
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
Index: gas/mips/mips-gp64-fp32-pic.d
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips-gp64-fp32-pic.d,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips-gp64-fp32-pic.d
--- gas/mips/mips-gp64-fp32-pic.d 2001/08/03 15:41:17 1.1.1.1
+++ gas/mips/mips-gp64-fp32-pic.d 2001/08/04 23:41:01
@@ -145,3 +145,6 @@ Disassembly of section .text:
21c: 0081082b sltu at,a0,at
220: 14200001 bnez at,228 <[^>]*>
224: 00000000 nop
+
+0+0228 <[^>]*>:
+ ...
Index: gas/mips/mips-gp64-fp32-pic.s
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips-gp64-fp32-pic.s,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips-gp64-fp32-pic.s
--- gas/mips/mips-gp64-fp32-pic.s 2001/08/03 15:41:17 1.1.1.1
+++ gas/mips/mips-gp64-fp32-pic.s 2001/08/04 23:41:01
@@ -160,4 +160,8 @@ func:
# Should produce warnings given -mfp32
# add.d $f1, $f2, $f3
+ .end func
end:
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
Index: gas/mips/mips-gp64-fp32.d
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips-gp64-fp32.d,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips-gp64-fp32.d
--- gas/mips/mips-gp64-fp32.d 2001/08/03 15:41:17 1.1.1.1
+++ gas/mips/mips-gp64-fp32.d 2001/08/04 23:41:01
@@ -92,3 +92,6 @@ Disassembly of section .text:
148: 00010c78 dsll at,at,0x11
14c: 0081082b sltu at,a0,at
150: 14200000 bnez at,154 <[^>]*>
+
+0+0154 <[^>]*>:
+ ...
Index: gas/mips/mips-gp64-fp32.s
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips-gp64-fp32.s,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips-gp64-fp32.s
--- gas/mips/mips-gp64-fp32.s 2001/08/03 15:41:17 1.1.1.1
+++ gas/mips/mips-gp64-fp32.s 2001/08/04 23:41:01
@@ -106,3 +106,6 @@ func:
# add.d $f1, $f2, $f3
end:
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
Index: gas/mips/mips-gp64-fp64-pic.d
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips-gp64-fp64-pic.d,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips-gp64-fp64-pic.d
--- gas/mips/mips-gp64-fp64-pic.d 2001/08/03 15:41:17 1.1.1.1
+++ gas/mips/mips-gp64-fp64-pic.d 2001/08/04 23:41:01
@@ -146,3 +146,6 @@ Disassembly of section .text:
220: 14200002 bnez at,22c <[^>]*>
224: 00000000 nop
228: 46231040 add.d \$f1,\$f2,\$f3
+
+0+022c <[^>]*>:
+ ...
Index: gas/mips/mips-gp64-fp64-pic.s
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips-gp64-fp64-pic.s,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips-gp64-fp64-pic.s
--- gas/mips/mips-gp64-fp64-pic.s 2001/08/03 15:41:17 1.1.1.1
+++ gas/mips/mips-gp64-fp64-pic.s 2001/08/04 23:41:01
@@ -159,4 +159,8 @@ func:
add.d $f1, $f2, $f3 # 0228 add.d $f1,$f2,$f3
+ .end func
end:
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
Index: gas/mips/mips-gp64-fp64.d
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips-gp64-fp64.d,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips-gp64-fp64.d
--- gas/mips/mips-gp64-fp64.d 2001/08/03 15:41:17 1.1.1.1
+++ gas/mips/mips-gp64-fp64.d 2001/08/04 23:41:01
@@ -93,3 +93,6 @@ Disassembly of section .text:
14c: 0081082b sltu at,a0,at
150: 14200001 bnez at,158 <[^>]*>
154: 46231040 add.d \$f1,\$f2,\$f3
+
+0+0158 <[^>]*>:
+ ...
Index: gas/mips/mips-gp64-fp64.s
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips-gp64-fp64.s,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips-gp64-fp64.s
--- gas/mips/mips-gp64-fp64.s 2001/08/03 15:41:17 1.1.1.1
+++ gas/mips/mips-gp64-fp64.s 2001/08/04 23:41:01
@@ -104,3 +104,6 @@ func:
add.d $f1, $f2, $f3 # 0154 add.d $f1,$f2,$f3
end:
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
Index: gas/mips/mips.exp
===================================================================
RCS file: /work/cvs/gnu/binutils/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.1.1.14
diff -u -p -r1.1.1.14 mips.exp
--- gas/mips/mips.exp 2001/08/04 00:04:00 1.1.1.14
+++ gas/mips/mips.exp 2001/08/04 23:41:01
@@ -151,10 +151,10 @@ if { [istarget mips*-*-*] } then {
run_dump_test "elf${el}-rel"
if [istarget mips64*-*-*] {
run_dump_test "elf${el}-rel2"
- run_dump_test "elf${el}-rel4"
+ run_dump_test "elf-rel4"
} {
run_dump_test "e32${el}-rel2"
- run_dump_test "e32${el}-rel4"
+ run_dump_test "e32-rel4"
}
run_dump_test "elf${el}-rel3"
run_dump_test "${tmips}${el}empic"
--- gas/mips/e32-rel4.s.orig Fri Aug 3 17:04:04 2001
+++ gas/mips/e32-rel4.s Sat Aug 4 16:41:14 2001
@@ -1,12 +0,0 @@
-
- .section .sdata
- .global a
- .4byte 1
-a: .4byte 2
-
- .section .text
- la $4,a
- la $4,a+4
- la $4,a+8
- la $4,a+12
-
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: MIPS pseudo-insns and Re: Patch to add -mfp32 support toMIPS gas
2001-08-04 16:45 ` MIPS pseudo-insns and Re: Patch to add -mfp32 support to MIPS gas H . J . Lu
@ 2001-08-07 15:30 ` cgd
0 siblings, 0 replies; 20+ messages in thread
From: cgd @ 2001-08-07 15:30 UTC (permalink / raw)
To: r.sandiford; +Cc: binutils
As things stand, i've got one more issue with these patches:
They fail because assembler errors on mips-ecoff. (Once these errors
are fixed, the tests still fail, of course. 8-)
I don't know whether they are expected to produce the same output on
ECOFF as on ELF, but i figure they should at least assemble with ECOFF
so that at some point in the future somebody can figure out what's
correct (and fix bugs or add different .d files if appropriate).
To this end, I've come up with the following patch.
It changes uses of .4byte to .word (the former seems to be supported
in ELF only?). I don't believe there could be negative consequences
from this part; .word generates 4-byte values on MIPS.
It also removes the .size directives which differ in usage from ELF to
ECOFF. This caused me some concern, but causes no failures with the
existing tests.
Comments?
chris
=====
for gas/testsuite/ChangeLog:
2001-08-07 Chris Demetriou <cgd@broadcom.com>
* gas/mips/mips-abi32-pic.s: Use ".word" rather than ".4byte".
Delete use of ".size".
* gas/mips/mips-abi32.s: Likewise.
* gas/mips/mips-gp32-fp32-pic.s: Likewise.
* gas/mips/mips-gp32-fp32.s: Likewise.
* gas/mips/mips-gp32-fp64-pic.s: Likewise.
* gas/mips/mips-gp32-fp64.s: Likewise.
* gas/mips/mips-gp64-fp32-pic.s: Likewise.
* gas/mips/mips-gp64-fp32.s: Likewise.
* gas/mips/mips-gp64-fp64-pic.s: Likewise.
* gas/mips/mips-gp64-fp64.s: Likewise.
Index: gas/mips/mips-abi32-pic.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips-abi32-pic.s,v
retrieving revision 1.2
diff -c -r1.2 mips-abi32-pic.s
*** mips-abi32-pic.s 2001/08/05 00:53:28 1.2
--- mips-abi32-pic.s 2001/08/07 22:26:33
***************
*** 1,14 ****
.sdata
! shared: .4byte 11
.data
- .size unshared,16
unshared:
! .4byte 1
! .4byte 2
! .4byte 3
! .4byte 4
.text
.ent func
--- 1,13 ----
.sdata
! shared: .word 11
.data
unshared:
! .word 1
! .word 2
! .word 3
! .word 4
.text
.ent func
Index: gas/mips/mips-abi32.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips-abi32.s,v
retrieving revision 1.2
diff -c -r1.2 mips-abi32.s
*** mips-abi32.s 2001/08/05 00:53:28 1.2
--- mips-abi32.s 2001/08/07 22:26:33
***************
*** 1,14 ****
.sdata
! shared: .4byte 11
.data
- .size unshared,16
unshared:
! .4byte 1
! .4byte 2
! .4byte 3
! .4byte 4
.text
func:
--- 1,13 ----
.sdata
! shared: .word 11
.data
unshared:
! .word 1
! .word 2
! .word 3
! .word 4
.text
func:
Index: gas/mips/mips-gp32-fp32-pic.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips-gp32-fp32-pic.s,v
retrieving revision 1.2
diff -c -r1.2 mips-gp32-fp32-pic.s
*** mips-gp32-fp32-pic.s 2001/08/05 00:53:28 1.2
--- mips-gp32-fp32-pic.s 2001/08/07 22:26:33
***************
*** 1,14 ****
.sdata
! shared: .4byte 11
.data
- .size unshared,16
unshared:
! .4byte 1
! .4byte 2
! .4byte 3
! .4byte 4
.text
.ent func
--- 1,13 ----
.sdata
! shared: .word 11
.data
unshared:
! .word 1
! .word 2
! .word 3
! .word 4
.text
.ent func
Index: gas/mips/mips-gp32-fp32.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips-gp32-fp32.s,v
retrieving revision 1.2
diff -c -r1.2 mips-gp32-fp32.s
*** mips-gp32-fp32.s 2001/08/05 00:53:28 1.2
--- mips-gp32-fp32.s 2001/08/07 22:26:33
***************
*** 1,14 ****
.sdata
! shared: .4byte 11
.data
- .size unshared,16
unshared:
! .4byte 1
! .4byte 2
! .4byte 3
! .4byte 4
.text
func:
--- 1,13 ----
.sdata
! shared: .word 11
.data
unshared:
! .word 1
! .word 2
! .word 3
! .word 4
.text
func:
Index: gas/mips/mips-gp32-fp64-pic.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips-gp32-fp64-pic.s,v
retrieving revision 1.2
diff -c -r1.2 mips-gp32-fp64-pic.s
*** mips-gp32-fp64-pic.s 2001/08/05 00:53:28 1.2
--- mips-gp32-fp64-pic.s 2001/08/07 22:26:33
***************
*** 1,14 ****
.sdata
! shared: .4byte 11
.data
- .size unshared,16
unshared:
! .4byte 1
! .4byte 2
! .4byte 3
! .4byte 4
.text
.ent func
--- 1,13 ----
.sdata
! shared: .word 11
.data
unshared:
! .word 1
! .word 2
! .word 3
! .word 4
.text
.ent func
Index: gas/mips/mips-gp32-fp64.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips-gp32-fp64.s,v
retrieving revision 1.2
diff -c -r1.2 mips-gp32-fp64.s
*** mips-gp32-fp64.s 2001/08/05 00:53:28 1.2
--- mips-gp32-fp64.s 2001/08/07 22:26:33
***************
*** 1,14 ****
.sdata
! shared: .4byte 11
.data
- .size unshared,16
unshared:
! .4byte 1
! .4byte 2
! .4byte 3
! .4byte 4
.text
func:
--- 1,13 ----
.sdata
! shared: .word 11
.data
unshared:
! .word 1
! .word 2
! .word 3
! .word 4
.text
func:
Index: gas/mips/mips-gp64-fp32-pic.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips-gp64-fp32-pic.s,v
retrieving revision 1.2
diff -c -r1.2 mips-gp64-fp32-pic.s
*** mips-gp64-fp32-pic.s 2001/08/05 00:53:28 1.2
--- mips-gp64-fp32-pic.s 2001/08/07 22:26:33
***************
*** 1,14 ****
.sdata
! shared: .4byte 11
.data
- .size unshared,16
unshared:
! .4byte 1
! .4byte 2
! .4byte 3
! .4byte 4
.text
.ent func
--- 1,13 ----
.sdata
! shared: .word 11
.data
unshared:
! .word 1
! .word 2
! .word 3
! .word 4
.text
.ent func
Index: gas/mips/mips-gp64-fp32.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips-gp64-fp32.s,v
retrieving revision 1.2
diff -c -r1.2 mips-gp64-fp32.s
*** mips-gp64-fp32.s 2001/08/05 00:53:28 1.2
--- mips-gp64-fp32.s 2001/08/07 22:26:33
***************
*** 1,14 ****
.sdata
! shared: .4byte 11
.data
- .size unshared,16
unshared:
! .4byte 1
! .4byte 2
! .4byte 3
! .4byte 4
.text
func:
--- 1,13 ----
.sdata
! shared: .word 11
.data
unshared:
! .word 1
! .word 2
! .word 3
! .word 4
.text
func:
Index: gas/mips/mips-gp64-fp64-pic.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips-gp64-fp64-pic.s,v
retrieving revision 1.2
diff -c -r1.2 mips-gp64-fp64-pic.s
*** mips-gp64-fp64-pic.s 2001/08/05 00:53:28 1.2
--- mips-gp64-fp64-pic.s 2001/08/07 22:26:33
***************
*** 1,14 ****
.sdata
! shared: .4byte 11
.data
- .size unshared,16
unshared:
! .4byte 1
! .4byte 2
! .4byte 3
! .4byte 4
.text
.ent func
--- 1,13 ----
.sdata
! shared: .word 11
.data
unshared:
! .word 1
! .word 2
! .word 3
! .word 4
.text
.ent func
Index: gas/mips/mips-gp64-fp64.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips-gp64-fp64.s,v
retrieving revision 1.2
diff -c -r1.2 mips-gp64-fp64.s
*** mips-gp64-fp64.s 2001/08/05 00:53:28 1.2
--- mips-gp64-fp64.s 2001/08/07 22:26:33
***************
*** 1,14 ****
.sdata
! shared: .4byte 11
.data
- .size unshared,16
unshared:
! .4byte 1
! .4byte 2
! .4byte 3
! .4byte 4
.text
func:
--- 1,13 ----
.sdata
! shared: .word 11
.data
unshared:
! .word 1
! .word 2
! .word 3
! .word 4
.text
func:
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2001-08-07 15:30 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2001-07-19 12:46 Patch to add -mfp32 support to MIPS gas Richard Sandiford
2001-07-19 16:11 ` Thiemo Seufer
2001-07-20 0:20 ` Eric Christopher
2001-07-20 1:41 ` Richard Sandiford
2001-07-20 12:17 ` Thiemo Seufer
2001-07-23 10:00 ` Richard Sandiford
2001-07-23 12:05 ` Thiemo Seufer
2001-07-24 7:01 ` Richard Sandiford
2001-07-24 13:37 ` Thiemo Seufer
2001-07-25 8:00 ` Richard Sandiford
2001-07-26 4:30 ` Thiemo Seufer
2001-07-30 8:33 ` Eric Christopher
2001-07-31 5:31 ` Richard Sandiford
2001-07-31 5:44 ` Eric Christopher
2001-07-31 6:02 ` Richard Sandiford
2001-07-31 9:02 ` Ian Lance Taylor
[not found] ` <mailpost.996584774.27152@postal.sibyte.com>
2001-08-03 16:38 ` MIPS pseudo-insns and Re: Patch to add -mfp32 support to MIPSgas cgd
2001-08-03 19:02 ` MIPS pseudo-insns and Re: Patch to add -mfp32 support toMIPS gas cgd
2001-08-04 16:45 ` MIPS pseudo-insns and Re: Patch to add -mfp32 support to MIPS gas H . J . Lu
2001-08-07 15:30 ` MIPS pseudo-insns and Re: Patch to add -mfp32 support toMIPS gas cgd
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).