MIPS R5900 support => Disabling a few I2 instructions

MIPS R5900 support => Disabling a few I2 instructions

[Doug Evans]

Ed Schouten writes:
 > Hi everyone,
 > 
 > The last couple of weeks I've been working on Binutils from CVS to
 > support the Toshiba R5900 CPU (found in Sony's Playstation 2).
 > 
 > The Toshiba R5900 supports the following instructions:
 > - It implements almost all MIPS3 instructions, though it supports
 >   MIPS4's movn/movz.
 > - It has a lot of instructions which allow you to do 128 bits register
 >   manipulations (vector rotations, etc)
 > - It *doesn't* support load linked and store conditional instructions
 >   (ll/lld/sc/scd, MIPS2).
 > 
 > That's why I chose to define it as a MIPS3 CPU.
 > 
 > When I look in opcodes/mips-opc.c, I see a lot of ways to add
 > instructions to a certain CPU, but I can't find a way to just disable
 > ll/lld/sc/scd (I can't just say I2&!T59 or something).
 > 
 > What would be the best way to disable ll/lld/sc/scd *only* on the MIPS
 > R5900?

I'm confused by "That's why I chose to define it as a MIPS3 CPU."

That suggests all of Cygnus's work circa 1998/1999 didn't get
folded back into the FSF tree.  I know the dvp stuff didn't get
folded back :-(, but the mips stuff too?

MIPS R5900 support => Disabling a few I2 instructions

[Doug Evans]

Doug Evans writes:
 > I'm confused by "That's why I chose to define it as a MIPS3 CPU."
 > 
 > That suggests all of Cygnus's work circa 1998/1999 didn't get
 > folded back into the FSF tree.  I know the dvp stuff didn't get
 > folded back :-(, but the mips stuff too?

btw, ooc, and all that.
Are you using gnu-ee-2.9-990721 from
http://ps2dev.sourceforge.net/downloads.html
?

[There may be copyright issues that need to be thought through,
but I dunno.]

Re: MIPS R5900 support => Disabling a few I2 instructions

[Thiemo Seufer]

Doug Evans wrote:
[snip]
>  > That's why I chose to define it as a MIPS3 CPU.
>  > 
>  > When I look in opcodes/mips-opc.c, I see a lot of ways to add
>  > instructions to a certain CPU, but I can't find a way to just disable
>  > ll/lld/sc/scd (I can't just say I2&!T59 or something).
>  > 
>  > What would be the best way to disable ll/lld/sc/scd *only* on the MIPS
>  > R5900?

That's not supported, because an CPU is supposed to provide all the
instructions the ISA defines. AFAICS you should use MIPS I ISA, and
add a R5900-specific flag, so you can say e.g. I1 | EE.

> I'm confused by "That's why I chose to define it as a MIPS3 CPU."
> 
> That suggests all of Cygnus's work circa 1998/1999 didn't get
> folded back into the FSF tree.  I know the dvp stuff didn't get
> folded back :-(, but the mips stuff too?

There are quite a lot of patches from various embedded mips toolchains
which never found their way in the FSF tree.


Thiemo

Re: MIPS R5900 support => Disabling a few I2 instructions

[Daniel Jacobowitz]

On Sun, May 01, 2005 at 11:37:22PM +0200, Thiemo Seufer wrote:
> > I'm confused by "That's why I chose to define it as a MIPS3 CPU."
> > 
> > That suggests all of Cygnus's work circa 1998/1999 didn't get
> > folded back into the FSF tree.  I know the dvp stuff didn't get
> > folded back :-(, but the mips stuff too?
> 
> There are quite a lot of patches from various embedded mips toolchains
> which never found their way in the FSF tree.

I believe that the fact that these particular bits haven't been
contributed is mostly accidental; the thing to do is to flog Eric C.
harder until he does it :-)

-- 
Daniel Jacobowitz
CodeSourcery, LLC