* [PATCH] Add POWER5 instructions
@ 2005-05-03 15:32 Anton Blanchard
2005-05-04 12:33 ` Alan Modra
2005-05-04 14:02 ` Kumar Gala
0 siblings, 2 replies; 4+ messages in thread
From: Anton Blanchard @ 2005-05-03 15:32 UTC (permalink / raw)
To: binutils
Hi,
The following patch adds some instructions new to POWER5.
Anton
--
2005-04-29 Anton Blanchard <anton@samba.org>
* gas/config/tc-ppc.c, gas/doc/c-ppc.texi, include/opcode/ppc.h,
opcodes/ppc-dis.c: Add POWER5 target.
* opcodes/ppc-opc.c: Add POWER5 specific instructions:
sc extended form, hrfid, popcntb, fsqrtes, fsqrtes., fre, fre.
diff -ur src.orig/gas/config/tc-ppc.c src/gas/config/tc-ppc.c
--- src.orig/gas/config/tc-ppc.c 2005-04-29 11:52:26.320653369 +1000
+++ src/gas/config/tc-ppc.c 2005-04-29 19:34:11.824762456 +1000
@@ -906,6 +906,12 @@
ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
| PPC_OPCODE_64 | PPC_OPCODE_POWER4);
}
+ else if (strcmp (arg, "power5") == 0)
+ {
+ ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
+ | PPC_OPCODE_64 | PPC_OPCODE_POWER4
+ | PPC_OPCODE_POWER5);
+ }
/* -mcom means assemble for the common intersection between Power
and PowerPC. At present, we just allow the union, rather
than the intersection. */
@@ -1100,6 +1106,7 @@
-mbooke64 generate code for 64-bit PowerPC BookE\n\
-mbooke, mbooke32 generate code for 32-bit PowerPC BookE\n\
-mpower4 generate code for Power4 architecture\n\
+-mpower5 generate code for Power5 architecture\n\
-mcom generate code Power/PowerPC common instructions\n\
-many generate code for any architecture (PWR/PWRX/PPC)\n"));
fprintf (stream, _("\
@@ -1255,7 +1262,10 @@
|| (ppc_cpu & PPC_OPCODE_BOOKE) == 0)
&& ((op->flags & (PPC_OPCODE_POWER4 | PPC_OPCODE_NOPOWER4)) == 0
|| ((op->flags & PPC_OPCODE_POWER4)
- == (ppc_cpu & PPC_OPCODE_POWER4))))
+ == (ppc_cpu & PPC_OPCODE_POWER4)))
+ && ((op->flags & PPC_OPCODE_POWER5) == 0
+ || ((op->flags & PPC_OPCODE_POWER5)
+ == (ppc_cpu & PPC_OPCODE_POWER5))))
{
const char *retval;
diff -ur src.orig/gas/doc/c-ppc.texi src/gas/doc/c-ppc.texi
--- src.orig/gas/doc/c-ppc.texi 2005-05-01 04:13:23.128427782 +1000
+++ src/gas/doc/c-ppc.texi 2005-04-29 19:35:14.703318321 +1000
@@ -73,6 +73,9 @@
@item -mpower4
Generate code for Power4 architecture.
+@item -mpower5
+Generate code for Power5 architecture.
+
@item -mcom
Generate code Power/PowerPC common instructions.
diff -ur src.orig/include/opcode/ppc.h src/include/opcode/ppc.h
--- src.orig/include/opcode/ppc.h 2005-04-29 11:52:26.411646429 +1000
+++ src/include/opcode/ppc.h 2005-04-12 00:47:26.562336689 +1000
@@ -134,6 +134,9 @@
/* Opcode is supported by machine check APU. */
#define PPC_OPCODE_RFMCI 0x800000
+/* Opcode is only supported by Power5 architecture. */
+#define PPC_OPCODE_POWER5 0x1000000
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
\f
diff -ur src.orig/opcodes/ppc-dis.c src/opcodes/ppc-dis.c
--- src.orig/opcodes/ppc-dis.c 2005-04-29 11:52:26.454643149 +1000
+++ src/opcodes/ppc-dis.c 2005-04-29 19:32:17.011186161 +1000
@@ -72,6 +72,10 @@
dialect |= PPC_OPCODE_POWER4;
if (info->disassembler_options
+ && strstr (info->disassembler_options, "power5") != NULL)
+ dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5;
+
+ if (info->disassembler_options
&& strstr (info->disassembler_options, "any") != NULL)
dialect |= PPC_OPCODE_ANY;
@@ -302,6 +306,7 @@
fprintf (stream, " e500|e500x2 Disassemble the e500 instructions\n");
fprintf (stream, " efs Disassemble the EFS instructions\n");
fprintf (stream, " power4 Disassemble the Power4 instructions\n");
+ fprintf (stream, " power5 Disassemble the Power5 instructions\n");
fprintf (stream, " 32 Do not disassemble 64-bit instructions\n");
fprintf (stream, " 64 Allow disassembly of 64-bit instructions\n");
}
diff -ur src.orig/opcodes/ppc-opc.c src/opcodes/ppc-opc.c
--- src.orig/opcodes/ppc-opc.c 2005-04-29 11:52:29.185830295 +1000
+++ src/opcodes/ppc-opc.c 2005-04-29 10:48:41.275248609 +1000
@@ -304,10 +304,14 @@
#define L FXM4 + 1
{ 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
- /* The LEV field in a POWER SC form instruction. */
-#define LEV L + 1
+ /* The LEV field in a POWER SVC form instruction. */
+#define SCV_LEV L + 1
{ 7, 5, NULL, NULL, 0 },
+ /* The LEV field in an SC form instruction. */
+#define LEV SCV_LEV + 1
+ { 7, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
+
/* The LI field in an I form instruction. The lower two bits are
forced to zero. */
#define LI LEV + 1
@@ -1818,6 +1822,7 @@
#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
#define POWER4 PPC_OPCODE_POWER4
+#define POWER5 PPC_OPCODE_POWER5
#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
#define PPC403 PPC_OPCODE_403
@@ -2749,9 +2754,9 @@
{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
-{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
-{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
-{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
+{ "sc", SC(17,1,0), SC_MASK, PPC, { LEV } },
+{ "svc", SC(17,0,0), SC_MASK, POWER, { SCV_LEV, FL1, FL2 } },
+{ "svcl", SC(17,0,1), SC_MASK, POWER, { SCV_LEV, FL1, FL2 } },
{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
@@ -3008,6 +3013,8 @@
{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
+{ "hrfid", XL(19,274), 0xffffffff, POWER5, { 0 } },
+
{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
@@ -3435,6 +3442,8 @@
{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
+{ "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } },
+
{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
@@ -4512,6 +4521,9 @@
{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
+{ "fsqrtes", A(59,26,0), AFRAFRC_MASK, POWER5, { FRT, FRB } },
+{ "fsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER5, { FRT, FRB } },
+
{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
@@ -4583,6 +4595,9 @@
{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
+{ "fre", A(63,24,0), AFRAFRC_MASK, POWER5, { FRT, FRB } },
+{ "fre.", A(63,24,1), AFRAFRC_MASK, POWER5, { FRT, FRB } },
+
{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] Add POWER5 instructions
2005-05-03 15:32 [PATCH] Add POWER5 instructions Anton Blanchard
@ 2005-05-04 12:33 ` Alan Modra
2005-05-04 14:02 ` Kumar Gala
1 sibling, 0 replies; 4+ messages in thread
From: Alan Modra @ 2005-05-04 12:33 UTC (permalink / raw)
To: Anton Blanchard; +Cc: binutils
On Tue, May 03, 2005 at 11:45:40PM +1000, Anton Blanchard wrote:
> The following patch adds some instructions new to POWER5.
This is OK except for the ChangeLog which isn't sufficiently detailed,
and file names in a ChangeLog should be relative to the dir of the
ChangeLog. Like this:
include/opcode/
2005-05-04 Anton Blanchard <anton@samba.org>
* ppc.h (PPC_OPCODE_POWER5): Define.
opcodes/
2005-05-04 Anton Blanchard <anton@samba.org>
* ppc-dis.c (powerpc_dialect): Handle "-Mpower5".
(print_ppc_disassembler_options): Document it.
* ppc-opc.c (SCV_LEV): Define.
(LEV): Allow optional operand.
(POWER5): Define.
(powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add
"hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.".
gas/
2005-05-04 Anton Blanchard <anton@samba.org>
* config/tc-ppc.c (parse_cpu): Handle "-mpower5".
(md_show_usage): Document it.
(ppc_setup_opcodes): Insert POWER5 mnemonics.
* doc/c-ppc.texi (PowerPC-Opts): Document "-mpower5".
--
Alan Modra
IBM OzLabs - Linux Technology Centre
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] Add POWER5 instructions
2005-05-03 15:32 [PATCH] Add POWER5 instructions Anton Blanchard
2005-05-04 12:33 ` Alan Modra
@ 2005-05-04 14:02 ` Kumar Gala
2005-05-04 15:51 ` Anton Blanchard
1 sibling, 1 reply; 4+ messages in thread
From: Kumar Gala @ 2005-05-04 14:02 UTC (permalink / raw)
To: Anton Blanchard; +Cc: binutils
Should these really be marked as POWER5, they are part of the PPC2.02
spec, however they may only be implemented in POWER5. I think it would
be better to have them in PPC, so any future PPC that implements these
instructions will pick them up.
- kumar
>
> +{ "fsqrtes", A(59,26,0), AFRAFRC_MASK, POWER5, {
> FRT, FRB } },
> +{ "fsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER5, {
> FRT, FRB } },
> +
> { "fmsubs", A(59,28,0), A_MASK, PPC, {
> FRT,FRA,FRC,FRB } },
> { "fmsubs.", A(59,28,1), A_MASK, PPC, {
> FRT,FRA,FRC,FRB } },
>
> @@ -4583,6 +4595,9 @@
> { "fsel", A(63,23,0), A_MASK, PPC, {
> FRT,FRA,FRC,FRB } },
> { "fsel.", A(63,23,1), A_MASK, PPC, {
> FRT,FRA,FRC,FRB } },
>
> +{ "fre", A(63,24,0), AFRAFRC_MASK, POWER5, { FRT, FRB }
> },
> +{ "fre.", A(63,24,1), AFRAFRC_MASK, POWER5, { FRT, FRB }
> },
> +
> { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA,
> FRC } },
> { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA,
> FRC } },
> { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA,
> FRC } },
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] Add POWER5 instructions
2005-05-04 14:02 ` Kumar Gala
@ 2005-05-04 15:51 ` Anton Blanchard
0 siblings, 0 replies; 4+ messages in thread
From: Anton Blanchard @ 2005-05-04 15:51 UTC (permalink / raw)
To: Kumar Gala; +Cc: binutils
Hi Kumar,
> Should these really be marked as POWER5, they are part of the PPC2.02
> spec, however they may only be implemented in POWER5. I think it would
> be better to have them in PPC, so any future PPC that implements these
> instructions will pick them up.
Indeed they are 2.02 instructions. We really need to clean up
this area of binutils, its a bit of a mess.
Anton
^ permalink raw reply [flat|nested] 4+ messages in thread
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2005-05-03 15:32 [PATCH] Add POWER5 instructions Anton Blanchard
2005-05-04 12:33 ` Alan Modra
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