* [PATCH] x86: Intel disassembly displacement adjustments
@ 2005-05-24 9:32 Jan Beulich
2005-05-25 4:49 ` Alan Modra
0 siblings, 1 reply; 2+ messages in thread
From: Jan Beulich @ 2005-05-24 9:32 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 4254 bytes --]
This adds missing code to deal with displacement in 16-bit memory operands
in Intel mode, and it changes 32-bit displacements to be shown in hex.
Built and tested on i686-pc-linux-gnu.
Jan
gas/testsuite/
2005-05-24 Jan Beulich <jbeulich@novell.com>
* gas/i386/intelok.d: Account for 32-bit displacements being shown
in hex.
opcodes/
2005-05-24 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
hex (but retain it being displayed as signed). Remove redundant
checks. Add handling of displacements for 16-bit addressing in Intel
mode.
--- /home/jbeulich/src/binutils/mainline/2005-05-18/gas/testsuite/gas/i386/intelok.d 2005-03-14 11:24:25.000000000 +0100
+++ 2005-05-18/gas/testsuite/gas/i386/intelok.d 2005-05-24 10:55:14.000000000 +0200
@@ -104,8 +104,8 @@ Disassembly of section .text:
[ ]*[0-9a-f]+: 8b 40 0c[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+12\]
[ ]*[0-9a-f]+: 8b 40 12[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+18\]
[ ]*[0-9a-f]+: 8b 40 12[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+18\]
-[ ]*[0-9a-f]+: 8b 04 85 02 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*4\+2\]
-[ ]*[0-9a-f]+: 8b 04 85 02 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*4\+2\]
+[ ]*[0-9a-f]+: 8b 04 85 02 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*4\+(0x)?2\]
+[ ]*[0-9a-f]+: 8b 04 85 02 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*4\+(0x)?2\]
[ ]*[0-9a-f]+: 8b 04 45 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*2\]
[ ]*[0-9a-f]+: 8b 04 45 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*2\]
[ ]*[0-9a-f]+: 8b 04 8d 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[ecx\*4\]
@@ -156,7 +156,7 @@ Disassembly of section .text:
[ ]*[0-9a-f]+: 8b 80 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\]
[ ]*[0-9a-f]+: 8b 40 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+1]
[ ]*[0-9a-f]+: 8b 80 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\]
-[ ]*[0-9a-f]+: 8b 80 01 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+1\]
+[ ]*[0-9a-f]+: 8b 80 01 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+(0x)?1\]
[ ]*[0-9a-f]+: 8b 80 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\]
[ ]*[0-9a-f]+: 8b 40 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+1\]
[ ]*[0-9a-f]+: a1 01 00 00 00[ ]+mov[ ]+eax,ds:0x1
--- /home/jbeulich/src/binutils/mainline/2005-05-18/opcodes/i386-dis.c 2005-05-09 08:31:57.000000000 +0200
+++ 2005-05-18/opcodes/i386-dis.c 2005-05-24 11:14:52.984223704 +0200
@@ -3342,22 +3342,23 @@ OP_E (int bytemode, int sizeflag)
oappend (scratchbuf);
}
}
- if (intel_syntax)
- if (mod != 0 || (base & 7) == 5)
- {
- /* Don't print zero displacements. */
- if (disp != 0)
- {
- if ((bfd_signed_vma) disp > 0)
- {
- *obufp++ = '+';
- *obufp = '\0';
- }
-
- print_operand_value (scratchbuf, 0, disp);
- oappend (scratchbuf);
- }
- }
+ if (intel_syntax && disp)
+ {
+ if ((bfd_signed_vma) disp > 0)
+ {
+ *obufp++ = '+';
+ *obufp = '\0';
+ }
+ else if (mod != 1)
+ {
+ *obufp++ = '-';
+ *obufp = '\0';
+ disp = - (bfd_signed_vma) disp;
+ }
+
+ print_operand_value (scratchbuf, mod != 1, disp);
+ oappend (scratchbuf);
+ }
*obufp++ = close_char;
*obufp = '\0';
@@ -3415,10 +3416,41 @@ OP_E (int bytemode, int sizeflag)
{
*obufp++ = open_char;
*obufp = '\0';
- oappend (index16[rm + add]);
+ oappend (index16[rm]);
+ if (intel_syntax && disp)
+ {
+ if ((bfd_signed_vma) disp > 0)
+ {
+ *obufp++ = '+';
+ *obufp = '\0';
+ }
+ else if (mod != 1)
+ {
+ *obufp++ = '-';
+ *obufp = '\0';
+ disp = - (bfd_signed_vma) disp;
+ }
+
+ print_operand_value (scratchbuf, mod != 1, disp);
+ oappend (scratchbuf);
+ }
+
*obufp++ = close_char;
*obufp = '\0';
}
+ else if (intel_syntax)
+ {
+ if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
+ | PREFIX_ES | PREFIX_FS | PREFIX_GS))
+ ;
+ else
+ {
+ oappend (names_seg[ds_reg - es_reg]);
+ oappend (":");
+ }
+ print_operand_value (scratchbuf, 1, disp & 0xffff);
+ oappend (scratchbuf);
+ }
}
}
[-- Attachment #2: binutils-mainline-x86-intel-mem-disasm.patch --]
[-- Type: text/plain, Size: 4124 bytes --]
This adds missing code to deal with displacement in 16-bit memory operands
in Intel mode, and it changes 32-bit displacements to be shown in hex.
Built and tested on i686-pc-linux-gnu.
Jan
gas/testsuite/
2005-05-24 Jan Beulich <jbeulich@novell.com>
* gas/i386/intelok.d: Account for 32-bit displacements being shown
in hex.
opcodes/
2005-05-24 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
hex (but retain it being displayed as signed). Remove redundant
checks. Add handling of displacements for 16-bit addressing in Intel
mode.
--- /home/jbeulich/src/binutils/mainline/2005-05-18/gas/testsuite/gas/i386/intelok.d 2005-03-14 11:24:25.000000000 +0100
+++ 2005-05-18/gas/testsuite/gas/i386/intelok.d 2005-05-24 10:55:14.000000000 +0200
@@ -104,8 +104,8 @@ Disassembly of section .text:
[ ]*[0-9a-f]+: 8b 40 0c[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+12\]
[ ]*[0-9a-f]+: 8b 40 12[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+18\]
[ ]*[0-9a-f]+: 8b 40 12[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+18\]
-[ ]*[0-9a-f]+: 8b 04 85 02 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*4\+2\]
-[ ]*[0-9a-f]+: 8b 04 85 02 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*4\+2\]
+[ ]*[0-9a-f]+: 8b 04 85 02 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*4\+(0x)?2\]
+[ ]*[0-9a-f]+: 8b 04 85 02 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*4\+(0x)?2\]
[ ]*[0-9a-f]+: 8b 04 45 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*2\]
[ ]*[0-9a-f]+: 8b 04 45 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*2\]
[ ]*[0-9a-f]+: 8b 04 8d 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[ecx\*4\]
@@ -156,7 +156,7 @@ Disassembly of section .text:
[ ]*[0-9a-f]+: 8b 80 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\]
[ ]*[0-9a-f]+: 8b 40 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+1]
[ ]*[0-9a-f]+: 8b 80 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\]
-[ ]*[0-9a-f]+: 8b 80 01 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+1\]
+[ ]*[0-9a-f]+: 8b 80 01 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+(0x)?1\]
[ ]*[0-9a-f]+: 8b 80 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\]
[ ]*[0-9a-f]+: 8b 40 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+1\]
[ ]*[0-9a-f]+: a1 01 00 00 00[ ]+mov[ ]+eax,ds:0x1
--- /home/jbeulich/src/binutils/mainline/2005-05-18/opcodes/i386-dis.c 2005-05-09 08:31:57.000000000 +0200
+++ 2005-05-18/opcodes/i386-dis.c 2005-05-24 11:14:52.984223704 +0200
@@ -3342,22 +3342,23 @@ OP_E (int bytemode, int sizeflag)
oappend (scratchbuf);
}
}
- if (intel_syntax)
- if (mod != 0 || (base & 7) == 5)
- {
- /* Don't print zero displacements. */
- if (disp != 0)
- {
- if ((bfd_signed_vma) disp > 0)
- {
- *obufp++ = '+';
- *obufp = '\0';
- }
-
- print_operand_value (scratchbuf, 0, disp);
- oappend (scratchbuf);
- }
- }
+ if (intel_syntax && disp)
+ {
+ if ((bfd_signed_vma) disp > 0)
+ {
+ *obufp++ = '+';
+ *obufp = '\0';
+ }
+ else if (mod != 1)
+ {
+ *obufp++ = '-';
+ *obufp = '\0';
+ disp = - (bfd_signed_vma) disp;
+ }
+
+ print_operand_value (scratchbuf, mod != 1, disp);
+ oappend (scratchbuf);
+ }
*obufp++ = close_char;
*obufp = '\0';
@@ -3415,10 +3416,41 @@ OP_E (int bytemode, int sizeflag)
{
*obufp++ = open_char;
*obufp = '\0';
- oappend (index16[rm + add]);
+ oappend (index16[rm]);
+ if (intel_syntax && disp)
+ {
+ if ((bfd_signed_vma) disp > 0)
+ {
+ *obufp++ = '+';
+ *obufp = '\0';
+ }
+ else if (mod != 1)
+ {
+ *obufp++ = '-';
+ *obufp = '\0';
+ disp = - (bfd_signed_vma) disp;
+ }
+
+ print_operand_value (scratchbuf, mod != 1, disp);
+ oappend (scratchbuf);
+ }
+
*obufp++ = close_char;
*obufp = '\0';
}
+ else if (intel_syntax)
+ {
+ if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
+ | PREFIX_ES | PREFIX_FS | PREFIX_GS))
+ ;
+ else
+ {
+ oappend (names_seg[ds_reg - es_reg]);
+ oappend (":");
+ }
+ print_operand_value (scratchbuf, 1, disp & 0xffff);
+ oappend (scratchbuf);
+ }
}
}
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] x86: Intel disassembly displacement adjustments
2005-05-24 9:32 [PATCH] x86: Intel disassembly displacement adjustments Jan Beulich
@ 2005-05-25 4:49 ` Alan Modra
0 siblings, 0 replies; 2+ messages in thread
From: Alan Modra @ 2005-05-25 4:49 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Tue, May 24, 2005 at 11:30:46AM +0200, Jan Beulich wrote:
> gas/testsuite/
> 2005-05-24 Jan Beulich <jbeulich@novell.com>
>
> * gas/i386/intelok.d: Account for 32-bit displacements being shown
> in hex.
>
> opcodes/
> 2005-05-24 Jan Beulich <jbeulich@novell.com>
>
> * i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
> hex (but retain it being displayed as signed). Remove redundant
> checks. Add handling of displacements for 16-bit addressing in Intel
> mode.
Looks good to me.
--
Alan Modra
IBM OzLabs - Linux Technology Centre
^ permalink raw reply [flat|nested] 2+ messages in thread
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2005-05-25 4:49 ` Alan Modra
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