* [PATCH] Improve comments in include/opcode/mips.h
@ 2006-04-27 1:14 Thiemo Seufer
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From: Thiemo Seufer @ 2006-04-27 1:14 UTC (permalink / raw)
To: binutils
Hello All,
I committed the appended patch.
Thiemo
2006-04-26 Thiemo Seufer <ths@networkno.de>
* mips.h: Improve comments describing the bitfield instruction
fields.
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.46
diff -u -p -r1.46 mips.h
--- include/opcode/mips.h 14 Nov 2005 02:25:39 -0000 1.46
+++ include/opcode/mips.h 26 Apr 2006 18:06:52 -0000
@@ -268,19 +268,20 @@ struct mips_opcode
"x" accept and ignore register name
"z" must be zero register
"K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
- "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
+ "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
+ LSB (OP_*_SHAMT).
Enforces: 0 <= pos < 32.
- "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB).
+ "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
Requires that "+A" or "+E" occur first to set position.
Enforces: 0 < (pos+size) <= 32.
- "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD).
+ "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
Requires that "+A" or "+E" occur first to set position.
Enforces: 0 < (pos+size) <= 32.
(Also used by "dext" w/ different limits, but limits for
that are checked by the M_DEXT macro.)
- "+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT).
+ "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
Enforces: 32 <= pos < 64.
- "+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB).
+ "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
Requires that "+A" or "+E" occur first to set position.
Enforces: 32 < (pos+size) <= 64.
"+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
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2006-04-27 1:14 [PATCH] Improve comments in include/opcode/mips.h Thiemo Seufer
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