From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 20168 invoked by alias); 22 May 2006 23:47:51 -0000 Received: (qmail 20160 invoked by uid 22791); 22 May 2006 23:47:51 -0000 X-Spam-Check-By: sourceware.org Received: from bender.bawue.de (HELO bender.bawue.de) (193.7.176.20) by sourceware.org (qpsmtpd/0.31) with ESMTP; Mon, 22 May 2006 23:47:49 +0000 Received: from lagash (88-106-136-76.dynamic.dsl.as9105.com [88.106.136.76]) (using TLSv1 with cipher DES-CBC3-SHA (168/168 bits)) (No client certificate requested) by bender.bawue.de (Postfix) with ESMTP id 0CA3944191; Tue, 23 May 2006 01:46:57 +0200 (MEST) Received: from ths by lagash with local (Exim 4.62) (envelope-from ) id 1FiK6k-0008NT-32; Tue, 23 May 2006 00:46:42 +0100 Date: Tue, 23 May 2006 04:40:00 -0000 From: Thiemo Seufer To: Eric Christopher Cc: binutils@sourceware.org Subject: Re: [PATCH] Better checking of ISA/ASE/ABI options for MIPS gas Message-ID: <20060522234641.GA9061@networkno.de> References: <20060522202627.GE30254@networkno.de> <9C4668ED-B9FB-4A18-BCF4-CA7F5DFFE0E1@apple.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <9C4668ED-B9FB-4A18-BCF4-CA7F5DFFE0E1@apple.com> User-Agent: Mutt/1.5.11+cvs20060403 X-IsSubscribed: yes Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org X-SW-Source: 2006-05/txt/msg00391.txt.bz2 Eric Christopher wrote: > > > >I'm somewhat uncertain about the ABI incompatibility warning for > >wrong FP register widths, does it make sense to force a different > >FP register width in the assembler in some cases? > > > > No. No more reading the minds of programmers. :) Well, for GP registers we do even as_bad(). > btw, the indention on the code in the diff is wacky. I assume it's > correct in your files? I think so. > >@@ -1031,7 +1052,13 @@ static int validate_mips_insn (const str > > struct mips_cpu_info > > { > > const char *name; /* CPU or ISA name. */ > >- int is_isa; /* Is this an ISA? (If 0, a CPU.) */ > >+ int flags; > >+#define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a > >CPU.) */ > >+#define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS > >ASE */ > >+#define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ > >+#define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ > >+#define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ > >+#define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ > > int isa; /* ISA level. */ > > int cpu; /* CPU number (default CPU if ISA). */ > > }; > > Ugh. Can you haul these defines out somewhere else? Sure. > And why change the table to include default extensions for the cpu? To handle them the same way as the ISA. This is for ASEs which are always implemented in that particular CPU. > > /* End of GCC-shared inference code. */ > > You need to make sure that this shared code is the same logic in both > places - preferably before committing this. Yes. Do you think the logic is ok (modulo the FP ABI warning)? > >+#if 0 /* XXX FIXME */ > >+ /* 32 bit code with 64 bit FP registers. */ > >+ if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) > >+ elf_elfheader (stdoutput)->e_flags |= ???; > >+#endif > > } > > > > ??? Same like for MIPS3D, we should tell the linker this object is (possibly) incompatible to other O32 objects with 32bit FP regs. Thiemo