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Date: Tue, 06 Jun 2006 13:41:00 -0000
To: binutils@sourceware.org
Subject: [PATCH] MIPS gas DSP64 ASE support
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From: Thiemo Seufer <ths@networkno.de>
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Hello All,

I committed the appended patch. It adds 64 bit DSP ASE support to gas.


Thiemo


2006-06-06  Thiemo Seufer  <ths@mips.com>
            Chao-ying Fu  <fu@mips.com>

	[ gas/ChangeLog ]
	* config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro.
	(CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete.
	(macro_build): Update comment.
	(mips_ip): Allow DSP64 instructions for MIPS64R2.
	(mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and
	CPU_HAS_MDMX.
	(mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and
	MIPS_CPU_ASE_MDMX flags for sb1.

	[ gas/testsuite/ChangeLog ]
	* gas/mips/mips64-dsp.s, gas/mips/mips64-dsp.d: New DSP64 tests.
	* gas/mips/mips.exp: Run DSP64 tests.

	[ opcodes/ChangeLog ]
	* mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
	* mips-opc.c: Add DSP64 instructions.


Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.339
diff -u -p -r1.339 tc-mips.c
--- gas/config/tc-mips.c	5 Jun 2006 16:28:36 -0000	1.339
+++ gas/config/tc-mips.c	6 Jun 2006 10:22:45 -0000
@@ -284,6 +284,8 @@ static int file_ase_dsp;
 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2		\
 			      || mips_opts.isa == ISA_MIPS64R2)
 
+#define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
+
 /* True if -mmt was passed or implied by arguments passed on the
    command line (e.g., by -march).  */
 static int file_ase_mt;
@@ -401,22 +403,6 @@ static int mips_32bitmode = 0;
    (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0		\
     || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
 
-/* Return true if the given CPU supports the MIPS3D ASE.  */
-#define CPU_HAS_MIPS3D(cpu)	((cpu) == CPU_SB1      \
-				 )
-
-/* Return true if the given CPU supports the MDMX ASE.  */
-#define CPU_HAS_MDMX(cpu)	(FALSE                 \
-				 )
-
-/* Return true if the given CPU supports the DSP ASE.  */
-#define CPU_HAS_DSP(cpu)	(FALSE                 \
-				 )
-
-/* Return true if the given CPU supports the MT ASE.  */
-#define CPU_HAS_MT(cpu)		(FALSE                 \
-				 )
-
 /* True if CPU has a dror instruction.  */
 #define CPU_HAS_DROR(CPU)	((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
 
@@ -3301,7 +3287,7 @@ macro_build (expressionS *ep, const char
   assert (strcmp (name, mo->name) == 0);
 
   /* Search until we get a match for NAME.  It is assumed here that
-     macros will never generate MDMX or MIPS-3D instructions.  */
+     macros will never generate MDMX, MIPS-3D, DSP or MT instructions.  */
   while (strcmp (fmt, mo->args) != 0
 	 || mo->pinfo == INSN_MACRO
 	 || !OPCODE_IS_MEMBER (mo,
@@ -8371,6 +8357,8 @@ mips_ip (char *str, struct mips_cl_insn 
 			     | (file_ase_mips16 ? INSN_MIPS16 : 0)
 	      		     | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
 	      		     | (mips_opts.ase_dsp ? INSN_DSP : 0)
+	      		     | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
+				? INSN_DSP64 : 0)
 	      		     | (mips_opts.ase_mt ? INSN_MT : 0)
 			     | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)
 			     | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
@@ -11451,15 +11439,13 @@ mips_after_parse_args (void)
   if (mips_opts.mips16 == -1)
     mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
   if (mips_opts.ase_mips3d == -1)
-    mips_opts.ase_mips3d = ((CPU_HAS_MIPS3D (file_mips_arch)
-			     || (arch_info->flags & MIPS_CPU_ASE_MIPS3D))
+    mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
 			    && file_mips_fp32 == 0) ? 1 : 0;
   if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
     as_bad (_("-mfp32 used with -mips3d"));
 
   if (mips_opts.ase_mdmx == -1)
-    mips_opts.ase_mdmx = ((CPU_HAS_MDMX (file_mips_arch)
-			   || (arch_info->flags & MIPS_CPU_ASE_MDMX))
+    mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
 			  && file_mips_fp32 == 0) ? 1 : 0;
   if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
     as_bad (_("-mfp32 used with -mdmx"));
@@ -14588,11 +14574,11 @@ static const struct mips_cpu_info mips_c
   { "24ke",           MIPS_CPU_ASE_DSP,		ISA_MIPS32R2,	CPU_MIPS32R2 },
   { "24kec",          MIPS_CPU_ASE_DSP,		ISA_MIPS32R2,	CPU_MIPS32R2 },
   { "24kef",          MIPS_CPU_ASE_DSP,		ISA_MIPS32R2,	CPU_MIPS32R2 },
-  { "24kex",         MIPS_CPU_ASE_DSP,		ISA_MIPS32R2,	CPU_MIPS32R2 },
+  { "24kex",          MIPS_CPU_ASE_DSP,		ISA_MIPS32R2,	CPU_MIPS32R2 },
   /* 34k is a 24k with MT ASE, other ASEs are optional.  */
   { "34kc",           MIPS_CPU_ASE_MT,		ISA_MIPS32R2,	CPU_MIPS32R2 },
   { "34kf",           MIPS_CPU_ASE_MT,		ISA_MIPS32R2,	CPU_MIPS32R2 },
-  { "34kx",          MIPS_CPU_ASE_MT,		ISA_MIPS32R2,	CPU_MIPS32R2 },
+  { "34kx",           MIPS_CPU_ASE_MT,		ISA_MIPS32R2,	CPU_MIPS32R2 },
 
   /* MIPS 64 */
   { "5kc",            0,			ISA_MIPS64,	CPU_MIPS64 },
@@ -14603,7 +14589,8 @@ static const struct mips_cpu_info mips_c
   { "25kf",           MIPS_CPU_ASE_MIPS3D,	ISA_MIPS64R2,   CPU_MIPS64R2 },
 
   /* Broadcom SB-1 CPU core */
-  { "sb1",            0,			ISA_MIPS64,	CPU_SB1 },
+  { "sb1",            MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
+						ISA_MIPS64,	CPU_SB1 },
 
   /* End marker */
   { NULL, 0, 0, 0 }
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.50
diff -u -p -r1.50 mips.h
--- include/opcode/mips.h	5 May 2006 15:41:23 -0000	1.50
+++ include/opcode/mips.h	31 May 2006 07:55:50 -0000
@@ -485,16 +485,15 @@ struct mips_opcode
 #define INSN_ISA64R2              0x00000100
 
 /* Masks used for MIPS-defined ASEs.  */
-#define INSN_ASE_MASK		  0x0c00f000
+#define INSN_ASE_MASK		  0x1c00f000
 
 /* DSP ASE */ 
 #define INSN_DSP                  0x00001000
+#define INSN_DSP64                0x00002000
 /* MIPS 16 ASE */
-#define INSN_MIPS16               0x00002000
+#define INSN_MIPS16               0x00004000
 /* MIPS-3D ASE */
-#define INSN_MIPS3D               0x00004000
-/* MDMX ASE */ 
-#define INSN_MDMX                 0x00008000
+#define INSN_MIPS3D               0x00008000
 
 /* Chip specific instructions.  These are bitmasks.  */
 
@@ -519,11 +518,12 @@ struct mips_opcode
 /* NEC VR5500 instruction.  */
 #define INSN_5500		  0x02000000
 
+/* MDMX ASE */ 
+#define INSN_MDMX                 0x04000000
 /* MT ASE */
-#define INSN_MT                   0x04000000
-
+#define INSN_MT                   0x08000000
 /* SmartMIPS ASE.  */
-#define INSN_SMARTMIPS            0x08000000
+#define INSN_SMARTMIPS            0x10000000
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.62
diff -u -p -r1.62 mips-dis.c
--- opcodes/mips-dis.c	4 May 2006 10:47:05 -0000	1.62
+++ opcodes/mips-dis.c	31 May 2006 07:56:01 -0000
@@ -414,7 +414,7 @@ const struct mips_arch_choice mips_arch_
     mips_hwr_names_numeric },
 
   { "mips64r2",	1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
-    (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP
+    (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSP64
      | INSN_MT | INSN_MDMX),
     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.58
diff -u -p -r1.58 mips-opc.c
--- opcodes/mips-opc.c	5 May 2006 15:41:23 -0000	1.58
+++ opcodes/mips-opc.c	31 May 2006 07:56:01 -0000
@@ -148,6 +148,7 @@ Software Foundation, 51 Franklin Street 
 #define MOD_a	WR_a|RD_a
 #define DSP_VOLA	INSN_TRAP
 #define D32	INSN_DSP
+#define D64	INSN_DSP64
 
 /* MIPS MT ASE support.  */
 #define MT32	INSN_MT
@@ -1391,40 +1392,94 @@ const struct mips_opcode mips_builtin_op
 {"cop1",     "C",	0,    (int) M_COP1,	INSN_MACRO,		0,		I1	},
 {"cop2",     "C",	0,    (int) M_COP2,	INSN_MACRO,		0,		I1	},
 {"cop3",     "C",	0,    (int) M_COP3,	INSN_MACRO,		0,		I1	},
-
   /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
      4010 any more, so move this insn out of the way.  If the object
      format gave us more info, we could do this right.  */
 {"addciu",  "t,r,j",	0x70000000, 0xfc000000,	WR_t|RD_s,		0,		L1	},
 /* MIPS DSP ASE */
 {"absq_s.ph", "d,t",	0x7c000252, 0xffe007ff, WR_d|RD_t,		0,		D32	},
+{"absq_s.pw", "d,t",	0x7c000456, 0xffe007ff, WR_d|RD_t,		0,		D64	},
+{"absq_s.qh", "d,t",	0x7c000256, 0xffe007ff, WR_d|RD_t,		0,		D64	},
 {"absq_s.w", "d,t",	0x7c000452, 0xffe007ff, WR_d|RD_t,		0,		D32	},
 {"addq.ph", "d,s,t",	0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
+{"addq.pw", "d,s,t",	0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
+{"addq.qh", "d,s,t",	0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
 {"addq_s.ph", "d,s,t",	0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
+{"addq_s.pw", "d,s,t",	0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
+{"addq_s.qh", "d,s,t",	0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
 {"addq_s.w", "d,s,t",	0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
 {"addsc",   "d,s,t",	0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
+{"addu.ob", "d,s,t",	0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
 {"addu.qb", "d,s,t",	0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
+{"addu_s.ob", "d,s,t",	0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
 {"addu_s.qb", "d,s,t",	0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
 {"addwc",   "d,s,t",	0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
 {"bitrev",  "d,t",	0x7c0006d2, 0xffe007ff, WR_d|RD_t,		0,		D32	},
 {"bposge32", "p",	0x041c0000, 0xffff0000, CBD,			0,		D32	},
+{"bposge64", "p",	0x041d0000, 0xffff0000, CBD,			0,		D64	},
 {"cmp.eq.ph", "s,t",	0x7c000211, 0xfc00ffff, RD_s|RD_t,		0,		D32	},
+{"cmp.eq.pw", "s,t",	0x7c000415, 0xfc00ffff, RD_s|RD_t,		0,		D64	},
+{"cmp.eq.qh", "s,t",	0x7c000215, 0xfc00ffff, RD_s|RD_t,		0,		D64	},
+{"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D64	},
 {"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
+{"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D64	},
 {"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
+{"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D64	},
 {"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
 {"cmp.le.ph", "s,t",	0x7c000291, 0xfc00ffff, RD_s|RD_t,		0,		D32	},
+{"cmp.le.pw", "s,t",	0x7c000495, 0xfc00ffff, RD_s|RD_t,		0,		D64	},
+{"cmp.le.qh", "s,t",	0x7c000295, 0xfc00ffff, RD_s|RD_t,		0,		D64	},
 {"cmp.lt.ph", "s,t",	0x7c000251, 0xfc00ffff, RD_s|RD_t,		0,		D32	},
+{"cmp.lt.pw", "s,t",	0x7c000455, 0xfc00ffff, RD_s|RD_t,		0,		D64	},
+{"cmp.lt.qh", "s,t",	0x7c000255, 0xfc00ffff, RD_s|RD_t,		0,		D64	},
+{"cmpu.eq.ob", "s,t",	0x7c000015, 0xfc00ffff, RD_s|RD_t,		0,		D64	},
 {"cmpu.eq.qb", "s,t",	0x7c000011, 0xfc00ffff, RD_s|RD_t,		0,		D32	},
+{"cmpu.le.ob", "s,t",	0x7c000095, 0xfc00ffff, RD_s|RD_t,		0,		D64	},
 {"cmpu.le.qb", "s,t",	0x7c000091, 0xfc00ffff, RD_s|RD_t,		0,		D32	},
+{"cmpu.lt.ob", "s,t",	0x7c000055, 0xfc00ffff, RD_s|RD_t,		0,		D64	},
 {"cmpu.lt.qb", "s,t",	0x7c000051, 0xfc00ffff, RD_s|RD_t,		0,		D32	},
+{"dextpdp", "t,7,6",	0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,	0,		D64	},
+{"dextpdpv", "t,7,s",	0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,		D64	},
+{"dextp",   "t,7,6",	0x7c0000bc, 0xfc00e7ff, WR_t|RD_a,		0,		D64	},
+{"dextpv",  "t,7,s",	0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s,		0,		D64	},
+{"dextr.l", "t,7,6",	0x7c00043c, 0xfc00e7ff, WR_t|RD_a,		0,		D64	},
+{"dextr_r.l", "t,7,6",	0x7c00053c, 0xfc00e7ff, WR_t|RD_a,		0,		D64	},
+{"dextr_rs.l", "t,7,6",	0x7c0005bc, 0xfc00e7ff, WR_t|RD_a,		0,		D64	},
+{"dextr_rs.w", "t,7,6",	0x7c0001bc, 0xfc00e7ff, WR_t|RD_a,		0,		D64	},
+{"dextr_r.w", "t,7,6",	0x7c00013c, 0xfc00e7ff, WR_t|RD_a,		0,		D64	},
+{"dextr_s.h", "t,7,6",	0x7c0003bc, 0xfc00e7ff, WR_t|RD_a,		0,		D64	},
+{"dextrv.l", "t,7,s",	0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s,		0,		D64	},
+{"dextrv_r.l", "t,7,s",	0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s,		0,		D64	},
+{"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s,	0,		D64	},
+{"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s,	0,		D64	},
+{"dextrv_r.w", "t,7,s",	0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s,		0,		D64	},
+{"dextrv_s.h", "t,7,s",	0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s,		0,		D64	},
+{"dextrv.w", "t,7,s",	0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s,		0,		D64	},
+{"dextr.w", "t,7,6",	0x7c00003c, 0xfc00e7ff, WR_t|RD_a,		0,		D64	},
+{"dinsv",   "t,s",	0x7c00000d, 0xfc00ffff, WR_t|RD_s,		0,		D64	},
+{"dmadd",   "7,s,t",	0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
+{"dmaddu",  "7,s,t",	0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
+{"dmsub",   "7,s,t",	0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
+{"dmsubu",  "7,s,t",	0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
+{"dmthlip", "s,7",	0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,	0,		D64	},
+{"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
 {"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
 {"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
+{"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
+{"dpau.h.obl", "7,s,t",	0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
+{"dpau.h.obr", "7,s,t",	0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
 {"dpau.h.qbl", "7,s,t",	0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
 {"dpau.h.qbr", "7,s,t",	0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
+{"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
 {"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
 {"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
+{"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
+{"dpsu.h.obl", "7,s,t",	0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
+{"dpsu.h.obr", "7,s,t",	0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
 {"dpsu.h.qbl", "7,s,t",	0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
 {"dpsu.h.qbr", "7,s,t",	0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
+{"dshilo",  "7,:",	0x7c0006bc, 0xfc07e7ff, MOD_a,			0,		D64	},
+{"dshilov", "7,s",	0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s,		0,		D64	},
 {"extpdp",  "t,7,6",	0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,	0,		D32	},
 {"extpdpv", "t,7,s",	0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,		D32	},
 {"extp",    "t,7,6",	0x7c0000b8, 0xfc00e7ff, WR_t|RD_a,		0,		D32	},
@@ -1439,66 +1494,140 @@ const struct mips_opcode mips_builtin_op
 {"extr.w",  "t,7,6",	0x7c000038, 0xfc00e7ff, WR_t|RD_a,		0,		D32	},
 {"insv",    "t,s",	0x7c00000c, 0xfc00ffff, WR_t|RD_s,		0,		D32	},
 {"lbux",    "d,t(b)",	0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,	0,		D32	},
+{"ldx",     "d,t(b)",	0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,	0,		D64	},
 {"lhx",     "d,t(b)",	0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,	0,		D32	},
 {"lwx",     "d,t(b)",	0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,	0,		D32	},
 {"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
 {"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
+{"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
+{"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
+{"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
+{"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
+{"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
+{"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
 {"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
 {"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
+{"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
+{"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
+{"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
+{"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
 {"modsub",  "d,s,t",	0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
 {"mthlip",  "s,7",	0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,	0,		D32	},
+{"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		D64	},
+{"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		D64	},
 {"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		D32	},
 {"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		D32	},
 {"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		D32	},
 {"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		D32	},
+{"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		D64	},
+{"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		D64	},
 {"mulq_rs.ph", "d,s,t",	0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO,	0,		D32	},
+{"mulq_rs.qh", "d,s,t",	0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO,	0,		D64	},
+{"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
 {"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
+{"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
 {"packrl.ph", "d,s,t",	0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
+{"packrl.pw", "d,s,t",	0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
+{"pick.ob", "d,s,t",	0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
 {"pick.ph", "d,s,t",	0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
+{"pick.pw", "d,s,t",	0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
 {"pick.qb", "d,s,t",	0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
+{"pick.qh", "d,s,t",	0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
+{"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t,		0,		D64	},
+{"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t,		0,		D64	},
+{"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t,		0,		D64	},
+{"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t,		0,		D64	},
+{"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t,		0,		D64	},
+{"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t,		0,		D64	},
 {"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t,		0,		D32	},
 {"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t,		0,		D32	},
 {"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t,		0,		D32	},
 {"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t,		0,		D32	},
+{"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t,		0,		D64	},
+{"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t,		0,		D64	},
+{"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t,		0,		D64	},
+{"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t,		0,		D64	},
 {"preceq.w.phl", "d,t",	0x7c000312, 0xffe007ff, WR_d|RD_t,		0,		D32	},
 {"preceq.w.phr", "d,t",	0x7c000352, 0xffe007ff, WR_d|RD_t,		0,		D32	},
 {"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t,		0,		D32	},
 {"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t,		0,		D32	},
 {"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t,		0,		D32	},
 {"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t,		0,		D32	},
+{"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t,		0,		D64	},
+{"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t,		0,		D64	},
+{"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t,		0,		D64	},
+{"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t,		0,		D64	},
+{"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D64	},
 {"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
+{"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D64	},
 {"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
+{"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D64	},
 {"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
+{"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D64	},
+{"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D64	},
 {"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
+{"raddu.l.ob", "d,s",	0x7c000514, 0xfc1f07ff, WR_d|RD_s,		0,		D64	},
 {"raddu.w.qb", "d,s",	0x7c000510, 0xfc1f07ff, WR_d|RD_s,		0,		D32	},
 {"rddsp",   "d",	0x7fff04b8, 0xffff07ff, WR_d,			0,		D32	},
 {"rddsp",   "d,'",	0x7c0004b8, 0xffc007ff, WR_d,			0,		D32	},
+{"repl.ob", "d,5",	0x7c000096, 0xff0007ff, WR_d,			0,		D64	},
 {"repl.ph", "d,@",	0x7c000292, 0xfc0007ff, WR_d,			0,		D32	},
+{"repl.pw", "d,@",	0x7c000496, 0xfc0007ff, WR_d,			0,		D64	},
 {"repl.qb", "d,5",	0x7c000092, 0xff0007ff, WR_d,			0,		D32	},
+{"repl.qh", "d,@",	0x7c000296, 0xfc0007ff, WR_d,			0,		D64	},
+{"replv.ob", "d,t",	0x7c0000d6, 0xffe007ff, WR_d|RD_t,		0,		D64	},
 {"replv.ph", "d,t",	0x7c0002d2, 0xffe007ff, WR_d|RD_t,		0,		D32	},
+{"replv.pw", "d,t",	0x7c0004d6, 0xffe007ff, WR_d|RD_t,		0,		D64	},
 {"replv.qb", "d,t",	0x7c0000d2, 0xffe007ff, WR_d|RD_t,		0,		D32	},
+{"replv.qh", "d,t",	0x7c0002d6, 0xffe007ff, WR_d|RD_t,		0,		D64	},
 {"shilo",   "7,0",	0x7c0006b8, 0xfc0fe7ff, MOD_a,			0,		D32	},
 {"shilov",  "7,s",	0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s,		0,		D32	},
+{"shll.ob", "d,t,3",	0x7c000017, 0xff0007ff, WR_d|RD_t,		0,		D64	},
 {"shll.ph", "d,t,4",	0x7c000213, 0xfe0007ff, WR_d|RD_t,		0,		D32	},
+{"shll.pw", "d,t,6",	0x7c000417, 0xfc0007ff, WR_d|RD_t,		0,		D64	},
 {"shll.qb", "d,t,3",	0x7c000013, 0xff0007ff, WR_d|RD_t,		0,		D32	},
+{"shll.qh", "d,t,4",	0x7c000217, 0xfe0007ff, WR_d|RD_t,		0,		D64	},
 {"shll_s.ph", "d,t,4",	0x7c000313, 0xfe0007ff, WR_d|RD_t,		0,		D32	},
+{"shll_s.pw", "d,t,6",	0x7c000517, 0xfc0007ff, WR_d|RD_t,		0,		D64	},
+{"shll_s.qh", "d,t,4",	0x7c000317, 0xfe0007ff, WR_d|RD_t,		0,		D64	},
 {"shll_s.w", "d,t,6",	0x7c000513, 0xfc0007ff, WR_d|RD_t,		0,		D32	},
+{"shllv.ob", "d,t,s",	0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
 {"shllv.ph", "d,t,s",	0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
+{"shllv.pw", "d,t,s",	0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
 {"shllv.qb", "d,t,s",	0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
+{"shllv.qh", "d,t,s",	0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
 {"shllv_s.ph", "d,t,s",	0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
+{"shllv_s.pw", "d,t,s",	0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
+{"shllv_s.qh", "d,t,s",	0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
 {"shllv_s.w", "d,t,s",	0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
 {"shra.ph", "d,t,4",	0x7c000253, 0xfe0007ff, WR_d|RD_t,		0,		D32	},
+{"shra.pw", "d,t,6",	0x7c000457, 0xfc0007ff, WR_d|RD_t,		0,		D64	},
+{"shra.qh", "d,t,4",	0x7c000257, 0xfe0007ff, WR_d|RD_t,		0,		D64	},
 {"shra_r.ph", "d,t,4",	0x7c000353, 0xfe0007ff, WR_d|RD_t,		0,		D32	},
+{"shra_r.pw", "d,t,6",	0x7c000557, 0xfc0007ff, WR_d|RD_t,		0,		D64	},
+{"shra_r.qh", "d,t,4",	0x7c000357, 0xfe0007ff, WR_d|RD_t,		0,		D64	},
 {"shra_r.w", "d,t,6",	0x7c000553, 0xfc0007ff, WR_d|RD_t,		0,		D32	},
 {"shrav.ph", "d,t,s",	0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
+{"shrav.pw", "d,t,s",	0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
+{"shrav.qh", "d,t,s",	0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
 {"shrav_r.ph", "d,t,s",	0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
+{"shrav_r.pw", "d,t,s",	0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
+{"shrav_r.qh", "d,t,s",	0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
 {"shrav_r.w", "d,t,s",	0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
+{"shrl.ob", "d,t,3",	0x7c000057, 0xff0007ff, WR_d|RD_t,		0,		D64	},
 {"shrl.qb", "d,t,3",	0x7c000053, 0xff0007ff, WR_d|RD_t,		0,		D32	},
+{"shrlv.ob", "d,t,s",	0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
 {"shrlv.qb", "d,t,s",	0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
 {"subq.ph", "d,s,t",	0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
+{"subq.pw", "d,s,t",	0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
+{"subq.qh", "d,s,t",	0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
 {"subq_s.ph", "d,s,t",	0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
+{"subq_s.pw", "d,s,t",	0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
+{"subq_s.qh", "d,s,t",	0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
 {"subq_s.w", "d,s,t",	0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
+{"subu.ob", "d,s,t",	0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
 {"subu.qb", "d,s,t",	0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
+{"subu_s.ob", "d,s,t",	0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
 {"subu_s.qb", "d,s,t",	0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
 {"wrdsp",   "s",	0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA,		0,		D32	},
 {"wrdsp",   "s,8",	0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA,		0,		D32	},
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.118
diff -u -p -r1.118 mips.exp
--- gas/testsuite/gas/mips/mips.exp	19 May 2006 22:48:13 -0000	1.118
+++ gas/testsuite/gas/mips/mips.exp	31 May 2006 07:55:45 -0000
@@ -770,6 +770,7 @@ if { [istarget mips*-*-vxworks*] } {
 
     run_dump_test_arches "smartmips"	[mips_arch_list_matching mips32 !gpr64]
     run_dump_test_arches "mips32-dsp"	[mips_arch_list_matching mips32r2]
+    run_dump_test_arches "mips64-dsp"	[mips_arch_list_matching mips64r2]
     run_dump_test_arches "mips32-mt"	[mips_arch_list_matching mips32r2 !gpr64]
 
     if { $elf && !$no_mips16 } {
--- /dev/null	2006-05-28 20:58:20.156000000 +0100
+++ gas/testsuite/gas/mips/mips64-dsp.d	2006-05-30 23:55:14.000000000 +0100
@@ -0,0 +1,172 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS DSP ASE for MIPS64
+#as: -mdsp
+
+# Check MIPS DSP ASE for MIPS64 Instruction Assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 7c010456 	absq_s\.pw	zero,at
+0+0004 <[^>]*> 7c1ff256 	absq_s\.qh	s8,ra
+0+0008 <[^>]*> 7cc72c94 	addq\.pw	a1,a2,a3
+0+000c <[^>]*> 7ce83594 	addq_s\.pw	a2,a3,t0
+0+0010 <[^>]*> 7c641294 	addq\.qh	v0,v1,a0
+0+0014 <[^>]*> 7c851b94 	addq_s\.qh	v1,a0,a1
+0+0018 <[^>]*> 7d4b4814 	addu\.ob	t1,t2,t3
+0+001c <[^>]*> 7d6c5114 	addu_s\.ob	t2,t3,t4
+0+0020 <[^>]*> 041dfff7 	bposge64	00000000 <text_label>
+0+0024 <[^>]*> 00000000 	nop
+0+0028 <[^>]*> 7e950415 	cmp\.eq\.pw	s4,s5
+0+002c <[^>]*> 7eb60455 	cmp\.lt\.pw	s5,s6
+0+0030 <[^>]*> 7ed70495 	cmp\.le\.pw	s6,s7
+0+0034 <[^>]*> 7e320215 	cmp\.eq\.qh	s1,s2
+0+0038 <[^>]*> 7e530255 	cmp\.lt\.qh	s2,s3
+0+003c <[^>]*> 7e740295 	cmp\.le\.qh	s3,s4
+0+0040 <[^>]*> 7dcf0015 	cmpu\.eq\.ob	t6,t7
+0+0044 <[^>]*> 7df00055 	cmpu\.lt\.ob	t7,s0
+0+0048 <[^>]*> 7e110095 	cmpu\.le\.ob	s0,s1
+0+004c <[^>]*> 7d2a4115 	cmpgu\.eq\.ob	t0,t1,t2
+0+0050 <[^>]*> 7d4b4955 	cmpgu\.lt\.ob	t1,t2,t3
+0+0054 <[^>]*> 7d6c5195 	cmpgu\.le\.ob	t2,t3,t4
+0+0058 <[^>]*> 7c1f1abc 	dextpdp	ra,\$ac3,0x0
+0+005c <[^>]*> 7c3f1abc 	dextpdp	ra,\$ac3,0x1
+0+0060 <[^>]*> 7fff1abc 	dextpdp	ra,\$ac3,0x1f
+0+0064 <[^>]*> 7c2002fc 	dextpdpv	zero,\$ac0,at
+0+0068 <[^>]*> 7c1d08bc 	dextp	sp,\$ac1,0x0
+0+006c <[^>]*> 7c3d08bc 	dextp	sp,\$ac1,0x1
+0+0070 <[^>]*> 7ffd08bc 	dextp	sp,\$ac1,0x1f
+0+0074 <[^>]*> 7ffe10fc 	dextpv	s8,\$ac2,ra
+0+0078 <[^>]*> 7c031c3c 	dextr\.l	v1,\$ac3,0x0
+0+007c <[^>]*> 7c231c3c 	dextr\.l	v1,\$ac3,0x1
+0+0080 <[^>]*> 7fe31c3c 	dextr\.l	v1,\$ac3,0x1f
+0+0084 <[^>]*> 7c04053c 	dextr_r\.l	a0,\$ac0,0x0
+0+0088 <[^>]*> 7c24053c 	dextr_r\.l	a0,\$ac0,0x1
+0+008c <[^>]*> 7fe4053c 	dextr_r\.l	a0,\$ac0,0x1f
+0+0090 <[^>]*> 7c050dbc 	dextr_rs\.l	a1,\$ac1,0x0
+0+0094 <[^>]*> 7c250dbc 	dextr_rs\.l	a1,\$ac1,0x1
+0+0098 <[^>]*> 7fe50dbc 	dextr_rs\.l	a1,\$ac1,0x1f
+0+009c <[^>]*> 7c01093c 	dextr_r\.w	at,\$ac1,0x0
+0+00a0 <[^>]*> 7c21093c 	dextr_r\.w	at,\$ac1,0x1
+0+00a4 <[^>]*> 7fe1093c 	dextr_r\.w	at,\$ac1,0x1f
+0+00a8 <[^>]*> 7c0211bc 	dextr_rs\.w	v0,\$ac2,0x0
+0+00ac <[^>]*> 7c2211bc 	dextr_rs\.w	v0,\$ac2,0x1
+0+00b0 <[^>]*> 7fe211bc 	dextr_rs\.w	v0,\$ac2,0x1f
+0+00b4 <[^>]*> 7c0213bc 	dextr_s\.h	v0,\$ac2,0x0
+0+00b8 <[^>]*> 7c2213bc 	dextr_s\.h	v0,\$ac2,0x1
+0+00bc <[^>]*> 7fe213bc 	dextr_s\.h	v0,\$ac2,0x1f
+0+00c0 <[^>]*> 7c00003c 	dextr\.w	zero,\$ac0,0x0
+0+00c4 <[^>]*> 7c20003c 	dextr\.w	zero,\$ac0,0x1
+0+00c8 <[^>]*> 7fe0003c 	dextr\.w	zero,\$ac0,0x1f
+0+00cc <[^>]*> 7d8b187c 	dextrv\.w	t3,\$ac3,t4
+0+00d0 <[^>]*> 7dac017c 	dextrv_r\.w	t4,\$ac0,t5
+0+00d4 <[^>]*> 7dcd09fc 	dextrv_rs\.w	t5,\$ac1,t6
+0+00d8 <[^>]*> 7dee147c 	dextrv\.l	t6,\$ac2,t7
+0+00dc <[^>]*> 7e0f1d7c 	dextrv_r\.l	t7,\$ac3,s0
+0+00e0 <[^>]*> 7e3005fc 	dextrv_rs\.l	s0,\$ac0,s1
+0+00e4 <[^>]*> 7f7a000d 	dinsv	k0,k1
+0+00e8 <[^>]*> 7e950e74 	dmadd	\$ac1,s4,s5
+0+00ec <[^>]*> 7eb61774 	dmaddu	\$ac2,s5,s6
+0+00f0 <[^>]*> 7ed71ef4 	dmsub	\$ac3,s6,s7
+0+00f4 <[^>]*> 7ef807f4 	dmsubu	\$ac0,s7,t8
+0+00f8 <[^>]*> 7c8017fc 	dmthlip	a0,\$ac2
+0+00fc <[^>]*> 7c010b34 	dpaq_sa\.l\.pw	\$ac1,zero,at
+0+0100 <[^>]*> 7eb61134 	dpaq_s\.w\.qh	\$ac2,s5,s6
+0+0104 <[^>]*> 7df000f4 	dpau\.h\.obl	\$ac0,t7,s0
+0+0108 <[^>]*> 7e1109f4 	dpau\.h\.obr	\$ac1,s0,s1
+0+010c <[^>]*> 7c640374 	dpsq_sa\.l\.pw	\$ac0,v1,a0
+0+0110 <[^>]*> 7f190974 	dpsq_s\.w\.qh	\$ac1,t8,t9
+0+0114 <[^>]*> 7e3212f4 	dpsu\.h\.obl	\$ac2,s1,s2
+0+0118 <[^>]*> 7e531bf4 	dpsu\.h\.obr	\$ac3,s2,s3
+0+011c <[^>]*> 7e001ebc 	dshilo	\$ac3,-64
+0+0120 <[^>]*> 7df81ebc 	dshilo	\$ac3,63
+0+0124 <[^>]*> 7c4006fc 	dshilov	\$ac0,v0
+0+0128 <[^>]*> 7e51820a 	ldx	s0,s1\(s2\)
+0+012c <[^>]*> 7d4b1c34 	maq_sa\.w\.qhll	\$ac3,t2,t3
+0+0130 <[^>]*> 7d6c0474 	maq_sa\.w\.qhlr	\$ac0,t3,t4
+0+0134 <[^>]*> 7d8d0cb4 	maq_sa\.w\.qhrl	\$ac1,t4,t5
+0+0138 <[^>]*> 7dae14f4 	maq_sa\.w\.qhrr	\$ac2,t5,t6
+0+013c <[^>]*> 7e110f34 	maq_s\.l\.pwl	\$ac1,s0,s1
+0+0140 <[^>]*> 7e3217b4 	maq_s\.l\.pwr	\$ac2,s1,s2
+0+0144 <[^>]*> 7d4b1d34 	maq_s\.w\.qhll	\$ac3,t2,t3
+0+0148 <[^>]*> 7d6c0574 	maq_s\.w\.qhlr	\$ac0,t3,t4
+0+014c <[^>]*> 7d8d0db4 	maq_s\.w\.qhrl	\$ac1,t4,t5
+0+0150 <[^>]*> 7dae15f4 	maq_s\.w\.qhrr	\$ac2,t5,t6
+0+0154 <[^>]*> 7d8d5f14 	muleq_s\.pw\.qhl	t3,t4,t5
+0+0158 <[^>]*> 7dae6754 	muleq_s\.pw\.qhr	t4,t5,t6
+0+015c <[^>]*> 7ca62194 	muleu_s\.qh\.obl	a0,a1,a2
+0+0160 <[^>]*> 7cc729d4 	muleu_s\.qh\.obr	a1,a2,a3
+0+0164 <[^>]*> 7ce837d0 	mulq_rs\.ph	a2,a3,t0
+0+0168 <[^>]*> 7d2a47d4 	mulq_rs\.qh	t0,t1,t2
+0+016c <[^>]*> 7f7c01b4 	mulsaq_s\.w\.qh	\$ac0,k1,gp
+0+0170 <[^>]*> 7fbe13b4 	mulsaq_s\.l\.pw	\$ac2,sp,s8
+0+0174 <[^>]*> 7fbee395 	packrl\.pw	gp,sp,s8
+0+0178 <[^>]*> 7f5bc8d5 	pick\.ob	t9,k0,k1
+0+017c <[^>]*> 7f7cd2d5 	pick\.qh	k0,k1,gp
+0+0180 <[^>]*> 7f9ddcd5 	pick\.pw	k1,gp,sp
+0+0184 <[^>]*> 7c0f7316 	preceq\.pw\.qhl	t6,t7
+0+0188 <[^>]*> 7c107b56 	preceq\.pw\.qhr	t7,s0
+0+018c <[^>]*> 7c118396 	preceq\.pw\.qhla	s0,s1
+0+0190 <[^>]*> 7c128bd6 	preceq\.pw\.qhra	s1,s2
+0+0194 <[^>]*> 7c139516 	preceq\.s\.l\.pwl	s2,s3
+0+0198 <[^>]*> 7c149d56 	preceq\.s\.l\.pwr	s3,s4
+0+019c <[^>]*> 7c19c116 	precequ\.pw\.qhl	t8,t9
+0+01a0 <[^>]*> 7c1ac956 	precequ\.pw\.qhr	t9,k0
+0+01a4 <[^>]*> 7c1bd196 	precequ\.pw\.qhla	k0,k1
+0+01a8 <[^>]*> 7c1cd9d6 	precequ\.pw\.qhra	k1,gp
+0+01ac <[^>]*> 7c1de716 	preceu\.qh\.obl	gp,sp
+0+01b0 <[^>]*> 7c1eef56 	preceu\.qh\.obr	sp,s8
+0+01b4 <[^>]*> 7c1ff796 	preceu\.qh\.obla	s8,ra
+0+01b8 <[^>]*> 7c00ffd6 	preceu\.qh\.obra	ra,zero
+0+01bc <[^>]*> 7ca62315 	precrq\.ob\.qh	a0,a1,a2
+0+01c0 <[^>]*> 7d093f15 	precrq\.pw\.l	a3,t0,t1
+0+01c4 <[^>]*> 7cc72d15 	precrq\.qh\.pw	a1,a2,a3
+0+01c8 <[^>]*> 7ce83555 	precrq_rs\.qh\.pw	a2,a3,t0
+0+01cc <[^>]*> 7d4b4bd5 	precrqu_s\.ob\.qh	t1,t2,t3
+0+01d0 <[^>]*> 7f60d514 	raddu\.l\.ob	k0,k1
+0+01d4 <[^>]*> 7c00e896 	repl\.ob	sp,0x0
+0+01d8 <[^>]*> 7cffe896 	repl\.ob	sp,0xff
+0+01dc <[^>]*> 7c1ff0d6 	replv\.ob	s8,ra
+0+01e0 <[^>]*> 7e000a96 	repl\.qh	at,-512
+0+01e4 <[^>]*> 7dff0a96 	repl\.qh	at,511
+0+01e8 <[^>]*> 7c0312d6 	replv\.qh	v0,v1
+0+01ec <[^>]*> 7e001c96 	repl\.pw	v1,-512
+0+01f0 <[^>]*> 7dff1c96 	repl\.pw	v1,511
+0+01f4 <[^>]*> 7c0524d6 	replv\.pw	a0,a1
+0+01f8 <[^>]*> 7c031017 	shll\.ob	v0,v1,0x0
+0+01fc <[^>]*> 7ce31017 	shll\.ob	v0,v1,0x7
+0+0200 <[^>]*> 7ca41897 	shllv\.ob	v1,a0,a1
+0+0204 <[^>]*> 7c094217 	shll\.qh	t0,t1,0x0
+0+0208 <[^>]*> 7de94217 	shll\.qh	t0,t1,0xf
+0+020c <[^>]*> 7d6a4a97 	shllv\.qh	t1,t2,t3
+0+0210 <[^>]*> 7c0b5317 	shll_s\.qh	t2,t3,0x0
+0+0214 <[^>]*> 7deb5317 	shll_s\.qh	t2,t3,0xf
+0+0218 <[^>]*> 7dac5b97 	shllv_s\.qh	t3,t4,t5
+0+021c <[^>]*> 7c0f7417 	shll\.pw	t6,t7,0x0
+0+0220 <[^>]*> 7fef7417 	shll\.pw	t6,t7,0x1f
+0+0224 <[^>]*> 7e307c97 	shllv\.pw	t7,s0,s1
+0+0228 <[^>]*> 7c118517 	shll_s\.pw	s0,s1,0x0
+0+022c <[^>]*> 7ff18517 	shll_s\.pw	s0,s1,0x1f
+0+0230 <[^>]*> 7e728d97 	shllv_s\.pw	s1,s2,s3
+0+0234 <[^>]*> 7c1de257 	shra\.qh	gp,sp,0x0
+0+0238 <[^>]*> 7dfde257 	shra\.qh	gp,sp,0xf
+0+023c <[^>]*> 7ffeead7 	shrav\.qh	sp,s8,ra
+0+0240 <[^>]*> 7c1ff357 	shra_r\.qh	s8,ra,0x0
+0+0244 <[^>]*> 7dfff357 	shra_r\.qh	s8,ra,0xf
+0+0248 <[^>]*> 7c20fbd7 	shrav_r\.qh	ra,zero,at
+0+024c <[^>]*> 7c010457 	shra\.pw	zero,at,0x0
+0+0250 <[^>]*> 7fe10457 	shra\.pw	zero,at,0x1f
+0+0254 <[^>]*> 7c620cd7 	shrav\.pw	at,v0,v1
+0+0258 <[^>]*> 7c031557 	shra_r\.pw	v0,v1,0x0
+0+025c <[^>]*> 7fe31557 	shra_r\.pw	v0,v1,0x1f
+0+0260 <[^>]*> 7ca41dd7 	shrav_r\.pw	v1,a0,a1
+0+0264 <[^>]*> 7c15a057 	shrl\.ob	s4,s5,0x0
+0+0268 <[^>]*> 7cf5a057 	shrl\.ob	s4,s5,0x7
+0+026c <[^>]*> 7ef6a8d7 	shrlv\.ob	s5,s6,s7
+0+0270 <[^>]*> 7e3282d4 	subq\.qh	s0,s1,s2
+0+0274 <[^>]*> 7e538bd4 	subq_s\.qh	s1,s2,s3
+0+0278 <[^>]*> 7e7494d4 	subq\.pw	s2,s3,s4
+0+027c <[^>]*> 7e959dd4 	subq_s\.pw	s3,s4,s5
+0+0280 <[^>]*> 7eb6a054 	subu\.ob	s4,s5,s6
+0+0284 <[^>]*> 7ed7a954 	subu_s\.ob	s5,s6,s7
+	\.\.\.
--- /dev/null	2006-05-28 20:58:20.156000000 +0100
+++ gas/testsuite/gas/mips/mips64-dsp.s	2006-05-30 21:26:07.000000000 +0100
@@ -0,0 +1,174 @@
+# source file to test assembly of MIPS DSP ASE for MIPS64 instructions
+
+	.set noreorder
+	.set nomacro
+	.set noat
+
+	.text
+text_label:
+
+	absq_s.pw	$0,$1
+	absq_s.qh	$30,$31
+	addq.pw		$5,$6,$7
+	addq_s.pw	$6,$7,$8
+	addq.qh		$2,$3,$4
+	addq_s.qh	$3,$4,$5
+	addu.ob		$9,$10,$11
+	addu_s.ob	$10,$11,$12
+	bposge64	text_label
+	nop
+	cmp.eq.pw	$20,$21
+	cmp.lt.pw	$21,$22
+	cmp.le.pw	$22,$23
+	cmp.eq.qh	$17,$18
+	cmp.lt.qh	$18,$19
+	cmp.le.qh	$19,$20
+	cmpu.eq.ob	$14,$15
+	cmpu.lt.ob	$15,$16
+	cmpu.le.ob	$16,$17
+	cmpgu.eq.ob	$8,$9,$10
+	cmpgu.lt.ob	$9,$10,$11
+	cmpgu.le.ob	$10,$11,$12
+	dextpdp		$31,$ac3,0
+	dextpdp		$31,$ac3,1
+	dextpdp		$31,$ac3,31
+	dextpdpv	$0,$ac0,$1
+	dextp		$29,$ac1,0
+	dextp		$29,$ac1,1
+	dextp		$29,$ac1,31
+	dextpv		$30,$ac2,$31
+	dextr.l		$3,$ac3,0
+	dextr.l		$3,$ac3,1
+	dextr.l		$3,$ac3,31
+	dextr_r.l	$4,$ac0,0
+	dextr_r.l	$4,$ac0,1
+	dextr_r.l	$4,$ac0,31
+	dextr_rs.l	$5,$ac1,0
+	dextr_rs.l	$5,$ac1,1
+	dextr_rs.l	$5,$ac1,31
+	dextr_r.w	$1,$ac1,0
+	dextr_r.w	$1,$ac1,1
+	dextr_r.w	$1,$ac1,31
+	dextr_rs.w	$2,$ac2,0
+	dextr_rs.w	$2,$ac2,1
+	dextr_rs.w	$2,$ac2,31
+	dextr_s.h	$2,$ac2,0
+	dextr_s.h	$2,$ac2,1
+	dextr_s.h	$2,$ac2,31
+	dextr.w		$0,$ac0,0
+	dextr.w		$0,$ac0,1
+	dextr.w		$0,$ac0,31
+	dextrv.w	$11,$ac3,$12
+	dextrv_r.w	$12,$ac0,$13
+	dextrv_rs.w	$13,$ac1,$14
+	dextrv.l	$14,$ac2,$15
+	dextrv_r.l	$15,$ac3,$16
+	dextrv_rs.l	$16,$ac0,$17
+	dinsv		$26,$27
+	dmadd		$ac1,$20,$21
+	dmaddu		$ac2,$21,$22
+	dmsub		$ac3,$22,$23
+	dmsubu		$ac0,$23,$24
+	dmthlip		$4,$ac2
+	dpaq_sa.l.pw	$ac1,$0,$1
+	dpaq_s.w.qh	$ac2,$21,$22
+	dpau.h.obl	$ac0,$15,$16
+	dpau.h.obr	$ac1,$16,$17
+	dpsq_sa.l.pw	$ac0,$3,$4
+	dpsq_s.w.qh	$ac1,$24,$25
+	dpsu.h.obl	$ac2,$17,$18
+	dpsu.h.obr	$ac3,$18,$19
+	dshilo		$ac3,-64
+	dshilo		$ac3,63
+	dshilov		$ac0,$2
+	ldx		$16,$17($18)
+	maq_sa.w.qhll	$ac3,$10,$11
+	maq_sa.w.qhlr	$ac0,$11,$12
+	maq_sa.w.qhrl	$ac1,$12,$13
+	maq_sa.w.qhrr	$ac2,$13,$14
+	maq_s.l.pwl	$ac1,$16,$17
+	maq_s.l.pwr	$ac2,$17,$18
+	maq_s.w.qhll	$ac3,$10,$11
+	maq_s.w.qhlr	$ac0,$11,$12
+	maq_s.w.qhrl	$ac1,$12,$13
+	maq_s.w.qhrr	$ac2,$13,$14
+	muleq_s.pw.qhl	$11,$12,$13
+	muleq_s.pw.qhr	$12,$13,$14
+	muleu_s.qh.obl	$4,$5,$6
+	muleu_s.qh.obr	$5,$6,$7
+	mulq_rs.ph	$6,$7,$8
+	mulq_rs.qh	$8,$9,$10
+	mulsaq_s.w.qh	$ac0,$27,$28
+	mulsaq_s.l.pw	$ac2,$29,$30
+	packrl.pw	$28,$29,$30
+	pick.ob		$25,$26,$27
+	pick.qh		$26,$27,$28
+	pick.pw		$27,$28,$29
+	preceq.pw.qhl	$14,$15
+	preceq.pw.qhr	$15,$16
+	preceq.pw.qhla	$16,$17
+	preceq.pw.qhra	$17,$18
+	preceq.s.l.pwl	$18,$19
+	preceq.s.l.pwr	$19,$20
+	precequ.pw.qhl	$24,$25
+	precequ.pw.qhr	$25,$26
+	precequ.pw.qhla	$26,$27
+	precequ.pw.qhra	$27,$28
+	preceu.qh.obl	$28,$29
+	preceu.qh.obr	$29,$30
+	preceu.qh.obla	$30,$31
+	preceu.qh.obra	$31,$0
+	precrq.ob.qh	$4,$5,$6
+	precrq.pw.l	$7,$8,$9
+	precrq.qh.pw	$5,$6,$7
+	precrq_rs.qh.pw	$6,$7,$8
+	precrqu_s.ob.qh	$9,$10,$11
+	raddu.l.ob	$26,$27
+	repl.ob		$29,0
+	repl.ob		$29,255
+	replv.ob	$30,$31
+	repl.qh		$1,-512
+	repl.qh		$1,511
+	replv.qh	$2,$3
+	repl.pw		$3,-512
+	repl.pw		$3,511
+	replv.pw	$4,$5
+	shll.ob		$2,$3,0
+	shll.ob		$2,$3,7
+	shllv.ob	$3,$4,$5
+	shll.qh		$8,$9,0
+	shll.qh		$8,$9,15
+	shllv.qh	$9,$10,$11
+	shll_s.qh	$10,$11,0
+	shll_s.qh	$10,$11,15
+	shllv_s.qh	$11,$12,$13
+	shll.pw		$14,$15,0
+	shll.pw		$14,$15,31
+	shllv.pw	$15,$16,$17
+	shll_s.pw	$16,$17,0
+	shll_s.pw	$16,$17,31
+	shllv_s.pw	$17,$18,$19
+	shra.qh		$28,$29,0
+	shra.qh		$28,$29,15
+	shrav.qh	$29,$30,$31
+	shra_r.qh	$30,$31,0
+	shra_r.qh	$30,$31,15
+	shrav_r.qh	$31,$0,$1
+	shra.pw		$0,$1,0
+	shra.pw		$0,$1,31
+	shrav.pw	$1,$2,$3
+	shra_r.pw	$2,$3,0
+	shra_r.pw	$2,$3,31
+	shrav_r.pw	$3,$4,$5
+	shrl.ob		$20,$21,0
+	shrl.ob		$20,$21,7
+	shrlv.ob	$21,$22,$23
+	subq.qh		$16,$17,$18
+	subq_s.qh	$17,$18,$19
+	subq.pw		$18,$19,$20
+	subq_s.pw	$19,$20,$21
+	subu.ob		$20,$21,$22
+	subu_s.ob	$21,$22,$23
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.space	8