From: "H. J. Lu" <hjl@lucon.org>
To: Alan Modra <amodra@bigpond.net.au>
Cc: binutils@sources.redhat.com
Subject: PATCH: Remove InvMem from MMX/SSE instructions
Date: Thu, 13 Jul 2006 23:09:00 -0000 [thread overview]
Message-ID: <20060713230903.GA24686@lucon.org> (raw)
Hi Alan,
Your patches
http://sourceware.org/ml/binutils/2001-05/msg00065.html
http://sourceware.org/ml/binutils/2001-05/msg00187.html
use InvMem on source operand to indicate that it must be register.
I don't believe it is correct since RegYYY won't match memory anyway
and InvMem is used to indicate how operand should be encoded. This
patch removes it.
H.J.
----
2006-07-13 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
movdq2q and movq2dq.
--- include/opcode/i386.h.invmem 2006-06-12 12:50:18.000000000 -0700
+++ include/opcode/i386.h 2006-07-13 15:51:55.000000000 -0700
@@ -1167,20 +1167,20 @@ static const template i386_optab[] =
{"divps", 2, 0x0f5e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
{"divss", 2, 0xf30f5e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
{"ldmxcsr", 1, 0x0fae, 2, CpuSSE, NoSuf|IgnoreSize|Modrm, { WordMem, 0, 0 } },
-{"maskmovq", 2, 0x0ff7, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|InvMem, RegMMX, 0 } },
+{"maskmovq", 2, 0x0ff7, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX, RegMMX, 0 } },
{"maxps", 2, 0x0f5f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
{"maxss", 2, 0xf30f5f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
{"minps", 2, 0x0f5d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
{"minss", 2, 0xf30f5d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
{"movaps", 2, 0x0f28, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
{"movaps", 2, 0x0f29, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
-{"movhlps", 2, 0x0f12, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
+{"movhlps", 2, 0x0f12, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM, 0 } },
{"movhps", 2, 0x0f16, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
{"movhps", 2, 0x0f17, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
-{"movlhps", 2, 0x0f16, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
+{"movlhps", 2, 0x0f16, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM, 0 } },
{"movlps", 2, 0x0f12, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
{"movlps", 2, 0x0f13, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
-{"movmskps", 2, 0x0f50, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
+{"movmskps", 2, 0x0f50, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64, 0 } },
{"movntps", 2, 0x0f2b, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
{"movntq", 2, 0x0fe7, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX, LLongMem, 0 } },
{"movntdq", 2, 0x660fe7, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
@@ -1195,8 +1195,8 @@ static const template i386_optab[] =
{"pavgb", 2, 0x660fe0, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
{"pavgw", 2, 0x0fe3, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
{"pavgw", 2, 0x660fe3, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pextrw", 3, 0x0fc5, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX|InvMem, Reg32|Reg64 } },
-{"pextrw", 3, 0x660fc5, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegXMM|InvMem, Reg32|Reg64 } },
+{"pextrw", 3, 0x0fc5, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX, Reg32|Reg64 } },
+{"pextrw", 3, 0x660fc5, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegXMM, Reg32|Reg64 } },
{"pinsrw", 3, 0x0fc4, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } },
{"pinsrw", 3, 0x660fc4, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } },
{"pmaxsw", 2, 0x0fee, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
@@ -1207,8 +1207,8 @@ static const template i386_optab[] =
{"pminsw", 2, 0x660fea, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
{"pminub", 2, 0x0fda, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
{"pminub", 2, 0x660fda, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pmovmskb", 2, 0x0fd7, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { RegMMX|InvMem, Reg32|Reg64, 0 } },
-{"pmovmskb", 2, 0x660fd7, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
+{"pmovmskb", 2, 0x0fd7, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { RegMMX, Reg32|Reg64, 0 } },
+{"pmovmskb", 2, 0x660fd7, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64, 0 } },
{"pmulhuw", 2, 0x0fe4, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
{"pmulhuw", 2, 0x660fe4, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
{"prefetchnta", 1, 0x0f18, 0, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } },
@@ -1276,7 +1276,7 @@ static const template i386_optab[] =
{"movhpd", 2, 0x660f17, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
{"movlpd", 2, 0x660f12, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
{"movlpd", 2, 0x660f13, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
-{"movmskpd", 2, 0x660f50, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
+{"movmskpd", 2, 0x660f50, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64, 0 } },
{"movntpd", 2, 0x660f2b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
/* Intel mode string move. */
{"movsd", 0, 0xa5, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
@@ -1311,13 +1311,13 @@ static const template i386_optab[] =
{"cvttsd2si", 2, 0xf20f2c, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },
{"cvttpd2dq", 2, 0x660fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
{"cvttps2dq", 2, 0xf30f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"maskmovdqu",2, 0x660ff7, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
+{"maskmovdqu",2, 0x660ff7, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM, 0 } },
{"movdqa", 2, 0x660f6f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
{"movdqa", 2, 0x660f7f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
{"movdqu", 2, 0xf30f6f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
{"movdqu", 2, 0xf30f7f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
-{"movdq2q", 2, 0xf20fd6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegMMX, 0 } },
-{"movq2dq", 2, 0xf30fd6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|InvMem, RegXMM, 0 } },
+{"movdq2q", 2, 0xf20fd6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegMMX, 0 } },
+{"movq2dq", 2, 0xf30fd6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX, RegXMM, 0 } },
{"pmuludq", 2, 0x0ff4, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
{"pmuludq", 2, 0x660ff4, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
{"pshufd", 3, 0x660f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
next reply other threads:[~2006-07-13 23:09 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-07-13 23:09 H. J. Lu [this message]
2006-07-16 3:54 ` Alan Modra
2006-07-16 17:13 ` H. J. Lu
2006-07-17 8:49 ` Alan Modra
2006-07-17 20:12 ` H. J. Lu
2006-07-17 21:14 ` H. J. Lu
2006-07-18 20:01 ` RFC: Use long long in x86 assembler H. J. Lu
2006-07-18 22:48 ` Alan Modra
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