From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 27556 invoked by alias); 7 Sep 2006 20:02:10 -0000 Received: (qmail 27548 invoked by uid 22791); 7 Sep 2006 20:02:09 -0000 X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (65.74.133.4) by sourceware.org (qpsmtpd/0.31) with ESMTP; Thu, 07 Sep 2006 20:02:08 +0000 Received: (qmail 9997 invoked from network); 7 Sep 2006 20:02:06 -0000 Received: from unknown (HELO 81-178-224-253.dsl.pipex.com) (paul@127.0.0.2) by mail.codesourcery.com with ESMTPA; 7 Sep 2006 20:02:06 -0000 From: Paul Brook To: binutils@sourceware.org Subject: [patch] Accept ARM IT on all cores Date: Thu, 07 Sep 2006 20:02:00 -0000 User-Agent: KMail/1.9.4 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200609072102.05244.paul@codesourcery.com> Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org X-SW-Source: 2006-09/txt/msg00044.txt.bz2 The ARM assembler accepts the IT instruction in ARM mode to allow the same assembly to be used for both ARM and Thumb-2. As it assembles to nothing it should be accepted on all cpus, not just those that support Thumb-2. Tested with cross to arm-none-eabi. Ok? Paul 2006-09-07 Paul Brook gas/ * config/tc-arm.c (insns): Allow ARM IT pseudo-insn on all cores. gas/testsuite/ * gas/arm/arm-it.s: New test. * gas/arm/arm-it.d: New test. Index: gas/config/tc-arm.c =================================================================== RCS file: /var/cvsroot/src-cvs/src/gas/config/tc-arm.c,v retrieving revision 1.250.2.30 diff -u -p -r1.250.2.30 tc-arm.c --- gas/config/tc-arm.c 6 Sep 2006 16:35:21 -0000 1.250.2.30 +++ gas/config/tc-arm.c 7 Sep 2006 19:11:54 -0000 @@ -14815,7 +14815,9 @@ static const struct asm_opcode insns[] = UT(cbnz, b900, 2, (RR, EXP), t_czb), UT(cbz, b100, 2, (RR, EXP), t_czb), - /* ARM does not really have an IT instruction. */ + /* ARM does not really have an IT instruction, so always allow it. */ +#undef ARM_VARIANT +#define ARM_VARIANT &arm_ext_v1 TUE(it, 0, bf08, 1, (COND), it, t_it), TUE(itt, 0, bf0c, 1, (COND), it, t_it), TUE(ite, 0, bf04, 1, (COND), it, t_it), Index: gas/testsuite/gas/arm/arm-it.d =================================================================== RCS file: gas/testsuite/gas/arm/arm-it.d diff -N gas/testsuite/gas/arm/arm-it.d --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ gas/testsuite/gas/arm/arm-it.d 7 Sep 2006 19:24:26 -0000 @@ -0,0 +1,9 @@ +#name: ARM IT instruction +#objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> 03a00000 ? moveq r0, #0 ; 0x0 +0+004 <[^>]*> e1a0f00e ? mov pc, lr Index: gas/testsuite/gas/arm/arm-it.s =================================================================== RCS file: gas/testsuite/gas/arm/arm-it.s diff -N gas/testsuite/gas/arm/arm-it.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ gas/testsuite/gas/arm/arm-it.s 7 Sep 2006 19:22:35 -0000 @@ -0,0 +1,8 @@ + # Check that IT is accepted in ARM mode on older architectures + .text + .syntax unified + .arch armv4 +label1: + it eq + moveq r0, #0 + mov pc, lr