* [PATCH] Lexra binutils
@ 2008-09-17 11:55 Sergey Lapin
2008-09-17 12:40 ` Thiemo Seufer
2008-09-19 17:00 ` [PATCH] Lexra binutils Adam Nemet
0 siblings, 2 replies; 34+ messages in thread
From: Sergey Lapin @ 2008-09-17 11:55 UTC (permalink / raw)
To: binutils; +Cc: Sergey Lapin
This patch is based on Lexra patches which were submitted to binutils
mainling list, rebased for current binutils and made it co-exist with
normal MIPS targets.
The base revision of binutils for this patch is 2.17.
This patch should not break anything (I have tested that, so I hope),
so it should be possible to commit it. But beforehand I'd like to have
some advice from binutils gurus about proper usage and proper review.
Usage:
mips-linux-uclibc-as -march=lexra -mtune=lexra somefile.s
Instead of "lexra" word you could also use "lx5280" if you like.
Theoretically, these flags should be used from gcc (as soon as I
look into Eugeny's patch and change it appropriately).
Waiting for your feedback.
S.
Signed-off-by: Sergey Lapin <slapin@ossfans.org>
---
bfd/bfd-in2.h | 1 +
bfd/cpu-mips.c | 4 ++-
gas/config/tc-mips.c | 80 +++++++++++++++++++++++++++++++++++++++++++++++--
include/opcode/mips.h | 5 ++-
opcodes/mips-opc.c | 25 ++++++++-------
5 files changed, 98 insertions(+), 17 deletions(-)
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 64c022f..f8045c1 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1757,6 +1757,7 @@ enum bfd_architecture
#define bfd_mach_mips16 16
#define bfd_mach_mips5 5
#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
+#define bfd_mach_mips_lexra 0x4c58
#define bfd_mach_mipsisa32 32
#define bfd_mach_mipsisa32r2 33
#define bfd_mach_mipsisa64 64
diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index 5f4dcca..a83fbbd 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -86,6 +86,7 @@ enum
I_mipsisa64,
I_mipsisa64r2,
I_sb1,
+ I_lexra,
};
#define NN(index) (&arch_info_struct[(index) + 1])
@@ -118,7 +119,8 @@ static const bfd_arch_info_type arch_info_struct[] =
N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)),
N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
- N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, 0),
+ N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
+ N (32, 32, bfd_mach_mips_lexra, "mips:lexra", FALSE, 0),
};
/* The default architecture is mips:3000, but with a machine number of
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index c885205..e8c0de6 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -411,6 +411,7 @@ static int mips_32bitmode = 0;
|| mips_opts.arch == CPU_R12000 \
|| mips_opts.arch == CPU_RM7000 \
|| mips_opts.arch == CPU_VR5500 \
+ || mips_opts.arch == CPU_LX5280 \
)
/* Whether the processor uses hardware interlocks to protect reads
@@ -420,7 +421,8 @@ static int mips_32bitmode = 0;
level I. */
#define gpr_interlocks \
(mips_opts.isa != ISA_MIPS1 \
- || mips_opts.arch == CPU_R3900)
+ || mips_opts.arch == CPU_R3900 \
+ || mips_opts.arch == CPU_LX5280)
/* Whether the processor uses hardware interlocks to avoid delays
required by coprocessor instructions, and thus does not require
@@ -435,6 +437,7 @@ static int mips_32bitmode = 0;
&& mips_opts.isa != ISA_MIPS2 \
&& mips_opts.isa != ISA_MIPS3) \
|| mips_opts.arch == CPU_R4300 \
+ || mips_opts.arch == CPU_LX5280 \
)
/* Whether the processor uses hardware interlocks to protect reads
@@ -442,7 +445,11 @@ static int mips_32bitmode = 0;
thus does not require nops to be inserted. This applies to
instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
requires at MIPS ISA level I. */
-#define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
+#define cop_mem_interlocks \
+ ((mips_opts.isa != ISA_MIPS1) \
+ || mips_opts.arch == CPU_LX5280 \
+ )
+
/* Is this a mfhi or mflo instruction? */
#define MF_HILO_INSN(PINFO) \
@@ -5719,10 +5726,20 @@ macro (struct mips_cl_insn *ip)
coproc = 1;
goto ld;
case M_LWL_AB:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "lwl";
lr = 1;
goto ld;
case M_LWR_AB:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "lwr";
lr = 1;
goto ld;
@@ -5803,9 +5820,19 @@ macro (struct mips_cl_insn *ip)
coproc = 1;
goto st;
case M_SWL_AB:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "swl";
goto st;
case M_SWR_AB:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "swr";
goto st;
case M_SC_AB:
@@ -7375,11 +7402,21 @@ macro2 (struct mips_cl_insn *ip)
break;
case M_ULD:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "ldl";
s2 = "ldr";
off = 7;
goto ulw;
case M_ULW:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "lwl";
s2 = "lwr";
off = 3;
@@ -7411,11 +7448,21 @@ macro2 (struct mips_cl_insn *ip)
break;
case M_ULD_A:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "ldl";
s2 = "ldr";
off = 7;
goto ulwa;
case M_ULW_A:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "lwl";
s2 = "lwr";
off = 3;
@@ -7471,11 +7518,21 @@ macro2 (struct mips_cl_insn *ip)
break;
case M_USD:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "sdl";
s2 = "sdr";
off = 7;
goto usw;
case M_USW:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "swl";
s2 = "swr";
off = 3;
@@ -7493,11 +7550,21 @@ macro2 (struct mips_cl_insn *ip)
break;
case M_USD_A:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "sdl";
s2 = "sdr";
off = 7;
goto uswa;
case M_USW_A:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "swl";
s2 = "swr";
off = 3;
@@ -8003,12 +8070,15 @@ mips_ip (char *str, struct mips_cl_insn *ip)
else
ok = FALSE;
+ if (mips_opts.arch == CPU_LX5280 && (insn->membership & INSN_LXMISS) != 0)
+ ok = FALSE;
+
if (insn->pinfo != INSN_MACRO)
{
if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
ok = FALSE;
- }
+ }
if (! ok)
{
if (insn + 1 < &mips_opcodes[NUMOPCODES]
@@ -14300,6 +14370,10 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
/* Broadcom SB-1 CPU core */
{ "sb1", 0, ISA_MIPS64, CPU_SB1 },
+ /* Lexra core w/o patented instructions */
+ { "lx5280", 0, ISA_MIPS1, CPU_LX5280 },
+ { "lexra", 0, ISA_MIPS1, CPU_LX5280 },
+
/* End marker */
{ NULL, 0, 0, 0 }
};
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 4bec5ed..f0345a2 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -502,6 +502,8 @@ struct mips_opcode
#define INSN_5500 0x02000000
/* MT ASE */
#define INSN_MT 0x04000000
+/* Absent on Lexra */
+#define INSN_LXMISS 0x08000000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@@ -549,6 +551,7 @@ struct mips_opcode
#define CPU_MIPS64 64
#define CPU_MIPS64R2 65
#define CPU_SB1 12310201 /* octal 'SB', 01. */
+#define CPU_LX5280 0x4c58
/* Test for membership in an ISA including chip specific ISAs. INSN
is pointer to an element of the opcode table; ISA is the specified
@@ -570,7 +573,7 @@ struct mips_opcode
|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
|| (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
- || 0) /* Please keep this term for easier source merging. */
+ || 0) /* Please keep this term for easier source merging. */ \
/* This is a list of macro expanded instructions.
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index cd92a9f..f5747a3 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -88,6 +88,7 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
#define I64 INSN_ISA64
#define I33 INSN_ISA32R2
#define I65 INSN_ISA64R2
+#define LXMISS INSN_LXMISS /* absent on Lexra */
/* MIPS64 MIPS-3D ASE support. */
#define I16 INSN_MIPS16
@@ -725,12 +726,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 },
-{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
-{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
+{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1|LXMISS},
+{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1|LXMISS},
{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2 }, /* as lwl */
-{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
-{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
+{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1|LXMISS},
+{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1|LXMISS},
{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as lwr */
{"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 },
@@ -1169,12 +1170,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 },
{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 },
-{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
-{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
+{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1|LXMISS},
+{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1|LXMISS},
{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2 }, /* as swl */
-{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
-{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 },
+{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1|LXMISS},
+{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1|LXMISS},
{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */
{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4|I33 },
@@ -1232,14 +1233,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 },
{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 },
{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 },
-{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 },
-{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 },
+{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1|LXMISS},
+{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1|LXMISS},
{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 },
{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 },
{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 },
{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 },
-{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 },
-{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 },
+{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1|LXMISS},
+{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1|LXMISS},
{"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX|SB1 },
{"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 },
{"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX },
--
1.5.6.5
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra binutils
2008-09-17 11:55 [PATCH] Lexra binutils Sergey Lapin
@ 2008-09-17 12:40 ` Thiemo Seufer
[not found] ` <20080917131851.GA3115@build.ossfans.org>
2008-09-19 17:00 ` [PATCH] Lexra binutils Adam Nemet
1 sibling, 1 reply; 34+ messages in thread
From: Thiemo Seufer @ 2008-09-17 12:40 UTC (permalink / raw)
To: Sergey Lapin; +Cc: binutils
Sergey Lapin wrote:
> This patch is based on Lexra patches which were submitted to binutils
> mainling list, rebased for current binutils and made it co-exist with
> normal MIPS targets.
>
> The base revision of binutils for this patch is 2.17.
>
> This patch should not break anything (I have tested that, so I hope),
> so it should be possible to commit it. But beforehand I'd like to have
> some advice from binutils gurus about proper usage and proper review.
>
> Usage:
>
> mips-linux-uclibc-as -march=lexra -mtune=lexra somefile.s
>
> Instead of "lexra" word you could also use "lx5280" if you like.
> Theoretically, these flags should be used from gcc (as soon as I
> look into Eugeny's patch and change it appropriately).
>
> Waiting for your feedback.
> S.
>
> Signed-off-by: Sergey Lapin <slapin@ossfans.org>
> ---
> bfd/bfd-in2.h | 1 +
> bfd/cpu-mips.c | 4 ++-
> gas/config/tc-mips.c | 80 +++++++++++++++++++++++++++++++++++++++++++++++--
> include/opcode/mips.h | 5 ++-
> opcodes/mips-opc.c | 25 ++++++++-------
> 5 files changed, 98 insertions(+), 17 deletions(-)
>
> diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
> index 64c022f..f8045c1 100644
> --- a/bfd/bfd-in2.h
> +++ b/bfd/bfd-in2.h
> @@ -1757,6 +1757,7 @@ enum bfd_architecture
> #define bfd_mach_mips16 16
> #define bfd_mach_mips5 5
> #define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
> +#define bfd_mach_mips_lexra 0x4c58
A comment like the one for SB-1 would be nice. (Likewise for the CPU
define in mips.h.)
[snip]
> @@ -5719,10 +5726,20 @@ macro (struct mips_cl_insn *ip)
> coproc = 1;
> goto ld;
> case M_LWL_AB:
> + if (mips_opts.arch == CPU_LX5280)
> + {
> + as_bad (_("opcode not supported on this processor"));
> + break;
> + }
[snip: many more of those]
> @@ -8003,12 +8070,15 @@ mips_ip (char *str, struct mips_cl_insn *ip)
> else
> ok = FALSE;
>
> + if (mips_opts.arch == CPU_LX5280 && (insn->membership & INSN_LXMISS) != 0)
> + ok = FALSE;
> +
[snip]
> diff --git a/include/opcode/mips.h b/include/opcode/mips.h
> index 4bec5ed..f0345a2 100644
> --- a/include/opcode/mips.h
> +++ b/include/opcode/mips.h
> @@ -502,6 +502,8 @@ struct mips_opcode
> #define INSN_5500 0x02000000
> /* MT ASE */
> #define INSN_MT 0x04000000
> +/* Absent on Lexra */
> +#define INSN_LXMISS 0x08000000
I don't like the approach subtracting instructions from a base ISA,
IMO the flags should be strictly additive. This avoids scattering
the code with exceptions for a particular CPU, and helps the
disassembler to know about the allowed instructions.
I recommend to add a new pseudo-ISA INSN_ISA1-, consisting of the
common subset of Lexra and MIPS I instructions.
[snip]
> /* MIPS ISA defines, use instead of hardcoding ISA level. */
>
> @@ -549,6 +551,7 @@ struct mips_opcode
> #define CPU_MIPS64 64
> #define CPU_MIPS64R2 65
> #define CPU_SB1 12310201 /* octal 'SB', 01. */
> +#define CPU_LX5280 0x4c58
Again, a comment for this magic number, please.
> /* Test for membership in an ISA including chip specific ISAs. INSN
> is pointer to an element of the opcode table; ISA is the specified
> @@ -570,7 +573,7 @@ struct mips_opcode
> || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
> || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
> || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
> - || 0) /* Please keep this term for easier source merging. */
> + || 0) /* Please keep this term for easier source merging. */ \
Superfluous change.
Thiemo
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra binutils
[not found] ` <20080917164747.GA9502@build.ossfans.org>
@ 2008-09-17 17:26 ` Sergey Lapin
2008-09-17 17:58 ` Thiemo Seufer
0 siblings, 1 reply; 34+ messages in thread
From: Sergey Lapin @ 2008-09-17 17:26 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: binutils
On Wed, Sep 17, 2008 at 08:47:47PM +0400, Sergey Lapin wrote:
> > opcodes/mips-opc.c:
> > #define I1U INSN_ISA1_UNALIGNED
> > ...
> > -{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1}
> > -{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1}
> > +{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1U}
> > +{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1U}
> > ...
>
> I would keep the ISA1 / I1 meaning for MIPS I, as this is a well known
> standard for many people.
Sorry, I can't get, what you would suggest there?
If keeping I1, then we can't use bits additively.
Or you suggest create something like ILX and mark with it
all instructions which are supported?
>
> > And all the stuff with adding CPU in both tc-mips.c and BFD.
> > Will it be sufficient?
>
> It also needs a E_MIPS_MACH value. Do the old Lexra toolchains set
> this flag?
No, just R3000.
All the best,
S.
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra binutils
2008-09-17 17:26 ` Sergey Lapin
@ 2008-09-17 17:58 ` Thiemo Seufer
2008-09-18 10:11 ` Maciej W. Rozycki
0 siblings, 1 reply; 34+ messages in thread
From: Thiemo Seufer @ 2008-09-17 17:58 UTC (permalink / raw)
To: Sergey Lapin; +Cc: binutils
Sergey Lapin wrote:
> On Wed, Sep 17, 2008 at 08:47:47PM +0400, Sergey Lapin wrote:
> > > opcodes/mips-opc.c:
> > > #define I1U INSN_ISA1_UNALIGNED
> > > ...
> > > -{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1}
> > > -{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1}
> > > +{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1U}
> > > +{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1U}
> > > ...
> >
> > I would keep the ISA1 / I1 meaning for MIPS I, as this is a well known
> > standard for many people.
> Sorry, I can't get, what you would suggest there?
> If keeping I1, then we can't use bits additively.
> Or you suggest create something like ILX and mark with it
> all instructions which are supported?
The latter, I called I1- ("MIPS I minus") what you call ILX.
That way, the progression of ISA supersets is I1- -> I1 -> I2 ...
> > > And all the stuff with adding CPU in both tc-mips.c and BFD.
> > > Will it be sufficient?
> >
> > It also needs a E_MIPS_MACH value. Do the old Lexra toolchains set
> > this flag?
> No, just R3000.
Then we should add a new value for Lexra (so the linker can complain
if it is asked to link non-Lexra objects into a Lexra binary).
Thiemo
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra binutils
2008-09-17 17:58 ` Thiemo Seufer
@ 2008-09-18 10:11 ` Maciej W. Rozycki
2008-09-18 10:53 ` Thiemo Seufer
2008-09-19 4:08 ` Adam Nemet
0 siblings, 2 replies; 34+ messages in thread
From: Maciej W. Rozycki @ 2008-09-18 10:11 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: Sergey Lapin, binutils
On Wed, 17 Sep 2008, Thiemo Seufer wrote:
> The latter, I called I1- ("MIPS I minus") what you call ILX.
> That way, the progression of ISA supersets is I1- -> I1 -> I2 ...
How about ISA0? ;) Hopefully no one will think about subsetting it any
further -- there isn't much left to subtract from.
Maciej
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra binutils
2008-09-18 10:11 ` Maciej W. Rozycki
@ 2008-09-18 10:53 ` Thiemo Seufer
2008-09-19 4:08 ` Adam Nemet
1 sibling, 0 replies; 34+ messages in thread
From: Thiemo Seufer @ 2008-09-18 10:53 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: Sergey Lapin, binutils
Maciej W. Rozycki wrote:
> On Wed, 17 Sep 2008, Thiemo Seufer wrote:
>
> > The latter, I called I1- ("MIPS I minus") what you call ILX.
> > That way, the progression of ISA supersets is I1- -> I1 -> I2 ...
>
> How about ISA0? ;) Hopefully no one will think about subsetting it any
> further -- there isn't much left to subtract from.
Agreed. :-)
Thiemo
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra binutils
2008-09-18 10:11 ` Maciej W. Rozycki
2008-09-18 10:53 ` Thiemo Seufer
@ 2008-09-19 4:08 ` Adam Nemet
2008-09-19 10:06 ` Maciej W. Rozycki
1 sibling, 1 reply; 34+ messages in thread
From: Adam Nemet @ 2008-09-19 4:08 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: Thiemo Seufer, Sergey Lapin, binutils
"Maciej W. Rozycki" <macro@linux-mips.org> writes:
> On Wed, 17 Sep 2008, Thiemo Seufer wrote:
>
>> The latter, I called I1- ("MIPS I minus") what you call ILX.
>> That way, the progression of ISA supersets is I1- -> I1 -> I2 ...
>
> How about ISA0? ;) Hopefully no one will think about subsetting it any
> further -- there isn't much left to subtract from.
It would be nice to add something more general than this. On Octeon we also
have a mode where there are replacement instructions for l[wd]l/l[wd]r. At
some pont I will try to add support for those on mainline so I guess along the
logic in this thread I would have to define a new ISA, 64r2-.
Can't we just instead do something similar to how I generalized Octeon's
omission of certain cop instructions with NO_ISA_COP?
Adam
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra binutils
2008-09-19 4:08 ` Adam Nemet
@ 2008-09-19 10:06 ` Maciej W. Rozycki
2008-09-19 17:01 ` Adam Nemet
0 siblings, 1 reply; 34+ messages in thread
From: Maciej W. Rozycki @ 2008-09-19 10:06 UTC (permalink / raw)
To: Adam Nemet; +Cc: Thiemo Seufer, Sergey Lapin, binutils
On Thu, 18 Sep 2008, Adam Nemet wrote:
> It would be nice to add something more general than this. On Octeon we also
> have a mode where there are replacement instructions for l[wd]l/l[wd]r. At
> some pont I will try to add support for those on mainline so I guess along the
> logic in this thread I would have to define a new ISA, 64r2-.
But it has to provide these partial transfer instructions anyway if it
wants to claim MIPS ISA compliance -- the ISAs do not permit subsetting.
Then if better alternatives are available as some sort of an extension,
then it is up to GCC to emit them as appropriate and possibly GAS to use
in the expansion of the unaligned transfer macros as instructed by the
-march= flag. No need to tweak base ISA flags.
Maciej
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra binutils
2008-09-17 11:55 [PATCH] Lexra binutils Sergey Lapin
2008-09-17 12:40 ` Thiemo Seufer
@ 2008-09-19 17:00 ` Adam Nemet
1 sibling, 0 replies; 34+ messages in thread
From: Adam Nemet @ 2008-09-19 17:00 UTC (permalink / raw)
To: Sergey Lapin; +Cc: binutils
Sergey Lapin <slapin@ossfans.org> writes:
> case M_LWL_AB:
> + if (mips_opts.arch == CPU_LX5280)
> + {
> + as_bad (_("opcode not supported on this processor"));
> + break;
> + }
Can you please also add a new test (something like lexra-ill.l) checking for
this error message to the testsuite.
I will have to do something similar for Octeon and I want to make sure I don't
break Lexra.
Adam
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra binutils
2008-09-19 10:06 ` Maciej W. Rozycki
@ 2008-09-19 17:01 ` Adam Nemet
2008-09-19 17:37 ` Maciej W. Rozycki
0 siblings, 1 reply; 34+ messages in thread
From: Adam Nemet @ 2008-09-19 17:01 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: Thiemo Seufer, Sergey Lapin, binutils
Maciej W. Rozycki writes:
> Then if better alternatives are available as some sort of an extension,
> then it is up to GCC to emit them as appropriate and possibly GAS to use
> in the expansion of the unaligned transfer macros as instructed by the
> -march= flag. No need to tweak base ISA flags.
I am not 100% sure that I understand but I think what you're saying is that
you want GCC to emit let's say uld and then gas would expand to ldr/ldl or the
Octeon-specific instruction.
First, this is not good because you want GCC to schedule ldr and ldl. Second,
just like Lexar, I'd like to signal an error if someone uses ldl when
Octeon-specific unaligned instructions are on because these instructions
replace the standard MIPS unaligned instructions.
Having something like NO_ISA_COP for unaligned instructions would work for
both Lexar and Octeon regardless of ISA they are derived from.
Adam
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra binutils
2008-09-19 17:01 ` Adam Nemet
@ 2008-09-19 17:37 ` Maciej W. Rozycki
2008-09-19 18:27 ` Adam Nemet
0 siblings, 1 reply; 34+ messages in thread
From: Maciej W. Rozycki @ 2008-09-19 17:37 UTC (permalink / raw)
To: Adam Nemet; +Cc: Thiemo Seufer, Sergey Lapin, binutils
On Fri, 19 Sep 2008, Adam Nemet wrote:
> > Then if better alternatives are available as some sort of an extension,
> > then it is up to GCC to emit them as appropriate and possibly GAS to use
> > in the expansion of the unaligned transfer macros as instructed by the
> > -march= flag. No need to tweak base ISA flags.
>
> I am not 100% sure that I understand but I think what you're saying is that
> you want GCC to emit let's say uld and then gas would expand to ldr/ldl or the
> Octeon-specific instruction.
I mean GCC would emit either ldr/ldl, etc. or the CPU-specific
alternatives based on the -march= setting. Handcoded assembly would have
to be updated manually if it was to benefit.
> First, this is not good because you want GCC to schedule ldr and ldl. Second,
> just like Lexar, I'd like to signal an error if someone uses ldl when
> Octeon-specific unaligned instructions are on because these instructions
> replace the standard MIPS unaligned instructions.
So this is in fact not a compliant MIPS processor... Hmm, what can I
say? No idea off the head -- I would have to think about it. In any
case, the approach to enable either set of instructions at a time, but not
both seems a bit unfortunate.
Maciej
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra binutils
2008-09-19 17:37 ` Maciej W. Rozycki
@ 2008-09-19 18:27 ` Adam Nemet
2008-09-19 22:59 ` Maciej W. Rozycki
0 siblings, 1 reply; 34+ messages in thread
From: Adam Nemet @ 2008-09-19 18:27 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: Thiemo Seufer, Sergey Lapin, binutils
Maciej W. Rozycki writes:
> So this is in fact not a compliant MIPS processor... Hmm, what can I
> say? No idea off the head -- I would have to think about it. In any
> case, the approach to enable either set of instructions at a time, but not
> both seems a bit unfortunate.
Well, this is not for us to decide. The question for us is how to best
support this in binutils.
I just wanted to give you guys a heads-up that besides Lexra other processors
might have similar requirements so generalizing the solution is likely to be
beneficial in the long run. Beyond this, this is up to the maintainers...
Adam
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra binutils
2008-09-19 18:27 ` Adam Nemet
@ 2008-09-19 22:59 ` Maciej W. Rozycki
2008-09-19 23:11 ` Adam Nemet
0 siblings, 1 reply; 34+ messages in thread
From: Maciej W. Rozycki @ 2008-09-19 22:59 UTC (permalink / raw)
To: Adam Nemet; +Cc: Thiemo Seufer, Sergey Lapin, binutils
On Fri, 19 Sep 2008, Adam Nemet wrote:
> > So this is in fact not a compliant MIPS processor... Hmm, what can I
> > say? No idea off the head -- I would have to think about it. In any
> > case, the approach to enable either set of instructions at a time, but not
> > both seems a bit unfortunate.
>
> Well, this is not for us to decide. The question for us is how to best
> support this in binutils.
Well, this is what I would have to think about to have an idea...
Maciej
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra binutils
2008-09-19 22:59 ` Maciej W. Rozycki
@ 2008-09-19 23:11 ` Adam Nemet
2008-09-21 4:25 ` [PATCH] Lexra support in binutils Sergey Lapin
0 siblings, 1 reply; 34+ messages in thread
From: Adam Nemet @ 2008-09-19 23:11 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: Thiemo Seufer, Sergey Lapin, binutils
Maciej W. Rozycki writes:
> Well, this is what I would have to think about to have an idea...
Sure and thanks for thinking about it. As I said earlier the NO_ISA_COP
approach is something I think we should consider.
Adam
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH] Lexra support in binutils
2008-09-19 23:11 ` Adam Nemet
@ 2008-09-21 4:25 ` Sergey Lapin
2008-09-24 23:49 ` Sergey Lapin
0 siblings, 1 reply; 34+ messages in thread
From: Sergey Lapin @ 2008-09-21 4:25 UTC (permalink / raw)
To: binutils; +Cc: Maciej W. Rozycki, Thiemo Seufer, Adam Nemet, Sergey Lapin
Hi, all!
I have managed to figure-out change to binutils, which stops gas from
understanding instructions for unaligned access, which is mandatory
on Lexra-core based CPUs (like RTL865xB, RTL865x, RTL8186, etc.).
This patch is based on Lexra patches which were submitted to binutils
mainling list, rebased for current binutils and made it co-exist with
normal MIPS targets.
This patch should not break anything (I have tested that, so I hope),
so it should be possible to commit it. But beforehand I'd like to have
some advice from binutils gurus about proper usage and proper review.
Usage:
mips-linux-uclibc-as -march=lexra -mtune=lexra somefile.s
Instead of "lexra" word you could also use "lx5280" if you like.
Theoretically, these flags should be used from gcc (as soon as I
look into Eugeny's patch and change it appropriately).
This is updated version of patch - ISAs are additive,
I have introduced ISA0 for Lexra-like CPUs.
E_MIPS_MACH field is also specified.
A simple test is added to test suite.
This patch is against binutils-2.17
Waiting for your feedback.
S.
Signed-off-by: Sergey Lapin <slapin@ossfans.org>
---
bfd/archures.c | 1 +
bfd/bfd-in2.h | 1 +
bfd/cpu-mips.c | 4 +-
bfd/elfxx-mips.c | 7 +
binutils/readelf.c | 1 +
gas/config/tc-mips.c | 76 +++++-
gas/testsuite/gas/mips/lexra-ill.l | 6 +
gas/testsuite/gas/mips/lexra-ill.s | 7 +
gas/testsuite/gas/mips/mips.exp | 9 +-
include/elf/mips.h | 1 +
include/opcode/mips.h | 3 +
opcodes/mips-opc.c | 595 ++++++++++++++++++------------------
12 files changed, 409 insertions(+), 302 deletions(-)
create mode 100644 gas/testsuite/gas/mips/lexra-ill.l
create mode 100644 gas/testsuite/gas/mips/lexra-ill.s
diff --git a/bfd/archures.c b/bfd/archures.c
index c1878f5..80f7817 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -160,6 +160,7 @@ DESCRIPTION
.#define bfd_mach_mips16 16
.#define bfd_mach_mips5 5
.#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *}
+.#define bfd_mach_mips_lexra 0x4c58 {* hexadecimal 'LX' *}
.#define bfd_mach_mipsisa32 32
.#define bfd_mach_mipsisa32r2 33
.#define bfd_mach_mipsisa64 64
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 64c022f..6b9f6a4 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1757,6 +1757,7 @@ enum bfd_architecture
#define bfd_mach_mips16 16
#define bfd_mach_mips5 5
#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
+#define bfd_mach_mips_lexra 0x4c58 /* hexadecimal 'LX' */
#define bfd_mach_mipsisa32 32
#define bfd_mach_mipsisa32r2 33
#define bfd_mach_mipsisa64 64
diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index 5f4dcca..a83fbbd 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -86,6 +86,7 @@ enum
I_mipsisa64,
I_mipsisa64r2,
I_sb1,
+ I_lexra,
};
#define NN(index) (&arch_info_struct[(index) + 1])
@@ -118,7 +119,8 @@ static const bfd_arch_info_type arch_info_struct[] =
N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)),
N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
- N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, 0),
+ N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
+ N (32, 32, bfd_mach_mips_lexra, "mips:lexra", FALSE, 0),
};
/* The default architecture is mips:3000, but with a machine number of
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 39420a6..1b7caba 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -4967,6 +4967,9 @@ _bfd_elf_mips_mach (flagword flags)
case E_MIPS_MACH_SB1:
return bfd_mach_mips_sb1;
+ case E_MIPS_MACH_LEXRA:
+ return bfd_mach_mips_lexra;
+
default:
switch (flags & EF_MIPS_ARCH)
{
@@ -9028,6 +9031,10 @@ mips_set_isa_flags (bfd *abfd)
val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
break;
+ case bfd_mach_mips_lexra:
+ val = E_MIPS_ARCH_1 | E_MIPS_MACH_LEXRA;
+ break;
+
case bfd_mach_mipsisa32:
val = E_MIPS_ARCH_32;
break;
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 9428a99..3d2d3df 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -2081,6 +2081,7 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
case E_MIPS_MACH_5500: strcat (buf, ", 5500"); break;
case E_MIPS_MACH_SB1: strcat (buf, ", sb1"); break;
case E_MIPS_MACH_9000: strcat (buf, ", 9000"); break;
+ case E_MIPS_MACH_LEXRA: strcat (buf, ", lexra"); break;
case 0:
/* We simply ignore the field in this case to avoid confusion:
MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index c885205..fe03e44 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -411,6 +411,7 @@ static int mips_32bitmode = 0;
|| mips_opts.arch == CPU_R12000 \
|| mips_opts.arch == CPU_RM7000 \
|| mips_opts.arch == CPU_VR5500 \
+ || mips_opts.arch == CPU_LX5280 \
)
/* Whether the processor uses hardware interlocks to protect reads
@@ -420,7 +421,8 @@ static int mips_32bitmode = 0;
level I. */
#define gpr_interlocks \
(mips_opts.isa != ISA_MIPS1 \
- || mips_opts.arch == CPU_R3900)
+ || mips_opts.arch == CPU_R3900 \
+ || mips_opts.arch == CPU_LX5280)
/* Whether the processor uses hardware interlocks to avoid delays
required by coprocessor instructions, and thus does not require
@@ -435,6 +437,7 @@ static int mips_32bitmode = 0;
&& mips_opts.isa != ISA_MIPS2 \
&& mips_opts.isa != ISA_MIPS3) \
|| mips_opts.arch == CPU_R4300 \
+ || mips_opts.arch == CPU_LX5280 \
)
/* Whether the processor uses hardware interlocks to protect reads
@@ -442,7 +445,11 @@ static int mips_32bitmode = 0;
thus does not require nops to be inserted. This applies to
instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
requires at MIPS ISA level I. */
-#define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
+#define cop_mem_interlocks \
+ ((mips_opts.isa != ISA_MIPS1) \
+ || mips_opts.arch == CPU_LX5280 \
+ )
+
/* Is this a mfhi or mflo instruction? */
#define MF_HILO_INSN(PINFO) \
@@ -5719,10 +5726,20 @@ macro (struct mips_cl_insn *ip)
coproc = 1;
goto ld;
case M_LWL_AB:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "lwl";
lr = 1;
goto ld;
case M_LWR_AB:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "lwr";
lr = 1;
goto ld;
@@ -5803,9 +5820,19 @@ macro (struct mips_cl_insn *ip)
coproc = 1;
goto st;
case M_SWL_AB:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "swl";
goto st;
case M_SWR_AB:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "swr";
goto st;
case M_SC_AB:
@@ -7375,11 +7402,21 @@ macro2 (struct mips_cl_insn *ip)
break;
case M_ULD:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "ldl";
s2 = "ldr";
off = 7;
goto ulw;
case M_ULW:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "lwl";
s2 = "lwr";
off = 3;
@@ -7411,11 +7448,21 @@ macro2 (struct mips_cl_insn *ip)
break;
case M_ULD_A:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "ldl";
s2 = "ldr";
off = 7;
goto ulwa;
case M_ULW_A:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "lwl";
s2 = "lwr";
off = 3;
@@ -7471,11 +7518,21 @@ macro2 (struct mips_cl_insn *ip)
break;
case M_USD:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "sdl";
s2 = "sdr";
off = 7;
goto usw;
case M_USW:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "swl";
s2 = "swr";
off = 3;
@@ -7493,11 +7550,21 @@ macro2 (struct mips_cl_insn *ip)
break;
case M_USD_A:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "sdl";
s2 = "sdr";
off = 7;
goto uswa;
case M_USW_A:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "swl";
s2 = "swr";
off = 3;
@@ -14242,6 +14309,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
{ "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
{ "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
{ "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 },
+ { "mips0", 1, ISA_MIPS0, CPU_LX5280 },
/* MIPS I */
{ "r3000", 0, ISA_MIPS1, CPU_R3000 },
@@ -14300,6 +14368,10 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
/* Broadcom SB-1 CPU core */
{ "sb1", 0, ISA_MIPS64, CPU_SB1 },
+ /* Lexra core w/o patented instructions */
+ { "lx5280", 0, ISA_MIPS0, CPU_LX5280 },
+ { "lexra", 0, ISA_MIPS0, CPU_LX5280 },
+
/* End marker */
{ NULL, 0, 0, 0 }
};
diff --git a/gas/testsuite/gas/mips/lexra-ill.l b/gas/testsuite/gas/mips/lexra-ill.l
new file mode 100644
index 0000000..0b86ac6
--- /dev/null
+++ b/gas/testsuite/gas/mips/lexra-ill.l
@@ -0,0 +1,6 @@
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: .* `lwl .*
+.*:5: Error: opcode not supported on this processor: .* `lwr .*
+.*:6: Error: opcode not supported on this processor: .* `swl .*
+.*:7: Error: opcode not supported on this processor: .* `swr .*
+
diff --git a/gas/testsuite/gas/mips/lexra-ill.s b/gas/testsuite/gas/mips/lexra-ill.s
new file mode 100644
index 0000000..71b428b
--- /dev/null
+++ b/gas/testsuite/gas/mips/lexra-ill.s
@@ -0,0 +1,7 @@
+# Source file used to test unsupported unaligned access instructions.
+
+foo:
+ lwl $5, 0($3)
+ lwr $5, 0($3)
+ swl $5, 0($3)
+ swr $5, 0($3)
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 7843f2a..cda1348 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -382,6 +382,8 @@ mips_arch_create vr5400 64 mips4 { ror } \
mips_arch_create sb1 64 mips64 { mips3d } \
{ -march=sb1 -mtune=sb1 } { -mmips:sb1 } \
{ mipsisa64sb1-*-* mipsisa64sb1el-*-* }
+mips_arch_create lexra 32 {} {gpr_ilocks} \
+ { -march=lexra -mtune=lexra } { -mmips:lexra }
#
# And now begin the actual tests! VxWorks uses RELA rather than REL
@@ -461,7 +463,7 @@ if { [istarget mips*-*-vxworks*] } {
if !$aout {
# XXX FIXME: Has mips2 and later insns with mips1 disassemblies.
# (Should split and then use appropriate arch lists.)
- run_dump_test_arches "lb" [mips_arch_list_matching !mips2]
+ run_dump_test_arches "lb" [mips_arch_list_matching !mips2 !lexra]
}
if $elf {
run_dump_test_arches "lb-svr4pic" [mips_arch_list_matching !gpr_ilocks]
@@ -519,9 +521,9 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "usd"
}
run_dump_test_arches "ulw2-eb" [mips_arch_list_matching !gpr_ilocks]
- run_dump_test_arches "ulw2-eb-ilocks" [mips_arch_list_matching gpr_ilocks]
+ run_dump_test_arches "ulw2-eb-ilocks" [mips_arch_list_matching gpr_ilocks !lexra]
run_dump_test_arches "ulw2-el" [mips_arch_list_matching !gpr_ilocks]
- run_dump_test_arches "ulw2-el-ilocks" [mips_arch_list_matching gpr_ilocks]
+ run_dump_test_arches "ulw2-el-ilocks" [mips_arch_list_matching gpr_ilocks !lexra]
run_dump_test_arches "uld2-eb" [mips_arch_list_matching mips3]
run_dump_test_arches "uld2-el" [mips_arch_list_matching mips3]
@@ -588,6 +590,7 @@ if { [istarget mips*-*-vxworks*] } {
run_list_test "illegal" "-32"
run_list_test "baddata1" "-32"
+ run_list_test_arches "lexra-ill" "" [mips_arch_list_matching lexra]
# LOSE: As of 2002-02-08, the next 4 tests fail for target mips-ecoff.
# It's unknown whether they _should_ pass as-is, or whether different
diff --git a/include/elf/mips.h b/include/elf/mips.h
index f22bd4d..dd84c5d 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -215,6 +215,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
#define E_MIPS_MACH_5400 0x00910000
#define E_MIPS_MACH_5500 0x00980000
#define E_MIPS_MACH_9000 0x00990000
+#define E_MIPS_MACH_LEXRA 0x009a0000
\f
/* Processor specific section indices. These sections do not actually
exist. Symbols with a st_shndx field corresponding to one of these
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 4bec5ed..91fb49a 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -456,6 +456,7 @@ struct mips_opcode
defined at the given level. */
#define INSN_ISA_MASK 0x00000fff
+#define INSN_ISA0 0x00000200
#define INSN_ISA1 0x00000001
#define INSN_ISA2 0x00000002
#define INSN_ISA3 0x00000004
@@ -506,6 +507,7 @@ struct mips_opcode
/* MIPS ISA defines, use instead of hardcoding ISA level. */
#define ISA_UNKNOWN 0 /* Gas internal use. */
+#define ISA_MIPS0 (INSN_ISA0)
#define ISA_MIPS1 (INSN_ISA1)
#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
@@ -549,6 +551,7 @@ struct mips_opcode
#define CPU_MIPS64 64
#define CPU_MIPS64R2 65
#define CPU_SB1 12310201 /* octal 'SB', 01. */
+#define CPU_LX5280 0x4c58 /* hexadecimal 'LX' */
/* Test for membership in an ISA including chip specific ISAs. INSN
is pointer to an element of the opcode table; ISA is the specified
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index cd92a9f..66b134c 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -79,6 +79,9 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
#define WR_MACC INSN2_WRITE_MDMX_ACC
#define RD_MACC INSN2_READ_MDMX_ACC
+/* All instructions except unaligned access instructions
+ * which are not supported on some CPUs like Lexra */
+#define I0 INSN_ISA0
#define I1 INSN_ISA1
#define I2 INSN_ISA2
#define I3 INSN_ISA3
@@ -170,28 +173,28 @@ const struct mips_opcode mips_builtin_opcodes[] =
/* name, args, match, mask, pinfo, pinfo2, membership */
{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 },
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4|I33 },
-{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
+{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1|I0 }, /* sll */
{"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I32|N55 }, /* sll */
{"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I33 }, /* sll */
-{"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* addiu */
-{"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* ori */
-{"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 },
-{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 },
+{"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN2_ALIAS, I1|I0 }, /* addiu */
+{"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN2_ALIAS, I1|I0 }, /* ori */
+{"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1|I0 },
+{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1|I0 },
{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */
-{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */
-{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */
-{"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* beq 0,0 */
-{"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */
-{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/
+{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1|I0 },/* addu */
+{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1|I0 },/* or */
+{"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1|I0 },/* beq 0,0 */
+{"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1|I0 },/* bgez 0 */
+{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1|I0 },/* bgezal 0*/
-{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 },
-{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
-{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
+{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1|I0 },
+{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1|I0 },
+{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1|I0 },
{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5 },
-{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
-{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
-{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
-{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1|I0 },
+{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1|I0 },
+{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1|I0 },
+{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1|I0 },
{"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
@@ -200,27 +203,27 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
{"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
{"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
-{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 },
-{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1|I0 },
+{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1|I0 },
{"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
{"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
{"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
-{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
-{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 },
+{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1|I0 },
+{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1|I0 },
{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, 0, N54 },
{"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, 0, I5 },
{"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX|SB1 },
{"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX },
-{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
-{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 },
+{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1|I0 },
+{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1|I0 },
{"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
{"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
-{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1|I0 },
/* b is at the top of the table. */
/* bal is at the top of the table. */
/* bc0[tf]l? are at the bottom of the table. */
@@ -228,93 +231,93 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
{"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
{"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
-{"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
+{"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1|I0 },
{"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 },
{"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 },
{"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 },
-{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
+{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1|I0 },
{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 },
{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 },
{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 },
/* bc2* are at the bottom of the table. */
-{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 },
+{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1|I0 },
{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
-{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 },
+{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1|I0 },
{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
-{"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
+{"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, 0, I1|I0 },
{"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
-{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 },
-{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 },
+{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1|I0 },
+{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1|I0 },
{"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 },
{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3 },
-{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 },
-{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 },
+{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1|I0 },
+{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1|I0 },
{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3 },
{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3 },
-{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 },
-{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 },
+{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1|I0 },
+{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1|I0 },
{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3 },
{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3 },
-{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, 0, I1 },
+{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, 0, I1|I0 },
{"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
-{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 },
+{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1|I0 },
{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 },
-{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 },
-{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 },
+{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1|I0 },
+{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1|I0 },
{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3 },
{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3 },
-{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 },
-{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 },
+{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1|I0 },
+{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1|I0 },
{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3 },
{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3 },
-{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
+{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, 0, I1|I0 },
{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
-{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 },
-{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 },
+{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1|I0 },
+{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1|I0 },
{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3 },
{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3 },
-{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 },
-{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 },
+{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1|I0 },
+{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1|I0 },
{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3 },
{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3 },
-{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
+{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, 0, I1|I0 },
{"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
-{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 },
-{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 },
+{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1|I0 },
+{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1|I0 },
{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3 },
{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3 },
-{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 },
-{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 },
+{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1|I0 },
+{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1|I0 },
{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3 },
{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3 },
-{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
+{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, 0, I1|I0 },
{"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
-{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 },
+{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1|I0 },
{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 },
-{"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
+{"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, 0, I1|I0 },
{"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
-{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 },
-{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 },
+{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1|I0 },
+{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1|I0 },
{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 },
{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 },
-{"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 },
-{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 },
-{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 },
-{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1|I0 },
+{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1|I0 },
+{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1|I0 },
+{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1|I0 },
{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
-{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1|I0 },
{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
-{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1|I0 },
{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
-{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1|I0 },
{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
-{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1|I0 },
{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
-{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1|I0 },
{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
{"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
@@ -323,63 +326,63 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
{"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX },
-{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1|I0 },
{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
-{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1|I0 },
{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
{"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
{"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
-{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1|I0 },
{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
-{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1|I0 },
{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
{"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
{"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
-{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1|I0 },
{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
-{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1|I0 },
{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
{"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
{"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
-{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1|I0 },
{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
-{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1|I0 },
{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
{"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
{"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
-{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1|I0 },
{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
-{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1|I0 },
{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
{"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
{"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
-{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1|I0 },
{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
-{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1|I0 },
{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
-{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1|I0 },
{"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
-{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1|I0 },
{"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
{"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
{"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
-{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1|I0 },
{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
-{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1|I0 },
{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
{"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
{"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
-{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1|I0 },
{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
-{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1|I0 },
{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
{"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
{"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
-{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1|I0 },
{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
-{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1|I0 },
{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
{"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
@@ -388,15 +391,15 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
{"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX },
-{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1|I0 },
{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
-{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1|I0 },
{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
{"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
{"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
-{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1|I0 },
{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
-{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1|I0 },
{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
{"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
@@ -405,9 +408,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
{"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX },
-{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1|I0 },
{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
-{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1|I0 },
{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 },
@@ -464,36 +467,36 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
-{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
-{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
-{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
+{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1|I0 },
+{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1|I0 },
+{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1|I0 },
/* cfc2 is at the bottom of the table. */
-{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
+{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1|I0 },
{"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
{"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
{"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
-{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
-{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
-{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
+{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1|I0 },
+{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1|I0 },
+{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1|I0 },
/* ctc2 is at the bottom of the table. */
-{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
+{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1|I0 },
{"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
{"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
{"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 },
{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
-{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
-{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
+{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1|I0 },
+{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1|I0 },
{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_S, 0, I3|I33 },
{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_S, 0, I3|I33 },
-{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
-{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
+{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1|I0 },
+{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1|I0 },
{"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5 },
{"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5 },
-{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
-{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
+{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1|I0 },
+{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, I1|I0 },
{"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D },
{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5 },
{"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D },
@@ -533,18 +536,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
though the first operand appeared twice (the first operand is both
a source and a destination). To get the div machine instruction,
you must use an explicit destination of $0. */
-{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
-{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 },
-{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 },
-{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 },
-{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
-{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
+{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1|I0 },
+{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1|I0 },
+{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1|I0 },
+{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1|I0 },
+{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1|I0 },
+{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1|I0 },
{"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
/* For divu, see the comments about div. */
-{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
-{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 },
-{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 },
-{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 },
+{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1|I0 },
+{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1|I0 },
+{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1|I0 },
+{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1|I0 },
{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 },
{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 },
{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3 }, /* addiu */
@@ -647,46 +650,46 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 },
{"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 },
{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 },
-{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 },
+{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1|I0 },
{"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I33 },
-{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */
+{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1|I0 }, /* jr */
/* SVR4 PIC code requires special handling for j, so it must be a
macro. */
-{"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1 },
+{"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1|I0 },
/* This form of j is used by the disassembler and internally by the
assembler, but will never match user input (because the line above
will match first). */
-{"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1 },
-{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1 },
-{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1 },
+{"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1|I0 },
+{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1|I0 },
+{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1|I0 },
{"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I33 },
{"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I33 },
/* SVR4 PIC code requires special handling for jal, so it must be a
macro. */
-{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 },
-{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1 },
-{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1 },
+{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1|I0 },
+{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1|I0 },
+{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1|I0 },
/* This form of jal is used by the disassembler and internally by the
assembler, but will never match user input (because the line above
will match first). */
-{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 },
-{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I16 },
-{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 },
-{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
-{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 },
-{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
-{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 },
-{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 },
+{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1|I0 },
+{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I1|I16 },
+{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1|I0 },
+{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1|I0 },
+{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1|I0 },
+{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1|I0 },
+{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1|I0 },
+{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1|I0 },
{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 },
-{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
-{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
+{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1|I0 },
+{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1|I0 },
{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */
-{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 },
-{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 },
+{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1|I0 },
+{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1|I0 },
{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 },
{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
@@ -696,35 +699,35 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 },
{"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 },
-{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
-{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1 },
-{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
-{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 },
+{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1|I0 },
+{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1|I0 },
+{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1|I0 },
+{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1|I0 },
/* li is at the start of the table. */
-{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, 0, I1 },
-{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, 0, I1 },
-{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, 0, I1 },
-{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, 0, I1 },
+{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, 0, I1|I0 },
+{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, 0, I1|I0 },
+{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, 0, I1|I0 },
+{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, 0, I1|I0 },
{"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 },
{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2 },
{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 },
{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 },
-{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 },
+{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1|I0 },
{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, 0, I5|N55 },
-{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
-{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 },
-{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
-{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 },
-{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
-{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
-{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
-{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
-{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
-{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
-{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
-{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
-{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
-{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 },
+{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1|I0 },
+{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1|I0 },
+{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1|I0 },
+{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1|I0 },
+{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1|I0 },
+{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1|I0 },
+{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1|I0 },
+{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1|I0 },
+{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1|I0 }, /* lwc1 */
+{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1|I0 },
+{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1|I0 },
+{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1|I0 },
+{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1|I0 },
+{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1|I0 },
{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
@@ -788,29 +791,29 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
{"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
{"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 },
-{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
+{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1|I0 },
{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
-{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
-{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
+{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1|I0 },
+{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1|I0 },
{"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 },
{"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 },
/* mfc2 is at the bottom of the table. */
/* mfhc2 is at the bottom of the table. */
-{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
+{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1|I0 },
{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 },
{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 },
-{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 },
+{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1|I0 },
{"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 },
-{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 },
+{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1|I0 },
{"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 },
{"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
{"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
-{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
-{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
+{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1|I0 },
+{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, 0, I1|I0 },
{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, 0, I5 },
{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 },
{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 },
@@ -853,21 +856,21 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
-{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 },
+{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1|I0 },
{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
-{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
-{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
+{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1|I0 },
+{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1|I0 },
{"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 },
{"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 },
/* mtc2 is at the bottom of the table. */
/* mthc2 is at the bottom of the table. */
-{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 },
+{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1|I0 },
{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 },
{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 },
-{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 },
+{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1|I0 },
{"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 },
-{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 },
+{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1|I0 },
{"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 },
{"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
{"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
@@ -887,8 +890,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
{"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
{"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, MT32 },
-{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
-{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
+{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1|I0 },
+{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1|I0 },
{"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
@@ -897,8 +900,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I32|P3|N55},
{"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N54 },
-{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1 },
-{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 },
+{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1|I0 },
+{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1|I0 },
{"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
{"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
{"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
@@ -911,10 +914,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
{"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
{"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
-{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 },
-{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 },
-{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 },
-{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 },
+{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1|I0 },
+{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1|I0 },
+{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1|I0 },
+{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1|I0 },
{"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
{"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
{"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
@@ -930,15 +933,15 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
{"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
{"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
-{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 },
+{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1|I0 },
{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
-{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 },
+{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1|I0 },
{"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
{"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
-{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */
-{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* subu 0 */
-{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
-{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
+{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1|I0 }, /* sub 0 */
+{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1|I0 }, /* subu 0 */
+{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1|I0 },
+{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1|I0 },
{"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5 },
{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
@@ -947,22 +950,22 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
{"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5 },
/* nop is at the start of the table. */
-{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
-{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 },
+{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1|I0 },
+{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1|I0 },
{"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
{"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
-{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, 0, I1 },/*nor d,s,0*/
-{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
-{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 },
+{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, 0, I1|I0 },/*nor d,s,0*/
+{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1|I0 },
+{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1|I0 },
{"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
{"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
-{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, 0, I1|I0 },
{"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
{"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1 },
{"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
@@ -999,25 +1002,25 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
{"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
{"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
-{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
-{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1 },
-{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1 },
-{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
-{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 },
-{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1 },
+{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1|I0 },
+{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1|I0 },
+{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1|I0 },
+{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1|I0 },
+{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1|I0 },
+{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1|I0 },
{"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, 0, I33 },
{"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, 0, I33 },
-{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3 },
+{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|I0|T3},
{"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
{"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
{"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
{"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
{"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
{"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
-{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 },
-{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 },
-{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 },
-{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 },
+{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1|I0 },
+{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1|I0 },
+{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1|I0 },
+{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1|I0 },
{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33 },
{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33 },
{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33 },
@@ -1042,15 +1045,15 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
{"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, 0, N54 },
{"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
-{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
-{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 },
+{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1|I0 },
+{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1|I0 },
{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2 },
{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2 },
{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3 },
{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 },
{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
-{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 },
-{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 },
+{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1|I0 },
+{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1|I0 },
{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 },
{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 },
{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 },
@@ -1065,8 +1068,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 },
{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 },
{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
-{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 },
-{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 },
+{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1|I0 },
+{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1|I0 },
{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 },
{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
@@ -1076,18 +1079,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 },
{"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
{"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
-{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 },
-{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 },
-{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 },
-{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 },
-{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1 },
-{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1 },
-{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1 },
-{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1 },
-{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1 },
-{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1 },
-{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
-{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1 },
+{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1|I0 },
+{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1|I0 },
+{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1|I0 },
+{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1|I0 },
+{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1|I0 },
+{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1|I0 },
+{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1|I0 },
+{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1|I0 },
+{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1|I0 },
+{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1|I0 },
+{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, 0, I1|I0 },
+{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1|I0 },
{"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
{"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
@@ -1102,45 +1105,45 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
{"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
-{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 },
-{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 },
-{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 },
-{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 },
-{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
-{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* sllv */
-{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1 },
+{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1|I0 },
+{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1|I0 },
+{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1|I0 },
+{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1|I0 },
+{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1|I0 },
+{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1|I0 }, /* sllv */
+{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1|I0 },
{"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
{"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
-{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
-{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 },
-{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1 },
-{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1 },
-{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
-{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 },
-{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 },
-{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 },
+{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1|I0 },
+{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1|I0 },
+{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1|I0 },
+{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1|I0 },
+{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1|I0 },
+{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1|I0 },
+{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1|I0 },
+{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1|I0 },
{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 },
{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
{"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 },
-{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
-{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */
-{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1 },
+{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1|I0 },
+{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1|I0 }, /* srav */
+{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1|I0 },
{"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
-{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
-{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */
-{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1 },
+{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1|I0 },
+{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1|I0 }, /* srlv */
+{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1|I0 },
{"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
{"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
/* ssnop is at the start of the table. */
{"standby", "", 0x42000021, 0xffffffff, 0, 0, V1 },
-{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
-{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 },
-{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
-{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
+{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1|I0 },
+{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1|I0 },
+{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1|I0 },
+{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1|I0 },
{"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
@@ -1151,24 +1154,24 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
{"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
{"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
-{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
-{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 },
+{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1|I0 },
+{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1|I0 },
{"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1 },
{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I5|N55 },
-{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
-{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 },
-{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 },
-{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 },
-{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
-{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
-{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
-{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
-{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
-{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
-{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 },
-{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
-{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 },
-{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 },
+{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1|I0 },
+{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1|I0 },
+{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1|I0 },
+{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1|I0 },
+{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1|I0 },
+{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1|I0 },
+{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1|I0 },
+{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1|I0 },
+{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1|I0 }, /* swc1 */
+{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1|I0 },
+{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1|I0 },
+{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1|I0 },
+{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1|I0 },
+{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1|I0 },
{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
@@ -1182,8 +1185,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I2 },
{"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2 },
{"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 },
-{"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 },
-{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 },
+{"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1|I0 },
+{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1|I0 },
{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
@@ -1199,10 +1202,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgeiu */
{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2 },
-{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 },
-{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 },
-{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 },
-{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1 },
+{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1|I0 },
+{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1|I0 },
+{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1|I0 },
+{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1|I0 },
{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
@@ -1222,22 +1225,22 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
{"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
-{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, 0, I1 },
+{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, 0, I1|I0 },
{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
-{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, 0, I1 },
+{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, 0, I1|I0 },
{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 },
{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 },
-{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 },
-{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 },
-{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 },
-{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 },
+{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1|I0 },
+{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1|I0 },
+{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1|I0 },
+{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1|I0 },
{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 },
{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 },
{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 },
{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 },
-{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 },
-{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 },
+{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1|I0 },
+{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1|I0 },
{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 },
{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 },
{"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX|SB1 },
@@ -1252,33 +1255,33 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 },
{"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 },
{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 },
-{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
-{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 },
+{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1|I0 },
+{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1|I0 },
{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
{"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
-{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1|I0 },
{"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 },
{"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 },
/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
instructions so they are here for the latters to take precedence. */
-{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 },
+{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1|I0 },
{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
-{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 },
+{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1|I0 },
{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
-{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
-{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
+{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1|I0 },
+{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1|I0 },
{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 },
{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 },
{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 },
{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 },
-{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
+{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1|I0 },
{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 },
{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 },
-{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 },
+{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1|I0 },
{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 },
{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 },
@@ -1286,14 +1289,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the
disassembler recognizes more specific versions first. */
-{"c0", "C", 0x42000000, 0xfe000000, 0, 0, I1 },
-{"c1", "C", 0x46000000, 0xfe000000, 0, 0, I1 },
-{"c2", "C", 0x4a000000, 0xfe000000, 0, 0, I1 },
-{"c3", "C", 0x4e000000, 0xfe000000, 0, 0, I1 },
-{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 },
-{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, 0, I1 },
-{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 },
-{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 },
+{"c0", "C", 0x42000000, 0xfe000000, 0, 0, I1|I0 },
+{"c1", "C", 0x46000000, 0xfe000000, 0, 0, I1|I0 },
+{"c2", "C", 0x4a000000, 0xfe000000, 0, 0, I1|I0 },
+{"c3", "C", 0x4e000000, 0xfe000000, 0, 0, I1|I0 },
+{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1|I0 },
+{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, 0, I1|I0 },
+{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1|I0 },
+{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1|I0 },
/* Conflicts with the 4650's "mul" instruction. Nobody's using the
4010 any more, so move this insn out of the way. If the object
@@ -1406,9 +1409,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 },
{"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 },
/* Move bc0* after mftr and mttr to avoid opcode collision. */
-{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 },
+{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1|I0 },
{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
-{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 },
+{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1|I0 },
{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
};
--
1.5.6.5
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra support in binutils
2008-09-21 4:25 ` [PATCH] Lexra support in binutils Sergey Lapin
@ 2008-09-24 23:49 ` Sergey Lapin
2008-09-29 15:45 ` Sergey Lapin
0 siblings, 1 reply; 34+ messages in thread
From: Sergey Lapin @ 2008-09-24 23:49 UTC (permalink / raw)
To: binutils; +Cc: Maciej W. Rozycki, Thiemo Seufer, Adam Nemet
On Sun, Sep 21, 2008 at 08:24:09AM +0400, Sergey Lapin wrote:
Hi, all!
>
> This is updated version of patch - ISAs are additive,
> I have introduced ISA0 for Lexra-like CPUs.
> E_MIPS_MACH field is also specified.
> A simple test is added to test suite.
>
> This patch is against binutils-2.17
>
> Waiting for your feedback.
> S.
>
> Signed-off-by: Sergey Lapin <slapin@ossfans.org>
> ---
> bfd/archures.c | 1 +
> bfd/bfd-in2.h | 1 +
> bfd/cpu-mips.c | 4 +-
> bfd/elfxx-mips.c | 7 +
> binutils/readelf.c | 1 +
> gas/config/tc-mips.c | 76 +++++-
> gas/testsuite/gas/mips/lexra-ill.l | 6 +
> gas/testsuite/gas/mips/lexra-ill.s | 7 +
> gas/testsuite/gas/mips/mips.exp | 9 +-
> include/elf/mips.h | 1 +
> include/opcode/mips.h | 3 +
> opcodes/mips-opc.c | 595 ++++++++++++++++++------------------
> 12 files changed, 409 insertions(+), 302 deletions(-)
> create mode 100644 gas/testsuite/gas/mips/lexra-ill.l
> create mode 100644 gas/testsuite/gas/mips/lexra-ill.s
What is about this patch?
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra support in binutils
2008-09-24 23:49 ` Sergey Lapin
@ 2008-09-29 15:45 ` Sergey Lapin
2008-10-07 17:52 ` Sergey Lapin
2008-10-14 21:04 ` Sergey Lapin
0 siblings, 2 replies; 34+ messages in thread
From: Sergey Lapin @ 2008-09-29 15:45 UTC (permalink / raw)
To: binutils; +Cc: Maciej W. Rozycki, Thiemo Seufer, Adam Nemet
Hi, all!
Is there any news regarding Lexra support in binutils?
1. Which steps are needed to be done to support
Lexra in upcoming binutils versions?
2. Was there any final conclusion regarding
which approach is preferred for MIPS-like CPUs not supporting
ISA1 fully?
Best regards,
S.
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra support in binutils
2008-09-29 15:45 ` Sergey Lapin
@ 2008-10-07 17:52 ` Sergey Lapin
2008-10-14 21:04 ` Sergey Lapin
1 sibling, 0 replies; 34+ messages in thread
From: Sergey Lapin @ 2008-10-07 17:52 UTC (permalink / raw)
To: binutils; +Cc: Maciej W. Rozycki, Thiemo Seufer, Adam Nemet
On Mon, Sep 29, 2008 at 06:21:02PM +0400, Sergey Lapin wrote:
> Hi, all!
>
> Is there any news regarding Lexra support in binutils?
>
> 1. Which steps are needed to be done to support
> Lexra in upcoming binutils versions?
>
> 2. Was there any final conclusion regarding
> which approach is preferred for MIPS-like CPUs not supporting
> ISA1 fully?
>
> Best regards,
> S.
Anything regarding this?
S.
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra support in binutils
2008-09-29 15:45 ` Sergey Lapin
2008-10-07 17:52 ` Sergey Lapin
@ 2008-10-14 21:04 ` Sergey Lapin
2008-10-22 15:08 ` Nick Clifton
1 sibling, 1 reply; 34+ messages in thread
From: Sergey Lapin @ 2008-10-14 21:04 UTC (permalink / raw)
To: binutils; +Cc: Maciej W. Rozycki, Thiemo Seufer, Adam Nemet
On Mon, Sep 29, 2008 at 06:21:02PM +0400, Sergey Lapin wrote:
Hi, all!
>
> Is there any news regarding Lexra support in binutils?
>
> 1. Which steps are needed to be done to support
> Lexra in upcoming binutils versions?
>
> 2. Was there any final conclusion regarding
> which approach is preferred for MIPS-like CPUs not supporting
> ISA1 fully?
>
> Best regards,
> S.
Anything regarding this?
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra support in binutils
2008-10-14 21:04 ` Sergey Lapin
@ 2008-10-22 15:08 ` Nick Clifton
2008-10-22 20:17 ` Sergey Lapin
0 siblings, 1 reply; 34+ messages in thread
From: Nick Clifton @ 2008-10-22 15:08 UTC (permalink / raw)
To: Sergey Lapin; +Cc: binutils, Maciej W. Rozycki, Thiemo Seufer, Adam Nemet
Hi Sergey,
>> Is there any news regarding Lexra support in binutils?
Did you see Theimo's response to your original patch submission:
http://sources.redhat.com/ml/binutils/2008-09/msg00132.html
& http://sources.redhat.com/ml/binutils/2008-09/msg00139.html
As well as Adam's ?
http://sources.redhat.com/ml/binutils/2008-09/msg00157.html
Also, my understanding is that the patches you have submitted are
against the 2.17 sources. Please could you submit a version generated
against the current mainline code instead ?
> Was there any final conclusion regarding
> which approach is preferred for MIPS-like CPUs not supporting
> ISA1 fully?
Lets stick with Maciej's suggestion for now:
http://sources.redhat.com/ml/binutils/2008-09/msg00143.html
Adam has pointed out that this will become cumbersome in the future, but
we can always have a separate patch to sort that out later on.
Cheers
Nick
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra support in binutils
2008-10-22 15:08 ` Nick Clifton
@ 2008-10-22 20:17 ` Sergey Lapin
2008-10-23 13:42 ` Nick Clifton
0 siblings, 1 reply; 34+ messages in thread
From: Sergey Lapin @ 2008-10-22 20:17 UTC (permalink / raw)
To: Nick Clifton; +Cc: binutils
On Wed, Oct 22, 2008 at 04:05:51PM +0100, Nick Clifton wrote:
Hi, Nick
>
>>> Is there any news regarding Lexra support in binutils?
>
> Did you see Theimo's response to your original patch submission:
>
> http://sources.redhat.com/ml/binutils/2008-09/msg00132.html
> & http://sources.redhat.com/ml/binutils/2008-09/msg00139.html
>
> As well as Adam's ?
>
> http://sources.redhat.com/ml/binutils/2008-09/msg00157.html
Of course, so I have produced this patch based on these suggestions and got no
answer at that time:
http://sourceware.org/ml/binutils/2008-09/msg00165.html
>
> Also, my understanding is that the patches you have submitted are
> against the 2.17 sources. Please could you submit a version generated
> against the current mainline code instead ?
Of course I will but I need advice on that changes (some smaller tips on
what change), since I'm not yet familarized myself with mainline
binutils yet.
>
>> Was there any final conclusion regarding
>> which approach is preferred for MIPS-like CPUs not supporting
>> ISA1 fully?
>
> Lets stick with Maciej's suggestion for now:
>
> http://sources.redhat.com/ml/binutils/2008-09/msg00143.html
>
> Adam has pointed out that this will become cumbersome in the future, but
> we can always have a separate patch to sort that out later on.
All the best,
S.
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra support in binutils
2008-10-22 20:17 ` Sergey Lapin
@ 2008-10-23 13:42 ` Nick Clifton
2008-10-24 18:58 ` Maciej W. Rozycki
0 siblings, 1 reply; 34+ messages in thread
From: Nick Clifton @ 2008-10-23 13:42 UTC (permalink / raw)
To: Sergey Lapin; +Cc: binutils
Hi Sergey,
> Of course, so I have produced this patch based on these suggestions and got no
> answer at that time:
>
> http://sourceware.org/ml/binutils/2008-09/msg00165.html
Sorry - my bad - I thought that was a reposting of your original patch
rather than an updated version.
> Of course I will but I need advice on that changes (some smaller tips on
> what change), since I'm not yet familarized myself with mainline
> binutils yet.
I think that you will find that apart from a some line number changes
most of the code you are patching is essentially the same now as it was
at the time of the 2.17 release. I suggest that you go ahead and apply
your current patch to the mainline sources, applying the rejected
portions by hand, and then (re)build and (re)test a mips toolchain to
make sure that everything is still working.
In fact I would say that the only thing currently missing from your
patch is a set of ChangeLog entries for the directories affected by the
changes and maybe an entry in the gas/NEWS file mentioning the support
for the Lexra.
Cheers
Nick
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra support in binutils
2008-10-23 13:42 ` Nick Clifton
@ 2008-10-24 18:58 ` Maciej W. Rozycki
2008-10-24 23:44 ` Thiemo Seufer
0 siblings, 1 reply; 34+ messages in thread
From: Maciej W. Rozycki @ 2008-10-24 18:58 UTC (permalink / raw)
To: Nick Clifton; +Cc: Sergey Lapin, binutils
On Thu, 23 Oct 2008, Nick Clifton wrote:
> In fact I would say that the only thing currently missing from your patch is a
> set of ChangeLog entries for the directories affected by the changes and maybe
> an entry in the gas/NEWS file mentioning the support for the Lexra.
One minor nit -- it would probably make sense to put the "mips0" entry in
mips_cpu_info_table[] separately before the list of "Entries for generic
ISAs," with a one-line comment like: "A fake ISA for MIPS I CPUs without
unaligned transfers."
Maciej
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra support in binutils
2008-10-24 18:58 ` Maciej W. Rozycki
@ 2008-10-24 23:44 ` Thiemo Seufer
2008-10-25 0:10 ` Adam Nemet
2008-10-25 3:22 ` Maciej W. Rozycki
0 siblings, 2 replies; 34+ messages in thread
From: Thiemo Seufer @ 2008-10-24 23:44 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: Nick Clifton, Sergey Lapin, binutils
Maciej W. Rozycki wrote:
> On Thu, 23 Oct 2008, Nick Clifton wrote:
>
> > In fact I would say that the only thing currently missing from your patch is a
> > set of ChangeLog entries for the directories affected by the changes and maybe
> > an entry in the gas/NEWS file mentioning the support for the Lexra.
>
> One minor nit -- it would probably make sense to put the "mips0" entry in
> mips_cpu_info_table[] separately before the list of "Entries for generic
> ISAs," with a one-line comment like: "A fake ISA for MIPS I CPUs without
> unaligned transfers."
I wonder how this will play with .set mips0. Maybe we should use "mips0.9"
for it, "mips0.8" for the compatible octeon subset, and "mips1.9" for the
R5900. :-)
Thiemo
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra support in binutils
2008-10-24 23:44 ` Thiemo Seufer
@ 2008-10-25 0:10 ` Adam Nemet
2008-10-25 1:09 ` Thiemo Seufer
2008-10-25 3:22 ` Maciej W. Rozycki
2008-10-25 3:22 ` Maciej W. Rozycki
1 sibling, 2 replies; 34+ messages in thread
From: Adam Nemet @ 2008-10-25 0:10 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: Maciej W. Rozycki, Nick Clifton, Sergey Lapin, binutils
Thiemo Seufer <ths@networkno.de> writes:
> Maciej W. Rozycki wrote:
>> On Thu, 23 Oct 2008, Nick Clifton wrote:
>>
>> > In fact I would say that the only thing currently missing from your patch is a
>> > set of ChangeLog entries for the directories affected by the changes and maybe
>> > an entry in the gas/NEWS file mentioning the support for the Lexra.
>>
>> One minor nit -- it would probably make sense to put the "mips0" entry in
>> mips_cpu_info_table[] separately before the list of "Entries for generic
>> ISAs," with a one-line comment like: "A fake ISA for MIPS I CPUs without
>> unaligned transfers."
>
> I wonder how this will play with .set mips0. Maybe we should use "mips0.9"
> for it, "mips0.8" for the compatible octeon subset, and "mips1.9" for the
> R5900. :-)
If I understand this correctly, shouldn't octeon be mips64r1.9 then?
Adam
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra support in binutils
2008-10-25 0:10 ` Adam Nemet
@ 2008-10-25 1:09 ` Thiemo Seufer
2008-10-25 1:50 ` Adam Nemet
2008-10-25 3:22 ` Maciej W. Rozycki
1 sibling, 1 reply; 34+ messages in thread
From: Thiemo Seufer @ 2008-10-25 1:09 UTC (permalink / raw)
To: Adam Nemet; +Cc: Maciej W. Rozycki, Nick Clifton, Sergey Lapin, binutils
Adam Nemet wrote:
> Thiemo Seufer <ths@networkno.de> writes:
> > Maciej W. Rozycki wrote:
> >> On Thu, 23 Oct 2008, Nick Clifton wrote:
> >>
> >> > In fact I would say that the only thing currently missing from your patch is a
> >> > set of ChangeLog entries for the directories affected by the changes and maybe
> >> > an entry in the gas/NEWS file mentioning the support for the Lexra.
> >>
> >> One minor nit -- it would probably make sense to put the "mips0" entry in
> >> mips_cpu_info_table[] separately before the list of "Entries for generic
> >> ISAs," with a one-line comment like: "A fake ISA for MIPS I CPUs without
> >> unaligned transfers."
> >
> > I wonder how this will play with .set mips0. Maybe we should use "mips0.9"
> > for it, "mips0.8" for the compatible octeon subset, and "mips1.9" for the
> > R5900. :-)
>
> If I understand this correctly, shouldn't octeon be mips64r1.9 then?
I had the octeon in the _other_ unaligned instruction mode in mind
with that.
Thiemo
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra support in binutils
2008-10-25 1:09 ` Thiemo Seufer
@ 2008-10-25 1:50 ` Adam Nemet
2008-10-25 14:20 ` Thiemo Seufer
0 siblings, 1 reply; 34+ messages in thread
From: Adam Nemet @ 2008-10-25 1:50 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: Maciej W. Rozycki, Nick Clifton, Sergey Lapin, binutils
Thiemo Seufer writes:
> Adam Nemet wrote:
> > Thiemo Seufer <ths@networkno.de> writes:
> > > Maciej W. Rozycki wrote:
> > >> On Thu, 23 Oct 2008, Nick Clifton wrote:
> > >>
> > >> > In fact I would say that the only thing currently missing from your patch is a
> > >> > set of ChangeLog entries for the directories affected by the changes and maybe
> > >> > an entry in the gas/NEWS file mentioning the support for the Lexra.
> > >>
> > >> One minor nit -- it would probably make sense to put the "mips0" entry in
> > >> mips_cpu_info_table[] separately before the list of "Entries for generic
> > >> ISAs," with a one-line comment like: "A fake ISA for MIPS I CPUs without
> > >> unaligned transfers."
> > >
> > > I wonder how this will play with .set mips0. Maybe we should use "mips0.9"
> > > for it, "mips0.8" for the compatible octeon subset, and "mips1.9" for the
> > > R5900. :-)
> >
> > If I understand this correctly, shouldn't octeon be mips64r1.9 then?
>
> I had the octeon in the _other_ unaligned instruction mode in mind
> with that.
Right so did I but isn't the "formula":
mips64r2 - MIPS unaligned instructions + custom unaligned instructions = mips64r1.9?
But maybe I misunderstanding what you meant by mips1.9 for R5900. I assumed
the logic there was:
mips2 - some mips2 instructions = mips1.9
?
Adam
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra support in binutils
2008-10-25 3:22 ` Maciej W. Rozycki
@ 2008-10-25 3:06 ` Adam Nemet
0 siblings, 0 replies; 34+ messages in thread
From: Adam Nemet @ 2008-10-25 3:06 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: Thiemo Seufer, Nick Clifton, Sergey Lapin, binutils
Maciej W. Rozycki writes:
> On Fri, 24 Oct 2008, Adam Nemet wrote:
>
> > > I wonder how this will play with .set mips0. Maybe we should use "mips0.9"
> > > for it, "mips0.8" for the compatible octeon subset, and "mips1.9" for the
> > > R5900. :-)
> >
> > If I understand this correctly, shouldn't octeon be mips64r1.9 then?
>
> Oh, we're not short of namespace here; it can be safely declared
> mips63r2.
My concern was not the actual name but to point out that octeon with the
custom unaligned instructions will have to be defined using ISA63R2 which will
be defined using ISA63 which will be defined using ISA31r2, etc.
Also on the patch specifically:
@@ -170,28 +173,28 @@ const struct mips_opcode mips_builtin_opcodes[] =
/* name, args, match, mask, pinfo, pinfo2, membership */
{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 },
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4|I33 },
-{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
+{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1|I0 }, /* sll */
I think these should only belong to I0 and I1 should include I0.
Adam
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra support in binutils
2008-10-24 23:44 ` Thiemo Seufer
2008-10-25 0:10 ` Adam Nemet
@ 2008-10-25 3:22 ` Maciej W. Rozycki
1 sibling, 0 replies; 34+ messages in thread
From: Maciej W. Rozycki @ 2008-10-25 3:22 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: Nick Clifton, Sergey Lapin, binutils
On Sat, 25 Oct 2008, Thiemo Seufer wrote:
> > One minor nit -- it would probably make sense to put the "mips0" entry in
> > mips_cpu_info_table[] separately before the list of "Entries for generic
> > ISAs," with a one-line comment like: "A fake ISA for MIPS I CPUs without
> > unaligned transfers."
>
> I wonder how this will play with .set mips0. Maybe we should use "mips0.9"
> for it, "mips0.8" for the compatible octeon subset, and "mips1.9" for the
> R5900. :-)
Heh. Good point anyway, but my understanding is the setting will only be
accessible through -march= and .set arch= and the traditional ISA
modifiers will stay intact. Code seems to agree.
Maciej
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra support in binutils
2008-10-25 0:10 ` Adam Nemet
2008-10-25 1:09 ` Thiemo Seufer
@ 2008-10-25 3:22 ` Maciej W. Rozycki
2008-10-25 3:06 ` Adam Nemet
1 sibling, 1 reply; 34+ messages in thread
From: Maciej W. Rozycki @ 2008-10-25 3:22 UTC (permalink / raw)
To: Adam Nemet; +Cc: Thiemo Seufer, Nick Clifton, Sergey Lapin, binutils
On Fri, 24 Oct 2008, Adam Nemet wrote:
> > I wonder how this will play with .set mips0. Maybe we should use "mips0.9"
> > for it, "mips0.8" for the compatible octeon subset, and "mips1.9" for the
> > R5900. :-)
>
> If I understand this correctly, shouldn't octeon be mips64r1.9 then?
Oh, we're not short of namespace here; it can be safely declared
mips63r2.
Maciej
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra support in binutils
2008-10-25 1:50 ` Adam Nemet
@ 2008-10-25 14:20 ` Thiemo Seufer
2008-10-25 20:08 ` Adam Nemet
0 siblings, 1 reply; 34+ messages in thread
From: Thiemo Seufer @ 2008-10-25 14:20 UTC (permalink / raw)
To: Adam Nemet; +Cc: Maciej W. Rozycki, Nick Clifton, Sergey Lapin, binutils
Adam Nemet wrote:
> Thiemo Seufer writes:
> > Adam Nemet wrote:
> > > Thiemo Seufer <ths@networkno.de> writes:
> > > > Maciej W. Rozycki wrote:
> > > >> On Thu, 23 Oct 2008, Nick Clifton wrote:
> > > >>
> > > >> > In fact I would say that the only thing currently missing from your patch is a
> > > >> > set of ChangeLog entries for the directories affected by the changes and maybe
> > > >> > an entry in the gas/NEWS file mentioning the support for the Lexra.
> > > >>
> > > >> One minor nit -- it would probably make sense to put the "mips0" entry in
> > > >> mips_cpu_info_table[] separately before the list of "Entries for generic
> > > >> ISAs," with a one-line comment like: "A fake ISA for MIPS I CPUs without
> > > >> unaligned transfers."
> > > >
> > > > I wonder how this will play with .set mips0. Maybe we should use "mips0.9"
> > > > for it, "mips0.8" for the compatible octeon subset, and "mips1.9" for the
> > > > R5900. :-)
> > >
> > > If I understand this correctly, shouldn't octeon be mips64r1.9 then?
> >
> > I had the octeon in the _other_ unaligned instruction mode in mind
> > with that.
>
> Right so did I but isn't the "formula":
>
> mips64r2 - MIPS unaligned instructions + custom unaligned instructions = mips64r1.9?
Anything without MIPS unaligned instructions would be mips0.9. I vaguely
(mis-?)remembered some octeon coprocessor instruction are different, too,
so I came up with mips0.8 for octeon.
Custom instructions of any sort would be processor specific, not
part of an (Pseudo-)ISA. From that POV, the octeon would be a
mips0.8 + mips2 + mips3 + mips4 + mips64 + mips64r2 + octeon
part.
Thiemo
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra support in binutils
2008-10-25 14:20 ` Thiemo Seufer
@ 2008-10-25 20:08 ` Adam Nemet
2008-10-25 21:12 ` Thiemo Seufer
0 siblings, 1 reply; 34+ messages in thread
From: Adam Nemet @ 2008-10-25 20:08 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: Maciej W. Rozycki, Nick Clifton, Sergey Lapin, binutils
Thiemo Seufer writes:
> Adam Nemet wrote:
> > Right so did I but isn't the "formula":
> >
> > mips64r2 - MIPS unaligned instructions + custom unaligned instructions = mips64r1.9?
>
> Anything without MIPS unaligned instructions would be mips0.9. I vaguely
> (mis-?)remembered some octeon coprocessor instruction are different, too,
> so I came up with mips0.8 for octeon.
Right. It's only an omission (certain cop2 instructions are not implemented).
Note that these instructions can be selectively implemented by processors so
defining an new ISA for each combination may not scale that well. (Hence was
my idea to create a way for a processor to be defined not just in terms of an
ISA + processor-specific instruction but also in terms of processor-specific
omissions.)
> Custom instructions of any sort would be processor specific, not
> part of an (Pseudo-)ISA. From that POV, the octeon would be a
> mips0.8 + mips2 + mips3 + mips4 + mips64 + mips64r2 + octeon
> part.
Sure but my question was targeted at the *ISA* that this "other" octeon would
be derived from. To avoid any misunderstanding, is this approximately what
you're proposing?:
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.59
diff -u -p -r1.59 mips.h
--- include/opcode/mips.h 12 Jun 2008 21:44:53 -0000 1.59
+++ include/opcode/mips.h 25 Oct 2008 20:01:32 -0000
@@ -511,6 +511,7 @@ struct mips_opcode
#define INSN_ISA_MASK 0x0000000ful
/* We cannot start at zero due to ISA_UNKNOWN below. */
+/* We're out values to define: INSN_ISA0_8 and INSN_ISA0_9. */
#define INSN_ISA1 1
#define INSN_ISA2 2
#define INSN_ISA3 3
@@ -519,16 +520,17 @@ struct mips_opcode
#define INSN_ISA32 6
#define INSN_ISA32R2 7
#define INSN_ISA64 8
-#define INSN_ISA64R2 9
+#define INSN_ISA64R2_0_9 9
+#define INSN_ISA64R2 10
/* Below this point the INSN_* values correspond to combinations of ISAs.
They are only for use in the opcodes table to indicate membership of
a combination of ISAs that cannot be expressed using the usual inclusion
ordering on the above INSN_* values. */
-#define INSN_ISA3_32 10
-#define INSN_ISA3_32R2 11
-#define INSN_ISA4_32 12
-#define INSN_ISA4_32R2 13
-#define INSN_ISA5_32R2 14
+#define INSN_ISA3_32 11
+#define INSN_ISA3_32R2 12
+#define INSN_ISA4_32 13
+#define INSN_ISA4_32R2 14
+#define INSN_ISA5_32R2 15
/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
@@ -539,7 +541,10 @@ struct mips_opcode
(mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
is non-zero. */
static const unsigned int mips_isa_table[] =
- { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
+ { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf,
+ /* Add INSN_ISA64R2_0_9 here: INSN_ISA0_8 + INSN_ISA2 ... + INSN_ISA64R2 */
+ 0x....,
+ 0x3fff };
/* Masks used for Chip specific instructions. */
#define INSN_CHIP_MASK 0xc3ff0800
@@ -605,6 +610,7 @@ static const unsigned int mips_isa_table
#define ISA_MIPS64 INSN_ISA64
#define ISA_MIPS32R2 INSN_ISA32R2
+#define ISA_MIPS64R2_0_9 INSN_ISA64R2_0_9
#define ISA_MIPS64R2 INSN_ISA64R2
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.394
diff -u -p -r1.394 tc-mips.c
--- gas/config/tc-mips.c 8 Aug 2008 19:24:49 -0000 1.394
+++ gas/config/tc-mips.c 25 Oct 2008 20:01:43 -0000
@@ -15173,6 +15173,7 @@ static const struct mips_cpu_info mips_c
ISA_MIPS64, CPU_SB1 },
/* Cavium Networks Octeon CPU core */
+ { "other-octeon" 0, ISA_MIPS64R2_0_9, CPU_OCTEON },
{ "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
/* End marker */
Adam
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra support in binutils
2008-10-25 20:08 ` Adam Nemet
@ 2008-10-25 21:12 ` Thiemo Seufer
2008-10-25 21:48 ` Adam Nemet
0 siblings, 1 reply; 34+ messages in thread
From: Thiemo Seufer @ 2008-10-25 21:12 UTC (permalink / raw)
To: Adam Nemet; +Cc: Maciej W. Rozycki, Nick Clifton, Sergey Lapin, binutils
Adam Nemet wrote:
> Thiemo Seufer writes:
> > Adam Nemet wrote:
> > > Right so did I but isn't the "formula":
> > >
> > > mips64r2 - MIPS unaligned instructions + custom unaligned instructions = mips64r1.9?
> >
> > Anything without MIPS unaligned instructions would be mips0.9. I vaguely
> > (mis-?)remembered some octeon coprocessor instruction are different, too,
> > so I came up with mips0.8 for octeon.
>
> Right. It's only an omission (certain cop2 instructions are not implemented).
> Note that these instructions can be selectively implemented by processors so
> defining an new ISA for each combination may not scale that well. (Hence was
> my idea to create a way for a processor to be defined not just in terms of an
> ISA + processor-specific instruction but also in terms of processor-specific
> omissions.)
Agreed, differences in COP2 which is largely unspecified anyway don't
justify an additional pseudo-ISA.
> > Custom instructions of any sort would be processor specific, not
> > part of an (Pseudo-)ISA. From that POV, the octeon would be a
> > mips0.8 + mips2 + mips3 + mips4 + mips64 + mips64r2 + octeon
> > part.
>
> Sure but my question was targeted at the *ISA* that this "other" octeon would
> be derived from. To avoid any misunderstanding, is this approximately what
> you're proposing?:
[snip]
> @@ -539,7 +541,10 @@ struct mips_opcode
> (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
> is non-zero. */
> static const unsigned int mips_isa_table[] =
> - { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
> + { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf,
> + /* Add INSN_ISA64R2_0_9 here: INSN_ISA0_8 + INSN_ISA2 ... + INSN_ISA64R2 */
> + 0x....,
> + 0x3fff };
Oh I see. I always had the vague feeling this clever trick would bite
use some day. :-) Yes, it should be something like that, probably with
applying Maciej's namespace observation: {ISA,INSN}_ISA63R2 instead of
the unwieldy {ISA,INSN}_ISA64_0_9.
Thiemo
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] Lexra support in binutils
2008-10-25 21:12 ` Thiemo Seufer
@ 2008-10-25 21:48 ` Adam Nemet
0 siblings, 0 replies; 34+ messages in thread
From: Adam Nemet @ 2008-10-25 21:48 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: Maciej W. Rozycki, Nick Clifton, Sergey Lapin, binutils
Thiemo Seufer writes:
> Adam Nemet wrote:
> [snip]
> > @@ -539,7 +541,10 @@ struct mips_opcode
> > (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
> > is non-zero. */
> > static const unsigned int mips_isa_table[] =
> > - { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
> > + { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf,
> > + /* Add INSN_ISA64R2_0_9 here: INSN_ISA0_8 + INSN_ISA2 ... + INSN_ISA64R2 */
> > + 0x....,
> > + 0x3fff };
>
> Oh I see. I always had the vague feeling this clever trick would bite
> use some day. :-) Yes, it should be something like that, probably with
> applying Maciej's namespace observation: {ISA,INSN}_ISA63R2 instead of
> the unwieldy {ISA,INSN}_ISA64_0_9.
OK. I actually think that we should experiment with extending the
mips_isa_table idea to the ASEs. ASEs should be orthogonal so it should be
rare for two ASEs to provide the same insn. Then we'd have more bits for
pseudo-ISAs and processors.
This is of course no concern for Lexra. There is still one more spot
available among the ISAs.
Adam
^ permalink raw reply [flat|nested] 34+ messages in thread
end of thread, other threads:[~2008-10-25 21:48 UTC | newest]
Thread overview: 34+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2008-09-17 11:55 [PATCH] Lexra binutils Sergey Lapin
2008-09-17 12:40 ` Thiemo Seufer
[not found] ` <20080917131851.GA3115@build.ossfans.org>
[not found] ` <20080917140048.GE11791@networkno.de>
[not found] ` <20080917164747.GA9502@build.ossfans.org>
2008-09-17 17:26 ` Sergey Lapin
2008-09-17 17:58 ` Thiemo Seufer
2008-09-18 10:11 ` Maciej W. Rozycki
2008-09-18 10:53 ` Thiemo Seufer
2008-09-19 4:08 ` Adam Nemet
2008-09-19 10:06 ` Maciej W. Rozycki
2008-09-19 17:01 ` Adam Nemet
2008-09-19 17:37 ` Maciej W. Rozycki
2008-09-19 18:27 ` Adam Nemet
2008-09-19 22:59 ` Maciej W. Rozycki
2008-09-19 23:11 ` Adam Nemet
2008-09-21 4:25 ` [PATCH] Lexra support in binutils Sergey Lapin
2008-09-24 23:49 ` Sergey Lapin
2008-09-29 15:45 ` Sergey Lapin
2008-10-07 17:52 ` Sergey Lapin
2008-10-14 21:04 ` Sergey Lapin
2008-10-22 15:08 ` Nick Clifton
2008-10-22 20:17 ` Sergey Lapin
2008-10-23 13:42 ` Nick Clifton
2008-10-24 18:58 ` Maciej W. Rozycki
2008-10-24 23:44 ` Thiemo Seufer
2008-10-25 0:10 ` Adam Nemet
2008-10-25 1:09 ` Thiemo Seufer
2008-10-25 1:50 ` Adam Nemet
2008-10-25 14:20 ` Thiemo Seufer
2008-10-25 20:08 ` Adam Nemet
2008-10-25 21:12 ` Thiemo Seufer
2008-10-25 21:48 ` Adam Nemet
2008-10-25 3:22 ` Maciej W. Rozycki
2008-10-25 3:06 ` Adam Nemet
2008-10-25 3:22 ` Maciej W. Rozycki
2008-09-19 17:00 ` [PATCH] Lexra binutils Adam Nemet
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).