PATCH: Add AppliedMicro Titan (APM83xxx) support

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* PATCH: Add AppliedMicro Titan (APM83xxx) support
@ 2009-11-19 23:46 Philipp Tomsich
  2009-11-20  4:12 ` Alan Modra
  0 siblings, 1 reply; 4+ messages in thread
From: Philipp Tomsich @ 2009-11-19 23:46 UTC (permalink / raw)
  To: binutils

This is a patch to add support for the AppliedMicro Titan core.

The Titan is a BookE-compliant PowerPC that supports the 440-style  
halfword-multiplication, but is missing a few FP instructions. We've  
also included pseudoinstructions for the various SPRs the Titan  
supports.

Best regards,
Phil.

--
diff --git a/bfd/archures.c b/bfd/archures.c
index 8df2ce1..b38f7cf 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -230,6 +230,7 @@ DESCRIPTION
.#define bfd_mach_ppc_7400	7400
.#define bfd_mach_ppc_e500      500
.#define bfd_mach_ppc_e500mc    5001
+.#define bfd_mach_ppc_titan     83
.  bfd_arch_rs6000,    {* IBM RS/6000 *}
.#define bfd_mach_rs6k		6000
.#define bfd_mach_rs6k_rs1	6001
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 455ec56..a900c25 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1901,6 +1901,7 @@ enum bfd_architecture
#define bfd_mach_ppc_7400      7400
#define bfd_mach_ppc_e500      500
#define bfd_mach_ppc_e500mc    5001
+#define bfd_mach_ppc_titan     83
   bfd_arch_rs6000,    /* IBM RS/6000 */
#define bfd_mach_rs6k          6000
#define bfd_mach_rs6k_rs1      6001
diff --git a/bfd/cpu-powerpc.c b/bfd/cpu-powerpc.c
index 0b511f3..c3db7a5 100644
--- a/bfd/cpu-powerpc.c
+++ b/bfd/cpu-powerpc.c
@@ -324,6 +324,21 @@ const bfd_arch_info_type bfd_powerpc_archs[] =
     FALSE, /* not the default */
     powerpc_compatible,
     bfd_default_scan,
+    &bfd_powerpc_archs[17]
+  },
+  {
+    32, /* 32 bits in a word */
+    32, /* 32 bits in an address */
+    8,  /* 8 bits in a byte */
+    bfd_arch_powerpc,
+    bfd_mach_ppc_titan,
+    "powerpc",
+    "powerpc:titan",
+    3,
+    FALSE, /* not the default */
+    powerpc_compatible,
+    bfd_default_scan,
     0
   }
+
};
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 2c7c219..16216c2 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2009-11-19  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
+	
+	* doc/c-ppc.texi (PowerPC-Opts): Document "-mtitan".
+	* testsuite/gas/ppc/titan.d: New file.
+	* testsuite/gas/ppc/titan.s: New file.
+
2009-11-19  Jan Beulich  <jbeulich@novell.com>

	* read.c (pseudo_set): Also call copy_symbol_attributes() for
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 1d615e9..6a430ed 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1211,6 +1211,7 @@ PowerPC options:\n\
-me500, -me500x2	generate code for Motorola e500 core complex\n\
-me500mc,               generate code for Freescale e500mc core complex 
\n\
-mspe			generate code for Motorola SPE instructions\n\
+-mtitan                 generate code for AppliedMicro Titan core  
complex\n\
-mregnames		Allow symbolic names for registers\n\
-mno-regnames		Do not allow symbolic names for registers\n"));
#ifdef OBJ_ELF
@@ -1288,6 +1289,8 @@ ppc_mach (void)
     return bfd_mach_ppc64;
   else if (ppc_arch () == bfd_arch_rs6000)
     return bfd_mach_rs6k;
+  else if (ppc_cpu & PPC_OPCODE_TITAN)
+    return bfd_mach_ppc_titan;
   else
     return bfd_mach_ppc;
}
diff --git a/gas/doc/c-ppc.texi b/gas/doc/c-ppc.texi
index cab461b..00b15cc 100644
--- a/gas/doc/c-ppc.texi
+++ b/gas/doc/c-ppc.texi
@@ -70,6 +70,9 @@ Generate code for Motorola e500 core complex.
@item -mspe
Generate code for Motorola SPE instructions.

+@item -mtitan
+Generate code for AppliedMicro Titan core complex.
+
@item -mppc64bridge
Generate code for PowerPC 64, including bridge insns.

diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ 
ppc.exp
index 0c8d852..3db0ade 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -50,5 +50,6 @@ if { [istarget powerpc*-*-*] } then {
	run_dump_test "power7"
	run_dump_test "vsx"
	run_dump_test "476"
+	run_dump_test "titan"
     }
}
diff --git a/gas/testsuite/gas/ppc/titan.d b/gas/testsuite/gas/ppc/ 
titan.d
new file mode 100644
index 0000000..fcbb973
--- /dev/null
+++ b/gas/testsuite/gas/ppc/titan.d
@@ -0,0 +1,267 @@
+#as: -mtitan
+#objdump: -dr -Mtitan
+#name: AppliedMicro Titan tests
+
+.*: +file format elf(32)?(64)?-powerpc.*
+
+Disassembly of section \.text:
+
+0+00 <test>:
+   0:	4e 80 00 20 	blr
+   4:	0c 81 00 00 	tweqi   r1,0
+   8:	10 41 01 58 	macchw  r2,r1,r0
+   c:	10 41 01 59 	macchw\. r2,r1,r0
+  10:	10 41 05 58 	macchwo r2,r1,r0
+  14:	10 41 05 59 	macchwo\. r2,r1,r0
+  18:	10 41 01 d8 	macchws r2,r1,r0
+  1c:	10 41 01 d9 	macchws\. r2,r1,r0
+  20:	10 41 05 d8 	macchwso r2,r1,r0
+  24:	10 41 05 d9 	macchwso\. r2,r1,r0
+  28:	10 41 01 98 	macchwsu r2,r1,r0
+  2c:	10 41 01 99 	macchwsu\. r2,r1,r0
+  30:	10 41 05 98 	macchwsuo r2,r1,r0
+  34:	10 41 05 99 	macchwsuo\. r2,r1,r0
+  38:	10 41 01 18 	macchwu r2,r1,r0
+  3c:	10 41 01 19 	macchwu\. r2,r1,r0
+  40:	10 41 05 18 	macchwuo r2,r1,r0
+  44:	10 41 05 19 	macchwuo\. r2,r1,r0
+  48:	10 41 00 58 	machhw  r2,r1,r0
+  4c:	10 41 00 59 	machhw\. r2,r1,r0
+  50:	10 41 04 58 	machhwo r2,r1,r0
+  54:	10 41 04 59 	machhwo\. r2,r1,r0
+  58:	10 41 00 d8 	machhws r2,r1,r0
+  5c:	10 41 00 d9 	machhws\. r2,r1,r0
+  60:	10 41 04 d8 	machhwso r2,r1,r0
+  64:	10 41 04 d9 	machhwso\. r2,r1,r0
+  68:	10 41 00 98 	machhwsu r2,r1,r0
+  6c:	10 41 00 99 	machhwsu\. r2,r1,r0
+  70:	10 41 04 98 	machhwsuo r2,r1,r0
+  74:	10 41 04 99 	machhwsuo\. r2,r1,r0
+  78:	10 41 00 18 	machhwu r2,r1,r0
+  7c:	10 41 00 19 	machhwu\. r2,r1,r0
+  80:	10 41 04 18 	machhwuo r2,r1,r0
+  84:	10 41 04 19 	machhwuo\. r2,r1,r0
+  88:	10 41 03 58 	maclhw  r2,r1,r0
+  8c:	10 41 03 59 	maclhw\. r2,r1,r0
+  90:	10 41 07 58 	maclhwo r2,r1,r0
+  94:	10 41 07 59 	maclhwo\. r2,r1,r0
+  98:	10 41 03 d8 	maclhws r2,r1,r0
+  9c:	10 41 03 d9 	maclhws\. r2,r1,r0
+  a0:	10 41 07 d8 	maclhwso r2,r1,r0
+  a4:	10 41 07 d9 	maclhwso\. r2,r1,r0
+  a8:	10 41 03 98 	maclhwsu r2,r1,r0
+  ac:	10 41 03 99 	maclhwsu\. r2,r1,r0
+  b0:	10 41 07 98 	maclhwsuo r2,r1,r0
+  b4:	10 41 07 99 	maclhwsuo\. r2,r1,r0
+  b8:	10 41 03 18 	maclhwu r2,r1,r0
+  bc:	10 41 03 19 	maclhwu\. r2,r1,r0
+  c0:	10 41 07 18 	maclhwuo r2,r1,r0
+  c4:	10 41 07 19 	maclhwuo\. r2,r1,r0
+  c8:	10 41 01 5c 	nmacchw r2,r1,r0
+  cc:	10 41 01 5d 	nmacchw\. r2,r1,r0
+  d0:	10 41 05 5c 	nmacchwo r2,r1,r0
+  d4:	10 41 05 5d 	nmacchwo\. r2,r1,r0
+  d8:	10 41 01 dc 	nmacchws r2,r1,r0
+  dc:	10 41 01 dd 	nmacchws\. r2,r1,r0
+  e0:	10 41 05 dc 	nmacchwso r2,r1,r0
+  e4:	10 41 05 dd 	nmacchwso\. r2,r1,r0
+  e8:	10 41 00 5c 	nmachhw r2,r1,r0
+  ec:	10 41 00 5d 	nmachhw\. r2,r1,r0
+  f0:	10 41 04 5c 	nmachhwo r2,r1,r0
+  f4:	10 41 04 5d 	nmachhwo\. r2,r1,r0
+  f8:	10 41 00 dc 	nmachhws r2,r1,r0
+  fc:	10 41 00 dd 	nmachhws\. r2,r1,r0
+ 100:	10 41 04 dc 	nmachhwso r2,r1,r0
+ 104:	10 41 04 dd 	nmachhwso\. r2,r1,r0
+ 108:	10 41 03 5c 	nmaclhw r2,r1,r0
+ 10c:	10 41 03 5d 	nmaclhw\. r2,r1,r0
+ 110:	10 41 07 5c 	nmaclhwo r2,r1,r0
+ 114:	10 41 07 5d 	nmaclhwo\. r2,r1,r0
+ 118:	10 41 03 dc 	nmaclhws r2,r1,r0
+ 11c:	10 41 03 dd 	nmaclhws\. r2,r1,r0
+ 120:	10 41 07 dc 	nmaclhwso r2,r1,r0
+ 124:	10 41 07 dd 	nmaclhwso\. r2,r1,r0
+ 128:	10 41 01 50 	mulchw  r2,r1,r0
+ 12c:	10 41 01 51 	mulchw\. r2,r1,r0
+ 130:	10 41 01 10 	mulchwu r2,r1,r0
+ 134:	10 41 01 11 	mulchwu\. r2,r1,r0
+ 138:	10 41 00 50 	mulhhw  r2,r1,r0
+ 13c:	10 41 00 51 	mulhhw\. r2,r1,r0
+ 140:	10 41 00 10 	mulhhwu r2,r1,r0
+ 144:	10 41 00 11 	mulhhwu\. r2,r1,r0
+ 148:	10 41 03 50 	mullhw  r2,r1,r0
+ 14c:	10 41 03 51 	mullhw\. r2,r1,r0
+ 150:	10 41 03 10 	mullhwu r2,r1,r0
+ 154:	10 41 03 11 	mullhwu\. r2,r1,r0
+ 158:	7c 22 00 9c 	dlmzb   r2,r1,r0
+ 15c:	7c 22 00 9d 	dlmzb\.  r2,r1,r0
+ 160:	7c 02 0b 8c 	dccci   r2,r1
+ 164:	7c 02 0f 8c 	iccci   r2,r1
+ 168:	7c 02 0b 0c 	dcblc   r2,r1
+ 16c:	7c 02 0b 0c 	dcblc   r2,r1
+ 170:	7c 22 0b 0c 	dcblc   1,r2,r1
+ 174:	7c 02 09 4c 	dcbtls  r2,r1
+ 178:	7c 02 09 4c 	dcbtls  r2,r1
+ 17c:	7c 22 09 4c 	dcbtls  1,r2,r1
+ 180:	7c 02 09 0c 	dcbtstls r2,r1
+ 184:	7c 02 09 0c 	dcbtstls r2,r1
+ 188:	7c 22 09 0c 	dcbtstls 1,r2,r1
+ 18c:	7c 02 09 cc 	icblc   r2,r1
+ 190:	7c 02 09 cc 	icblc   r2,r1
+ 194:	7c 22 09 cc 	icblc   1,r2,r1
+ 198:	7c 02 0b cc 	icbtls  r2,r1
+ 19c:	7c 02 0b cc 	icbtls  r2,r1
+ 1a0:	7c 22 0b cc 	icbtls  1,r2,r1
+ 1a4:	7c 41 02 8c 	dcread  r2,r1,r0
+ 1a8:	7c 02 0f cc 	icread  r2,r1
+ 1ac:	7c 41 02 9c 	mfpmr   r2,pmctr1
+ 1b0:	7c 22 02 9c 	mfpmr   r1,pmctr2
+ 1b4:	7c 81 02 a6 	mfxer   r4
+ 1b8:	7c 81 02 a6 	mfxer   r4
+ 1bc:	7c 88 02 a6 	mflr    r4
+ 1c0:	7c 88 02 a6 	mflr    r4
+ 1c4:	7c 89 02 a6 	mfctr   r4
+ 1c8:	7c 89 02 a6 	mfctr   r4
+ 1cc:	7c 96 02 a6 	mfdec   r4
+ 1d0:	7c 96 02 a6 	mfdec   r4
+ 1d4:	7c 9a 02 a6 	mfsrr0  r4
+ 1d8:	7c 9a 02 a6 	mfsrr0  r4
+ 1dc:	7c 9b 02 a6 	mfsrr1  r4
+ 1e0:	7c 9b 02 a6 	mfsrr1  r4
+ 1e4:	7c 90 0a a6 	mfpid   r4
+ 1e8:	7c 90 0a a6 	mfpid   r4
+ 1ec:	7c 9a 0a a6 	mfcsrr0 r4
+ 1f0:	7c 9a 0a a6 	mfcsrr0 r4
+ 1f4:	7c 9b 0a a6 	mfcsrr1 r4
+ 1f8:	7c 9b 0a a6 	mfcsrr1 r4
+ 1fc:	7c 9d 0a a6 	mfdear  r4
+ 200:	7c 9d 0a a6 	mfdear  r4
+ 204:	7c 9e 0a a6 	mfesr   r4
+ 208:	7c 9e 0a a6 	mfesr   r4
+ 20c:	7c 9f 0a a6 	mfivpr  r4
+ 210:	7c 9f 0a a6 	mfivpr  r4
+ 214:	7c 80 42 a6 	mfusprg0 r4
+ 218:	7c 80 42 a6 	mfusprg0 r4
+ 21c:	7c 84 42 a6 	mfsprg  r4,4
+ 220:	7c 84 42 a6 	mfsprg  r4,4
+ 224:	7c 85 42 a6 	mfsprg  r4,5
+ 228:	7c 85 42 a6 	mfsprg  r4,5
+ 22c:	7c 86 42 a6 	mfsprg  r4,6
+ 230:	7c 86 42 a6 	mfsprg  r4,6
+ 234:	7c 87 42 a6 	mfsprg  r4,7
+ 238:	7c 87 42 a6 	mfsprg  r4,7
+ 23c:	7c 8c 42 a6 	mftb    r4
+ 240:	7c 8c 42 a6 	mftb    r4
+ 244:	7c 8c 42 a6 	mftb    r4
+ 248:	7c 8d 42 a6 	mftbu   r4
+ 24c:	7c 8d 42 a6 	mftbu   r4
+ 250:	7c 90 42 a6 	mfsprg  r4,0
+ 254:	7c 90 42 a6 	mfsprg  r4,0
+ 258:	7c 91 42 a6 	mfsprg  r4,1
+ 25c:	7c 91 42 a6 	mfsprg  r4,1
+ 260:	7c 92 42 a6 	mfsprg  r4,2
+ 264:	7c 92 42 a6 	mfsprg  r4,2
+ 268:	7c 93 42 a6 	mfsprg  r4,3
+ 26c:	7c 93 42 a6 	mfsprg  r4,3
+ 270:	7c 9e 42 a6 	mfpir   r4
+ 274:	7c 9e 42 a6 	mfpir   r4
+ 278:	7c 9f 42 a6 	mfpvr   r4
+ 27c:	7c 9f 42 a6 	mfpvr   r4
+ 280:	7c 90 4a a6 	mfdbsr  r4
+ 284:	7c 90 4a a6 	mfdbsr  r4
+ 288:	7c 94 4a a6 	mfdbcr0 r4
+ 28c:	7c 94 4a a6 	mfdbcr0 r4
+ 290:	7c 95 4a a6 	mfdbcr1 r4
+ 294:	7c 95 4a a6 	mfdbcr1 r4
+ 298:	7c 96 4a a6 	mfdbcr2 r4
+ 29c:	7c 96 4a a6 	mfdbcr2 r4
+ 2a0:	7c 98 4a a6 	mfiac1  r4
+ 2a4:	7c 98 4a a6 	mfiac1  r4
+ 2a8:	7c 99 4a a6 	mfiac2  r4
+ 2ac:	7c 99 4a a6 	mfiac2  r4
+ 2b0:	7c 9a 4a a6 	mfiac3  r4
+ 2b4:	7c 9a 4a a6 	mfiac3  r4
+ 2b8:	7c 9b 4a a6 	mfiac4  r4
+ 2bc:	7c 9b 4a a6 	mfiac4  r4
+ 2c0:	7c 9c 4a a6 	mfdac1  r4
+ 2c4:	7c 9c 4a a6 	mfdac1  r4
+ 2c8:	7c 9d 4a a6 	mfdac2  r4
+ 2cc:	7c 9d 4a a6 	mfdac2  r4
+ 2d0:	7c 9e 4a a6 	mfdvc1  r4
+ 2d4:	7c 9e 4a a6 	mfdvc1  r4
+ 2d8:	7c 9f 4a a6 	mfdvc2  r4
+ 2dc:	7c 9f 4a a6 	mfdvc2  r4
+ 2e0:	7c 90 52 a6 	mftsr   r4
+ 2e4:	7c 90 52 a6 	mftsr   r4
+ 2e8:	7c 94 52 a6 	mftcr   r4
+ 2ec:	7c 94 52 a6 	mftcr   r4
+ 2f0:	7c 90 62 a6 	mfivor0 r4
+ 2f4:	7c 90 62 a6 	mfivor0 r4
+ 2f8:	7c 91 62 a6 	mfivor1 r4
+ 2fc:	7c 91 62 a6 	mfivor1 r4
+ 300:	7c 92 62 a6 	mfivor2 r4
+ 304:	7c 92 62 a6 	mfivor2 r4
+ 308:	7c 93 62 a6 	mfivor3 r4
+ 30c:	7c 93 62 a6 	mfivor3 r4
+ 310:	7c 94 62 a6 	mfivor4 r4
+ 314:	7c 94 62 a6 	mfivor4 r4
+ 318:	7c 95 62 a6 	mfivor5 r4
+ 31c:	7c 95 62 a6 	mfivor5 r4
+ 320:	7c 96 62 a6 	mfivor6 r4
+ 324:	7c 96 62 a6 	mfivor6 r4
+ 328:	7c 97 62 a6 	mfivor7 r4
+ 32c:	7c 97 62 a6 	mfivor7 r4
+ 330:	7c 98 62 a6 	mfivor8 r4
+ 334:	7c 98 62 a6 	mfivor8 r4
+ 338:	7c 99 62 a6 	mfivor9 r4
+ 33c:	7c 99 62 a6 	mfivor9 r4
+ 340:	7c 9a 62 a6 	mfivor10 r4
+ 344:	7c 9a 62 a6 	mfivor10 r4
+ 348:	7c 9b 62 a6 	mfivor11 r4
+ 34c:	7c 9b 62 a6 	mfivor11 r4
+ 350:	7c 9c 62 a6 	mfivor12 r4
+ 354:	7c 9c 62 a6 	mfivor12 r4
+ 358:	7c 9d 62 a6 	mfivor13 r4
+ 35c:	7c 9d 62 a6 	mfivor13 r4
+ 360:	7c 9e 62 a6 	mfivor14 r4
+ 364:	7c 9e 62 a6 	mfivor14 r4
+ 368:	7c 9f 62 a6 	mfivor15 r4
+ 36c:	7c 9f 62 a6 	mfivor15 r4
+ 370:	7c 93 82 a6 	mfivor35 r4
+ 374:	7c 93 82 a6 	mfivor35 r4
+ 378:	7c 9a 8a a6 	mfdc_dat r4
+ 37c:	7c 9a 8a a6 	mfdc_dat r4
+ 380:	7c 9b 8a a6 	mfmcsrr1 r4
+ 384:	7c 9b 8a a6 	mfmcsrr1 r4
+ 388:	7c 9c 8a a6 	mfmcsr  r4
+ 38c:	7c 9c 8a a6 	mfmcsr  r4
+ 390:	7c 90 da a6 	mfivndx r4
+ 394:	7c 90 da a6 	mfivndx r4
+ 398:	7c 91 da a6 	mfdvndx r4
+ 39c:	7c 91 da a6 	mfdvndx r4
+ 3a0:	7c 92 da a6 	mfivlim r4
+ 3a4:	7c 92 da a6 	mfivlim r4
+ 3a8:	7c 93 da a6 	mfdvlim r4
+ 3ac:	7c 93 da a6 	mfdvlim r4
+ 3b0:	7c 94 da a6 	mfclcsr r4
+ 3b4:	7c 94 da a6 	mfclcsr r4
+ 3b8:	7c 98 da a6 	mfccr1  r4
+ 3bc:	7c 98 da a6 	mfccr1  r4
+ 3c0:	7c 9b e2 a6 	mfrstcfg r4
+ 3c4:	7c 9b e2 a6 	mfrstcfg r4
+ 3c8:	7c 9c e2 a6 	mfdcdbtrl r4
+ 3cc:	7c 9c e2 a6 	mfdcdbtrl r4
+ 3d0:	7c 9d e2 a6 	mfdcdbtrh r4
+ 3d4:	7c 9d e2 a6 	mfdcdbtrh r4
+ 3d8:	7c 9f e2 a6 	mficdbtr r4
+ 3dc:	7c 9f e2 a6 	mficdbtr r4
+ 3e0:	7c 92 ea a6 	mfmmucr r4
+ 3e4:	7c 92 ea a6 	mfmmucr r4
+ 3e8:	7c 93 ea a6 	mfccr0  r4
+ 3ec:	7c 93 ea a6 	mfccr0  r4
+ 3f0:	7c 93 f2 a6 	mficdbdr r4
+ 3f4:	7c 93 f2 a6 	mficdbdr r4
+ 3f8:	7c 93 fa a6 	mfdbdr  r4
+ 3fc:	7c 93 fa a6 	mfdbdr  r4
+ 400:	7c 96 0b a6 	mtdecar r4
+ 404:	7c 96 0b a6 	mtdecar r4
diff --git a/gas/testsuite/gas/ppc/titan.s b/gas/testsuite/gas/ppc/ 
titan.s
new file mode 100644
index 0000000..7155a5a
--- /dev/null
+++ b/gas/testsuite/gas/ppc/titan.s
@@ -0,0 +1,261 @@
+# AppliedMicro Titan tests
+	.section ".text"
+start:
+	blr
+	tweqi		1, 0
+	macchw		2, 1, 0
+	macchw.		2, 1, 0
+	macchwo		2, 1, 0
+	macchwo.	2, 1, 0
+	macchws		2, 1, 0
+	macchws.	2, 1, 0
+	macchwso	2, 1, 0
+	macchwso.	2, 1, 0
+	macchwsu	2, 1, 0
+	macchwsu.	2, 1, 0
+	macchwsuo	2, 1, 0
+	macchwsuo.	2, 1, 0
+	macchwu		2, 1, 0
+	macchwu.	2, 1, 0
+	macchwuo	2, 1, 0
+	macchwuo.	2, 1, 0
+	machhw		2, 1, 0
+	machhw.		2, 1, 0
+	machhwo		2, 1, 0
+	machhwo.	2, 1, 0
+	machhws		2, 1, 0
+	machhws.	2, 1, 0
+	machhwso	2, 1, 0
+	machhwso.	2, 1, 0
+	machhwsu	2, 1, 0
+	machhwsu.	2, 1, 0
+	machhwsuo	2, 1, 0
+	machhwsuo.	2, 1, 0
+	machhwu		2, 1, 0
+	machhwu.	2, 1, 0
+	machhwuo	2, 1, 0
+	machhwuo.	2, 1, 0
+	maclhw		2, 1, 0
+	maclhw.		2, 1, 0
+	maclhwo		2, 1, 0
+	maclhwo.	2, 1, 0
+	maclhws		2, 1, 0
+	maclhws.	2, 1, 0
+	maclhwso	2, 1, 0
+	maclhwso.	2, 1, 0
+	maclhwsu	2, 1, 0
+	maclhwsu.	2, 1, 0
+	maclhwsuo	2, 1, 0
+	maclhwsuo.	2, 1, 0
+	maclhwu		2, 1, 0
+	maclhwu.	2, 1, 0
+	maclhwuo	2, 1, 0
+	maclhwuo.	2, 1, 0
+	nmacchw		2, 1, 0
+	nmacchw.	2, 1, 0
+	nmacchwo	2, 1, 0
+	nmacchwo.	2, 1, 0
+	nmacchws	2, 1, 0
+	nmacchws.	2, 1, 0
+	nmacchwso	2, 1, 0
+	nmacchwso.	2, 1, 0	
+	nmachhw		2, 1, 0
+	nmachhw.	2, 1, 0
+	nmachhwo	2, 1, 0
+	nmachhwo.	2, 1, 0
+	nmachhws	2, 1, 0
+	nmachhws.	2, 1, 0
+	nmachhwso	2, 1, 0
+	nmachhwso.	2, 1, 0
+	nmaclhw		2, 1, 0
+	nmaclhw.	2, 1, 0
+	nmaclhwo	2, 1, 0
+	nmaclhwo.	2, 1, 0
+	nmaclhws	2, 1, 0
+	nmaclhws.	2, 1, 0
+	nmaclhwso	2, 1, 0
+	nmaclhwso.	2, 1, 0
+	mulchw		2, 1, 0
+	mulchw.		2, 1, 0
+	mulchwu		2, 1, 0
+	mulchwu.	2, 1, 0
+	mulhhw		2, 1, 0
+	mulhhw.		2, 1, 0
+	mulhhwu		2, 1, 0
+	mulhhwu.	2, 1, 0
+	mullhw		2, 1, 0
+	mullhw.		2, 1, 0
+	mullhwu		2, 1, 0
+	mullhwu.	2, 1, 0
+	dlmzb		2, 1, 0
+	dlmzb.		2, 1, 0
+	dccci		2, 1
+	iccci		2, 1
+	dcblc		0, 2, 1
+	dcblc		2, 1
+	dcblc		1, 2, 1
+	dcbtls		0, 2, 1
+	dcbtls		2, 1
+	dcbtls		1, 2, 1
+	dcbtstls	0, 2, 1
+	dcbtstls	2, 1
+	dcbtstls	1, 2, 1
+	icblc		0, 2, 1
+	icblc		2, 1
+	icblc		1, 2, 1
+	icbtls		0, 2, 1
+	icbtls		2, 1
+	icbtls		1, 2, 1
+	dcread 		2, 1, 0
+	icread 		2, 1
+	mfpmr		2, 1
+	mfpmr		1, 2
+	mfspr		4, 0x001
+	mfxer		4
+	mfspr		4, 0x008
+	mflr		4
+	mfspr		4, 0x009
+	mfctr		4
+	mfspr		4, 0x016
+	mfdec		4
+	mfspr		4, 0x01a
+	mfsrr0		4
+	mfspr		4, 0x01b
+	mfsrr1		4
+	mfspr		4, 0x030
+	mfpid		4
+	mfspr		4, 0x03a
+	mfcsrr0		4
+	mfspr		4, 0x03b
+	mfcsrr1		4
+	mfspr		4, 0x03d
+	mfdear		4
+	mfspr		4, 0x03e
+	mfesr		4
+	mfspr		4, 0x03f
+	mfivpr		4
+	mfspr		4, 0x100
+	mfusprg0	4
+	mfspr		4, 0x104
+	mfsprg4		4
+	mfspr		4, 0x105
+	mfsprg5		4
+	mfspr		4, 0x106
+	mfsprg6		4
+	mfspr		4, 0x107
+	mfsprg7		4
+	mfspr		4, 0x10c
+	mftbl		4
+	mftb		4
+	mfspr		4, 0x10d
+	mftbu		4
+	mfspr		4, 0x110
+	mfsprg0		4
+	mfspr		4, 0x111
+	mfsprg1		4
+	mfspr		4, 0x112
+	mfsprg2		4
+	mfspr		4, 0x113
+	mfsprg3		4
+	mfspr		4, 0x11e
+	mfpir		4
+	mfspr		4, 0x11f
+	mfpvr		4
+	mfspr		4, 0x130
+	mfdbsr		4
+	mfspr		4, 0x134
+	mfdbcr0		4
+	mfspr		4, 0x135
+	mfdbcr1		4
+	mfspr		4, 0x136
+	mfdbcr2		4
+	mfspr		4, 0x138
+	mfiac1		4
+	mfspr		4, 0x139
+	mfiac2		4
+	mfspr		4, 0x13a
+	mfiac3		4
+	mfspr		4, 0x13b
+	mfiac4		4
+	mfspr		4, 0x13c
+	mfdac1		4
+	mfspr		4, 0x13d
+	mfdac2		4
+	mfspr		4, 0x13e
+	mfdvc1		4
+	mfspr		4, 0x13f
+	mfdvc2		4
+	mfspr		4, 0x150
+	mftsr		4
+	mfspr		4, 0x154
+	mftcr		4
+	mfspr		4, 0x190
+	mfivor0		4
+	mfspr		4, 0x191
+	mfivor1		4
+	mfspr		4, 0x192
+	mfivor2		4
+	mfspr		4, 0x193
+	mfivor3		4
+	mfspr		4, 0x194
+	mfivor4		4
+	mfspr		4, 0x195
+	mfivor5		4
+	mfspr		4, 0x196
+	mfivor6		4
+	mfspr		4, 0x197
+	mfivor7		4
+	mfspr		4, 0x198
+	mfivor8		4
+	mfspr		4, 0x199
+	mfivor9		4
+	mfspr		4, 0x19a
+	mfivor10	4
+	mfspr		4, 0x19b
+	mfivor11	4
+	mfspr		4, 0x19c
+	mfivor12	4
+	mfspr		4, 0x19d
+	mfivor13	4
+	mfspr		4, 0x19e
+	mfivor14	4
+	mfspr		4, 0x19f
+	mfivor15	4
+	mfspr		4, 0x213
+	mfivor35	4
+	mfspr		4, 0x23a
+	mfmcsrr0	4
+	mfspr		4, 0x23b
+	mfmcsrr1	4
+	mfspr		4, 0x23c
+	mfmcsr		4
+	mfspr		4, 0x370
+	mfivndx		4
+	mfspr		4, 0x371
+	mfdvndx		4
+	mfspr		4, 0x372
+	mfivlim		4
+	mfspr		4, 0x373
+	mfdvlim		4
+	mfspr		4, 0x374
+	mfclcsr		4
+	mfspr		4, 0x378
+	mfccr1		4
+	mfspr		4, 0x39b
+	mfrstcfg	4
+	mfspr		4, 0x39c
+	mfdcdbtrl	4
+	mfspr		4, 0x39d
+	mfdcdbtrh	4
+	mfspr		4, 0x39f
+	mficdbtr	4
+	mfspr		4, 0x3b2
+	mfmmucr		4
+	mfspr		4, 0x3b3
+	mfccr0		4
+	mfspr		4, 0x3d3
+	mficdbdr	4
+	mfspr		4, 0x3f3
+	mfdbdr		4
+	mtspr		0x036, 4
+	mtdecar		4
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 51120ff..5c1482a 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2009-11-19  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
+
+	* ppc.h (PPC_OPCODE_TITAN, PPC_OPCODE_MULHW): Define
+
2009-11-18  Paul Brook  <paul@codesourcery.com>

	* arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 1dc2f1d..718ceb2 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -168,11 +168,17 @@ extern const int powerpc_num_opcodes;
#define PPC_OPCODE_VSX		 0x80000000

/* Opcode is supported by A2.  */
-#define PPC_OPCODE_A2	 	0x100000000ULL
+#define PPC_OPCODE_A2	 	 0x100000000ULL

/* Opcode is supported by PowerPC 476 processor.  */
#define PPC_OPCODE_476		 0x200000000ULL

+/* Opcode is supported by AppliedMicro Titan core */
+#define PPC_OPCODE_TITAN         0x400000000ULL
+
+/* Opcode is supported by CPUs with PPC440-syle half-word multiply  
instructions */
+#define PPC_OPCODE_MULHW         0x800000000ULL
+
/* A macro to extract the major opcode from an instruction.  */
#define PPC_OP(i) (((i) >> 26) & 0x3f)

@@ -332,6 +338,10 @@ extern const unsigned int num_powerpc_operands;
/* This operand names a vector-scalar unit register.  The disassembler
    prints these with a leading 'vs'.  */
#define PPC_OPERAND_VSR (0x100000)
+
+/* This operand names performance counter registers. The disassembler
+   prints these with a leading 'pmctr'. */
+#define PPC_OPERAND_PMR (0x200000)

/* The POWER and PowerPC assemblers use a few macros.  We keep them
    with the operands table for simplicity.  The macro table is an
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 58e48c6..b026ec7 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,13 @@
+2009-11-19  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
+
+	* ppc-opc.c (powerpc_opcodes): Added support for the AppliedMicro
+	Titan core (APM83xxx). Refactored flags for PPC405/PPC440-style
+	halfword multiplication.
+	* ppc-opc.c (TITAN, MULHW): Define.
+	* ppc-dis.c (ppc_opts): Added AppliedMicro APM83xxx Titan target
+	(-mtitan). Changed PPC405 and PPC440 to use the (newly factored
+	out) halfword-multiplication opcode flag.
+
2009-11-19  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Add IsLockable to cmpxch16b.
@@ -7,7 +17,7 @@

	PR binutils/10924
	* arm-dis.c (print_insn_arm): Do not print an offset of zero when
-	decoding Immediaate Offset addressing.
+	decoding Immediate Offset addressing.

2009-11-18  Sebastian Pop  <sebastian.pop@amd.com>

diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index ac88f76..201e2af 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -54,13 +54,15 @@ struct ppc_mopt ppc_opts[] = {
		| PPC_OPCODE_32),
     0 },
   { "405",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_403
-		| PPC_OPCODE_405 | PPC_OPCODE_32),
+		| PPC_OPCODE_405 | PPC_OPCODE_32 | PPC_OPCODE_MULHW),
     0 },
   { "440",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32
-		| PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
+		| PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI
+		| PPC_OPCODE_MULHW),
     0 },
   { "464",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32
-		| PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
+		| PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI
+		| PPC_OPCODE_MULHW),
     0 },
   { "476",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL
		| PPC_OPCODE_440 | PPC_OPCODE_476 | PPC_OPCODE_POWER4
@@ -159,6 +161,10 @@ struct ppc_mopt ppc_opts[] = {
     0 },
   { "spe",     (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
     PPC_OPCODE_SPE },
+  { "titan",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32
+                | PPC_OPCODE_PMR | PPC_OPCODE_RFMCI | PPC_OPCODE_MULHW
+		| PPC_OPCODE_TITAN),
+    0 },
   { "vsx",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC),
     PPC_OPCODE_VSX },
};
@@ -449,6 +455,8 @@ print_insn_powerpc (bfd_vma memaddr,
	    (*info->fprintf_func) (info->stream, "v%ld", value);
	  else if ((operand->flags & PPC_OPERAND_VSR) != 0)
	    (*info->fprintf_func) (info->stream, "vs%ld", value);
+	  else if ((operand->flags & PPC_OPERAND_PMR) != 0)
+	    (*info->fprintf_func) (info->stream, "pmctr%ld", value);
	  else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
	    (*info->print_address_func) (memaddr + value, info);
	  else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 123436c..726fce3 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -440,10 +440,12 @@ const struct powerpc_operand powerpc_operands[] =
#define SISIGNOPT SI + 1
   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },

+#define PMR SISIGNOPT + 1
+  { 0x3ff, 11, insert_spr, extract_spr, PPC_OPERAND_PMR },
+
   /* The SPR field in an XFX form instruction.  This is flipped--the
      lower 5 bits are stored in the upper 5 and vice- versa.  */
-#define SPR SISIGNOPT + 1
-#define PMR SPR
+#define SPR PMR + 1
#define SPR_MASK (0x3ff << 11)
   { 0x3ff, 11, insert_spr, extract_spr, 0 },

@@ -1935,6 +1937,8 @@ extract_dm (unsigned long insn,
#define PPCRFMCI	PPC_OPCODE_RFMCI
#define E500MC  PPC_OPCODE_E500MC
#define PPCA2	PPC_OPCODE_A2
+#define TITAN   PPC_OPCODE_TITAN
+#define MULHW   PPC_OPCODE_MULHW

/* The opcode table.

@@ -2017,16 +2021,16 @@ const struct powerpc_opcode powerpc_opcodes[]  
= {
{"vmrghb",	VX (4,	12),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"psq_stx",	XW (4,	 7,0),	XW_MASK,     PPCPS,	PPCNONE,	 
{FRS,RA,RB,PSWM,PSQM}},
{"vpkuhum",	VX (4,	14),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"mulhhwu",	XRC(4,	 8,0),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"mulhhwu.",	XRC(4,	 8,1),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
+{"mulhhwu",	XRC(4,	 8,0),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
+{"mulhhwu.",	XRC(4,	 8,1),	X_MASK,      MULHW, 	PPCNONE,	{RT, RA, RB}},
{"ps_sum0",	A  (4,	10,0),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC,  
FRB}},
{"ps_sum0.",	A  (4,	10,1),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA,  
FRC, FRB}},
{"ps_sum1",	A  (4,	11,0),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC,  
FRB}},
{"ps_sum1.",	A  (4,	11,1),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA,  
FRC, FRB}},
{"ps_muls0",	A  (4,	12,0),	AFRB_MASK,   PPCPS,	PPCNONE,	{FRT, FRA,  
FRC}},
-{"machhwu",	XO (4,	12,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
+{"machhwu",	XO (4,	12,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
{"ps_muls0.",	A  (4,	12,1),	AFRB_MASK,   PPCPS,	PPCNONE,	{FRT, FRA,  
FRC}},
-{"machhwu.",	XO (4,	12,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
+{"machhwu.",	XO (4,	12,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
{"ps_muls1",	A  (4,	13,0),	AFRB_MASK,   PPCPS,	PPCNONE,	{FRT, FRA,  
FRC}},
{"ps_muls1.",	A  (4,	13,1),	AFRB_MASK,   PPCPS,	PPCNONE,	{FRT, FRA,  
FRC}},
{"ps_madds0",	A  (4,	14,0),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA,  
FRC, FRB}},
@@ -2081,13 +2085,13 @@ const struct powerpc_opcode powerpc_opcodes[]  
= {
{"psq_stux",	XW (4,	39,0),	XW_MASK,     PPCPS,	PPCNONE,	 
{FRS,RA,RB,PSWM,PSQM}},
{"vpkuwum",	VX (4,	78),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"ps_neg",	XRC(4,	40,0),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
-{"mulhhw",	XRC(4,	40,0),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
+{"mulhhw",	XRC(4,	40,0),	X_MASK,      MULHW, 	PPCNONE,	{RT, RA, RB}},
{"ps_neg.",	XRC(4,	40,1),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
-{"mulhhw.",	XRC(4,	40,1),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"machhw",	XO (4,	44,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"machhw.",	XO (4,	44,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"nmachhw",	XO (4,	46,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"nmachhw.",	XO (4,	46,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
+{"mulhhw.",	XRC(4,	40,1),	X_MASK,      MULHW, 	PPCNONE,	{RT, RA, RB}},
+{"machhw",	XO (4,	44,0,0),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
+{"machhw.",	XO (4,	44,0,1),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
+{"nmachhw",	XO (4,	46,0,0),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
+{"nmachhw.",	XO (4,	46,0,1),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA,  
RB}},
{"ps_cmpu1",	X  (4,	64), X_MASK|(3<<21), PPCPS,	PPCNONE,	{BF, FRA,  
FRB}},
{"vadduwm",	VX (4,	128),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vmaxuw",	VX (4,	130),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
@@ -2097,15 +2101,15 @@ const struct powerpc_opcode powerpc_opcodes[]  
= {
{"vpkuhus",	VX (4,	142),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"ps_mr",	XRC(4,	72,0),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
{"ps_mr.",	XRC(4,	72,1),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
-{"machhwsu",	XO (4,	76,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"machhwsu.",	XO (4,	76,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"machhwsu",	XO (4,	76,0,0),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA,  
RB}},
+{"machhwsu.",	XO (4,	76,0,1),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA,  
RB}},
{"ps_cmpo1",	X  (4,	96), X_MASK|(3<<21), PPCPS,	PPCNONE,	{BF, FRA,  
FRB}},
{"vcmpeqfp",	VXR(4, 198,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vpkuwus",	VX (4, 206),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"machhws",	XO (4, 108,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"machhws.",	XO (4, 108,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"nmachhws",	XO (4, 110,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"nmachhws.",	XO (4, 110,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"machhws",	XO (4, 108,0,0),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA,  
RB}},
+{"machhws.",	XO (4, 108,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"nmachhws",	XO (4, 110,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"nmachhws.",	XO (4, 110,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"vmaxsb",	VX (4, 258),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vslb",	VX (4, 260),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vmulosb",	VX (4, 264),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
@@ -2113,39 +2117,39 @@ const struct powerpc_opcode powerpc_opcodes[]  
= {
{"vmrglb",	VX (4, 268),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vpkshus",	VX (4, 270),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"ps_nabs",	XRC(4, 136,0),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
-{"mulchwu",	XRC(4, 136,0),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
+{"mulchwu",	XRC(4, 136,0),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
{"ps_nabs.",	XRC(4, 136,1),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
-{"mulchwu.",	XRC(4, 136,1),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"macchwu",	XO (4, 140,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"macchwu.",	XO (4, 140,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"mulchwu.",	XRC(4, 136,1),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchwu",	XO (4, 140,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchwu.",	XO (4, 140,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"vmaxsh",	VX (4, 322),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vslh",	VX (4, 324),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vmulosh",	VX (4, 328),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vrsqrtefp",	VX (4, 330),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
{"vmrglh",	VX (4, 332),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vpkswus",	VX (4, 334),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"mulchw",	XRC(4, 168,0),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"mulchw.",	XRC(4, 168,1),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"macchw",	XO (4, 172,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"macchw.",	XO (4, 172,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"nmacchw",	XO (4, 174,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"nmacchw.",	XO (4, 174,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"mulchw",	XRC(4, 168,0),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
+{"mulchw.",	XRC(4, 168,1),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchw",	XO (4, 172,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchw.",	XO (4, 172,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmacchw",	XO (4, 174,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmacchw.",	XO (4, 174,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"vaddcuw",	VX (4, 384),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vmaxsw",	VX (4, 386),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vslw",	VX (4, 388),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vexptefp",	VX (4, 394),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
{"vmrglw",	VX (4, 396),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vpkshss",	VX (4, 398),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"macchwsu",	XO (4, 204,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"macchwsu.",	XO (4, 204,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"macchwsu",	XO (4, 204,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"macchwsu.",	XO (4, 204,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"vsl",		VX (4, 452),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vcmpgefp",	VXR(4, 454,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vlogefp",	VX (4, 458),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
{"vpkswss",	VX (4, 462),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"macchws",	XO (4, 236,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"macchws.",	XO (4, 236,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"nmacchws",	XO (4, 238,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"nmacchws.",	XO (4, 238,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"macchws",	XO (4, 236,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchws.",	XO (4, 236,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"nmacchws",	XO (4, 238,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"nmacchws.",	XO (4, 238,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"evaddw",	VX (4, 512),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
{"vaddubs",	VX (4, 512),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"evaddiw",	VX (4, 514),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RB, UIMM}},
@@ -2322,17 +2326,17 @@ const struct powerpc_opcode powerpc_opcodes[]  
= {
{"evlhhossplatx",VX(4, 782),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
{"vpkpx",	VX (4, 782),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"evlhhossplat",VX (4, 783),	VX_MASK,     PPCSPE,	PPCNONE,	{RS,  
EVUIMM_2, RA}},
-{"mullhwu",	XRC(4, 392,0),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
+{"mullhwu",	XRC(4, 392,0),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
{"evlwhex",	VX (4, 784),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"mullhwu.",	XRC(4, 392,1),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
+{"mullhwu.",	XRC(4, 392,1),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
{"evlwhe",	VX (4, 785),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_4,  
RA}},
{"evlwhoux",	VX (4, 788),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
{"evlwhou",	VX (4, 789),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_4,  
RA}},
{"evlwhosx",	VX (4, 790),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
{"evlwhos",	VX (4, 791),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_4,  
RA}},
-{"maclhwu",	XO (4, 396,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
+{"maclhwu",	XO (4, 396,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
{"evlwwsplatx",	VX (4, 792),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
-{"maclhwu.",	XO (4, 396,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"maclhwu.",	XO (4, 396,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"evlwwsplat",	VX (4, 793),	VX_MASK,     PPCSPE,	PPCNONE,	{RS,  
EVUIMM_4, RA}},
{"evlwhsplatx",	VX (4, 796),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
{"evlwhsplat",	VX (4, 797),	VX_MASK,     PPCSPE,	PPCNONE,	{RS,  
EVUIMM_4, RA}},
@@ -2358,27 +2362,27 @@ const struct powerpc_opcode powerpc_opcodes[]  
= {
{"vcfsx",	VX (4, 842),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB, UIMM}},
{"vspltish",	VX (4, 844),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, SIMM}},
{"vupkhpx",	VX (4, 846),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
-{"mullhw",	XRC(4, 424,0),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"mullhw.",	XRC(4, 424,1),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"maclhw",	XO (4, 428,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"maclhw.",	XO (4, 428,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"nmaclhw",	XO (4, 430,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"nmaclhw.",	XO (4, 430,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"mullhw",	XRC(4, 424,0),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
+{"mullhw.",	XRC(4, 424,1),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
+{"maclhw",	XO (4, 428,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"maclhw.",	XO (4, 428,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmaclhw",	XO (4, 430,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmaclhw.",	XO (4, 430,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"vaddsws",	VX (4, 896),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vminsw",	VX (4, 898),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vsraw",	VX (4, 900),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vcmpgtsw",	VXR(4, 902,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vctuxs",	VX (4, 906),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB, UIMM}},
{"vspltisw",	VX (4, 908),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, SIMM}},
-{"maclhwsu",	XO (4, 460,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"maclhwsu.",	XO (4, 460,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"maclhwsu",	XO (4, 460,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"maclhwsu.",	XO (4, 460,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"vcmpbfp",	VXR(4, 966,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vctsxs",	VX (4, 970),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB, UIMM}},
{"vupklpx",	VX (4, 974),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
-{"maclhws",	XO (4, 492,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"maclhws.",	XO (4, 492,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"nmaclhws",	XO (4, 494,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"nmaclhws.",	XO (4, 494,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"maclhws",	XO (4, 492,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"maclhws.",	XO (4, 492,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"nmaclhws",	XO (4, 494,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"nmaclhws.",	XO (4, 494,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"vsububm",	VX (4,1024),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vavgub",	VX (4,1026),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"evmhessf",	VX (4,1027),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2395,8 +2399,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"vslo",	VX (4,1036),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"evmhosmi",	VX (4,1037),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
{"evmhosmf",	VX (4,1039),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"machhwuo",	XO (4,	12,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"machhwuo.",	XO (4,	12,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"machhwuo",	XO (4,	12,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"machhwuo.",	XO (4,	12,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"ps_merge00",	XOPS(4,528,0),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA,  
FRB}},
{"ps_merge00.",	XOPS(4,528,1),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA,  
FRB}},
{"evmhessfa",	VX (4,1059),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2421,13 +2425,13 @@ const struct powerpc_opcode powerpc_opcodes[]  
= {
{"evmwhsmi",	VX (4,1101),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
{"evmwhsmf",	VX (4,1103),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
{"evmwssf",	VX (4,1107),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"machhwo",	XO (4,	44,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
+{"machhwo",	XO (4,	44,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
{"evmwumi",	VX (4,1112),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"machhwo.",	XO (4,	44,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
+{"machhwo.",	XO (4,	44,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
{"evmwsmi",	VX (4,1113),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
{"evmwsmf",	VX (4,1115),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"nmachhwo",	XO (4,	46,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"nmachhwo.",	XO (4,	46,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"nmachhwo",	XO (4,	46,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmachhwo.",	XO (4,	46,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"ps_merge01",	XOPS(4,560,0),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA,  
FRB}},
{"ps_merge01.",	XOPS(4,560,1),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA,  
FRB}},
{"evmwhssfa",	VX (4,1127),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2445,8 +2449,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"vcmpequw.",	VXR(4, 134,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA,  
VB}},
{"udi2fcm.",	APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476,		{URT,  
URA, URB}},
{"udi2fcm",	APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476,		{URT,  
URA, URB}},
-{"machhwsuo",	XO (4,	76,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"machhwsuo.",	XO (4,	76,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"machhwsuo",	XO (4,	76,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"machhwsuo.",	XO (4,	76,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"ps_merge10",	XOPS(4,592,0),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA,  
FRB}},
{"ps_merge10.",	XOPS(4,592,1),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA,  
FRB}},
{"evaddusiaaw",	VX (4,1216),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
@@ -2464,10 +2468,10 @@ const struct powerpc_opcode powerpc_opcodes[]  
= {
{"evaddsmiaaw",	VX (4,1225),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
{"evsubfumiaaw",VX (4,1226),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
{"evsubfsmiaaw",VX (4,1227),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
-{"machhwso",	XO (4, 108,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"machhwso.",	XO (4, 108,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"nmachhwso",	XO (4, 110,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"nmachhwso.",	XO (4, 110,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"machhwso",	XO (4, 108,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"machhwso.",	XO (4, 108,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"nmachhwso",	XO (4, 110,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"nmachhwso.",	XO (4, 110,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"ps_merge11",	XOPS(4,624,0),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA,  
FRB}},
{"ps_merge11.",	XOPS(4,624,1),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA,  
FRB}},
{"evmheusiaaw",	VX (4,1280),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
@@ -2486,8 +2490,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"evmhoumiaaw",	VX (4,1292),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
{"evmhosmiaaw",	VX (4,1293),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
{"evmhosmfaaw",	VX (4,1295),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
-{"macchwuo",	XO (4, 140,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"macchwuo.",	XO (4, 140,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"macchwuo",	XO (4, 140,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"macchwuo.",	XO (4, 140,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"evmhegumiaa",	VX (4,1320),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
{"evmhegsmiaa",	VX (4,1321),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
{"evmhegsmfaa",	VX (4,1323),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
@@ -2502,13 +2506,13 @@ const struct powerpc_opcode powerpc_opcodes[]  
= {
{"evmwlumiaaw",	VX (4,1352),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
{"evmwlsmiaaw",	VX (4,1353),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
{"evmwssfaa",	VX (4,1363),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"macchwo",	XO (4, 172,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
+{"macchwo",	XO (4, 172,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
{"evmwumiaa",	VX (4,1368),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"macchwo.",	XO (4, 172,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"macchwo.",	XO (4, 172,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"evmwsmiaa",	VX (4,1369),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
{"evmwsmfaa",	VX (4,1371),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"nmacchwo",	XO (4, 174,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"nmacchwo.",	XO (4, 174,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"nmacchwo",	XO (4, 174,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"nmacchwo.",	XO (4, 174,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"evmheusianw",	VX (4,1408),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
{"vsubcuw",	VX (4,1408),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"evmhessianw",	VX (4,1409),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
@@ -2525,8 +2529,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"evmhoumianw",	VX (4,1420),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
{"evmhosmianw",	VX (4,1421),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
{"evmhosmfanw",	VX (4,1423),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
-{"macchwsuo",	XO (4, 204,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"macchwsuo.",	XO (4, 204,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"macchwsuo",	XO (4, 204,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"macchwsuo.",	XO (4, 204,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"evmhegumian",	VX (4,1448),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
{"evmhegsmian",	VX (4,1449),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
{"evmhegsmfan",	VX (4,1451),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
@@ -2541,13 +2545,13 @@ const struct powerpc_opcode powerpc_opcodes[]  
= {
{"evmwlumianw",	VX (4,1480),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
{"evmwlsmianw",	VX (4,1481),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA,  
RB}},
{"evmwssfan",	VX (4,1491),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"macchwso",	XO (4, 236,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"macchwso",	XO (4, 236,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"evmwumian",	VX (4,1496),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"macchwso.",	XO (4, 236,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"macchwso.",	XO (4, 236,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"evmwsmian",	VX (4,1497),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
{"evmwsmfan",	VX (4,1499),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"nmacchwso",	XO (4, 238,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"nmacchwso.",	XO (4, 238,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"nmacchwso",	XO (4, 238,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"nmacchwso.",	XO (4, 238,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"vsububs",	VX (4,1536),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"mfvscr",	VX (4,1540),	VX_MASK,     PPCVEC,	PPCNONE,	{VD}},
{"vcmpgtub.",	VXR(4, 518,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA,  
VB}},
@@ -2573,30 +2577,30 @@ const struct powerpc_opcode powerpc_opcodes[]  
= {
{"udi12fcm.",	APU(4, 899,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA,  
URB}},
{"udi12fcm",	APU(4, 899,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA,  
URB}},
{"vsum4sbs",	VX (4,1800),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"maclhwuo",	XO (4, 396,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"maclhwuo.",	XO (4, 396,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"maclhwuo",	XO (4, 396,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"maclhwuo.",	XO (4, 396,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"vsubshs",	VX (4,1856),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vcmpgtsh.",	VXR(4, 838,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA,  
VB}},
{"udi13fcm.",	APU(4, 931,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA,  
URB}},
{"udi13fcm",	APU(4, 931,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA,  
URB}},
-{"maclhwo",	XO (4, 428,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA,  
RB}},
-{"maclhwo.",	XO (4, 428,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"nmaclhwo",	XO (4, 430,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"nmaclhwo.",	XO (4, 430,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"maclhwo",	XO (4, 428,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"maclhwo.",	XO (4, 428,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"nmaclhwo",	XO (4, 430,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"nmaclhwo.",	XO (4, 430,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"vsubsws",	VX (4,1920),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"vcmpgtsw.",	VXR(4, 902,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA,  
VB}},
{"udi14fcm.",	APU(4, 963,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA,  
URB}},
{"udi14fcm",	APU(4, 963,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA,  
URB}},
{"vsumsws",	VX (4,1928),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"maclhwsuo",	XO (4, 460,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"maclhwsuo.",	XO (4, 460,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"maclhwsuo",	XO (4, 460,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"maclhwsuo.",	XO (4, 460,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"vcmpbfp.",	VXR(4, 966,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
{"udi15fcm.",	APU(4, 995,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA,  
URB}},
{"udi15fcm",	APU(4, 995,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA,  
URB}},
-{"maclhwso",	XO (4, 492,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"maclhwso.",	XO (4, 492,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"nmaclhwso",	XO (4, 494,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
-{"nmaclhwso.",	XO (4, 494,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT,  
RA, RB}},
+{"maclhwso",	XO (4, 492,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"maclhwso.",	XO (4, 492,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"nmaclhwso",	XO (4, 494,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
+{"nmaclhwso.",	XO (4, 494,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA,  
RB}},
{"dcbz_l",	X  (4,1014),	XRT_MASK,    PPCPS,	PPCNONE,	{RA, RB}},

{"mulli",	OP(7),		OP_MASK,     PPCCOM,	PPCNONE,	{RT, RA, SI}},
@@ -3532,7 +3536,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {

{"iseleq",	X(31,79),	X_MASK,      PPCISEL,	PPCNONE,	{RT, RA, RB}},

-{"isel",	XISEL(31,15),	XISEL_MASK,  PPCISEL,	PPCNONE,	{RT, RA, RB,  
CRB}},
+{"isel",	XISEL(31,15),	XISEL_MASK,  PPCISEL|TITAN,	PPCNONE,	{RT, RA,  
RB, CRB}},

{"subf",	XO(31,40,0,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
{"sub",		XO(31,40,0,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RB, RA}},
@@ -3585,8 +3589,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mulhw",	XO(31,75,0,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
{"mulhw.",	XO(31,75,0,1),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},

-{"dlmzb",	XRC(31,78,0),	X_MASK,  PPC403|PPC440,	PPCNONE,	{RA, RS, RB}},
-{"dlmzb.",	XRC(31,78,1),	X_MASK,  PPC403|PPC440,	PPCNONE,	{RA, RS,  
RB}},
+{"dlmzb",	XRC(31,78,0),	X_MASK,  PPC403|PPC440|TITAN,	PPCNONE,	{RA,  
RS, RB}},
+{"dlmzb.",	XRC(31,78,1),	X_MASK,  PPC403|PPC440|TITAN,	PPCNONE,	{RA,  
RS, RB}},

{"mtsrd",	X(31,82),  XRB_MASK|(1<<20), PPC64,	PPCNONE,	{SR, RS}},

@@ -3629,7 +3633,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {

{"wrtee",	X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE,  
{RS}},

-{"dcbtstls",	X(31,134),	X_MASK, PPCCHLK|PPC476,	PPCNONE,	{CT, RA, RB}},
+{"dcbtstls",	X(31,134),	X_MASK, PPCCHLK|PPC476|TITAN,	PPCNONE,	{CT,  
RA, RB}},

{"stvebx",	X(31,135),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
{"stbfcmx",	APU(31,135,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA,  
RB}},
@@ -3676,7 +3680,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {

{"wrteei",	X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE,	{E}},

-{"dcbtls",	X(31,166),	X_MASK, PPCCHLK|PPC476,	PPCNONE,	{CT, RA, RB}},
+{"dcbtls",	X(31,166),	X_MASK, PPCCHLK|PPC476|TITAN,	PPCNONE,	{CT, RA,  
RB}},

{"stvehx",	X(31,167),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
{"sthfcmx",	APU(31,167,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA,  
RB}},
@@ -3714,7 +3718,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {

{"msgsnd",	XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2, PPCNONE,	{RB}},

-{"mtsr",	X(31,210), XRB_MASK|(1<<20), COM32,	PPCNONE,	{SR, RS}},
+{"mtsr",	X(31,210), XRB_MASK|(1<<20), COM32,	TITAN,  	{SR, RS}},

{"eratwe",	X(31,211),	X_MASK,	     PPCA2,	PPCNONE,	{RS, RA, WS}},

@@ -3732,7 +3736,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {

{"stbepx",	X(31,223),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{RS, RA, RB}},

-{"icblc",	X(31,230),	X_MASK, PPCCHLK|PPC476,	PPCNONE,	{CT, RA, RB}},
+{"icblc",	X(31,230),	X_MASK, PPCCHLK|PPC476|TITAN,	PPCNONE,	{CT, RA,  
RB}},

{"stvx",	X(31,231),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
{"stqfcmx",	APU(31,231,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA,  
RB}},
@@ -3757,7 +3761,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {

{"icblce",	X(31,238),	X_MASK,      PPCCHLK,	E500MC|PPCA2,	{CT, RA, RB}},
{"msgclr",	XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2, PPCNONE,	{RB}},
-{"mtsrin",	X(31,242),	XRA_MASK,    PPC32,	PPCNONE,	{RS, RB}},
+{"mtsrin",	X(31,242),	XRA_MASK,    PPC32,	TITAN,  	{RS, RB}},
{"mtsri",	X(31,242),	XRA_MASK,    POWER32,	PPCNONE,	{RS, RB}},

{"dcbtstt",	XRT(31,246,0x10), XRT_MASK,  POWER7,	PPCNONE,	{RA, RB}},
@@ -3773,7 +3777,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {

{"dcbtstep",	XRT(31,255,0),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{RT, RA,  
RB}},

-{"mfdcrx",	X(31,259),	X_MASK, BOOKE|PPCA2|PPC476, PPCNONE,	{RS, RA}},
+{"mfdcrx",	X(31,259),	X_MASK, BOOKE|PPCA2|PPC476, TITAN,	{RS, RA}},
{"mfdcrx.",	XRC(31,259,1),	X_MASK,      PPCA2,	PPCNONE,	{RS, RA}},

{"icbt",	X(31,262),	XRT_MASK,    PPC403,	PPCNONE,	{RA, RB}},
@@ -3791,7 +3795,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {

{"tlbiel",	X(31,274),	XRTLRA_MASK, POWER4,	PPC476,		{RB, L}},

-{"mfapidi",	X(31,275),	X_MASK,      BOOKE,	PPCNONE,	{RT, RA}},
+{"mfapidi",	X(31,275),	X_MASK,      BOOKE,	TITAN,  	{RT, RA}},

{"lscbx",	XRC(31,277,0),	X_MASK,      M601,	PPCNONE,	{RT, RA, RB}},
{"lscbx.",	XRC(31,277,1),	X_MASK,      M601,	PPCNONE,	{RT, RA, RB}},
@@ -3811,10 +3815,10 @@ const struct powerpc_opcode powerpc_opcodes[]  
= {

{"mfdcrux",	X(31,291),	X_MASK,      PPC464,	PPCNONE,	{RS, RA}},

-{"tlbie",	X(31,306),	XRTLRA_MASK, PPC,	PPCNONE,	{RB, L}},
+{"tlbie",	X(31,306),	XRTLRA_MASK, PPC,	TITAN,  	{RB, L}},
{"tlbi",	X(31,306),	XRT_MASK,    POWER,	PPCNONE,	{RA0, RB}},

-{"eciwx",	X(31,310),	X_MASK,      PPC,	PPCNONE,	{RT, RA, RB}},
+{"eciwx",	X(31,310),	X_MASK,      PPC,	TITAN,  	{RT, RA, RB}},

{"lhzux",	X(31,311),	X_MASK,      COM,	PPCNONE,	{RT, RAL, RB}},

@@ -3859,10 +3863,10 @@ const struct powerpc_opcode powerpc_opcodes[]  
= {
{"mfdmasa3",	XSPR(31,323,219), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
{"mfdmacc3",	XSPR(31,323,220), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
{"mfdmasr",	XSPR(31,323,224), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
-{"mfdcr",	X(31,323),	X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RT,  
SPR}},
+{"mfdcr",	X(31,323),	X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {RT,  
SPR}},
{"mfdcr.",	XRC(31,323,1),	X_MASK,      PPCA2,	PPCNONE,	{RT, SPR}},

-{"dcread",	X(31,326),	X_MASK,      PPC476,	PPCNONE,	{RT, RA, RB}},
+{"dcread",	X(31,326),	X_MASK,  PPC476|TITAN,	PPCNONE,	{RT, RA, RB}},

{"div",		XO(31,331,0,0),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
{"div.",	XO(31,331,0,1),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
@@ -3873,17 +3877,17 @@ const struct powerpc_opcode powerpc_opcodes[]  
= {

{"mfmq",	XSPR(31,339,  0), XSPR_MASK, M601,	PPCNONE,	{RT}},
{"mfxer",	XSPR(31,339,  1), XSPR_MASK, COM,	PPCNONE,	{RT}},
-{"mfrtcu",	XSPR(31,339,  4), XSPR_MASK, COM,	PPCNONE,	{RT}},
-{"mfrtcl",	XSPR(31,339,  5), XSPR_MASK, COM,	PPCNONE,	{RT}},
+{"mfrtcu",	XSPR(31,339,  4), XSPR_MASK, COM,	TITAN,  	{RT}},
+{"mfrtcl",	XSPR(31,339,  5), XSPR_MASK, COM,	TITAN,  	{RT}},
{"mfdec",	XSPR(31,339,  6), XSPR_MASK, MFDEC1,	PPCNONE,	{RT}},
{"mflr",	XSPR(31,339,  8), XSPR_MASK, COM,	PPCNONE,	{RT}},
{"mfctr",	XSPR(31,339,  9), XSPR_MASK, COM,	PPCNONE,	{RT}},
{"mftid",	XSPR(31,339, 17), XSPR_MASK, POWER,	PPCNONE,	{RT}},
-{"mfdsisr",	XSPR(31,339, 18), XSPR_MASK, COM,	PPCNONE,	{RT}},
-{"mfdar",	XSPR(31,339, 19), XSPR_MASK, COM,	PPCNONE,	{RT}},
-{"mfdec",	XSPR(31,339, 22), XSPR_MASK, MFDEC2,	PPCNONE,	{RT}},
+{"mfdsisr",	XSPR(31,339, 18), XSPR_MASK, COM,	TITAN,  	{RT}},
+{"mfdar",	XSPR(31,339, 19), XSPR_MASK, COM,	TITAN,  	{RT}},
+{"mfdec",	XSPR(31,339, 22), XSPR_MASK, MFDEC2|TITAN,	PPCNONE,	{RT}},
{"mfsdr0",	XSPR(31,339, 24), XSPR_MASK, POWER,	PPCNONE,	{RT}},
-{"mfsdr1",	XSPR(31,339, 25), XSPR_MASK, COM,	PPCNONE,	{RT}},
+{"mfsdr1",	XSPR(31,339, 25), XSPR_MASK, COM,	TITAN,  	{RT}},
{"mfsrr0",	XSPR(31,339, 26), XSPR_MASK, COM,	PPCNONE,	{RT}},
{"mfsrr1",	XSPR(31,339, 27), XSPR_MASK, COM,	PPCNONE,	{RT}},
{"mfcfar",	XSPR(31,339, 28), XSPR_MASK, POWER6,	PPCNONE,	{RT}},
@@ -3924,7 +3928,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mfsprg2",	XSPR(31,339,274), XSPR_MASK, PPC,	PPCNONE,	{RT}},
{"mfsprg3",	XSPR(31,339,275), XSPR_MASK, PPC,	PPCNONE,	{RT}},
{"mfasr",	XSPR(31,339,280), XSPR_MASK, PPC64,	PPCNONE,	{RT}},
-{"mfear",	XSPR(31,339,282), XSPR_MASK, PPC,	PPCNONE,	{RT}},
+{"mfear",	XSPR(31,339,282), XSPR_MASK, PPC,	TITAN,  	{RT}},
{"mfpir",	XSPR(31,339,286), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
{"mfpvr",	XSPR(31,339,287), XSPR_MASK, PPC,	PPCNONE,	{RT}},
{"mfdbsr",	XSPR(31,339,304), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
@@ -3961,13 +3965,13 @@ const struct powerpc_opcode powerpc_opcodes[]  
= {
{"mfbbear",	XSPR(31,339,513), XSPR_MASK, PPCBRLK,	PPCNONE,	{RT}},
{"mfbbtar",	XSPR(31,339,514), XSPR_MASK, PPCBRLK,	PPCNONE,	{RT}},
{"mfivor32",	XSPR(31,339,528), XSPR_MASK, PPCSPE,	PPCNONE,	{RT}},
-{"mfibatu",	XSPR(31,339,528), XSPRBAT_MASK, PPC,	PPCNONE,	{RT,  
SPRBAT}},
+{"mfibatu",	XSPR(31,339,528), XSPRBAT_MASK, PPC,	TITAN,  	{RT,  
SPRBAT}},
{"mfivor33",	XSPR(31,339,529), XSPR_MASK, PPCSPE,	PPCNONE,	{RT}},
-{"mfibatl",	XSPR(31,339,529), XSPRBAT_MASK, PPC,	PPCNONE,	{RT,  
SPRBAT}},
+{"mfibatl",	XSPR(31,339,529), XSPRBAT_MASK, PPC,	TITAN,  	{RT,  
SPRBAT}},
{"mfivor34",	XSPR(31,339,530), XSPR_MASK, PPCSPE,	PPCNONE,	{RT}},
{"mfivor35",	XSPR(31,339,531), XSPR_MASK, PPCPMR,	PPCNONE,	{RT}},
-{"mfdbatu",	XSPR(31,339,536), XSPRBAT_MASK, PPC,	PPCNONE,	{RT,  
SPRBAT}},
-{"mfdbatl",	XSPR(31,339,537), XSPRBAT_MASK, PPC,	PPCNONE,	{RT,  
SPRBAT}},
+{"mfdbatu",	XSPR(31,339,536), XSPRBAT_MASK, PPC,	TITAN,  	{RT,  
SPRBAT}},
+{"mfdbatl",	XSPR(31,339,537), XSPRBAT_MASK, PPC,	TITAN,  	{RT,  
SPRBAT}},
{"mfic_cst",	XSPR(31,339,560), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
{"mfic_adr",	XSPR(31,339,561), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
{"mfic_dat",	XSPR(31,339,562), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
@@ -3977,7 +3981,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mfmcsrr0",	XSPR(31,339,570), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RT}},
{"mfmcsrr1",	XSPR(31,339,571), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RT}},
{"mfmcsr",	XSPR(31,339,572), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RT}},
-{"mfmcar",	XSPR(31,339,573), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RT}},
+{"mfmcar",	XSPR(31,339,573), XSPR_MASK, PPCRFMCI,	TITAN,  	{RT}},
{"mfdpdr",	XSPR(31,339,630), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
{"mfdpir",	XSPR(31,339,631), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
{"mfimmr",	XSPR(31,339,638), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
@@ -4000,6 +4004,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mfmd_dbcam",	XSPR(31,339,824), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
{"mfmd_dbram0",	XSPR(31,339,825), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
{"mfmd_dbram1",	XSPR(31,339,826), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
+{"mfivndx",	XSPR(31,339,880), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfdvndx",	XSPR(31,339,881), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfivlim",	XSPR(31,339,882), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfdvlim",	XSPR(31,339,883), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfclcsr",	XSPR(31,339,884), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfccr1",	XSPR(31,339,888), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfrstcfg",	XSPR(31,339,923), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfdcdbtrl",	XSPR(31,339,924), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfdcdbtrh",	XSPR(31,339,925), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mficdbtr",	XSPR(31,339,927), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
{"mfummcr0",	XSPR(31,339,936), XSPR_MASK, PPC750,	PPCNONE,	{RT}},
{"mfupmc1",	XSPR(31,339,937), XSPR_MASK, PPC750,	PPCNONE,	{RT}},
{"mfupmc2",	XSPR(31,339,938), XSPR_MASK, PPC750,	PPCNONE,	{RT}},
@@ -4009,7 +4023,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mfupmc4",	XSPR(31,339,942), XSPR_MASK, PPC750,	PPCNONE,	{RT}},
{"mfzpr",	XSPR(31,339,944), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
{"mfpid",	XSPR(31,339,945), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
-{"mfccr0",	XSPR(31,339,947), XSPR_MASK, PPC405,	PPCNONE,	{RT}},
+{"mfmmucr",	XSPR(31,339,946), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfccr0",	XSPR(31,339,947), XSPR_MASK, PPC405|TITAN,	PPCNONE,	{RT}},
{"mfiac3",	XSPR(31,339,948), XSPR_MASK, PPC405,	PPCNONE,	{RT}},
{"mfiac4",	XSPR(31,339,949), XSPR_MASK, PPC405,	PPCNONE,	{RT}},
{"mfdvc1",	XSPR(31,339,950), XSPR_MASK, PPC405,	PPCNONE,	{RT}},
@@ -4026,7 +4041,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mfdbcr1",	XSPR(31,339,957), XSPR_MASK, PPC405,	PPCNONE,	{RT}},
{"mfpmc3",	XSPR(31,339,957), XSPR_MASK, PPC750,	PPCNONE,	{RT}},
{"mfpmc4",	XSPR(31,339,958), XSPR_MASK, PPC750,	PPCNONE,	{RT}},
-{"mficdbdr",	XSPR(31,339,979), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
+{"mficdbdr",	XSPR(31,339,979), XSPR_MASK, PPC403|TITAN,	PPCNONE,	{RT}},
{"mfesr",	XSPR(31,339,980), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
{"mfdear",	XSPR(31,339,981), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
{"mfevpr",	XSPR(31,339,982), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
@@ -4040,6 +4055,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mfsrr3",	XSPR(31,339,991), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
{"mfdbsr",	XSPR(31,339,1008), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
{"mfdbcr0",	XSPR(31,339,1010), XSPR_MASK, PPC405,	PPCNONE,	{RT}},
+{"mfdbdr",	XSPR(31,339,1011), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
{"mfiac1",	XSPR(31,339,1012), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
{"mfiac2",	XSPR(31,339,1013), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
{"mfdac1",	XSPR(31,339,1014), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
@@ -4071,7 +4087,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"divs",	XO(31,363,0,0),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
{"divs.",	XO(31,363,0,1),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},

-{"tlbia",	X(31,370),	0xffffffff,  PPC,	PPCNONE,	{0}},
+{"tlbia",	X(31,370),	0xffffffff,  PPC,	TITAN,  	{0}},

{"mftbl",	XSPR(31,371,268), XSPR_MASK, CLASSIC,	PPCNONE,	{RT}},
{"mftbu",	XSPR(31,371,269), XSPR_MASK, CLASSIC,	PPCNONE,	{RT}},
@@ -4085,10 +4101,10 @@ const struct powerpc_opcode powerpc_opcodes[]  
= {

{"popcntw",	X(31,378),	XRB_MASK, POWER7|PPCA2,	PPCNONE,	{RA, RS}},

-{"mtdcrx",	X(31,387),	X_MASK, BOOKE|PPCA2|PPC476, PPCNONE,	{RA, RS}},
+{"mtdcrx",	X(31,387),	X_MASK, BOOKE|PPCA2|PPC476, TITAN,	{RA, RS}},
{"mtdcrx.",	XRC(31,387,1),	X_MASK,      PPCA2,	PPCNONE,	{RA, RS}},

-{"dcblc",	X(31,390),	X_MASK, PPCCHLK|PPC476,	PPCNONE,	{CT, RA, RB}},
+{"dcblc",	X(31,390),	X_MASK, PPCCHLK|PPC476|TITAN,	PPCNONE,	{CT, RA,  
RB}},
{"stdfcmx",	APU(31,391,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA,  
RB}},

{"divdeu",	XO(31,393,0,0),	XO_MASK,     POWER7,	PPCNONE,	{RT, RA, RB}},
@@ -4119,7 +4135,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {

{"slbie",	X(31,434),	XRTRA_MASK,  PPC64,	PPCNONE,	{RB}},

-{"ecowx",	X(31,438),	X_MASK,      PPC,	PPCNONE,	{RT, RA, RB}},
+{"ecowx",	X(31,438),	X_MASK,      PPC,	TITAN,  	{RT, RA, RB}},

{"sthux",	X(31,439),	X_MASK,      COM,	PPCNONE,	{RS, RAS, RB}},

@@ -4164,10 +4180,10 @@ const struct powerpc_opcode powerpc_opcodes[]  
= {
{"mtdmasa3",	XSPR(31,451,219), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
{"mtdmacc3",	XSPR(31,451,220), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
{"mtdmasr",	XSPR(31,451,224), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
-{"mtdcr",	X(31,451),     X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE,  
{SPR, RS}},
+{"mtdcr",	X(31,451),     X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN,  
{SPR, RS}},
{"mtdcr.",	XRC(31,451,1), X_MASK,       PPCA2,	PPCNONE,	{SPR, RS}},

-{"dccci",	X(31,454),     XRT_MASK, PPC403|PPC440,	PPCA2|PPC476,	{RA,  
RB}},
+{"dccci",	X(31,454),     XRT_MASK, PPC403|PPC440|TITAN,	PPCA2|PPC476,	 
{RA, RB}},
{"dci",		X(31,454),	XRARB_MASK, PPCA2|PPC476, PPCNONE,	{CT}},

{"divdu",	XO(31,457,0,0),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
@@ -4181,15 +4197,15 @@ const struct powerpc_opcode powerpc_opcodes[]  
= {
{"mtmq",	XSPR(31,467,  0), XSPR_MASK, M601,	PPCNONE,	{RS}},
{"mtxer",	XSPR(31,467,  1), XSPR_MASK, COM,	PPCNONE,	{RS}},
{"mtlr",	XSPR(31,467,  8), XSPR_MASK, COM,	PPCNONE,	{RS}},
-{"mtctr",	XSPR(31,467,  9), XSPR_MASK, COM,	PPCNONE,	{RS}},
+{"mtctr", 	XSPR(31,467,  9), XSPR_MASK, COM,	PPCNONE,	{RS}},
{"mttid",	XSPR(31,467, 17), XSPR_MASK, POWER,	PPCNONE,	{RS}},
-{"mtdsisr",	XSPR(31,467, 18), XSPR_MASK, COM,	PPCNONE,	{RS}},
-{"mtdar",	XSPR(31,467, 19), XSPR_MASK, COM,	PPCNONE,	{RS}},
-{"mtrtcu",	XSPR(31,467, 20), XSPR_MASK, COM,	PPCNONE,	{RS}},
-{"mtrtcl",	XSPR(31,467, 21), XSPR_MASK, COM,	PPCNONE,	{RS}},
+{"mtdsisr",	XSPR(31,467, 18), XSPR_MASK, COM,	TITAN,  	{RS}},
+{"mtdar",	XSPR(31,467, 19), XSPR_MASK, COM,	TITAN,  	{RS}},
+{"mtrtcu",	XSPR(31,467, 20), XSPR_MASK, COM,	TITAN,  	{RS}},
+{"mtrtcl",	XSPR(31,467, 21), XSPR_MASK, COM,	TITAN,  	{RS}},
{"mtdec",	XSPR(31,467, 22), XSPR_MASK, COM,	PPCNONE,	{RS}},
{"mtsdr0",	XSPR(31,467, 24), XSPR_MASK, POWER,	PPCNONE,	{RS}},
-{"mtsdr1",	XSPR(31,467, 25), XSPR_MASK, COM,	PPCNONE,	{RS}},
+{"mtsdr1",	XSPR(31,467, 25), XSPR_MASK, COM,	TITAN,  	{RS}},
{"mtsrr0",	XSPR(31,467, 26), XSPR_MASK, COM,	PPCNONE,	{RS}},
{"mtsrr1",	XSPR(31,467, 27), XSPR_MASK, COM,	PPCNONE,	{RS}},
{"mtcfar",	XSPR(31,467, 28), XSPR_MASK, POWER6,	PPCNONE,	{RS}},
@@ -4228,7 +4244,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mtsprg6",	XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, PPCNONE,	{RS}},
{"mtsprg7",	XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, PPCNONE,	{RS}},
{"mtasr",	XSPR(31,467,280), XSPR_MASK, PPC64,	PPCNONE,	{RS}},
-{"mtear",	XSPR(31,467,282), XSPR_MASK, PPC,	PPCNONE,	{RS}},
+{"mtear",	XSPR(31,467,282), XSPR_MASK, PPC,	TITAN,  	{RS}},
{"mttbl",	XSPR(31,467,284), XSPR_MASK, PPC,	PPCNONE,	{RS}},
{"mttbu",	XSPR(31,467,285), XSPR_MASK, PPC,	PPCNONE,	{RS}},
{"mtdbsr",	XSPR(31,467,304), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
@@ -4265,16 +4281,22 @@ const struct powerpc_opcode powerpc_opcodes[]  
= {
{"mtbbear",	XSPR(31,467,513), XSPR_MASK, PPCBRLK,	PPCNONE,	{RS}},
{"mtbbtar",	XSPR(31,467,514), XSPR_MASK, PPCBRLK,	PPCNONE,	{RS}},
{"mtivor32",	XSPR(31,467,528), XSPR_MASK, PPCSPE,	PPCNONE,	{RS}},
-{"mtibatu",	XSPR(31,467,528), XSPRBAT_MASK, PPC,	PPCNONE,	{SPRBAT,  
RS}},
+{"mtibatu",	XSPR(31,467,528), XSPRBAT_MASK, PPC,	TITAN,  	{SPRBAT,  
RS}},
{"mtivor33",	XSPR(31,467,529), XSPR_MASK, PPCSPE,	PPCNONE,	{RS}},
-{"mtibatl",	XSPR(31,467,529), XSPRBAT_MASK, PPC,	PPCNONE,	{SPRBAT,  
RS}},
+{"mtibatl",	XSPR(31,467,529), XSPRBAT_MASK, PPC,	TITAN,  	{SPRBAT,  
RS}},
{"mtivor34",	XSPR(31,467,530), XSPR_MASK, PPCSPE,	PPCNONE,	{RS}},
{"mtivor35",	XSPR(31,467,531), XSPR_MASK, PPCPMR,	PPCNONE,	{RS}},
-{"mtdbatu",	XSPR(31,467,536), XSPRBAT_MASK, PPC,	PPCNONE,	{SPRBAT,  
RS}},
-{"mtdbatl",	XSPR(31,467,537), XSPRBAT_MASK, PPC,	PPCNONE,	{SPRBAT,  
RS}},
+{"mtdbatu",	XSPR(31,467,536), XSPRBAT_MASK, PPC,	TITAN,  	{SPRBAT,  
RS}},
+{"mtdbatl",	XSPR(31,467,537), XSPRBAT_MASK, PPC,	TITAN,  	{SPRBAT,  
RS}},
{"mtmcsrr0",	XSPR(31,467,570), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RS}},
{"mtmcsrr1",	XSPR(31,467,571), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RS}},
{"mtmcsr",	XSPR(31,467,572), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RS}},
+{"mtivndx",	XSPR(31,467,880), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
+{"mtdvndx",	XSPR(31,467,881), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
+{"mtivlim",	XSPR(31,467,882), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
+{"mtdvlim",	XSPR(31,467,883), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
+{"mtclcsr",	XSPR(31,467,884), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
+{"mtccr1",	XSPR(31,467,888), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
{"mtummcr0",	XSPR(31,467,936), XSPR_MASK, PPC750,	PPCNONE,	{RS}},
{"mtupmc1",	XSPR(31,467,937), XSPR_MASK, PPC750,	PPCNONE,	{RS}},
{"mtupmc2",	XSPR(31,467,938), XSPR_MASK, PPC750,	PPCNONE,	{RS}},
@@ -4284,7 +4306,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mtupmc4",	XSPR(31,467,942), XSPR_MASK, PPC750,	PPCNONE,	{RS}},
{"mtzpr",	XSPR(31,467,944), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
{"mtpid",	XSPR(31,467,945), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
-{"mtccr0",	XSPR(31,467,947), XSPR_MASK, PPC405,	PPCNONE,	{RS}},
+{"mtrmmucr",	XSPR(31,467,946), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
+{"mtccr0",	XSPR(31,467,947), XSPR_MASK, PPC405|TITAN,	PPCNONE,	{RS}},
{"mtiac3",	XSPR(31,467,948), XSPR_MASK, PPC405,	PPCNONE,	{RS}},
{"mtiac4",	XSPR(31,467,949), XSPR_MASK, PPC405,	PPCNONE,	{RS}},
{"mtdvc1",	XSPR(31,467,950), XSPR_MASK, PPC405,	PPCNONE,	{RS}},
@@ -4314,6 +4337,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mtsrr2",	XSPR(31,467,990), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
{"mtsrr3",	XSPR(31,467,991), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
{"mtdbsr",	XSPR(31,467,1008), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
+{"mtdbdr",	XSPR(31,467,1011), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
{"mtdbcr0",	XSPR(31,467,1010), XSPR_MASK, PPC405,	PPCNONE,	{RS}},
{"mtiac1",	XSPR(31,467,1012), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
{"mtiac2",	XSPR(31,467,1013), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
@@ -4341,7 +4365,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {

{"dcread",	X(31,486),	X_MASK,  PPC403|PPC440,	PPCA2|PPC476,	{RT, RA,  
RB}},

-{"icbtls",	X(31,486),	X_MASK, PPCCHLK|PPC476,	PPCNONE,	{CT, RA, RB}},
+{"icbtls",	X(31,486),	X_MASK, PPCCHLK|PPC476|TITAN,	PPCNONE,	{CT, RA,  
RB}},

{"stvxl",	X(31,487),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},

@@ -4433,7 +4457,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {

{"lxsdx",	X(31,588),	XX1_MASK,    PPCVSX,	PPCNONE,	{XT6, RA, RB}},

-{"mfsr",	X(31,595), XRB_MASK|(1<<20), COM32,	PPCNONE,	{RT, SR}},
+{"mfsr",	X(31,595), XRB_MASK|(1<<20), COM32,	TITAN,  	{RT, SR}},

{"lswi",	X(31,597),	X_MASK,      PPCCOM,	PPCNONE,	{RT, RA0, NB}},
{"lsi",		X(31,597),	X_MASK,      PWRCOM,	PPCNONE,	{RT, RA0, NB}},
@@ -4480,7 +4504,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"addeo.",	XO(31,138,1,1),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
{"aeo.",	XO(31,138,1,1),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},

-{"mfsrin",	X(31,659),	XRA_MASK,    PPC32,	PPCNONE,	{RT, RB}},
+{"mfsrin",	X(31,659),	XRA_MASK,    PPC32,	TITAN,  	{RT, RB}},

{"stdbrx",	X(31,660),	X_MASK, CELL|POWER7|PPCA2, PPCNONE,	{RS, RA0,  
RB}},

@@ -4711,7 +4735,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"extsb",	XRC(31,954,0),	XRB_MASK,    PPC,	PPCNONE,	{RA, RS}},
{"extsb.",	XRC(31,954,1),	XRB_MASK,    PPC,	PPCNONE,	{RA, RS}},

-{"iccci",	X(31,966),     XRT_MASK, PPC403|PPC440,	PPC476,		{RA, RB}},
+{"iccci",	X(31,966),     XRT_MASK, PPC403|PPC440|TITAN,	PPC476,		{RA,  
RB}},
{"ici",		X(31,966),	XRARB_MASK,  PPCA2|PPC476, PPCNONE,	{CT}},

{"divduo",	XO(31,457,1,0),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
@@ -4738,7 +4762,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {

{"icbiep",	XRT(31,991,0),	XRT_MASK, E500MC|PPCA2,	PPCNONE,	{RA, RB}},

-{"icread",	X(31,998),     XRT_MASK, PPC403|PPC440|PPC476, PPCNONE,	 
{RA, RB}},
+{"icread",	X(31,998),     XRT_MASK, PPC403|PPC440|PPC476|TITAN,  
PPCNONE,	{RA, RB}},

{"nabso",	XO(31,488,1,0),	XORB_MASK,   M601,	PPCNONE,	{RT, RA}},
{"nabso.",	XO(31,488,1,1),	XORB_MASK,   M601,	PPCNONE,	{RT, RA}},
@@ -4749,7 +4773,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"divwo",	XO(31,491,1,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
{"divwo.",	XO(31,491,1,1),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},

-{"tlbli",	X(31,1010),	XRTRA_MASK,  PPC,	PPCNONE,	{RB}},
+{"tlbli",	X(31,1010),	XRTRA_MASK,  PPC,	TITAN,  	{RB}},

{"stdcix",	X(31,1013),	X_MASK,      POWER6,	PPCNONE,	{RS, RA0, RB}},

@@ -4854,8 +4878,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"fadds",	A(59,21,0),	AFRC_MASK,   PPC,	PPCNONE,	{FRT, FRA, FRB}},
{"fadds.",	A(59,21,1),	AFRC_MASK,   PPC,	PPCNONE,	{FRT, FRA, FRB}},

-{"fsqrts",	A(59,22,0),    AFRAFRC_MASK, PPC,	PPCNONE,	{FRT, FRB}},
-{"fsqrts.",	A(59,22,1),    AFRAFRC_MASK, PPC,	PPCNONE,	{FRT, FRB}},
+{"fsqrts",	A(59,22,0),    AFRAFRC_MASK, PPC,	TITAN,  	{FRT, FRB}},
+{"fsqrts.",	A(59,22,1),    AFRAFRC_MASK, PPC,	TITAN,  	{FRT, FRB}},

{"fres",	A(59,24,0),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
{"fres",	A(59,24,0),   AFRALFRC_MASK, PPC,	POWER7,		{FRT, FRB, A_L}},
@@ -5141,8 +5165,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"fadd.",	A(63,21,1),	AFRC_MASK,   PPCCOM,	PPCNONE,	{FRT, FRA, FRB}},
{"fa.",		A(63,21,1),	AFRC_MASK,   PWRCOM,	PPCNONE,	{FRT, FRA, FRB}},

-{"fsqrt",	A(63,22,0),    AFRAFRC_MASK, PPCPWR2,	PPCNONE,	{FRT, FRB}},
-{"fsqrt.",	A(63,22,1),    AFRAFRC_MASK, PPCPWR2,	PPCNONE,	{FRT, FRB}},
+{"fsqrt",	A(63,22,0),    AFRAFRC_MASK, PPCPWR2,	TITAN,  	{FRT, FRB}},
+{"fsqrt.",	A(63,22,1),    AFRAFRC_MASK, PPCPWR2,	TITAN,  	{FRT, FRB}},

{"fsel",	A(63,23,0),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
{"fsel.",	A(63,23,1),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: PATCH: Add AppliedMicro Titan (APM83xxx) support
  2009-11-19 23:46 PATCH: Add AppliedMicro Titan (APM83xxx) support Philipp Tomsich
@ 2009-11-20  4:12 ` Alan Modra
  2009-11-20 16:04   ` PATCH [version 2]: " Philipp Tomsich
  0 siblings, 1 reply; 4+ messages in thread
From: Alan Modra @ 2009-11-20  4:12 UTC (permalink / raw)
  To: Philipp Tomsich; +Cc: binutils

On Fri, Nov 20, 2009 at 12:44:37AM +0100, Philipp Tomsich wrote:
> This is a patch to add support for the AppliedMicro Titan core.

Your email client destroyed whitespace so the patch won't apply.
Also, please don't submit the ChangeLog entries as diffs (unless you
have CVS write privilege and can apply the patch yourself).

> +/* Opcode is supported by CPUs with PPC440-syle half-word multiply  
> instructions */
> +#define PPC_OPCODE_MULHW         0x800000000ULL

Don't invent unnecessary opcode flags.  You broke powerpc 476 with
this change.  It's fine to add a MULHW macro in ppc-opc.c which
combines existing flags to keep the opcode table formatted nicely.

> +	  else if ((operand->flags & PPC_OPERAND_PMR) != 0)
> +	    (*info->fprintf_func) (info->stream, "pmctr%ld", value);

E300 calls these registers pmr<n>, so your choice for titan might look
a little confusing to E300 programmers.  Also, the resulting
disassembly is that much harder to assemble.  I think I'd prefer you
not make this change.

Please resubmit the patch.

-- 
Alan Modra
Australia Development Lab, IBM

^ permalink raw reply	[flat|nested] 4+ messages in thread

* PATCH [version 2]: Add AppliedMicro Titan (APM83xxx) support
  2009-11-20  4:12 ` Alan Modra
@ 2009-11-20 16:04   ` Philipp Tomsich
  2010-02-08  2:00     ` Alan Modra
  0 siblings, 1 reply; 4+ messages in thread
From: Philipp Tomsich @ 2009-11-20 16:04 UTC (permalink / raw)
  To: binutils; +Cc: Alan Modra

[-- Attachment #1: Type: text/plain, Size: 516 bytes --]

Hi everyone,

The updated patch is attached to this mail (to avoid any further  
formatting issues with my mail client).
The following changes are contained in this revision of the patch:
* addition of a "-mtitan" option
* updates to the PPC opcode table to support the AppliedMicro Titan core
* an additional test case for GAS for the AppliedMicro Titan core

Thanks to Alan for the lightning-fast review and the feedback.

Best regards,
Phil.

--
Dr. Philipp Tomsich
Theobroma Systems Design und Consulting GmbH



[-- Attachment #2: titan.diff --]
[-- Type: application/octet-stream, Size: 68882 bytes --]

diff --git a/bfd/archures.c b/bfd/archures.c
index 8df2ce1..b38f7cf 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -230,6 +230,7 @@ DESCRIPTION
 .#define bfd_mach_ppc_7400	7400
 .#define bfd_mach_ppc_e500      500
 .#define bfd_mach_ppc_e500mc    5001
+.#define bfd_mach_ppc_titan     83
 .  bfd_arch_rs6000,    {* IBM RS/6000 *}
 .#define bfd_mach_rs6k		6000
 .#define bfd_mach_rs6k_rs1	6001
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 455ec56..a900c25 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1901,6 +1901,7 @@ enum bfd_architecture
 #define bfd_mach_ppc_7400      7400
 #define bfd_mach_ppc_e500      500
 #define bfd_mach_ppc_e500mc    5001
+#define bfd_mach_ppc_titan     83
   bfd_arch_rs6000,    /* IBM RS/6000 */
 #define bfd_mach_rs6k          6000
 #define bfd_mach_rs6k_rs1      6001
diff --git a/bfd/cpu-powerpc.c b/bfd/cpu-powerpc.c
index 0b511f3..c3db7a5 100644
--- a/bfd/cpu-powerpc.c
+++ b/bfd/cpu-powerpc.c
@@ -324,6 +324,21 @@ const bfd_arch_info_type bfd_powerpc_archs[] =
     FALSE, /* not the default */
     powerpc_compatible,
     bfd_default_scan,
+    &bfd_powerpc_archs[17]
+  },
+  {
+    32, /* 32 bits in a word */
+    32, /* 32 bits in an address */
+    8,  /* 8 bits in a byte */
+    bfd_arch_powerpc,
+    bfd_mach_ppc_titan,
+    "powerpc",
+    "powerpc:titan",
+    3,
+    FALSE, /* not the default */
+    powerpc_compatible,
+    bfd_default_scan,
     0
   }
+
 };
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 1d615e9..6a430ed 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1211,6 +1211,7 @@ PowerPC options:\n\
 -me500, -me500x2	generate code for Motorola e500 core complex\n\
 -me500mc,               generate code for Freescale e500mc core complex\n\
 -mspe			generate code for Motorola SPE instructions\n\
+-mtitan                 generate code for AppliedMicro Titan core complex\n\
 -mregnames		Allow symbolic names for registers\n\
 -mno-regnames		Do not allow symbolic names for registers\n"));
 #ifdef OBJ_ELF
@@ -1288,6 +1289,8 @@ ppc_mach (void)
     return bfd_mach_ppc64;
   else if (ppc_arch () == bfd_arch_rs6000)
     return bfd_mach_rs6k;
+  else if (ppc_cpu & PPC_OPCODE_TITAN)
+    return bfd_mach_ppc_titan;
   else
     return bfd_mach_ppc;
 }
diff --git a/gas/doc/c-ppc.texi b/gas/doc/c-ppc.texi
index cab461b..00b15cc 100644
--- a/gas/doc/c-ppc.texi
+++ b/gas/doc/c-ppc.texi
@@ -70,6 +70,9 @@ Generate code for Motorola e500 core complex.
 @item -mspe
 Generate code for Motorola SPE instructions.
 
+@item -mtitan
+Generate code for AppliedMicro Titan core complex.
+
 @item -mppc64bridge
 Generate code for PowerPC 64, including bridge insns.
 
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 0c8d852..3db0ade 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -50,5 +50,6 @@ if { [istarget powerpc*-*-*] } then {
 	run_dump_test "power7"
 	run_dump_test "vsx"
 	run_dump_test "476"
+	run_dump_test "titan"
     }
 }
diff --git a/gas/testsuite/gas/ppc/titan.d b/gas/testsuite/gas/ppc/titan.d
new file mode 100644
index 0000000..2b59928
--- /dev/null
+++ b/gas/testsuite/gas/ppc/titan.d
@@ -0,0 +1,267 @@
+#as: -mtitan
+#objdump: -dr -Mtitan
+#name: AppliedMicro Titan tests
+
+.*: +file format elf(32)?(64)?-powerpc.*
+
+Disassembly of section \.text:
+
+0+0000000 <start>:
+   0:	4e 80 00 20 	blr
+   4:	0c 81 00 00 	tweqi   r1,0
+   8:	10 41 01 58 	macchw  r2,r1,r0
+   c:	10 41 01 59 	macchw\. r2,r1,r0
+  10:	10 41 05 58 	macchwo r2,r1,r0
+  14:	10 41 05 59 	macchwo\. r2,r1,r0
+  18:	10 41 01 d8 	macchws r2,r1,r0
+  1c:	10 41 01 d9 	macchws\. r2,r1,r0
+  20:	10 41 05 d8 	macchwso r2,r1,r0
+  24:	10 41 05 d9 	macchwso\. r2,r1,r0
+  28:	10 41 01 98 	macchwsu r2,r1,r0
+  2c:	10 41 01 99 	macchwsu\. r2,r1,r0
+  30:	10 41 05 98 	macchwsuo r2,r1,r0
+  34:	10 41 05 99 	macchwsuo\. r2,r1,r0
+  38:	10 41 01 18 	macchwu r2,r1,r0
+  3c:	10 41 01 19 	macchwu\. r2,r1,r0
+  40:	10 41 05 18 	macchwuo r2,r1,r0
+  44:	10 41 05 19 	macchwuo\. r2,r1,r0
+  48:	10 41 00 58 	machhw  r2,r1,r0
+  4c:	10 41 00 59 	machhw\. r2,r1,r0
+  50:	10 41 04 58 	machhwo r2,r1,r0
+  54:	10 41 04 59 	machhwo\. r2,r1,r0
+  58:	10 41 00 d8 	machhws r2,r1,r0
+  5c:	10 41 00 d9 	machhws\. r2,r1,r0
+  60:	10 41 04 d8 	machhwso r2,r1,r0
+  64:	10 41 04 d9 	machhwso\. r2,r1,r0
+  68:	10 41 00 98 	machhwsu r2,r1,r0
+  6c:	10 41 00 99 	machhwsu\. r2,r1,r0
+  70:	10 41 04 98 	machhwsuo r2,r1,r0
+  74:	10 41 04 99 	machhwsuo\. r2,r1,r0
+  78:	10 41 00 18 	machhwu r2,r1,r0
+  7c:	10 41 00 19 	machhwu\. r2,r1,r0
+  80:	10 41 04 18 	machhwuo r2,r1,r0
+  84:	10 41 04 19 	machhwuo\. r2,r1,r0
+  88:	10 41 03 58 	maclhw  r2,r1,r0
+  8c:	10 41 03 59 	maclhw\. r2,r1,r0
+  90:	10 41 07 58 	maclhwo r2,r1,r0
+  94:	10 41 07 59 	maclhwo\. r2,r1,r0
+  98:	10 41 03 d8 	maclhws r2,r1,r0
+  9c:	10 41 03 d9 	maclhws\. r2,r1,r0
+  a0:	10 41 07 d8 	maclhwso r2,r1,r0
+  a4:	10 41 07 d9 	maclhwso\. r2,r1,r0
+  a8:	10 41 03 98 	maclhwsu r2,r1,r0
+  ac:	10 41 03 99 	maclhwsu\. r2,r1,r0
+  b0:	10 41 07 98 	maclhwsuo r2,r1,r0
+  b4:	10 41 07 99 	maclhwsuo\. r2,r1,r0
+  b8:	10 41 03 18 	maclhwu r2,r1,r0
+  bc:	10 41 03 19 	maclhwu\. r2,r1,r0
+  c0:	10 41 07 18 	maclhwuo r2,r1,r0
+  c4:	10 41 07 19 	maclhwuo\. r2,r1,r0
+  c8:	10 41 01 5c 	nmacchw r2,r1,r0
+  cc:	10 41 01 5d 	nmacchw\. r2,r1,r0
+  d0:	10 41 05 5c 	nmacchwo r2,r1,r0
+  d4:	10 41 05 5d 	nmacchwo\. r2,r1,r0
+  d8:	10 41 01 dc 	nmacchws r2,r1,r0
+  dc:	10 41 01 dd 	nmacchws\. r2,r1,r0
+  e0:	10 41 05 dc 	nmacchwso r2,r1,r0
+  e4:	10 41 05 dd 	nmacchwso\. r2,r1,r0
+  e8:	10 41 00 5c 	nmachhw r2,r1,r0
+  ec:	10 41 00 5d 	nmachhw\. r2,r1,r0
+  f0:	10 41 04 5c 	nmachhwo r2,r1,r0
+  f4:	10 41 04 5d 	nmachhwo\. r2,r1,r0
+  f8:	10 41 00 dc 	nmachhws r2,r1,r0
+  fc:	10 41 00 dd 	nmachhws\. r2,r1,r0
+ 100:	10 41 04 dc 	nmachhwso r2,r1,r0
+ 104:	10 41 04 dd 	nmachhwso\. r2,r1,r0
+ 108:	10 41 03 5c 	nmaclhw r2,r1,r0
+ 10c:	10 41 03 5d 	nmaclhw\. r2,r1,r0
+ 110:	10 41 07 5c 	nmaclhwo r2,r1,r0
+ 114:	10 41 07 5d 	nmaclhwo\. r2,r1,r0
+ 118:	10 41 03 dc 	nmaclhws r2,r1,r0
+ 11c:	10 41 03 dd 	nmaclhws\. r2,r1,r0
+ 120:	10 41 07 dc 	nmaclhwso r2,r1,r0
+ 124:	10 41 07 dd 	nmaclhwso\. r2,r1,r0
+ 128:	10 41 01 50 	mulchw  r2,r1,r0
+ 12c:	10 41 01 51 	mulchw\. r2,r1,r0
+ 130:	10 41 01 10 	mulchwu r2,r1,r0
+ 134:	10 41 01 11 	mulchwu\. r2,r1,r0
+ 138:	10 41 00 50 	mulhhw  r2,r1,r0
+ 13c:	10 41 00 51 	mulhhw\. r2,r1,r0
+ 140:	10 41 00 10 	mulhhwu r2,r1,r0
+ 144:	10 41 00 11 	mulhhwu\. r2,r1,r0
+ 148:	10 41 03 50 	mullhw  r2,r1,r0
+ 14c:	10 41 03 51 	mullhw\. r2,r1,r0
+ 150:	10 41 03 10 	mullhwu r2,r1,r0
+ 154:	10 41 03 11 	mullhwu\. r2,r1,r0
+ 158:	7c 22 00 9c 	dlmzb   r2,r1,r0
+ 15c:	7c 22 00 9d 	dlmzb\.  r2,r1,r0
+ 160:	7c 02 0b 8c 	dccci   r2,r1
+ 164:	7c 02 0f 8c 	iccci   r2,r1
+ 168:	7c 02 0b 0c 	dcblc   r2,r1
+ 16c:	7c 02 0b 0c 	dcblc   r2,r1
+ 170:	7c 22 0b 0c 	dcblc   1,r2,r1
+ 174:	7c 02 09 4c 	dcbtls  r2,r1
+ 178:	7c 02 09 4c 	dcbtls  r2,r1
+ 17c:	7c 22 09 4c 	dcbtls  1,r2,r1
+ 180:	7c 02 09 0c 	dcbtstls r2,r1
+ 184:	7c 02 09 0c 	dcbtstls r2,r1
+ 188:	7c 22 09 0c 	dcbtstls 1,r2,r1
+ 18c:	7c 02 09 cc 	icblc   r2,r1
+ 190:	7c 02 09 cc 	icblc   r2,r1
+ 194:	7c 22 09 cc 	icblc   1,r2,r1
+ 198:	7c 02 0b cc 	icbtls  r2,r1
+ 19c:	7c 02 0b cc 	icbtls  r2,r1
+ 1a0:	7c 22 0b cc 	icbtls  1,r2,r1
+ 1a4:	7c 41 02 8c 	dcread  r2,r1,r0
+ 1a8:	7c 02 0f cc 	icread  r2,r1
+ 1ac:	7c 41 02 9c 	mfpmr   r2,1
+ 1b0:	7c 22 02 9c 	mfpmr   r1,2
+ 1b4:	7c 81 02 a6 	mfxer   r4
+ 1b8:	7c 81 02 a6 	mfxer   r4
+ 1bc:	7c 88 02 a6 	mflr    r4
+ 1c0:	7c 88 02 a6 	mflr    r4
+ 1c4:	7c 89 02 a6 	mfctr   r4
+ 1c8:	7c 89 02 a6 	mfctr   r4
+ 1cc:	7c 96 02 a6 	mfdec   r4
+ 1d0:	7c 96 02 a6 	mfdec   r4
+ 1d4:	7c 9a 02 a6 	mfsrr0  r4
+ 1d8:	7c 9a 02 a6 	mfsrr0  r4
+ 1dc:	7c 9b 02 a6 	mfsrr1  r4
+ 1e0:	7c 9b 02 a6 	mfsrr1  r4
+ 1e4:	7c 90 0a a6 	mfpid   r4
+ 1e8:	7c 90 0a a6 	mfpid   r4
+ 1ec:	7c 9a 0a a6 	mfcsrr0 r4
+ 1f0:	7c 9a 0a a6 	mfcsrr0 r4
+ 1f4:	7c 9b 0a a6 	mfcsrr1 r4
+ 1f8:	7c 9b 0a a6 	mfcsrr1 r4
+ 1fc:	7c 9d 0a a6 	mfdear  r4
+ 200:	7c 9d 0a a6 	mfdear  r4
+ 204:	7c 9e 0a a6 	mfesr   r4
+ 208:	7c 9e 0a a6 	mfesr   r4
+ 20c:	7c 9f 0a a6 	mfivpr  r4
+ 210:	7c 9f 0a a6 	mfivpr  r4
+ 214:	7c 80 42 a6 	mfusprg0 r4
+ 218:	7c 80 42 a6 	mfusprg0 r4
+ 21c:	7c 84 42 a6 	mfsprg  r4,4
+ 220:	7c 84 42 a6 	mfsprg  r4,4
+ 224:	7c 85 42 a6 	mfsprg  r4,5
+ 228:	7c 85 42 a6 	mfsprg  r4,5
+ 22c:	7c 86 42 a6 	mfsprg  r4,6
+ 230:	7c 86 42 a6 	mfsprg  r4,6
+ 234:	7c 87 42 a6 	mfsprg  r4,7
+ 238:	7c 87 42 a6 	mfsprg  r4,7
+ 23c:	7c 8c 42 a6 	mftb    r4
+ 240:	7c 8c 42 a6 	mftb    r4
+ 244:	7c 8c 42 a6 	mftb    r4
+ 248:	7c 8d 42 a6 	mftbu   r4
+ 24c:	7c 8d 42 a6 	mftbu   r4
+ 250:	7c 90 42 a6 	mfsprg  r4,0
+ 254:	7c 90 42 a6 	mfsprg  r4,0
+ 258:	7c 91 42 a6 	mfsprg  r4,1
+ 25c:	7c 91 42 a6 	mfsprg  r4,1
+ 260:	7c 92 42 a6 	mfsprg  r4,2
+ 264:	7c 92 42 a6 	mfsprg  r4,2
+ 268:	7c 93 42 a6 	mfsprg  r4,3
+ 26c:	7c 93 42 a6 	mfsprg  r4,3
+ 270:	7c 9e 42 a6 	mfpir   r4
+ 274:	7c 9e 42 a6 	mfpir   r4
+ 278:	7c 9f 42 a6 	mfpvr   r4
+ 27c:	7c 9f 42 a6 	mfpvr   r4
+ 280:	7c 90 4a a6 	mfdbsr  r4
+ 284:	7c 90 4a a6 	mfdbsr  r4
+ 288:	7c 94 4a a6 	mfdbcr0 r4
+ 28c:	7c 94 4a a6 	mfdbcr0 r4
+ 290:	7c 95 4a a6 	mfdbcr1 r4
+ 294:	7c 95 4a a6 	mfdbcr1 r4
+ 298:	7c 96 4a a6 	mfdbcr2 r4
+ 29c:	7c 96 4a a6 	mfdbcr2 r4
+ 2a0:	7c 98 4a a6 	mfiac1  r4
+ 2a4:	7c 98 4a a6 	mfiac1  r4
+ 2a8:	7c 99 4a a6 	mfiac2  r4
+ 2ac:	7c 99 4a a6 	mfiac2  r4
+ 2b0:	7c 9a 4a a6 	mfiac3  r4
+ 2b4:	7c 9a 4a a6 	mfiac3  r4
+ 2b8:	7c 9b 4a a6 	mfiac4  r4
+ 2bc:	7c 9b 4a a6 	mfiac4  r4
+ 2c0:	7c 9c 4a a6 	mfdac1  r4
+ 2c4:	7c 9c 4a a6 	mfdac1  r4
+ 2c8:	7c 9d 4a a6 	mfdac2  r4
+ 2cc:	7c 9d 4a a6 	mfdac2  r4
+ 2d0:	7c 9e 4a a6 	mfdvc1  r4
+ 2d4:	7c 9e 4a a6 	mfdvc1  r4
+ 2d8:	7c 9f 4a a6 	mfdvc2  r4
+ 2dc:	7c 9f 4a a6 	mfdvc2  r4
+ 2e0:	7c 90 52 a6 	mftsr   r4
+ 2e4:	7c 90 52 a6 	mftsr   r4
+ 2e8:	7c 94 52 a6 	mftcr   r4
+ 2ec:	7c 94 52 a6 	mftcr   r4
+ 2f0:	7c 90 62 a6 	mfivor0 r4
+ 2f4:	7c 90 62 a6 	mfivor0 r4
+ 2f8:	7c 91 62 a6 	mfivor1 r4
+ 2fc:	7c 91 62 a6 	mfivor1 r4
+ 300:	7c 92 62 a6 	mfivor2 r4
+ 304:	7c 92 62 a6 	mfivor2 r4
+ 308:	7c 93 62 a6 	mfivor3 r4
+ 30c:	7c 93 62 a6 	mfivor3 r4
+ 310:	7c 94 62 a6 	mfivor4 r4
+ 314:	7c 94 62 a6 	mfivor4 r4
+ 318:	7c 95 62 a6 	mfivor5 r4
+ 31c:	7c 95 62 a6 	mfivor5 r4
+ 320:	7c 96 62 a6 	mfivor6 r4
+ 324:	7c 96 62 a6 	mfivor6 r4
+ 328:	7c 97 62 a6 	mfivor7 r4
+ 32c:	7c 97 62 a6 	mfivor7 r4
+ 330:	7c 98 62 a6 	mfivor8 r4
+ 334:	7c 98 62 a6 	mfivor8 r4
+ 338:	7c 99 62 a6 	mfivor9 r4
+ 33c:	7c 99 62 a6 	mfivor9 r4
+ 340:	7c 9a 62 a6 	mfivor10 r4
+ 344:	7c 9a 62 a6 	mfivor10 r4
+ 348:	7c 9b 62 a6 	mfivor11 r4
+ 34c:	7c 9b 62 a6 	mfivor11 r4
+ 350:	7c 9c 62 a6 	mfivor12 r4
+ 354:	7c 9c 62 a6 	mfivor12 r4
+ 358:	7c 9d 62 a6 	mfivor13 r4
+ 35c:	7c 9d 62 a6 	mfivor13 r4
+ 360:	7c 9e 62 a6 	mfivor14 r4
+ 364:	7c 9e 62 a6 	mfivor14 r4
+ 368:	7c 9f 62 a6 	mfivor15 r4
+ 36c:	7c 9f 62 a6 	mfivor15 r4
+ 370:	7c 93 82 a6 	mfivor35 r4
+ 374:	7c 93 82 a6 	mfivor35 r4
+ 378:	7c 9a 8a a6 	mfdc_dat r4
+ 37c:	7c 9a 8a a6 	mfdc_dat r4
+ 380:	7c 9b 8a a6 	mfmcsrr1 r4
+ 384:	7c 9b 8a a6 	mfmcsrr1 r4
+ 388:	7c 9c 8a a6 	mfmcsr  r4
+ 38c:	7c 9c 8a a6 	mfmcsr  r4
+ 390:	7c 90 da a6 	mfivndx r4
+ 394:	7c 90 da a6 	mfivndx r4
+ 398:	7c 91 da a6 	mfdvndx r4
+ 39c:	7c 91 da a6 	mfdvndx r4
+ 3a0:	7c 92 da a6 	mfivlim r4
+ 3a4:	7c 92 da a6 	mfivlim r4
+ 3a8:	7c 93 da a6 	mfdvlim r4
+ 3ac:	7c 93 da a6 	mfdvlim r4
+ 3b0:	7c 94 da a6 	mfclcsr r4
+ 3b4:	7c 94 da a6 	mfclcsr r4
+ 3b8:	7c 98 da a6 	mfccr1  r4
+ 3bc:	7c 98 da a6 	mfccr1  r4
+ 3c0:	7c 9b e2 a6 	mfrstcfg r4
+ 3c4:	7c 9b e2 a6 	mfrstcfg r4
+ 3c8:	7c 9c e2 a6 	mfdcdbtrl r4
+ 3cc:	7c 9c e2 a6 	mfdcdbtrl r4
+ 3d0:	7c 9d e2 a6 	mfdcdbtrh r4
+ 3d4:	7c 9d e2 a6 	mfdcdbtrh r4
+ 3d8:	7c 9f e2 a6 	mficdbtr r4
+ 3dc:	7c 9f e2 a6 	mficdbtr r4
+ 3e0:	7c 92 ea a6 	mfmmucr r4
+ 3e4:	7c 92 ea a6 	mfmmucr r4
+ 3e8:	7c 93 ea a6 	mfccr0  r4
+ 3ec:	7c 93 ea a6 	mfccr0  r4
+ 3f0:	7c 93 f2 a6 	mficdbdr r4
+ 3f4:	7c 93 f2 a6 	mficdbdr r4
+ 3f8:	7c 93 fa a6 	mfdbdr  r4
+ 3fc:	7c 93 fa a6 	mfdbdr  r4
+ 400:	7c 96 0b a6 	mtdecar r4
+ 404:	7c 96 0b a6 	mtdecar r4
diff --git a/gas/testsuite/gas/ppc/titan.s b/gas/testsuite/gas/ppc/titan.s
new file mode 100644
index 0000000..7155a5a
--- /dev/null
+++ b/gas/testsuite/gas/ppc/titan.s
@@ -0,0 +1,261 @@
+# AppliedMicro Titan tests 
+	.section ".text"
+start:
+	blr
+	tweqi		1, 0
+	macchw		2, 1, 0
+	macchw.		2, 1, 0
+	macchwo		2, 1, 0
+	macchwo.	2, 1, 0
+	macchws		2, 1, 0
+	macchws.	2, 1, 0
+	macchwso	2, 1, 0
+	macchwso.	2, 1, 0
+	macchwsu	2, 1, 0
+	macchwsu.	2, 1, 0
+	macchwsuo	2, 1, 0
+	macchwsuo.	2, 1, 0
+	macchwu		2, 1, 0
+	macchwu.	2, 1, 0
+	macchwuo	2, 1, 0
+	macchwuo.	2, 1, 0
+	machhw		2, 1, 0
+	machhw.		2, 1, 0
+	machhwo		2, 1, 0
+	machhwo.	2, 1, 0
+	machhws		2, 1, 0
+	machhws.	2, 1, 0
+	machhwso	2, 1, 0
+	machhwso.	2, 1, 0
+	machhwsu	2, 1, 0
+	machhwsu.	2, 1, 0
+	machhwsuo	2, 1, 0
+	machhwsuo.	2, 1, 0
+	machhwu		2, 1, 0
+	machhwu.	2, 1, 0
+	machhwuo	2, 1, 0
+	machhwuo.	2, 1, 0
+	maclhw		2, 1, 0
+	maclhw.		2, 1, 0
+	maclhwo		2, 1, 0
+	maclhwo.	2, 1, 0
+	maclhws		2, 1, 0
+	maclhws.	2, 1, 0
+	maclhwso	2, 1, 0
+	maclhwso.	2, 1, 0
+	maclhwsu	2, 1, 0
+	maclhwsu.	2, 1, 0
+	maclhwsuo	2, 1, 0
+	maclhwsuo.	2, 1, 0
+	maclhwu		2, 1, 0
+	maclhwu.	2, 1, 0
+	maclhwuo	2, 1, 0
+	maclhwuo.	2, 1, 0
+	nmacchw		2, 1, 0
+	nmacchw.	2, 1, 0
+	nmacchwo	2, 1, 0
+	nmacchwo.	2, 1, 0
+	nmacchws	2, 1, 0
+	nmacchws.	2, 1, 0
+	nmacchwso	2, 1, 0
+	nmacchwso.	2, 1, 0	
+	nmachhw		2, 1, 0
+	nmachhw.	2, 1, 0
+	nmachhwo	2, 1, 0
+	nmachhwo.	2, 1, 0
+	nmachhws	2, 1, 0
+	nmachhws.	2, 1, 0
+	nmachhwso	2, 1, 0
+	nmachhwso.	2, 1, 0
+	nmaclhw		2, 1, 0
+	nmaclhw.	2, 1, 0
+	nmaclhwo	2, 1, 0
+	nmaclhwo.	2, 1, 0
+	nmaclhws	2, 1, 0
+	nmaclhws.	2, 1, 0
+	nmaclhwso	2, 1, 0
+	nmaclhwso.	2, 1, 0
+	mulchw		2, 1, 0
+	mulchw.		2, 1, 0
+	mulchwu		2, 1, 0
+	mulchwu.	2, 1, 0
+	mulhhw		2, 1, 0
+	mulhhw.		2, 1, 0
+	mulhhwu		2, 1, 0
+	mulhhwu.	2, 1, 0
+	mullhw		2, 1, 0
+	mullhw.		2, 1, 0
+	mullhwu		2, 1, 0
+	mullhwu.	2, 1, 0
+	dlmzb		2, 1, 0
+	dlmzb.		2, 1, 0
+	dccci		2, 1
+	iccci		2, 1
+	dcblc		0, 2, 1
+	dcblc		2, 1
+	dcblc		1, 2, 1
+	dcbtls		0, 2, 1
+	dcbtls		2, 1
+	dcbtls		1, 2, 1
+	dcbtstls	0, 2, 1
+	dcbtstls	2, 1
+	dcbtstls	1, 2, 1
+	icblc		0, 2, 1
+	icblc		2, 1
+	icblc		1, 2, 1
+	icbtls		0, 2, 1
+	icbtls		2, 1
+	icbtls		1, 2, 1
+	dcread 		2, 1, 0
+	icread 		2, 1
+	mfpmr		2, 1
+	mfpmr		1, 2
+	mfspr		4, 0x001
+	mfxer		4
+	mfspr		4, 0x008
+	mflr		4
+	mfspr		4, 0x009
+	mfctr		4
+	mfspr		4, 0x016
+	mfdec		4
+	mfspr		4, 0x01a
+	mfsrr0		4
+	mfspr		4, 0x01b
+	mfsrr1		4
+	mfspr		4, 0x030
+	mfpid		4
+	mfspr		4, 0x03a
+	mfcsrr0		4
+	mfspr		4, 0x03b
+	mfcsrr1		4
+	mfspr		4, 0x03d
+	mfdear		4
+	mfspr		4, 0x03e
+	mfesr		4
+	mfspr		4, 0x03f
+	mfivpr		4
+	mfspr		4, 0x100
+	mfusprg0	4
+	mfspr		4, 0x104
+	mfsprg4		4
+	mfspr		4, 0x105
+	mfsprg5		4
+	mfspr		4, 0x106
+	mfsprg6		4
+	mfspr		4, 0x107
+	mfsprg7		4
+	mfspr		4, 0x10c
+	mftbl		4
+	mftb		4
+	mfspr		4, 0x10d
+	mftbu		4
+	mfspr		4, 0x110
+	mfsprg0		4
+	mfspr		4, 0x111
+	mfsprg1		4
+	mfspr		4, 0x112
+	mfsprg2		4
+	mfspr		4, 0x113
+	mfsprg3		4
+	mfspr		4, 0x11e
+	mfpir		4
+	mfspr		4, 0x11f
+	mfpvr		4
+	mfspr		4, 0x130
+	mfdbsr		4
+	mfspr		4, 0x134
+	mfdbcr0		4
+	mfspr		4, 0x135
+	mfdbcr1		4
+	mfspr		4, 0x136
+	mfdbcr2		4
+	mfspr		4, 0x138
+	mfiac1		4
+	mfspr		4, 0x139
+	mfiac2		4
+	mfspr		4, 0x13a
+	mfiac3		4
+	mfspr		4, 0x13b
+	mfiac4		4
+	mfspr		4, 0x13c
+	mfdac1		4
+	mfspr		4, 0x13d
+	mfdac2		4
+	mfspr		4, 0x13e
+	mfdvc1		4
+	mfspr		4, 0x13f
+	mfdvc2		4
+	mfspr		4, 0x150
+	mftsr		4
+	mfspr		4, 0x154
+	mftcr		4
+	mfspr		4, 0x190
+	mfivor0		4
+	mfspr		4, 0x191
+	mfivor1		4
+	mfspr		4, 0x192
+	mfivor2		4
+	mfspr		4, 0x193
+	mfivor3		4
+	mfspr		4, 0x194
+	mfivor4		4
+	mfspr		4, 0x195
+	mfivor5		4
+	mfspr		4, 0x196
+	mfivor6		4
+	mfspr		4, 0x197
+	mfivor7		4
+	mfspr		4, 0x198
+	mfivor8		4
+	mfspr		4, 0x199
+	mfivor9		4
+	mfspr		4, 0x19a
+	mfivor10	4
+	mfspr		4, 0x19b
+	mfivor11	4
+	mfspr		4, 0x19c
+	mfivor12	4
+	mfspr		4, 0x19d
+	mfivor13	4
+	mfspr		4, 0x19e
+	mfivor14	4
+	mfspr		4, 0x19f
+	mfivor15	4
+	mfspr		4, 0x213
+	mfivor35	4
+	mfspr		4, 0x23a
+	mfmcsrr0	4
+	mfspr		4, 0x23b
+	mfmcsrr1	4
+	mfspr		4, 0x23c
+	mfmcsr		4
+	mfspr		4, 0x370
+	mfivndx		4
+	mfspr		4, 0x371
+	mfdvndx		4
+	mfspr		4, 0x372
+	mfivlim		4
+	mfspr		4, 0x373
+	mfdvlim		4
+	mfspr		4, 0x374
+	mfclcsr		4
+	mfspr		4, 0x378
+	mfccr1		4
+	mfspr		4, 0x39b
+	mfrstcfg	4
+	mfspr		4, 0x39c
+	mfdcdbtrl	4
+	mfspr		4, 0x39d
+	mfdcdbtrh	4
+	mfspr		4, 0x39f
+	mficdbtr	4
+	mfspr		4, 0x3b2
+	mfmmucr		4
+	mfspr		4, 0x3b3
+	mfccr0		4
+	mfspr		4, 0x3d3
+	mficdbdr	4
+	mfspr		4, 0x3f3
+	mfdbdr		4
+	mtspr		0x036, 4
+	mtdecar		4
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 1dc2f1d..ea97b3a 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -168,11 +168,14 @@ extern const int powerpc_num_opcodes;
 #define PPC_OPCODE_VSX		 0x80000000
 
 /* Opcode is supported by A2.  */
-#define PPC_OPCODE_A2	 	0x100000000ULL
+#define PPC_OPCODE_A2	 	 0x100000000ULL
 
 /* Opcode is supported by PowerPC 476 processor.  */
 #define PPC_OPCODE_476		 0x200000000ULL
 
+/* Opcode is supported by AppliedMicro Titan core */
+#define PPC_OPCODE_TITAN         0x400000000ULL
+
 /* A macro to extract the major opcode from an instruction.  */
 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 \f
@@ -332,6 +335,7 @@ extern const unsigned int num_powerpc_operands;
 /* This operand names a vector-scalar unit register.  The disassembler
    prints these with a leading 'vs'.  */
 #define PPC_OPERAND_VSR (0x100000)
+
 \f
 /* The POWER and PowerPC assemblers use a few macros.  We keep them
    with the operands table for simplicity.  The macro table is an
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index ac88f76..249abf1 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -159,6 +159,9 @@ struct ppc_mopt ppc_opts[] = {
     0 },
   { "spe",     (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
     PPC_OPCODE_SPE },
+  { "titan",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32 
+                | PPC_OPCODE_PMR | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
+    0 },
   { "vsx",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC),
     PPC_OPCODE_VSX },
 };
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 123436c..73afbe5 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -442,8 +442,8 @@ const struct powerpc_operand powerpc_operands[] =
 
   /* The SPR field in an XFX form instruction.  This is flipped--the
      lower 5 bits are stored in the upper 5 and vice- versa.  */
-#define SPR SISIGNOPT + 1
-#define PMR SPR
+#define SPR SISIGNOPT + 1                                                                                                        
+#define PMR SPR                                                                                                                  
 #define SPR_MASK (0x3ff << 11)
   { 0x3ff, 11, insert_spr, extract_spr, 0 },
 
@@ -1935,6 +1935,8 @@ extract_dm (unsigned long insn,
 #define PPCRFMCI	PPC_OPCODE_RFMCI
 #define E500MC  PPC_OPCODE_E500MC
 #define PPCA2	PPC_OPCODE_A2
+#define TITAN   PPC_OPCODE_TITAN  
+#define MULHW   PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
 \f
 /* The opcode table.
 
@@ -2017,16 +2019,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vmrghb",	VX (4,	12),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"psq_stx",	XW (4,	 7,0),	XW_MASK,     PPCPS,	PPCNONE,	{FRS,RA,RB,PSWM,PSQM}},
 {"vpkuhum",	VX (4,	14),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"mulhhwu",	XRC(4,	 8,0),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"mulhhwu.",	XRC(4,	 8,1),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"mulhhwu",	XRC(4,	 8,0),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
+{"mulhhwu.",	XRC(4,	 8,1),	X_MASK,      MULHW, 	PPCNONE,	{RT, RA, RB}},
 {"ps_sum0",	A  (4,	10,0),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
 {"ps_sum0.",	A  (4,	10,1),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
 {"ps_sum1",	A  (4,	11,0),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
 {"ps_sum1.",	A  (4,	11,1),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
 {"ps_muls0",	A  (4,	12,0),	AFRB_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRC}},
-{"machhwu",	XO (4,	12,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"machhwu",	XO (4,	12,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"ps_muls0.",	A  (4,	12,1),	AFRB_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRC}},
-{"machhwu.",	XO (4,	12,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"machhwu.",	XO (4,	12,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"ps_muls1",	A  (4,	13,0),	AFRB_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRC}},
 {"ps_muls1.",	A  (4,	13,1),	AFRB_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRC}},
 {"ps_madds0",	A  (4,	14,0),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
@@ -2081,13 +2083,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"psq_stux",	XW (4,	39,0),	XW_MASK,     PPCPS,	PPCNONE,	{FRS,RA,RB,PSWM,PSQM}},
 {"vpkuwum",	VX (4,	78),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"ps_neg",	XRC(4,	40,0),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
-{"mulhhw",	XRC(4,	40,0),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"mulhhw",	XRC(4,	40,0),	X_MASK,      MULHW, 	PPCNONE,	{RT, RA, RB}},
 {"ps_neg.",	XRC(4,	40,1),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
-{"mulhhw.",	XRC(4,	40,1),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"machhw",	XO (4,	44,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"machhw.",	XO (4,	44,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmachhw",	XO (4,	46,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmachhw.",	XO (4,	46,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"mulhhw.",	XRC(4,	40,1),	X_MASK,      MULHW, 	PPCNONE,	{RT, RA, RB}},
+{"machhw",	XO (4,	44,0,0),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
+{"machhw.",	XO (4,	44,0,1),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
+{"nmachhw",	XO (4,	46,0,0),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
+{"nmachhw.",	XO (4,	46,0,1),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
 {"ps_cmpu1",	X  (4,	64), X_MASK|(3<<21), PPCPS,	PPCNONE,	{BF, FRA, FRB}},
 {"vadduwm",	VX (4,	128),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vmaxuw",	VX (4,	130),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
@@ -2097,15 +2099,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vpkuhus",	VX (4,	142),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"ps_mr",	XRC(4,	72,0),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
 {"ps_mr.",	XRC(4,	72,1),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
-{"machhwsu",	XO (4,	76,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"machhwsu.",	XO (4,	76,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"machhwsu",	XO (4,	76,0,0),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
+{"machhwsu.",	XO (4,	76,0,1),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
 {"ps_cmpo1",	X  (4,	96), X_MASK|(3<<21), PPCPS,	PPCNONE,	{BF, FRA, FRB}},
 {"vcmpeqfp",	VXR(4, 198,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vpkuwus",	VX (4, 206),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"machhws",	XO (4, 108,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"machhws.",	XO (4, 108,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmachhws",	XO (4, 110,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmachhws.",	XO (4, 110,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"machhws",	XO (4, 108,0,0),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
+{"machhws.",	XO (4, 108,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmachhws",	XO (4, 110,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmachhws.",	XO (4, 110,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vmaxsb",	VX (4, 258),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vslb",	VX (4, 260),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vmulosb",	VX (4, 264),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
@@ -2113,39 +2115,39 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vmrglb",	VX (4, 268),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vpkshus",	VX (4, 270),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"ps_nabs",	XRC(4, 136,0),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
-{"mulchwu",	XRC(4, 136,0),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"mulchwu",	XRC(4, 136,0),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
 {"ps_nabs.",	XRC(4, 136,1),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
-{"mulchwu.",	XRC(4, 136,1),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"macchwu",	XO (4, 140,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"macchwu.",	XO (4, 140,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"mulchwu.",	XRC(4, 136,1),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchwu",	XO (4, 140,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchwu.",	XO (4, 140,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vmaxsh",	VX (4, 322),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vslh",	VX (4, 324),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vmulosh",	VX (4, 328),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vrsqrtefp",	VX (4, 330),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
 {"vmrglh",	VX (4, 332),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vpkswus",	VX (4, 334),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"mulchw",	XRC(4, 168,0),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"mulchw.",	XRC(4, 168,1),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"macchw",	XO (4, 172,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"macchw.",	XO (4, 172,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmacchw",	XO (4, 174,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmacchw.",	XO (4, 174,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"mulchw",	XRC(4, 168,0),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
+{"mulchw.",	XRC(4, 168,1),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchw",	XO (4, 172,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchw.",	XO (4, 172,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmacchw",	XO (4, 174,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmacchw.",	XO (4, 174,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vaddcuw",	VX (4, 384),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vmaxsw",	VX (4, 386),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vslw",	VX (4, 388),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vexptefp",	VX (4, 394),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
 {"vmrglw",	VX (4, 396),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vpkshss",	VX (4, 398),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"macchwsu",	XO (4, 204,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"macchwsu.",	XO (4, 204,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"macchwsu",	XO (4, 204,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchwsu.",	XO (4, 204,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vsl",		VX (4, 452),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vcmpgefp",	VXR(4, 454,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vlogefp",	VX (4, 458),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
 {"vpkswss",	VX (4, 462),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"macchws",	XO (4, 236,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"macchws.",	XO (4, 236,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmacchws",	XO (4, 238,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmacchws.",	XO (4, 238,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"macchws",	XO (4, 236,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchws.",	XO (4, 236,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmacchws",	XO (4, 238,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmacchws.",	XO (4, 238,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evaddw",	VX (4, 512),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"vaddubs",	VX (4, 512),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"evaddiw",	VX (4, 514),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RB, UIMM}},
@@ -2322,17 +2324,17 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evlhhossplatx",VX(4, 782),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"vpkpx",	VX (4, 782),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"evlhhossplat",VX (4, 783),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_2, RA}},
-{"mullhwu",	XRC(4, 392,0),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"mullhwu",	XRC(4, 392,0),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evlwhex",	VX (4, 784),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"mullhwu.",	XRC(4, 392,1),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"mullhwu.",	XRC(4, 392,1),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evlwhe",	VX (4, 785),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_4, RA}},
 {"evlwhoux",	VX (4, 788),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evlwhou",	VX (4, 789),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_4, RA}},
 {"evlwhosx",	VX (4, 790),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evlwhos",	VX (4, 791),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_4, RA}},
-{"maclhwu",	XO (4, 396,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"maclhwu",	XO (4, 396,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evlwwsplatx",	VX (4, 792),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"maclhwu.",	XO (4, 396,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"maclhwu.",	XO (4, 396,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evlwwsplat",	VX (4, 793),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_4, RA}},
 {"evlwhsplatx",	VX (4, 796),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evlwhsplat",	VX (4, 797),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_4, RA}},
@@ -2358,27 +2360,27 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vcfsx",	VX (4, 842),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB, UIMM}},
 {"vspltish",	VX (4, 844),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, SIMM}},
 {"vupkhpx",	VX (4, 846),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
-{"mullhw",	XRC(4, 424,0),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"mullhw.",	XRC(4, 424,1),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"maclhw",	XO (4, 428,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"maclhw.",	XO (4, 428,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmaclhw",	XO (4, 430,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmaclhw.",	XO (4, 430,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"mullhw",	XRC(4, 424,0),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
+{"mullhw.",	XRC(4, 424,1),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
+{"maclhw",	XO (4, 428,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"maclhw.",	XO (4, 428,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmaclhw",	XO (4, 430,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmaclhw.",	XO (4, 430,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vaddsws",	VX (4, 896),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vminsw",	VX (4, 898),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vsraw",	VX (4, 900),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vcmpgtsw",	VXR(4, 902,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vctuxs",	VX (4, 906),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB, UIMM}},
 {"vspltisw",	VX (4, 908),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, SIMM}},
-{"maclhwsu",	XO (4, 460,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"maclhwsu.",	XO (4, 460,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"maclhwsu",	XO (4, 460,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"maclhwsu.",	XO (4, 460,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vcmpbfp",	VXR(4, 966,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vctsxs",	VX (4, 970),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB, UIMM}},
 {"vupklpx",	VX (4, 974),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
-{"maclhws",	XO (4, 492,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"maclhws.",	XO (4, 492,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmaclhws",	XO (4, 494,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmaclhws.",	XO (4, 494,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"maclhws",	XO (4, 492,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"maclhws.",	XO (4, 492,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmaclhws",	XO (4, 494,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmaclhws.",	XO (4, 494,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vsububm",	VX (4,1024),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vavgub",	VX (4,1026),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"evmhessf",	VX (4,1027),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2395,8 +2397,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vslo",	VX (4,1036),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"evmhosmi",	VX (4,1037),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhosmf",	VX (4,1039),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"machhwuo",	XO (4,	12,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"machhwuo.",	XO (4,	12,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"machhwuo",	XO (4,	12,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"machhwuo.",	XO (4,	12,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"ps_merge00",	XOPS(4,528,0),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
 {"ps_merge00.",	XOPS(4,528,1),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
 {"evmhessfa",	VX (4,1059),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2421,13 +2423,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmwhsmi",	VX (4,1101),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwhsmf",	VX (4,1103),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwssf",	VX (4,1107),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"machhwo",	XO (4,	44,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"machhwo",	XO (4,	44,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evmwumi",	VX (4,1112),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"machhwo.",	XO (4,	44,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"machhwo.",	XO (4,	44,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evmwsmi",	VX (4,1113),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwsmf",	VX (4,1115),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"nmachhwo",	XO (4,	46,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmachhwo.",	XO (4,	46,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"nmachhwo",	XO (4,	46,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmachhwo.",	XO (4,	46,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"ps_merge01",	XOPS(4,560,0),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
 {"ps_merge01.",	XOPS(4,560,1),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
 {"evmwhssfa",	VX (4,1127),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2445,8 +2447,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vcmpequw.",	VXR(4, 134,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"udi2fcm.",	APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476,		{URT, URA, URB}},
 {"udi2fcm",	APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476,		{URT, URA, URB}},   
-{"machhwsuo",	XO (4,	76,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"machhwsuo.",	XO (4,	76,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"machhwsuo",	XO (4,	76,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"machhwsuo.",	XO (4,	76,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"ps_merge10",	XOPS(4,592,0),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
 {"ps_merge10.",	XOPS(4,592,1),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
 {"evaddusiaaw",	VX (4,1216),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
@@ -2464,10 +2466,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evaddsmiaaw",	VX (4,1225),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
 {"evsubfumiaaw",VX (4,1226),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
 {"evsubfsmiaaw",VX (4,1227),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
-{"machhwso",	XO (4, 108,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"machhwso.",	XO (4, 108,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmachhwso",	XO (4, 110,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmachhwso.",	XO (4, 110,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"machhwso",	XO (4, 108,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"machhwso.",	XO (4, 108,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmachhwso",	XO (4, 110,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmachhwso.",	XO (4, 110,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"ps_merge11",	XOPS(4,624,0),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
 {"ps_merge11.",	XOPS(4,624,1),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
 {"evmheusiaaw",	VX (4,1280),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2486,8 +2488,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmhoumiaaw",	VX (4,1292),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhosmiaaw",	VX (4,1293),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhosmfaaw",	VX (4,1295),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"macchwuo",	XO (4, 140,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"macchwuo.",	XO (4, 140,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"macchwuo",	XO (4, 140,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchwuo.",	XO (4, 140,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evmhegumiaa",	VX (4,1320),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhegsmiaa",	VX (4,1321),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhegsmfaa",	VX (4,1323),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2502,13 +2504,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmwlumiaaw",	VX (4,1352),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwlsmiaaw",	VX (4,1353),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwssfaa",	VX (4,1363),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"macchwo",	XO (4, 172,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"macchwo",	XO (4, 172,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evmwumiaa",	VX (4,1368),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"macchwo.",	XO (4, 172,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"macchwo.",	XO (4, 172,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evmwsmiaa",	VX (4,1369),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwsmfaa",	VX (4,1371),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"nmacchwo",	XO (4, 174,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmacchwo.",	XO (4, 174,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"nmacchwo",	XO (4, 174,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmacchwo.",	XO (4, 174,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evmheusianw",	VX (4,1408),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"vsubcuw",	VX (4,1408),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"evmhessianw",	VX (4,1409),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2525,8 +2527,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmhoumianw",	VX (4,1420),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhosmianw",	VX (4,1421),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhosmfanw",	VX (4,1423),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"macchwsuo",	XO (4, 204,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"macchwsuo.",	XO (4, 204,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"macchwsuo",	XO (4, 204,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchwsuo.",	XO (4, 204,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evmhegumian",	VX (4,1448),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhegsmian",	VX (4,1449),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhegsmfan",	VX (4,1451),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2541,13 +2543,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmwlumianw",	VX (4,1480),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwlsmianw",	VX (4,1481),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwssfan",	VX (4,1491),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"macchwso",	XO (4, 236,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"macchwso",	XO (4, 236,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evmwumian",	VX (4,1496),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"macchwso.",	XO (4, 236,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"macchwso.",	XO (4, 236,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evmwsmian",	VX (4,1497),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwsmfan",	VX (4,1499),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"nmacchwso",	XO (4, 238,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmacchwso.",	XO (4, 238,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"nmacchwso",	XO (4, 238,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmacchwso.",	XO (4, 238,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vsububs",	VX (4,1536),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"mfvscr",	VX (4,1540),	VX_MASK,     PPCVEC,	PPCNONE,	{VD}},
 {"vcmpgtub.",	VXR(4, 518,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
@@ -2573,30 +2575,30 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"udi12fcm.",	APU(4, 899,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"udi12fcm",	APU(4, 899,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"vsum4sbs",	VX (4,1800),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"maclhwuo",	XO (4, 396,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"maclhwuo.",	XO (4, 396,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"maclhwuo",	XO (4, 396,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"maclhwuo.",	XO (4, 396,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vsubshs",	VX (4,1856),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vcmpgtsh.",	VXR(4, 838,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"udi13fcm.",	APU(4, 931,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"udi13fcm",	APU(4, 931,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
-{"maclhwo",	XO (4, 428,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"maclhwo.",	XO (4, 428,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmaclhwo",	XO (4, 430,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmaclhwo.",	XO (4, 430,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"maclhwo",	XO (4, 428,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"maclhwo.",	XO (4, 428,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmaclhwo",	XO (4, 430,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmaclhwo.",	XO (4, 430,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vsubsws",	VX (4,1920),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vcmpgtsw.",	VXR(4, 902,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"udi14fcm.",	APU(4, 963,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"udi14fcm",	APU(4, 963,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"vsumsws",	VX (4,1928),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"maclhwsuo",	XO (4, 460,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"maclhwsuo.",	XO (4, 460,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"maclhwsuo",	XO (4, 460,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"maclhwsuo.",	XO (4, 460,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vcmpbfp.",	VXR(4, 966,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"udi15fcm.",	APU(4, 995,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"udi15fcm",	APU(4, 995,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
-{"maclhwso",	XO (4, 492,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"maclhwso.",	XO (4, 492,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmaclhwso",	XO (4, 494,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmaclhwso.",	XO (4, 494,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"maclhwso",	XO (4, 492,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"maclhwso.",	XO (4, 492,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmaclhwso",	XO (4, 494,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmaclhwso.",	XO (4, 494,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"dcbz_l",	X  (4,1014),	XRT_MASK,    PPCPS,	PPCNONE,	{RA, RB}},
 
 {"mulli",	OP(7),		OP_MASK,     PPCCOM,	PPCNONE,	{RT, RA, SI}},
@@ -3532,7 +3534,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"iseleq",	X(31,79),	X_MASK,      PPCISEL,	PPCNONE,	{RT, RA, RB}},
 
-{"isel",	XISEL(31,15),	XISEL_MASK,  PPCISEL,	PPCNONE,	{RT, RA, RB, CRB}},
+{"isel",	XISEL(31,15),	XISEL_MASK,  PPCISEL|TITAN,	PPCNONE,	{RT, RA, RB, CRB}},
 
 {"subf",	XO(31,40,0,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
 {"sub",		XO(31,40,0,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RB, RA}},
@@ -3585,8 +3587,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mulhw",	XO(31,75,0,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
 {"mulhw.",	XO(31,75,0,1),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
 
-{"dlmzb",	XRC(31,78,0),	X_MASK,  PPC403|PPC440,	PPCNONE,	{RA, RS, RB}},
-{"dlmzb.",	XRC(31,78,1),	X_MASK,  PPC403|PPC440,	PPCNONE,	{RA, RS, RB}},
+{"dlmzb",	XRC(31,78,0),	X_MASK,  PPC403|PPC440|TITAN,	PPCNONE,	{RA, RS, RB}},
+{"dlmzb.",	XRC(31,78,1),	X_MASK,  PPC403|PPC440|TITAN,	PPCNONE,	{RA, RS, RB}},
 
 {"mtsrd",	X(31,82),  XRB_MASK|(1<<20), PPC64,	PPCNONE,	{SR, RS}},
 
@@ -3629,7 +3631,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"wrtee",	X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RS}},
 
-{"dcbtstls",	X(31,134),	X_MASK, PPCCHLK|PPC476,	PPCNONE,	{CT, RA, RB}},
+{"dcbtstls",	X(31,134),	X_MASK, PPCCHLK|PPC476|TITAN,	PPCNONE,	{CT, RA, RB}},
 
 {"stvebx",	X(31,135),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
 {"stbfcmx",	APU(31,135,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
@@ -3676,7 +3678,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"wrteei",	X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE,	{E}},
 
-{"dcbtls",	X(31,166),	X_MASK, PPCCHLK|PPC476,	PPCNONE,	{CT, RA, RB}},
+{"dcbtls",	X(31,166),	X_MASK, PPCCHLK|PPC476|TITAN,	PPCNONE,	{CT, RA, RB}},
 
 {"stvehx",	X(31,167),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
 {"sthfcmx",	APU(31,167,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
@@ -3714,7 +3716,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"msgsnd",	XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2, PPCNONE,	{RB}},
 
-{"mtsr",	X(31,210), XRB_MASK|(1<<20), COM32,	PPCNONE,	{SR, RS}},
+{"mtsr",	X(31,210), XRB_MASK|(1<<20), COM32,	TITAN,  	{SR, RS}},
 
 {"eratwe",	X(31,211),	X_MASK,	     PPCA2,	PPCNONE,	{RS, RA, WS}},
 
@@ -3732,7 +3734,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"stbepx",	X(31,223),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{RS, RA, RB}},
 
-{"icblc",	X(31,230),	X_MASK, PPCCHLK|PPC476,	PPCNONE,	{CT, RA, RB}},
+{"icblc",	X(31,230),	X_MASK, PPCCHLK|PPC476|TITAN,	PPCNONE,	{CT, RA, RB}},
 
 {"stvx",	X(31,231),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
 {"stqfcmx",	APU(31,231,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
@@ -3757,7 +3759,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"icblce",	X(31,238),	X_MASK,      PPCCHLK,	E500MC|PPCA2,	{CT, RA, RB}},
 {"msgclr",	XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2, PPCNONE,	{RB}},
-{"mtsrin",	X(31,242),	XRA_MASK,    PPC32,	PPCNONE,	{RS, RB}},
+{"mtsrin",	X(31,242),	XRA_MASK,    PPC32,	TITAN,  	{RS, RB}},
 {"mtsri",	X(31,242),	XRA_MASK,    POWER32,	PPCNONE,	{RS, RB}},
 
 {"dcbtstt",	XRT(31,246,0x10), XRT_MASK,  POWER7,	PPCNONE,	{RA, RB}},
@@ -3773,7 +3775,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"dcbtstep",	XRT(31,255,0),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{RT, RA, RB}},
 
-{"mfdcrx",	X(31,259),	X_MASK, BOOKE|PPCA2|PPC476, PPCNONE,	{RS, RA}},
+{"mfdcrx",	X(31,259),	X_MASK, BOOKE|PPCA2|PPC476, TITAN,	{RS, RA}},
 {"mfdcrx.",	XRC(31,259,1),	X_MASK,      PPCA2,	PPCNONE,	{RS, RA}},
 
 {"icbt",	X(31,262),	XRT_MASK,    PPC403,	PPCNONE,	{RA, RB}},
@@ -3791,7 +3793,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"tlbiel",	X(31,274),	XRTLRA_MASK, POWER4,	PPC476,		{RB, L}},
 
-{"mfapidi",	X(31,275),	X_MASK,      BOOKE,	PPCNONE,	{RT, RA}},
+{"mfapidi",	X(31,275),	X_MASK,      BOOKE,	TITAN,  	{RT, RA}},
 
 {"lscbx",	XRC(31,277,0),	X_MASK,      M601,	PPCNONE,	{RT, RA, RB}},
 {"lscbx.",	XRC(31,277,1),	X_MASK,      M601,	PPCNONE,	{RT, RA, RB}},
@@ -3811,10 +3813,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"mfdcrux",	X(31,291),	X_MASK,      PPC464,	PPCNONE,	{RS, RA}},
 
-{"tlbie",	X(31,306),	XRTLRA_MASK, PPC,	PPCNONE,	{RB, L}},
+{"tlbie",	X(31,306),	XRTLRA_MASK, PPC,	TITAN,  	{RB, L}},
 {"tlbi",	X(31,306),	XRT_MASK,    POWER,	PPCNONE,	{RA0, RB}},
 
-{"eciwx",	X(31,310),	X_MASK,      PPC,	PPCNONE,	{RT, RA, RB}},
+{"eciwx",	X(31,310),	X_MASK,      PPC,	TITAN,  	{RT, RA, RB}},
 
 {"lhzux",	X(31,311),	X_MASK,      COM,	PPCNONE,	{RT, RAL, RB}},
 
@@ -3859,10 +3861,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mfdmasa3",	XSPR(31,323,219), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfdmacc3",	XSPR(31,323,220), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfdmasr",	XSPR(31,323,224), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
-{"mfdcr",	X(31,323),	X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RT, SPR}},
+{"mfdcr",	X(31,323),	X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {RT, SPR}},
 {"mfdcr.",	XRC(31,323,1),	X_MASK,      PPCA2,	PPCNONE,	{RT, SPR}},
 
-{"dcread",	X(31,326),	X_MASK,      PPC476,	PPCNONE,	{RT, RA, RB}},
+{"dcread",	X(31,326),	X_MASK,  PPC476|TITAN,	PPCNONE,	{RT, RA, RB}},
 
 {"div",		XO(31,331,0,0),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
 {"div.",	XO(31,331,0,1),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
@@ -3873,17 +3875,17 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"mfmq",	XSPR(31,339,  0), XSPR_MASK, M601,	PPCNONE,	{RT}},
 {"mfxer",	XSPR(31,339,  1), XSPR_MASK, COM,	PPCNONE,	{RT}},
-{"mfrtcu",	XSPR(31,339,  4), XSPR_MASK, COM,	PPCNONE,	{RT}},
-{"mfrtcl",	XSPR(31,339,  5), XSPR_MASK, COM,	PPCNONE,	{RT}},
+{"mfrtcu",	XSPR(31,339,  4), XSPR_MASK, COM,	TITAN,  	{RT}},
+{"mfrtcl",	XSPR(31,339,  5), XSPR_MASK, COM,	TITAN,  	{RT}},
 {"mfdec",	XSPR(31,339,  6), XSPR_MASK, MFDEC1,	PPCNONE,	{RT}},
 {"mflr",	XSPR(31,339,  8), XSPR_MASK, COM,	PPCNONE,	{RT}},
 {"mfctr",	XSPR(31,339,  9), XSPR_MASK, COM,	PPCNONE,	{RT}},
 {"mftid",	XSPR(31,339, 17), XSPR_MASK, POWER,	PPCNONE,	{RT}},
-{"mfdsisr",	XSPR(31,339, 18), XSPR_MASK, COM,	PPCNONE,	{RT}},
-{"mfdar",	XSPR(31,339, 19), XSPR_MASK, COM,	PPCNONE,	{RT}},
-{"mfdec",	XSPR(31,339, 22), XSPR_MASK, MFDEC2,	PPCNONE,	{RT}},
+{"mfdsisr",	XSPR(31,339, 18), XSPR_MASK, COM,	TITAN,  	{RT}},
+{"mfdar",	XSPR(31,339, 19), XSPR_MASK, COM,	TITAN,  	{RT}},
+{"mfdec",	XSPR(31,339, 22), XSPR_MASK, MFDEC2|TITAN,	PPCNONE,	{RT}},
 {"mfsdr0",	XSPR(31,339, 24), XSPR_MASK, POWER,	PPCNONE,	{RT}},
-{"mfsdr1",	XSPR(31,339, 25), XSPR_MASK, COM,	PPCNONE,	{RT}},
+{"mfsdr1",	XSPR(31,339, 25), XSPR_MASK, COM,	TITAN,  	{RT}},
 {"mfsrr0",	XSPR(31,339, 26), XSPR_MASK, COM,	PPCNONE,	{RT}},
 {"mfsrr1",	XSPR(31,339, 27), XSPR_MASK, COM,	PPCNONE,	{RT}},
 {"mfcfar",	XSPR(31,339, 28), XSPR_MASK, POWER6,	PPCNONE,	{RT}},
@@ -3924,7 +3926,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mfsprg2",	XSPR(31,339,274), XSPR_MASK, PPC,	PPCNONE,	{RT}},
 {"mfsprg3",	XSPR(31,339,275), XSPR_MASK, PPC,	PPCNONE,	{RT}},
 {"mfasr",	XSPR(31,339,280), XSPR_MASK, PPC64,	PPCNONE,	{RT}},
-{"mfear",	XSPR(31,339,282), XSPR_MASK, PPC,	PPCNONE,	{RT}},
+{"mfear",	XSPR(31,339,282), XSPR_MASK, PPC,	TITAN,  	{RT}},
 {"mfpir",	XSPR(31,339,286), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
 {"mfpvr",	XSPR(31,339,287), XSPR_MASK, PPC,	PPCNONE,	{RT}},
 {"mfdbsr",	XSPR(31,339,304), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
@@ -3961,13 +3963,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mfbbear",	XSPR(31,339,513), XSPR_MASK, PPCBRLK,	PPCNONE,	{RT}},
 {"mfbbtar",	XSPR(31,339,514), XSPR_MASK, PPCBRLK,	PPCNONE,	{RT}},
 {"mfivor32",	XSPR(31,339,528), XSPR_MASK, PPCSPE,	PPCNONE,	{RT}},
-{"mfibatu",	XSPR(31,339,528), XSPRBAT_MASK, PPC,	PPCNONE,	{RT, SPRBAT}},
+{"mfibatu",	XSPR(31,339,528), XSPRBAT_MASK, PPC,	TITAN,  	{RT, SPRBAT}},
 {"mfivor33",	XSPR(31,339,529), XSPR_MASK, PPCSPE,	PPCNONE,	{RT}},
-{"mfibatl",	XSPR(31,339,529), XSPRBAT_MASK, PPC,	PPCNONE,	{RT, SPRBAT}},
+{"mfibatl",	XSPR(31,339,529), XSPRBAT_MASK, PPC,	TITAN,  	{RT, SPRBAT}},
 {"mfivor34",	XSPR(31,339,530), XSPR_MASK, PPCSPE,	PPCNONE,	{RT}},
 {"mfivor35",	XSPR(31,339,531), XSPR_MASK, PPCPMR,	PPCNONE,	{RT}},
-{"mfdbatu",	XSPR(31,339,536), XSPRBAT_MASK, PPC,	PPCNONE,	{RT, SPRBAT}},
-{"mfdbatl",	XSPR(31,339,537), XSPRBAT_MASK, PPC,	PPCNONE,	{RT, SPRBAT}},
+{"mfdbatu",	XSPR(31,339,536), XSPRBAT_MASK, PPC,	TITAN,  	{RT, SPRBAT}},
+{"mfdbatl",	XSPR(31,339,537), XSPRBAT_MASK, PPC,	TITAN,  	{RT, SPRBAT}},
 {"mfic_cst",	XSPR(31,339,560), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfic_adr",	XSPR(31,339,561), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfic_dat",	XSPR(31,339,562), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
@@ -3977,7 +3979,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mfmcsrr0",	XSPR(31,339,570), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RT}},
 {"mfmcsrr1",	XSPR(31,339,571), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RT}},
 {"mfmcsr",	XSPR(31,339,572), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RT}},
-{"mfmcar",	XSPR(31,339,573), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RT}},
+{"mfmcar",	XSPR(31,339,573), XSPR_MASK, PPCRFMCI,	TITAN,  	{RT}},
 {"mfdpdr",	XSPR(31,339,630), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfdpir",	XSPR(31,339,631), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfimmr",	XSPR(31,339,638), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
@@ -4000,6 +4002,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mfmd_dbcam",	XSPR(31,339,824), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfmd_dbram0",	XSPR(31,339,825), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfmd_dbram1",	XSPR(31,339,826), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
+{"mfivndx",	XSPR(31,339,880), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfdvndx",	XSPR(31,339,881), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfivlim",	XSPR(31,339,882), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfdvlim",	XSPR(31,339,883), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfclcsr",	XSPR(31,339,884), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfccr1",	XSPR(31,339,888), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfrstcfg",	XSPR(31,339,923), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfdcdbtrl",	XSPR(31,339,924), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfdcdbtrh",	XSPR(31,339,925), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mficdbtr",	XSPR(31,339,927), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
 {"mfummcr0",	XSPR(31,339,936), XSPR_MASK, PPC750,	PPCNONE,	{RT}},
 {"mfupmc1",	XSPR(31,339,937), XSPR_MASK, PPC750,	PPCNONE,	{RT}},
 {"mfupmc2",	XSPR(31,339,938), XSPR_MASK, PPC750,	PPCNONE,	{RT}},
@@ -4009,7 +4021,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mfupmc4",	XSPR(31,339,942), XSPR_MASK, PPC750,	PPCNONE,	{RT}},
 {"mfzpr",	XSPR(31,339,944), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfpid",	XSPR(31,339,945), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
-{"mfccr0",	XSPR(31,339,947), XSPR_MASK, PPC405,	PPCNONE,	{RT}},
+{"mfmmucr",	XSPR(31,339,946), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfccr0",	XSPR(31,339,947), XSPR_MASK, PPC405|TITAN,	PPCNONE,	{RT}},
 {"mfiac3",	XSPR(31,339,948), XSPR_MASK, PPC405,	PPCNONE,	{RT}},
 {"mfiac4",	XSPR(31,339,949), XSPR_MASK, PPC405,	PPCNONE,	{RT}},
 {"mfdvc1",	XSPR(31,339,950), XSPR_MASK, PPC405,	PPCNONE,	{RT}},
@@ -4026,7 +4039,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mfdbcr1",	XSPR(31,339,957), XSPR_MASK, PPC405,	PPCNONE,	{RT}},
 {"mfpmc3",	XSPR(31,339,957), XSPR_MASK, PPC750,	PPCNONE,	{RT}},
 {"mfpmc4",	XSPR(31,339,958), XSPR_MASK, PPC750,	PPCNONE,	{RT}},
-{"mficdbdr",	XSPR(31,339,979), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
+{"mficdbdr",	XSPR(31,339,979), XSPR_MASK, PPC403|TITAN,	PPCNONE,	{RT}},
 {"mfesr",	XSPR(31,339,980), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfdear",	XSPR(31,339,981), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfevpr",	XSPR(31,339,982), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
@@ -4040,6 +4053,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mfsrr3",	XSPR(31,339,991), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfdbsr",	XSPR(31,339,1008), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfdbcr0",	XSPR(31,339,1010), XSPR_MASK, PPC405,	PPCNONE,	{RT}},
+{"mfdbdr",	XSPR(31,339,1011), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
 {"mfiac1",	XSPR(31,339,1012), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfiac2",	XSPR(31,339,1013), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfdac1",	XSPR(31,339,1014), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
@@ -4071,7 +4085,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"divs",	XO(31,363,0,0),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
 {"divs.",	XO(31,363,0,1),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
 
-{"tlbia",	X(31,370),	0xffffffff,  PPC,	PPCNONE,	{0}},
+{"tlbia",	X(31,370),	0xffffffff,  PPC,	TITAN,  	{0}},
 
 {"mftbl",	XSPR(31,371,268), XSPR_MASK, CLASSIC,	PPCNONE,	{RT}},
 {"mftbu",	XSPR(31,371,269), XSPR_MASK, CLASSIC,	PPCNONE,	{RT}},
@@ -4085,10 +4099,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"popcntw",	X(31,378),	XRB_MASK, POWER7|PPCA2,	PPCNONE,	{RA, RS}},
 
-{"mtdcrx",	X(31,387),	X_MASK, BOOKE|PPCA2|PPC476, PPCNONE,	{RA, RS}},
+{"mtdcrx",	X(31,387),	X_MASK, BOOKE|PPCA2|PPC476, TITAN,	{RA, RS}},
 {"mtdcrx.",	XRC(31,387,1),	X_MASK,      PPCA2,	PPCNONE,	{RA, RS}},
 
-{"dcblc",	X(31,390),	X_MASK, PPCCHLK|PPC476,	PPCNONE,	{CT, RA, RB}},
+{"dcblc",	X(31,390),	X_MASK, PPCCHLK|PPC476|TITAN,	PPCNONE,	{CT, RA, RB}},
 {"stdfcmx",	APU(31,391,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
 {"divdeu",	XO(31,393,0,0),	XO_MASK,     POWER7,	PPCNONE,	{RT, RA, RB}},
@@ -4119,7 +4133,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"slbie",	X(31,434),	XRTRA_MASK,  PPC64,	PPCNONE,	{RB}},
 
-{"ecowx",	X(31,438),	X_MASK,      PPC,	PPCNONE,	{RT, RA, RB}},
+{"ecowx",	X(31,438),	X_MASK,      PPC,	TITAN,  	{RT, RA, RB}},
 
 {"sthux",	X(31,439),	X_MASK,      COM,	PPCNONE,	{RS, RAS, RB}},
 
@@ -4164,10 +4178,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mtdmasa3",	XSPR(31,451,219), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
 {"mtdmacc3",	XSPR(31,451,220), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
 {"mtdmasr",	XSPR(31,451,224), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
-{"mtdcr",	X(31,451),     X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {SPR, RS}},
+{"mtdcr",	X(31,451),     X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {SPR, RS}},
 {"mtdcr.",	XRC(31,451,1), X_MASK,       PPCA2,	PPCNONE,	{SPR, RS}},
 
-{"dccci",	X(31,454),     XRT_MASK, PPC403|PPC440,	PPCA2|PPC476,	{RA, RB}},
+{"dccci",	X(31,454),     XRT_MASK, PPC403|PPC440|TITAN,	PPCA2|PPC476,	{RA, RB}},
 {"dci",		X(31,454),	XRARB_MASK, PPCA2|PPC476, PPCNONE,	{CT}},
 
 {"divdu",	XO(31,457,0,0),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
@@ -4181,15 +4195,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mtmq",	XSPR(31,467,  0), XSPR_MASK, M601,	PPCNONE,	{RS}},
 {"mtxer",	XSPR(31,467,  1), XSPR_MASK, COM,	PPCNONE,	{RS}},
 {"mtlr",	XSPR(31,467,  8), XSPR_MASK, COM,	PPCNONE,	{RS}},
-{"mtctr",	XSPR(31,467,  9), XSPR_MASK, COM,	PPCNONE,	{RS}},
+{"mtctr", 	XSPR(31,467,  9), XSPR_MASK, COM,	PPCNONE,	{RS}},
 {"mttid",	XSPR(31,467, 17), XSPR_MASK, POWER,	PPCNONE,	{RS}},
-{"mtdsisr",	XSPR(31,467, 18), XSPR_MASK, COM,	PPCNONE,	{RS}},
-{"mtdar",	XSPR(31,467, 19), XSPR_MASK, COM,	PPCNONE,	{RS}},
-{"mtrtcu",	XSPR(31,467, 20), XSPR_MASK, COM,	PPCNONE,	{RS}},
-{"mtrtcl",	XSPR(31,467, 21), XSPR_MASK, COM,	PPCNONE,	{RS}},
+{"mtdsisr",	XSPR(31,467, 18), XSPR_MASK, COM,	TITAN,  	{RS}},
+{"mtdar",	XSPR(31,467, 19), XSPR_MASK, COM,	TITAN,  	{RS}},
+{"mtrtcu",	XSPR(31,467, 20), XSPR_MASK, COM,	TITAN,  	{RS}},
+{"mtrtcl",	XSPR(31,467, 21), XSPR_MASK, COM,	TITAN,  	{RS}},
 {"mtdec",	XSPR(31,467, 22), XSPR_MASK, COM,	PPCNONE,	{RS}},
 {"mtsdr0",	XSPR(31,467, 24), XSPR_MASK, POWER,	PPCNONE,	{RS}},
-{"mtsdr1",	XSPR(31,467, 25), XSPR_MASK, COM,	PPCNONE,	{RS}},
+{"mtsdr1",	XSPR(31,467, 25), XSPR_MASK, COM,	TITAN,  	{RS}},
 {"mtsrr0",	XSPR(31,467, 26), XSPR_MASK, COM,	PPCNONE,	{RS}},
 {"mtsrr1",	XSPR(31,467, 27), XSPR_MASK, COM,	PPCNONE,	{RS}},
 {"mtcfar",	XSPR(31,467, 28), XSPR_MASK, POWER6,	PPCNONE,	{RS}},
@@ -4228,7 +4242,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mtsprg6",	XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, PPCNONE,	{RS}},
 {"mtsprg7",	XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, PPCNONE,	{RS}},
 {"mtasr",	XSPR(31,467,280), XSPR_MASK, PPC64,	PPCNONE,	{RS}},
-{"mtear",	XSPR(31,467,282), XSPR_MASK, PPC,	PPCNONE,	{RS}},
+{"mtear",	XSPR(31,467,282), XSPR_MASK, PPC,	TITAN,  	{RS}},
 {"mttbl",	XSPR(31,467,284), XSPR_MASK, PPC,	PPCNONE,	{RS}},
 {"mttbu",	XSPR(31,467,285), XSPR_MASK, PPC,	PPCNONE,	{RS}},
 {"mtdbsr",	XSPR(31,467,304), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
@@ -4265,16 +4279,22 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mtbbear",	XSPR(31,467,513), XSPR_MASK, PPCBRLK,	PPCNONE,	{RS}},
 {"mtbbtar",	XSPR(31,467,514), XSPR_MASK, PPCBRLK,	PPCNONE,	{RS}},
 {"mtivor32",	XSPR(31,467,528), XSPR_MASK, PPCSPE,	PPCNONE,	{RS}},
-{"mtibatu",	XSPR(31,467,528), XSPRBAT_MASK, PPC,	PPCNONE,	{SPRBAT, RS}},
+{"mtibatu",	XSPR(31,467,528), XSPRBAT_MASK, PPC,	TITAN,  	{SPRBAT, RS}},
 {"mtivor33",	XSPR(31,467,529), XSPR_MASK, PPCSPE,	PPCNONE,	{RS}},
-{"mtibatl",	XSPR(31,467,529), XSPRBAT_MASK, PPC,	PPCNONE,	{SPRBAT, RS}},
+{"mtibatl",	XSPR(31,467,529), XSPRBAT_MASK, PPC,	TITAN,  	{SPRBAT, RS}},
 {"mtivor34",	XSPR(31,467,530), XSPR_MASK, PPCSPE,	PPCNONE,	{RS}},
 {"mtivor35",	XSPR(31,467,531), XSPR_MASK, PPCPMR,	PPCNONE,	{RS}},
-{"mtdbatu",	XSPR(31,467,536), XSPRBAT_MASK, PPC,	PPCNONE,	{SPRBAT, RS}},
-{"mtdbatl",	XSPR(31,467,537), XSPRBAT_MASK, PPC,	PPCNONE,	{SPRBAT, RS}},
+{"mtdbatu",	XSPR(31,467,536), XSPRBAT_MASK, PPC,	TITAN,  	{SPRBAT, RS}},
+{"mtdbatl",	XSPR(31,467,537), XSPRBAT_MASK, PPC,	TITAN,  	{SPRBAT, RS}},
 {"mtmcsrr0",	XSPR(31,467,570), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RS}},
 {"mtmcsrr1",	XSPR(31,467,571), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RS}},
 {"mtmcsr",	XSPR(31,467,572), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RS}},
+{"mtivndx",	XSPR(31,467,880), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
+{"mtdvndx",	XSPR(31,467,881), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
+{"mtivlim",	XSPR(31,467,882), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
+{"mtdvlim",	XSPR(31,467,883), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
+{"mtclcsr",	XSPR(31,467,884), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
+{"mtccr1",	XSPR(31,467,888), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
 {"mtummcr0",	XSPR(31,467,936), XSPR_MASK, PPC750,	PPCNONE,	{RS}},
 {"mtupmc1",	XSPR(31,467,937), XSPR_MASK, PPC750,	PPCNONE,	{RS}},
 {"mtupmc2",	XSPR(31,467,938), XSPR_MASK, PPC750,	PPCNONE,	{RS}},
@@ -4284,7 +4304,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mtupmc4",	XSPR(31,467,942), XSPR_MASK, PPC750,	PPCNONE,	{RS}},
 {"mtzpr",	XSPR(31,467,944), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
 {"mtpid",	XSPR(31,467,945), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
-{"mtccr0",	XSPR(31,467,947), XSPR_MASK, PPC405,	PPCNONE,	{RS}},
+{"mtrmmucr",	XSPR(31,467,946), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
+{"mtccr0",	XSPR(31,467,947), XSPR_MASK, PPC405|TITAN,	PPCNONE,	{RS}},
 {"mtiac3",	XSPR(31,467,948), XSPR_MASK, PPC405,	PPCNONE,	{RS}},
 {"mtiac4",	XSPR(31,467,949), XSPR_MASK, PPC405,	PPCNONE,	{RS}},
 {"mtdvc1",	XSPR(31,467,950), XSPR_MASK, PPC405,	PPCNONE,	{RS}},
@@ -4314,6 +4335,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mtsrr2",	XSPR(31,467,990), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
 {"mtsrr3",	XSPR(31,467,991), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
 {"mtdbsr",	XSPR(31,467,1008), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
+{"mtdbdr",	XSPR(31,467,1011), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
 {"mtdbcr0",	XSPR(31,467,1010), XSPR_MASK, PPC405,	PPCNONE,	{RS}},
 {"mtiac1",	XSPR(31,467,1012), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
 {"mtiac2",	XSPR(31,467,1013), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
@@ -4341,7 +4363,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"dcread",	X(31,486),	X_MASK,  PPC403|PPC440,	PPCA2|PPC476,	{RT, RA, RB}},
 
-{"icbtls",	X(31,486),	X_MASK, PPCCHLK|PPC476,	PPCNONE,	{CT, RA, RB}},
+{"icbtls",	X(31,486),	X_MASK, PPCCHLK|PPC476|TITAN,	PPCNONE,	{CT, RA, RB}},
 
 {"stvxl",	X(31,487),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
 
@@ -4433,7 +4455,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lxsdx",	X(31,588),	XX1_MASK,    PPCVSX,	PPCNONE,	{XT6, RA, RB}},
 
-{"mfsr",	X(31,595), XRB_MASK|(1<<20), COM32,	PPCNONE,	{RT, SR}},
+{"mfsr",	X(31,595), XRB_MASK|(1<<20), COM32,	TITAN,  	{RT, SR}},
 
 {"lswi",	X(31,597),	X_MASK,      PPCCOM,	PPCNONE,	{RT, RA0, NB}},
 {"lsi",		X(31,597),	X_MASK,      PWRCOM,	PPCNONE,	{RT, RA0, NB}},
@@ -4480,7 +4502,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"addeo.",	XO(31,138,1,1),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
 {"aeo.",	XO(31,138,1,1),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
 
-{"mfsrin",	X(31,659),	XRA_MASK,    PPC32,	PPCNONE,	{RT, RB}},
+{"mfsrin",	X(31,659),	XRA_MASK,    PPC32,	TITAN,  	{RT, RB}},
 
 {"stdbrx",	X(31,660),	X_MASK, CELL|POWER7|PPCA2, PPCNONE,	{RS, RA0, RB}},
 
@@ -4711,7 +4733,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"extsb",	XRC(31,954,0),	XRB_MASK,    PPC,	PPCNONE,	{RA, RS}},
 {"extsb.",	XRC(31,954,1),	XRB_MASK,    PPC,	PPCNONE,	{RA, RS}},
 
-{"iccci",	X(31,966),     XRT_MASK, PPC403|PPC440,	PPC476,		{RA, RB}},
+{"iccci",	X(31,966),     XRT_MASK, PPC403|PPC440|TITAN,	PPC476,		{RA, RB}},
 {"ici",		X(31,966),	XRARB_MASK,  PPCA2|PPC476, PPCNONE,	{CT}},
 
 {"divduo",	XO(31,457,1,0),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
@@ -4738,7 +4760,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"icbiep",	XRT(31,991,0),	XRT_MASK, E500MC|PPCA2,	PPCNONE,	{RA, RB}},
 
-{"icread",	X(31,998),     XRT_MASK, PPC403|PPC440|PPC476, PPCNONE,	{RA, RB}},
+{"icread",	X(31,998),     XRT_MASK, PPC403|PPC440|PPC476|TITAN, PPCNONE,	{RA, RB}},
 
 {"nabso",	XO(31,488,1,0),	XORB_MASK,   M601,	PPCNONE,	{RT, RA}},
 {"nabso.",	XO(31,488,1,1),	XORB_MASK,   M601,	PPCNONE,	{RT, RA}},
@@ -4749,7 +4771,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"divwo",	XO(31,491,1,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
 {"divwo.",	XO(31,491,1,1),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
 
-{"tlbli",	X(31,1010),	XRTRA_MASK,  PPC,	PPCNONE,	{RB}},
+{"tlbli",	X(31,1010),	XRTRA_MASK,  PPC,	TITAN,  	{RB}},
 
 {"stdcix",	X(31,1013),	X_MASK,      POWER6,	PPCNONE,	{RS, RA0, RB}},
 
@@ -4854,8 +4876,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"fadds",	A(59,21,0),	AFRC_MASK,   PPC,	PPCNONE,	{FRT, FRA, FRB}},
 {"fadds.",	A(59,21,1),	AFRC_MASK,   PPC,	PPCNONE,	{FRT, FRA, FRB}},
 
-{"fsqrts",	A(59,22,0),    AFRAFRC_MASK, PPC,	PPCNONE,	{FRT, FRB}},
-{"fsqrts.",	A(59,22,1),    AFRAFRC_MASK, PPC,	PPCNONE,	{FRT, FRB}},
+{"fsqrts",	A(59,22,0),    AFRAFRC_MASK, PPC,	TITAN,  	{FRT, FRB}},
+{"fsqrts.",	A(59,22,1),    AFRAFRC_MASK, PPC,	TITAN,  	{FRT, FRB}},
 
 {"fres",	A(59,24,0),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
 {"fres",	A(59,24,0),   AFRALFRC_MASK, PPC,	POWER7,		{FRT, FRB, A_L}},
@@ -5141,8 +5163,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"fadd.",	A(63,21,1),	AFRC_MASK,   PPCCOM,	PPCNONE,	{FRT, FRA, FRB}},
 {"fa.",		A(63,21,1),	AFRC_MASK,   PWRCOM,	PPCNONE,	{FRT, FRA, FRB}},
 
-{"fsqrt",	A(63,22,0),    AFRAFRC_MASK, PPCPWR2,	PPCNONE,	{FRT, FRB}},
-{"fsqrt.",	A(63,22,1),    AFRAFRC_MASK, PPCPWR2,	PPCNONE,	{FRT, FRB}},
+{"fsqrt",	A(63,22,0),    AFRAFRC_MASK, PPCPWR2,	TITAN,  	{FRT, FRB}},
+{"fsqrt.",	A(63,22,1),    AFRAFRC_MASK, PPCPWR2,	TITAN,  	{FRT, FRB}},
 
 {"fsel",	A(63,23,0),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
 {"fsel.",	A(63,23,1),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: PATCH [version 2]: Add AppliedMicro Titan (APM83xxx) support
  2009-11-20 16:04   ` PATCH [version 2]: " Philipp Tomsich
@ 2010-02-08  2:00     ` Alan Modra
  0 siblings, 0 replies; 4+ messages in thread
From: Alan Modra @ 2010-02-08  2:00 UTC (permalink / raw)
  To: Philipp Tomsich; +Cc: binutils

Applied.

include/
	* opcode/ppc.h (PPC_OPCODE_TITAN): Define.
bfd/
	* archures.c (bfd_mach_ppc_titan): Define.
	* bfd-in2.h: Regenerate.
	* cpu-powerpc.c (bfd_powerpc_archs): Add titan entry.
opcodes/
	* ppc-dis.c (ppc_opts): Add titan entry.
	* ppc-opc.c (TITAN, MULHW): Define.
	(powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
gas/
	* config/tc-ppc.c (md_show_usage): Mention -mtitan.  Don't use tabs.
	(ppc_mach): Handle titan.
	* doc/c-ppc.texi: Mention -mtitan.
gas/testsuite/
	* gas/ppc/titan.d, * gas/ppc/titan.s: New test.
	* gas/ppc/ppc.exp: Run it.

Index: bfd/archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.146
diff -u -p -r1.146 archures.c
--- bfd/archures.c	4 Jan 2010 02:32:55 -0000	1.146
+++ bfd/archures.c	8 Feb 2010 01:16:07 -0000
@@ -230,7 +230,8 @@ DESCRIPTION
 .#define bfd_mach_ppc_7400	7400
 .#define bfd_mach_ppc_e500      500
 .#define bfd_mach_ppc_e500mc    5001
-.#define bfd_mach_ppc_e500mc64    5005
+.#define bfd_mach_ppc_e500mc64  5005
+.#define bfd_mach_ppc_titan     83
 .  bfd_arch_rs6000,    {* IBM RS/6000 *}
 .#define bfd_mach_rs6k		6000
 .#define bfd_mach_rs6k_rs1	6001
Index: bfd/cpu-powerpc.c
===================================================================
RCS file: /cvs/src/src/bfd/cpu-powerpc.c,v
retrieving revision 1.23
diff -u -p -r1.23 cpu-powerpc.c
--- bfd/cpu-powerpc.c	4 Jan 2010 02:32:55 -0000	1.23
+++ bfd/cpu-powerpc.c	8 Feb 2010 01:16:08 -0000
@@ -338,6 +338,20 @@ const bfd_arch_info_type bfd_powerpc_arc
     FALSE, /* not the default */
     powerpc_compatible,
     bfd_default_scan,
+    &bfd_powerpc_archs[18]
+  },
+  {
+    32, /* 32 bits in a word */
+    32, /* 32 bits in an address */
+    8,  /* 8 bits in a byte */
+    bfd_arch_powerpc,
+    bfd_mach_ppc_titan,
+    "powerpc",
+    "powerpc:titan",
+    3,
+    FALSE, /* not the default */
+    powerpc_compatible,
+    bfd_default_scan,
     0
   }
 };
Index: gas/config/tc-ppc.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-ppc.c,v
retrieving revision 1.162
diff -u -p -r1.162 tc-ppc.c
--- gas/config/tc-ppc.c	23 Jan 2010 12:05:32 -0000	1.162
+++ gas/config/tc-ppc.c	8 Feb 2010 01:16:17 -0000
@@ -1178,57 +1178,58 @@ md_show_usage (FILE *stream)
 {
   fprintf (stream, _("\
 PowerPC options:\n\
--a32			generate ELF32/XCOFF32\n\
--a64			generate ELF64/XCOFF64\n\
--u			ignored\n\
--mpwrx, -mpwr2		generate code for POWER/2 (RIOS2)\n\
--mpwr			generate code for POWER (RIOS1)\n\
--m601			generate code for PowerPC 601\n\
+-a32                    generate ELF32/XCOFF32\n\
+-a64                    generate ELF64/XCOFF64\n\
+-u                      ignored\n\
+-mpwrx, -mpwr2          generate code for POWER/2 (RIOS2)\n\
+-mpwr                   generate code for POWER (RIOS1)\n\
+-m601                   generate code for PowerPC 601\n\
 -mppc, -mppc32, -m603, -m604\n\
-			generate code for PowerPC 603/604\n\
--m403			generate code for PowerPC 403\n\
--m405			generate code for PowerPC 405\n\
--m440			generate code for PowerPC 440\n\
--m464			generate code for PowerPC 464\n\
--m476			generate code for PowerPC 476\n\
+                        generate code for PowerPC 603/604\n\
+-m403                   generate code for PowerPC 403\n\
+-m405                   generate code for PowerPC 405\n\
+-m440                   generate code for PowerPC 440\n\
+-m464                   generate code for PowerPC 464\n\
+-m476                   generate code for PowerPC 476\n\
 -m7400, -m7410, -m7450, -m7455\n\
-			generate code for PowerPC 7400/7410/7450/7455\n\
--m750cl			generate code for PowerPC 750cl\n"));
+                        generate code for PowerPC 7400/7410/7450/7455\n\
+-m750cl                 generate code for PowerPC 750cl\n"));
   fprintf (stream, _("\
--mppc64, -m620		generate code for PowerPC 620/625/630\n\
--mppc64bridge		generate code for PowerPC 64, including bridge insns\n\
--mbooke			generate code for 32-bit PowerPC BookE\n\
--ma2			generate code for A2 architecture\n\
--mpower4		generate code for Power4 architecture\n\
--mpower5		generate code for Power5 architecture\n\
--mpower6		generate code for Power6 architecture\n\
--mpower7		generate code for Power7 architecture\n\
--mcell			generate code for Cell Broadband Engine architecture\n\
--mcom			generate code Power/PowerPC common instructions\n\
--many			generate code for any architecture (PWR/PWRX/PPC)\n"));
+-mppc64, -m620          generate code for PowerPC 620/625/630\n\
+-mppc64bridge           generate code for PowerPC 64, including bridge insns\n\
+-mbooke                 generate code for 32-bit PowerPC BookE\n\
+-ma2                    generate code for A2 architecture\n\
+-mpower4                generate code for Power4 architecture\n\
+-mpower5                generate code for Power5 architecture\n\
+-mpower6                generate code for Power6 architecture\n\
+-mpower7                generate code for Power7 architecture\n\
+-mcell                  generate code for Cell Broadband Engine architecture\n\
+-mcom                   generate code Power/PowerPC common instructions\n\
+-many                   generate code for any architecture (PWR/PWRX/PPC)\n"));
   fprintf (stream, _("\
--maltivec		generate code for AltiVec\n\
--mvsx			generate code for Vector-Scalar (VSX) instructions\n\
--me300			generate code for PowerPC e300 family\n\
--me500, -me500x2	generate code for Motorola e500 core complex\n\
--me500mc,		generate code for Freescale e500mc core complex\n\
--me500mc64,		generate code for Freescale e500mc64 core complex\n\
--mspe			generate code for Motorola SPE instructions\n\
--mregnames		Allow symbolic names for registers\n\
--mno-regnames		Do not allow symbolic names for registers\n"));
+-maltivec               generate code for AltiVec\n\
+-mvsx                   generate code for Vector-Scalar (VSX) instructions\n\
+-me300                  generate code for PowerPC e300 family\n\
+-me500, -me500x2        generate code for Motorola e500 core complex\n\
+-me500mc,               generate code for Freescale e500mc core complex\n\
+-me500mc64,             generate code for Freescale e500mc64 core complex\n\
+-mspe                   generate code for Motorola SPE instructions\n\
+-mtitan                 generate code for AppliedMicro Titan core complex\n\
+-mregnames              Allow symbolic names for registers\n\
+-mno-regnames           Do not allow symbolic names for registers\n"));
 #ifdef OBJ_ELF
   fprintf (stream, _("\
--mrelocatable		support for GCC's -mrelocatble option\n\
--mrelocatable-lib	support for GCC's -mrelocatble-lib option\n\
--memb			set PPC_EMB bit in ELF flags\n\
+-mrelocatable           support for GCC's -mrelocatble option\n\
+-mrelocatable-lib       support for GCC's -mrelocatble-lib option\n\
+-memb                   set PPC_EMB bit in ELF flags\n\
 -mlittle, -mlittle-endian, -l, -le\n\
-			generate code for a little endian machine\n\
+                        generate code for a little endian machine\n\
 -mbig, -mbig-endian, -b, -be\n\
-			generate code for a big endian machine\n\
--msolaris		generate code for Solaris\n\
--mno-solaris		do not generate code for Solaris\n\
--V			print assembler version number\n\
--Qy, -Qn		ignored\n"));
+                        generate code for a big endian machine\n\
+-msolaris               generate code for Solaris\n\
+-mno-solaris            do not generate code for Solaris\n\
+-V                      print assembler version number\n\
+-Qy, -Qn                ignored\n"));
 #endif
 }
 \f
@@ -1291,6 +1292,8 @@ ppc_mach (void)
     return bfd_mach_ppc64;
   else if (ppc_arch () == bfd_arch_rs6000)
     return bfd_mach_rs6k;
+  else if (ppc_cpu & PPC_OPCODE_TITAN)
+    return bfd_mach_ppc_titan;
   else
     return bfd_mach_ppc;
 }
Index: gas/doc/c-ppc.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-ppc.texi,v
retrieving revision 1.18
diff -u -p -r1.18 c-ppc.texi
--- gas/doc/c-ppc.texi	2 Oct 2009 14:42:41 -0000	1.18
+++ gas/doc/c-ppc.texi	8 Feb 2010 01:16:17 -0000
@@ -1,4 +1,4 @@
-@c Copyright 2001, 2002, 2003, 2005, 2006, 2007, 2008
+@c Copyright 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2010
 @c Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
@@ -70,6 +70,9 @@ Generate code for Motorola e500 core com
 @item -mspe
 Generate code for Motorola SPE instructions.
 
+@item -mtitan
+Generate code for AppliedMicro Titan core complex.
+
 @item -mppc64bridge
 Generate code for PowerPC 64, including bridge insns.
 
Index: gas/testsuite/gas/ppc/ppc.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/ppc.exp,v
retrieving revision 1.26
diff -u -p -r1.26 ppc.exp
--- gas/testsuite/gas/ppc/ppc.exp	2 Oct 2009 14:42:42 -0000	1.26
+++ gas/testsuite/gas/ppc/ppc.exp	8 Feb 2010 01:16:20 -0000
@@ -50,5 +50,6 @@ if { [istarget powerpc*-*-*] } then {
 	run_dump_test "power7"
 	run_dump_test "vsx"
 	run_dump_test "476"
+	run_dump_test "titan"
     }
 }
Index: gas/testsuite/gas/ppc/titan.d
===================================================================
RCS file: gas/testsuite/gas/ppc/titan.d
diff -N gas/testsuite/gas/ppc/titan.d
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/ppc/titan.d	8 Feb 2010 01:16:20 -0000
@@ -0,0 +1,267 @@
+#as: -mtitan
+#objdump: -dr -Mtitan
+#name: AppliedMicro Titan tests
+
+.*: +file format elf(32)?(64)?-powerpc.*
+
+Disassembly of section \.text:
+
+0+0000000 <start>:
+   0:	4e 80 00 20 	blr
+   4:	0c 81 00 00 	tweqi   r1,0
+   8:	10 41 01 58 	macchw  r2,r1,r0
+   c:	10 41 01 59 	macchw\. r2,r1,r0
+  10:	10 41 05 58 	macchwo r2,r1,r0
+  14:	10 41 05 59 	macchwo\. r2,r1,r0
+  18:	10 41 01 d8 	macchws r2,r1,r0
+  1c:	10 41 01 d9 	macchws\. r2,r1,r0
+  20:	10 41 05 d8 	macchwso r2,r1,r0
+  24:	10 41 05 d9 	macchwso\. r2,r1,r0
+  28:	10 41 01 98 	macchwsu r2,r1,r0
+  2c:	10 41 01 99 	macchwsu\. r2,r1,r0
+  30:	10 41 05 98 	macchwsuo r2,r1,r0
+  34:	10 41 05 99 	macchwsuo\. r2,r1,r0
+  38:	10 41 01 18 	macchwu r2,r1,r0
+  3c:	10 41 01 19 	macchwu\. r2,r1,r0
+  40:	10 41 05 18 	macchwuo r2,r1,r0
+  44:	10 41 05 19 	macchwuo\. r2,r1,r0
+  48:	10 41 00 58 	machhw  r2,r1,r0
+  4c:	10 41 00 59 	machhw\. r2,r1,r0
+  50:	10 41 04 58 	machhwo r2,r1,r0
+  54:	10 41 04 59 	machhwo\. r2,r1,r0
+  58:	10 41 00 d8 	machhws r2,r1,r0
+  5c:	10 41 00 d9 	machhws\. r2,r1,r0
+  60:	10 41 04 d8 	machhwso r2,r1,r0
+  64:	10 41 04 d9 	machhwso\. r2,r1,r0
+  68:	10 41 00 98 	machhwsu r2,r1,r0
+  6c:	10 41 00 99 	machhwsu\. r2,r1,r0
+  70:	10 41 04 98 	machhwsuo r2,r1,r0
+  74:	10 41 04 99 	machhwsuo\. r2,r1,r0
+  78:	10 41 00 18 	machhwu r2,r1,r0
+  7c:	10 41 00 19 	machhwu\. r2,r1,r0
+  80:	10 41 04 18 	machhwuo r2,r1,r0
+  84:	10 41 04 19 	machhwuo\. r2,r1,r0
+  88:	10 41 03 58 	maclhw  r2,r1,r0
+  8c:	10 41 03 59 	maclhw\. r2,r1,r0
+  90:	10 41 07 58 	maclhwo r2,r1,r0
+  94:	10 41 07 59 	maclhwo\. r2,r1,r0
+  98:	10 41 03 d8 	maclhws r2,r1,r0
+  9c:	10 41 03 d9 	maclhws\. r2,r1,r0
+  a0:	10 41 07 d8 	maclhwso r2,r1,r0
+  a4:	10 41 07 d9 	maclhwso\. r2,r1,r0
+  a8:	10 41 03 98 	maclhwsu r2,r1,r0
+  ac:	10 41 03 99 	maclhwsu\. r2,r1,r0
+  b0:	10 41 07 98 	maclhwsuo r2,r1,r0
+  b4:	10 41 07 99 	maclhwsuo\. r2,r1,r0
+  b8:	10 41 03 18 	maclhwu r2,r1,r0
+  bc:	10 41 03 19 	maclhwu\. r2,r1,r0
+  c0:	10 41 07 18 	maclhwuo r2,r1,r0
+  c4:	10 41 07 19 	maclhwuo\. r2,r1,r0
+  c8:	10 41 01 5c 	nmacchw r2,r1,r0
+  cc:	10 41 01 5d 	nmacchw\. r2,r1,r0
+  d0:	10 41 05 5c 	nmacchwo r2,r1,r0
+  d4:	10 41 05 5d 	nmacchwo\. r2,r1,r0
+  d8:	10 41 01 dc 	nmacchws r2,r1,r0
+  dc:	10 41 01 dd 	nmacchws\. r2,r1,r0
+  e0:	10 41 05 dc 	nmacchwso r2,r1,r0
+  e4:	10 41 05 dd 	nmacchwso\. r2,r1,r0
+  e8:	10 41 00 5c 	nmachhw r2,r1,r0
+  ec:	10 41 00 5d 	nmachhw\. r2,r1,r0
+  f0:	10 41 04 5c 	nmachhwo r2,r1,r0
+  f4:	10 41 04 5d 	nmachhwo\. r2,r1,r0
+  f8:	10 41 00 dc 	nmachhws r2,r1,r0
+  fc:	10 41 00 dd 	nmachhws\. r2,r1,r0
+ 100:	10 41 04 dc 	nmachhwso r2,r1,r0
+ 104:	10 41 04 dd 	nmachhwso\. r2,r1,r0
+ 108:	10 41 03 5c 	nmaclhw r2,r1,r0
+ 10c:	10 41 03 5d 	nmaclhw\. r2,r1,r0
+ 110:	10 41 07 5c 	nmaclhwo r2,r1,r0
+ 114:	10 41 07 5d 	nmaclhwo\. r2,r1,r0
+ 118:	10 41 03 dc 	nmaclhws r2,r1,r0
+ 11c:	10 41 03 dd 	nmaclhws\. r2,r1,r0
+ 120:	10 41 07 dc 	nmaclhwso r2,r1,r0
+ 124:	10 41 07 dd 	nmaclhwso\. r2,r1,r0
+ 128:	10 41 01 50 	mulchw  r2,r1,r0
+ 12c:	10 41 01 51 	mulchw\. r2,r1,r0
+ 130:	10 41 01 10 	mulchwu r2,r1,r0
+ 134:	10 41 01 11 	mulchwu\. r2,r1,r0
+ 138:	10 41 00 50 	mulhhw  r2,r1,r0
+ 13c:	10 41 00 51 	mulhhw\. r2,r1,r0
+ 140:	10 41 00 10 	mulhhwu r2,r1,r0
+ 144:	10 41 00 11 	mulhhwu\. r2,r1,r0
+ 148:	10 41 03 50 	mullhw  r2,r1,r0
+ 14c:	10 41 03 51 	mullhw\. r2,r1,r0
+ 150:	10 41 03 10 	mullhwu r2,r1,r0
+ 154:	10 41 03 11 	mullhwu\. r2,r1,r0
+ 158:	7c 22 00 9c 	dlmzb   r2,r1,r0
+ 15c:	7c 22 00 9d 	dlmzb\.  r2,r1,r0
+ 160:	7c 02 0b 8c 	dccci   r2,r1
+ 164:	7c 02 0f 8c 	iccci   r2,r1
+ 168:	7c 02 0b 0c 	dcblc   r2,r1
+ 16c:	7c 02 0b 0c 	dcblc   r2,r1
+ 170:	7c 22 0b 0c 	dcblc   1,r2,r1
+ 174:	7c 02 09 4c 	dcbtls  r2,r1
+ 178:	7c 02 09 4c 	dcbtls  r2,r1
+ 17c:	7c 22 09 4c 	dcbtls  1,r2,r1
+ 180:	7c 02 09 0c 	dcbtstls r2,r1
+ 184:	7c 02 09 0c 	dcbtstls r2,r1
+ 188:	7c 22 09 0c 	dcbtstls 1,r2,r1
+ 18c:	7c 02 09 cc 	icblc   r2,r1
+ 190:	7c 02 09 cc 	icblc   r2,r1
+ 194:	7c 22 09 cc 	icblc   1,r2,r1
+ 198:	7c 02 0b cc 	icbtls  r2,r1
+ 19c:	7c 02 0b cc 	icbtls  r2,r1
+ 1a0:	7c 22 0b cc 	icbtls  1,r2,r1
+ 1a4:	7c 41 02 8c 	dcread  r2,r1,r0
+ 1a8:	7c 02 0f cc 	icread  r2,r1
+ 1ac:	7c 41 02 9c 	mfpmr   r2,1
+ 1b0:	7c 22 02 9c 	mfpmr   r1,2
+ 1b4:	7c 81 02 a6 	mfxer   r4
+ 1b8:	7c 81 02 a6 	mfxer   r4
+ 1bc:	7c 88 02 a6 	mflr    r4
+ 1c0:	7c 88 02 a6 	mflr    r4
+ 1c4:	7c 89 02 a6 	mfctr   r4
+ 1c8:	7c 89 02 a6 	mfctr   r4
+ 1cc:	7c 96 02 a6 	mfdec   r4
+ 1d0:	7c 96 02 a6 	mfdec   r4
+ 1d4:	7c 9a 02 a6 	mfsrr0  r4
+ 1d8:	7c 9a 02 a6 	mfsrr0  r4
+ 1dc:	7c 9b 02 a6 	mfsrr1  r4
+ 1e0:	7c 9b 02 a6 	mfsrr1  r4
+ 1e4:	7c 90 0a a6 	mfpid   r4
+ 1e8:	7c 90 0a a6 	mfpid   r4
+ 1ec:	7c 9a 0a a6 	mfcsrr0 r4
+ 1f0:	7c 9a 0a a6 	mfcsrr0 r4
+ 1f4:	7c 9b 0a a6 	mfcsrr1 r4
+ 1f8:	7c 9b 0a a6 	mfcsrr1 r4
+ 1fc:	7c 9d 0a a6 	mfdear  r4
+ 200:	7c 9d 0a a6 	mfdear  r4
+ 204:	7c 9e 0a a6 	mfesr   r4
+ 208:	7c 9e 0a a6 	mfesr   r4
+ 20c:	7c 9f 0a a6 	mfivpr  r4
+ 210:	7c 9f 0a a6 	mfivpr  r4
+ 214:	7c 80 42 a6 	mfusprg0 r4
+ 218:	7c 80 42 a6 	mfusprg0 r4
+ 21c:	7c 84 42 a6 	mfsprg  r4,4
+ 220:	7c 84 42 a6 	mfsprg  r4,4
+ 224:	7c 85 42 a6 	mfsprg  r4,5
+ 228:	7c 85 42 a6 	mfsprg  r4,5
+ 22c:	7c 86 42 a6 	mfsprg  r4,6
+ 230:	7c 86 42 a6 	mfsprg  r4,6
+ 234:	7c 87 42 a6 	mfsprg  r4,7
+ 238:	7c 87 42 a6 	mfsprg  r4,7
+ 23c:	7c 8c 42 a6 	mftb    r4
+ 240:	7c 8c 42 a6 	mftb    r4
+ 244:	7c 8c 42 a6 	mftb    r4
+ 248:	7c 8d 42 a6 	mftbu   r4
+ 24c:	7c 8d 42 a6 	mftbu   r4
+ 250:	7c 90 42 a6 	mfsprg  r4,0
+ 254:	7c 90 42 a6 	mfsprg  r4,0
+ 258:	7c 91 42 a6 	mfsprg  r4,1
+ 25c:	7c 91 42 a6 	mfsprg  r4,1
+ 260:	7c 92 42 a6 	mfsprg  r4,2
+ 264:	7c 92 42 a6 	mfsprg  r4,2
+ 268:	7c 93 42 a6 	mfsprg  r4,3
+ 26c:	7c 93 42 a6 	mfsprg  r4,3
+ 270:	7c 9e 42 a6 	mfpir   r4
+ 274:	7c 9e 42 a6 	mfpir   r4
+ 278:	7c 9f 42 a6 	mfpvr   r4
+ 27c:	7c 9f 42 a6 	mfpvr   r4
+ 280:	7c 90 4a a6 	mfdbsr  r4
+ 284:	7c 90 4a a6 	mfdbsr  r4
+ 288:	7c 94 4a a6 	mfdbcr0 r4
+ 28c:	7c 94 4a a6 	mfdbcr0 r4
+ 290:	7c 95 4a a6 	mfdbcr1 r4
+ 294:	7c 95 4a a6 	mfdbcr1 r4
+ 298:	7c 96 4a a6 	mfdbcr2 r4
+ 29c:	7c 96 4a a6 	mfdbcr2 r4
+ 2a0:	7c 98 4a a6 	mfiac1  r4
+ 2a4:	7c 98 4a a6 	mfiac1  r4
+ 2a8:	7c 99 4a a6 	mfiac2  r4
+ 2ac:	7c 99 4a a6 	mfiac2  r4
+ 2b0:	7c 9a 4a a6 	mfiac3  r4
+ 2b4:	7c 9a 4a a6 	mfiac3  r4
+ 2b8:	7c 9b 4a a6 	mfiac4  r4
+ 2bc:	7c 9b 4a a6 	mfiac4  r4
+ 2c0:	7c 9c 4a a6 	mfdac1  r4
+ 2c4:	7c 9c 4a a6 	mfdac1  r4
+ 2c8:	7c 9d 4a a6 	mfdac2  r4
+ 2cc:	7c 9d 4a a6 	mfdac2  r4
+ 2d0:	7c 9e 4a a6 	mfdvc1  r4
+ 2d4:	7c 9e 4a a6 	mfdvc1  r4
+ 2d8:	7c 9f 4a a6 	mfdvc2  r4
+ 2dc:	7c 9f 4a a6 	mfdvc2  r4
+ 2e0:	7c 90 52 a6 	mftsr   r4
+ 2e4:	7c 90 52 a6 	mftsr   r4
+ 2e8:	7c 94 52 a6 	mftcr   r4
+ 2ec:	7c 94 52 a6 	mftcr   r4
+ 2f0:	7c 90 62 a6 	mfivor0 r4
+ 2f4:	7c 90 62 a6 	mfivor0 r4
+ 2f8:	7c 91 62 a6 	mfivor1 r4
+ 2fc:	7c 91 62 a6 	mfivor1 r4
+ 300:	7c 92 62 a6 	mfivor2 r4
+ 304:	7c 92 62 a6 	mfivor2 r4
+ 308:	7c 93 62 a6 	mfivor3 r4
+ 30c:	7c 93 62 a6 	mfivor3 r4
+ 310:	7c 94 62 a6 	mfivor4 r4
+ 314:	7c 94 62 a6 	mfivor4 r4
+ 318:	7c 95 62 a6 	mfivor5 r4
+ 31c:	7c 95 62 a6 	mfivor5 r4
+ 320:	7c 96 62 a6 	mfivor6 r4
+ 324:	7c 96 62 a6 	mfivor6 r4
+ 328:	7c 97 62 a6 	mfivor7 r4
+ 32c:	7c 97 62 a6 	mfivor7 r4
+ 330:	7c 98 62 a6 	mfivor8 r4
+ 334:	7c 98 62 a6 	mfivor8 r4
+ 338:	7c 99 62 a6 	mfivor9 r4
+ 33c:	7c 99 62 a6 	mfivor9 r4
+ 340:	7c 9a 62 a6 	mfivor10 r4
+ 344:	7c 9a 62 a6 	mfivor10 r4
+ 348:	7c 9b 62 a6 	mfivor11 r4
+ 34c:	7c 9b 62 a6 	mfivor11 r4
+ 350:	7c 9c 62 a6 	mfivor12 r4
+ 354:	7c 9c 62 a6 	mfivor12 r4
+ 358:	7c 9d 62 a6 	mfivor13 r4
+ 35c:	7c 9d 62 a6 	mfivor13 r4
+ 360:	7c 9e 62 a6 	mfivor14 r4
+ 364:	7c 9e 62 a6 	mfivor14 r4
+ 368:	7c 9f 62 a6 	mfivor15 r4
+ 36c:	7c 9f 62 a6 	mfivor15 r4
+ 370:	7c 93 82 a6 	mfivor35 r4
+ 374:	7c 93 82 a6 	mfivor35 r4
+ 378:	7c 9a 8a a6 	mfdc_dat r4
+ 37c:	7c 9a 8a a6 	mfdc_dat r4
+ 380:	7c 9b 8a a6 	mfmcsrr1 r4
+ 384:	7c 9b 8a a6 	mfmcsrr1 r4
+ 388:	7c 9c 8a a6 	mfmcsr  r4
+ 38c:	7c 9c 8a a6 	mfmcsr  r4
+ 390:	7c 90 da a6 	mfivndx r4
+ 394:	7c 90 da a6 	mfivndx r4
+ 398:	7c 91 da a6 	mfdvndx r4
+ 39c:	7c 91 da a6 	mfdvndx r4
+ 3a0:	7c 92 da a6 	mfivlim r4
+ 3a4:	7c 92 da a6 	mfivlim r4
+ 3a8:	7c 93 da a6 	mfdvlim r4
+ 3ac:	7c 93 da a6 	mfdvlim r4
+ 3b0:	7c 94 da a6 	mfclcsr r4
+ 3b4:	7c 94 da a6 	mfclcsr r4
+ 3b8:	7c 98 da a6 	mfccr1  r4
+ 3bc:	7c 98 da a6 	mfccr1  r4
+ 3c0:	7c 9b e2 a6 	mfrstcfg r4
+ 3c4:	7c 9b e2 a6 	mfrstcfg r4
+ 3c8:	7c 9c e2 a6 	mfdcdbtrl r4
+ 3cc:	7c 9c e2 a6 	mfdcdbtrl r4
+ 3d0:	7c 9d e2 a6 	mfdcdbtrh r4
+ 3d4:	7c 9d e2 a6 	mfdcdbtrh r4
+ 3d8:	7c 9f e2 a6 	mficdbtr r4
+ 3dc:	7c 9f e2 a6 	mficdbtr r4
+ 3e0:	7c 92 ea a6 	mfmmucr r4
+ 3e4:	7c 92 ea a6 	mfmmucr r4
+ 3e8:	7c 93 ea a6 	mfccr0  r4
+ 3ec:	7c 93 ea a6 	mfccr0  r4
+ 3f0:	7c 93 f2 a6 	mficdbdr r4
+ 3f4:	7c 93 f2 a6 	mficdbdr r4
+ 3f8:	7c 93 fa a6 	mfdbdr  r4
+ 3fc:	7c 93 fa a6 	mfdbdr  r4
+ 400:	7c 96 0b a6 	mtdecar r4
+ 404:	7c 96 0b a6 	mtdecar r4
Index: gas/testsuite/gas/ppc/titan.s
===================================================================
RCS file: gas/testsuite/gas/ppc/titan.s
diff -N gas/testsuite/gas/ppc/titan.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/ppc/titan.s	8 Feb 2010 01:16:20 -0000
@@ -0,0 +1,261 @@
+# AppliedMicro Titan tests 
+	.section ".text"
+start:
+	blr
+	tweqi		1, 0
+	macchw		2, 1, 0
+	macchw.		2, 1, 0
+	macchwo		2, 1, 0
+	macchwo.	2, 1, 0
+	macchws		2, 1, 0
+	macchws.	2, 1, 0
+	macchwso	2, 1, 0
+	macchwso.	2, 1, 0
+	macchwsu	2, 1, 0
+	macchwsu.	2, 1, 0
+	macchwsuo	2, 1, 0
+	macchwsuo.	2, 1, 0
+	macchwu		2, 1, 0
+	macchwu.	2, 1, 0
+	macchwuo	2, 1, 0
+	macchwuo.	2, 1, 0
+	machhw		2, 1, 0
+	machhw.		2, 1, 0
+	machhwo		2, 1, 0
+	machhwo.	2, 1, 0
+	machhws		2, 1, 0
+	machhws.	2, 1, 0
+	machhwso	2, 1, 0
+	machhwso.	2, 1, 0
+	machhwsu	2, 1, 0
+	machhwsu.	2, 1, 0
+	machhwsuo	2, 1, 0
+	machhwsuo.	2, 1, 0
+	machhwu		2, 1, 0
+	machhwu.	2, 1, 0
+	machhwuo	2, 1, 0
+	machhwuo.	2, 1, 0
+	maclhw		2, 1, 0
+	maclhw.		2, 1, 0
+	maclhwo		2, 1, 0
+	maclhwo.	2, 1, 0
+	maclhws		2, 1, 0
+	maclhws.	2, 1, 0
+	maclhwso	2, 1, 0
+	maclhwso.	2, 1, 0
+	maclhwsu	2, 1, 0
+	maclhwsu.	2, 1, 0
+	maclhwsuo	2, 1, 0
+	maclhwsuo.	2, 1, 0
+	maclhwu		2, 1, 0
+	maclhwu.	2, 1, 0
+	maclhwuo	2, 1, 0
+	maclhwuo.	2, 1, 0
+	nmacchw		2, 1, 0
+	nmacchw.	2, 1, 0
+	nmacchwo	2, 1, 0
+	nmacchwo.	2, 1, 0
+	nmacchws	2, 1, 0
+	nmacchws.	2, 1, 0
+	nmacchwso	2, 1, 0
+	nmacchwso.	2, 1, 0	
+	nmachhw		2, 1, 0
+	nmachhw.	2, 1, 0
+	nmachhwo	2, 1, 0
+	nmachhwo.	2, 1, 0
+	nmachhws	2, 1, 0
+	nmachhws.	2, 1, 0
+	nmachhwso	2, 1, 0
+	nmachhwso.	2, 1, 0
+	nmaclhw		2, 1, 0
+	nmaclhw.	2, 1, 0
+	nmaclhwo	2, 1, 0
+	nmaclhwo.	2, 1, 0
+	nmaclhws	2, 1, 0
+	nmaclhws.	2, 1, 0
+	nmaclhwso	2, 1, 0
+	nmaclhwso.	2, 1, 0
+	mulchw		2, 1, 0
+	mulchw.		2, 1, 0
+	mulchwu		2, 1, 0
+	mulchwu.	2, 1, 0
+	mulhhw		2, 1, 0
+	mulhhw.		2, 1, 0
+	mulhhwu		2, 1, 0
+	mulhhwu.	2, 1, 0
+	mullhw		2, 1, 0
+	mullhw.		2, 1, 0
+	mullhwu		2, 1, 0
+	mullhwu.	2, 1, 0
+	dlmzb		2, 1, 0
+	dlmzb.		2, 1, 0
+	dccci		2, 1
+	iccci		2, 1
+	dcblc		0, 2, 1
+	dcblc		2, 1
+	dcblc		1, 2, 1
+	dcbtls		0, 2, 1
+	dcbtls		2, 1
+	dcbtls		1, 2, 1
+	dcbtstls	0, 2, 1
+	dcbtstls	2, 1
+	dcbtstls	1, 2, 1
+	icblc		0, 2, 1
+	icblc		2, 1
+	icblc		1, 2, 1
+	icbtls		0, 2, 1
+	icbtls		2, 1
+	icbtls		1, 2, 1
+	dcread 		2, 1, 0
+	icread 		2, 1
+	mfpmr		2, 1
+	mfpmr		1, 2
+	mfspr		4, 0x001
+	mfxer		4
+	mfspr		4, 0x008
+	mflr		4
+	mfspr		4, 0x009
+	mfctr		4
+	mfspr		4, 0x016
+	mfdec		4
+	mfspr		4, 0x01a
+	mfsrr0		4
+	mfspr		4, 0x01b
+	mfsrr1		4
+	mfspr		4, 0x030
+	mfpid		4
+	mfspr		4, 0x03a
+	mfcsrr0		4
+	mfspr		4, 0x03b
+	mfcsrr1		4
+	mfspr		4, 0x03d
+	mfdear		4
+	mfspr		4, 0x03e
+	mfesr		4
+	mfspr		4, 0x03f
+	mfivpr		4
+	mfspr		4, 0x100
+	mfusprg0	4
+	mfspr		4, 0x104
+	mfsprg4		4
+	mfspr		4, 0x105
+	mfsprg5		4
+	mfspr		4, 0x106
+	mfsprg6		4
+	mfspr		4, 0x107
+	mfsprg7		4
+	mfspr		4, 0x10c
+	mftbl		4
+	mftb		4
+	mfspr		4, 0x10d
+	mftbu		4
+	mfspr		4, 0x110
+	mfsprg0		4
+	mfspr		4, 0x111
+	mfsprg1		4
+	mfspr		4, 0x112
+	mfsprg2		4
+	mfspr		4, 0x113
+	mfsprg3		4
+	mfspr		4, 0x11e
+	mfpir		4
+	mfspr		4, 0x11f
+	mfpvr		4
+	mfspr		4, 0x130
+	mfdbsr		4
+	mfspr		4, 0x134
+	mfdbcr0		4
+	mfspr		4, 0x135
+	mfdbcr1		4
+	mfspr		4, 0x136
+	mfdbcr2		4
+	mfspr		4, 0x138
+	mfiac1		4
+	mfspr		4, 0x139
+	mfiac2		4
+	mfspr		4, 0x13a
+	mfiac3		4
+	mfspr		4, 0x13b
+	mfiac4		4
+	mfspr		4, 0x13c
+	mfdac1		4
+	mfspr		4, 0x13d
+	mfdac2		4
+	mfspr		4, 0x13e
+	mfdvc1		4
+	mfspr		4, 0x13f
+	mfdvc2		4
+	mfspr		4, 0x150
+	mftsr		4
+	mfspr		4, 0x154
+	mftcr		4
+	mfspr		4, 0x190
+	mfivor0		4
+	mfspr		4, 0x191
+	mfivor1		4
+	mfspr		4, 0x192
+	mfivor2		4
+	mfspr		4, 0x193
+	mfivor3		4
+	mfspr		4, 0x194
+	mfivor4		4
+	mfspr		4, 0x195
+	mfivor5		4
+	mfspr		4, 0x196
+	mfivor6		4
+	mfspr		4, 0x197
+	mfivor7		4
+	mfspr		4, 0x198
+	mfivor8		4
+	mfspr		4, 0x199
+	mfivor9		4
+	mfspr		4, 0x19a
+	mfivor10	4
+	mfspr		4, 0x19b
+	mfivor11	4
+	mfspr		4, 0x19c
+	mfivor12	4
+	mfspr		4, 0x19d
+	mfivor13	4
+	mfspr		4, 0x19e
+	mfivor14	4
+	mfspr		4, 0x19f
+	mfivor15	4
+	mfspr		4, 0x213
+	mfivor35	4
+	mfspr		4, 0x23a
+	mfmcsrr0	4
+	mfspr		4, 0x23b
+	mfmcsrr1	4
+	mfspr		4, 0x23c
+	mfmcsr		4
+	mfspr		4, 0x370
+	mfivndx		4
+	mfspr		4, 0x371
+	mfdvndx		4
+	mfspr		4, 0x372
+	mfivlim		4
+	mfspr		4, 0x373
+	mfdvlim		4
+	mfspr		4, 0x374
+	mfclcsr		4
+	mfspr		4, 0x378
+	mfccr1		4
+	mfspr		4, 0x39b
+	mfrstcfg	4
+	mfspr		4, 0x39c
+	mfdcdbtrl	4
+	mfspr		4, 0x39d
+	mfdcdbtrh	4
+	mfspr		4, 0x39f
+	mficdbtr	4
+	mfspr		4, 0x3b2
+	mfmmucr		4
+	mfspr		4, 0x3b3
+	mfccr0		4
+	mfspr		4, 0x3d3
+	mficdbdr	4
+	mfspr		4, 0x3f3
+	mfdbdr		4
+	mtspr		0x036, 4
+	mtdecar		4
Index: include/opcode/ppc.h
===================================================================
RCS file: /cvs/src/src/include/opcode/ppc.h,v
retrieving revision 1.37
diff -u -p -r1.37 ppc.h
--- include/opcode/ppc.h	2 Oct 2009 14:42:42 -0000	1.37
+++ include/opcode/ppc.h	8 Feb 2010 01:16:22 -0000
@@ -1,6 +1,6 @@
 /* ppc.h -- Header file for PowerPC opcode table
    Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
-   2007, 2008, 2009 Free Software Foundation, Inc.
+   2007, 2008, 2009, 2010 Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support
 
 This file is part of GDB, GAS, and the GNU binutils.
@@ -168,11 +168,14 @@ extern const int powerpc_num_opcodes;
 #define PPC_OPCODE_VSX		 0x80000000
 
 /* Opcode is supported by A2.  */
-#define PPC_OPCODE_A2	 	0x100000000ULL
+#define PPC_OPCODE_A2	 	 0x100000000ULL
 
 /* Opcode is supported by PowerPC 476 processor.  */
 #define PPC_OPCODE_476		 0x200000000ULL
 
+/* Opcode is supported by AppliedMicro Titan core */
+#define PPC_OPCODE_TITAN         0x400000000ULL
+
 /* A macro to extract the major opcode from an instruction.  */
 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 \f
Index: opcodes/ppc-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-dis.c,v
retrieving revision 1.44
diff -u -p -r1.44 ppc-dis.c
--- opcodes/ppc-dis.c	4 Jan 2010 02:32:56 -0000	1.44
+++ opcodes/ppc-dis.c	8 Feb 2010 01:16:32 -0000
@@ -164,6 +164,9 @@ struct ppc_mopt ppc_opts[] = {
     0 },
   { "spe",     (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
     PPC_OPCODE_SPE },
+  { "titan",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32 
+                | PPC_OPCODE_PMR | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
+    0 },
   { "vsx",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC),
     PPC_OPCODE_VSX },
 };
Index: opcodes/ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.126
diff -u -p -r1.126 ppc-opc.c
--- opcodes/ppc-opc.c	2 Oct 2009 14:42:42 -0000	1.126
+++ opcodes/ppc-opc.c	8 Feb 2010 01:16:33 -0000
@@ -1,6 +1,6 @@
 /* ppc-opc.c -- PowerPC opcode list
    Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
-   2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
+   2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support
 
    This file is part of the GNU opcodes library.
@@ -1935,6 +1935,8 @@ extract_dm (unsigned long insn,
 #define PPCRFMCI	PPC_OPCODE_RFMCI
 #define E500MC  PPC_OPCODE_E500MC
 #define PPCA2	PPC_OPCODE_A2
+#define TITAN   PPC_OPCODE_TITAN  
+#define MULHW   PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
 \f
 /* The opcode table.
 
@@ -2017,16 +2019,16 @@ const struct powerpc_opcode powerpc_opco
 {"vmrghb",	VX (4,	12),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"psq_stx",	XW (4,	 7,0),	XW_MASK,     PPCPS,	PPCNONE,	{FRS,RA,RB,PSWM,PSQM}},
 {"vpkuhum",	VX (4,	14),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"mulhhwu",	XRC(4,	 8,0),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"mulhhwu.",	XRC(4,	 8,1),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"mulhhwu",	XRC(4,	 8,0),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
+{"mulhhwu.",	XRC(4,	 8,1),	X_MASK,      MULHW, 	PPCNONE,	{RT, RA, RB}},
 {"ps_sum0",	A  (4,	10,0),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
 {"ps_sum0.",	A  (4,	10,1),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
 {"ps_sum1",	A  (4,	11,0),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
 {"ps_sum1.",	A  (4,	11,1),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
 {"ps_muls0",	A  (4,	12,0),	AFRB_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRC}},
-{"machhwu",	XO (4,	12,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"machhwu",	XO (4,	12,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"ps_muls0.",	A  (4,	12,1),	AFRB_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRC}},
-{"machhwu.",	XO (4,	12,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"machhwu.",	XO (4,	12,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"ps_muls1",	A  (4,	13,0),	AFRB_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRC}},
 {"ps_muls1.",	A  (4,	13,1),	AFRB_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRC}},
 {"ps_madds0",	A  (4,	14,0),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
@@ -2081,13 +2083,13 @@ const struct powerpc_opcode powerpc_opco
 {"psq_stux",	XW (4,	39,0),	XW_MASK,     PPCPS,	PPCNONE,	{FRS,RA,RB,PSWM,PSQM}},
 {"vpkuwum",	VX (4,	78),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"ps_neg",	XRC(4,	40,0),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
-{"mulhhw",	XRC(4,	40,0),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"mulhhw",	XRC(4,	40,0),	X_MASK,      MULHW, 	PPCNONE,	{RT, RA, RB}},
 {"ps_neg.",	XRC(4,	40,1),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
-{"mulhhw.",	XRC(4,	40,1),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"machhw",	XO (4,	44,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"machhw.",	XO (4,	44,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmachhw",	XO (4,	46,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmachhw.",	XO (4,	46,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"mulhhw.",	XRC(4,	40,1),	X_MASK,      MULHW, 	PPCNONE,	{RT, RA, RB}},
+{"machhw",	XO (4,	44,0,0),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
+{"machhw.",	XO (4,	44,0,1),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
+{"nmachhw",	XO (4,	46,0,0),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
+{"nmachhw.",	XO (4,	46,0,1),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
 {"ps_cmpu1",	X  (4,	64), X_MASK|(3<<21), PPCPS,	PPCNONE,	{BF, FRA, FRB}},
 {"vadduwm",	VX (4,	128),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vmaxuw",	VX (4,	130),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
@@ -2097,15 +2099,15 @@ const struct powerpc_opcode powerpc_opco
 {"vpkuhus",	VX (4,	142),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"ps_mr",	XRC(4,	72,0),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
 {"ps_mr.",	XRC(4,	72,1),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
-{"machhwsu",	XO (4,	76,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"machhwsu.",	XO (4,	76,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"machhwsu",	XO (4,	76,0,0),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
+{"machhwsu.",	XO (4,	76,0,1),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
 {"ps_cmpo1",	X  (4,	96), X_MASK|(3<<21), PPCPS,	PPCNONE,	{BF, FRA, FRB}},
 {"vcmpeqfp",	VXR(4, 198,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vpkuwus",	VX (4, 206),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"machhws",	XO (4, 108,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"machhws.",	XO (4, 108,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmachhws",	XO (4, 110,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmachhws.",	XO (4, 110,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"machhws",	XO (4, 108,0,0),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
+{"machhws.",	XO (4, 108,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmachhws",	XO (4, 110,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmachhws.",	XO (4, 110,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vmaxsb",	VX (4, 258),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vslb",	VX (4, 260),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vmulosb",	VX (4, 264),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
@@ -2113,39 +2115,39 @@ const struct powerpc_opcode powerpc_opco
 {"vmrglb",	VX (4, 268),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vpkshus",	VX (4, 270),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"ps_nabs",	XRC(4, 136,0),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
-{"mulchwu",	XRC(4, 136,0),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"mulchwu",	XRC(4, 136,0),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
 {"ps_nabs.",	XRC(4, 136,1),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
-{"mulchwu.",	XRC(4, 136,1),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"macchwu",	XO (4, 140,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"macchwu.",	XO (4, 140,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"mulchwu.",	XRC(4, 136,1),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchwu",	XO (4, 140,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchwu.",	XO (4, 140,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vmaxsh",	VX (4, 322),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vslh",	VX (4, 324),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vmulosh",	VX (4, 328),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vrsqrtefp",	VX (4, 330),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
 {"vmrglh",	VX (4, 332),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vpkswus",	VX (4, 334),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"mulchw",	XRC(4, 168,0),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"mulchw.",	XRC(4, 168,1),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"macchw",	XO (4, 172,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"macchw.",	XO (4, 172,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmacchw",	XO (4, 174,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmacchw.",	XO (4, 174,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"mulchw",	XRC(4, 168,0),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
+{"mulchw.",	XRC(4, 168,1),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchw",	XO (4, 172,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchw.",	XO (4, 172,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmacchw",	XO (4, 174,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmacchw.",	XO (4, 174,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vaddcuw",	VX (4, 384),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vmaxsw",	VX (4, 386),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vslw",	VX (4, 388),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vexptefp",	VX (4, 394),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
 {"vmrglw",	VX (4, 396),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vpkshss",	VX (4, 398),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"macchwsu",	XO (4, 204,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"macchwsu.",	XO (4, 204,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"macchwsu",	XO (4, 204,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchwsu.",	XO (4, 204,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vsl",		VX (4, 452),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vcmpgefp",	VXR(4, 454,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vlogefp",	VX (4, 458),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
 {"vpkswss",	VX (4, 462),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"macchws",	XO (4, 236,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"macchws.",	XO (4, 236,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmacchws",	XO (4, 238,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmacchws.",	XO (4, 238,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"macchws",	XO (4, 236,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchws.",	XO (4, 236,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmacchws",	XO (4, 238,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmacchws.",	XO (4, 238,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evaddw",	VX (4, 512),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"vaddubs",	VX (4, 512),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"evaddiw",	VX (4, 514),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RB, UIMM}},
@@ -2322,17 +2324,17 @@ const struct powerpc_opcode powerpc_opco
 {"evlhhossplatx",VX(4, 782),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"vpkpx",	VX (4, 782),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"evlhhossplat",VX (4, 783),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_2, RA}},
-{"mullhwu",	XRC(4, 392,0),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"mullhwu",	XRC(4, 392,0),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evlwhex",	VX (4, 784),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"mullhwu.",	XRC(4, 392,1),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"mullhwu.",	XRC(4, 392,1),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evlwhe",	VX (4, 785),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_4, RA}},
 {"evlwhoux",	VX (4, 788),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evlwhou",	VX (4, 789),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_4, RA}},
 {"evlwhosx",	VX (4, 790),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evlwhos",	VX (4, 791),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_4, RA}},
-{"maclhwu",	XO (4, 396,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"maclhwu",	XO (4, 396,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evlwwsplatx",	VX (4, 792),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"maclhwu.",	XO (4, 396,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"maclhwu.",	XO (4, 396,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evlwwsplat",	VX (4, 793),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_4, RA}},
 {"evlwhsplatx",	VX (4, 796),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evlwhsplat",	VX (4, 797),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_4, RA}},
@@ -2358,27 +2360,27 @@ const struct powerpc_opcode powerpc_opco
 {"vcfsx",	VX (4, 842),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB, UIMM}},
 {"vspltish",	VX (4, 844),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, SIMM}},
 {"vupkhpx",	VX (4, 846),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
-{"mullhw",	XRC(4, 424,0),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"mullhw.",	XRC(4, 424,1),	X_MASK,  PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"maclhw",	XO (4, 428,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"maclhw.",	XO (4, 428,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmaclhw",	XO (4, 430,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmaclhw.",	XO (4, 430,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"mullhw",	XRC(4, 424,0),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
+{"mullhw.",	XRC(4, 424,1),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
+{"maclhw",	XO (4, 428,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"maclhw.",	XO (4, 428,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmaclhw",	XO (4, 430,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmaclhw.",	XO (4, 430,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vaddsws",	VX (4, 896),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vminsw",	VX (4, 898),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vsraw",	VX (4, 900),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vcmpgtsw",	VXR(4, 902,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vctuxs",	VX (4, 906),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB, UIMM}},
 {"vspltisw",	VX (4, 908),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, SIMM}},
-{"maclhwsu",	XO (4, 460,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"maclhwsu.",	XO (4, 460,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"maclhwsu",	XO (4, 460,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"maclhwsu.",	XO (4, 460,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vcmpbfp",	VXR(4, 966,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vctsxs",	VX (4, 970),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB, UIMM}},
 {"vupklpx",	VX (4, 974),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
-{"maclhws",	XO (4, 492,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"maclhws.",	XO (4, 492,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmaclhws",	XO (4, 494,0,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmaclhws.",	XO (4, 494,0,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"maclhws",	XO (4, 492,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"maclhws.",	XO (4, 492,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmaclhws",	XO (4, 494,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmaclhws.",	XO (4, 494,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vsububm",	VX (4,1024),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vavgub",	VX (4,1026),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"evmhessf",	VX (4,1027),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2395,8 +2397,8 @@ const struct powerpc_opcode powerpc_opco
 {"vslo",	VX (4,1036),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"evmhosmi",	VX (4,1037),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhosmf",	VX (4,1039),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"machhwuo",	XO (4,	12,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"machhwuo.",	XO (4,	12,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"machhwuo",	XO (4,	12,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"machhwuo.",	XO (4,	12,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"ps_merge00",	XOPS(4,528,0),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
 {"ps_merge00.",	XOPS(4,528,1),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
 {"evmhessfa",	VX (4,1059),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2421,13 +2423,13 @@ const struct powerpc_opcode powerpc_opco
 {"evmwhsmi",	VX (4,1101),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwhsmf",	VX (4,1103),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwssf",	VX (4,1107),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"machhwo",	XO (4,	44,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"machhwo",	XO (4,	44,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evmwumi",	VX (4,1112),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"machhwo.",	XO (4,	44,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"machhwo.",	XO (4,	44,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evmwsmi",	VX (4,1113),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwsmf",	VX (4,1115),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"nmachhwo",	XO (4,	46,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmachhwo.",	XO (4,	46,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"nmachhwo",	XO (4,	46,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmachhwo.",	XO (4,	46,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"ps_merge01",	XOPS(4,560,0),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
 {"ps_merge01.",	XOPS(4,560,1),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
 {"evmwhssfa",	VX (4,1127),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2445,8 +2447,8 @@ const struct powerpc_opcode powerpc_opco
 {"vcmpequw.",	VXR(4, 134,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"udi2fcm.",	APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476,		{URT, URA, URB}},
 {"udi2fcm",	APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476,		{URT, URA, URB}},   
-{"machhwsuo",	XO (4,	76,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"machhwsuo.",	XO (4,	76,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"machhwsuo",	XO (4,	76,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"machhwsuo.",	XO (4,	76,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"ps_merge10",	XOPS(4,592,0),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
 {"ps_merge10.",	XOPS(4,592,1),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
 {"evaddusiaaw",	VX (4,1216),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
@@ -2464,10 +2466,10 @@ const struct powerpc_opcode powerpc_opco
 {"evaddsmiaaw",	VX (4,1225),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
 {"evsubfumiaaw",VX (4,1226),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
 {"evsubfsmiaaw",VX (4,1227),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
-{"machhwso",	XO (4, 108,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"machhwso.",	XO (4, 108,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmachhwso",	XO (4, 110,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmachhwso.",	XO (4, 110,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"machhwso",	XO (4, 108,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"machhwso.",	XO (4, 108,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmachhwso",	XO (4, 110,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmachhwso.",	XO (4, 110,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"ps_merge11",	XOPS(4,624,0),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
 {"ps_merge11.",	XOPS(4,624,1),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
 {"evmheusiaaw",	VX (4,1280),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2486,8 +2488,8 @@ const struct powerpc_opcode powerpc_opco
 {"evmhoumiaaw",	VX (4,1292),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhosmiaaw",	VX (4,1293),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhosmfaaw",	VX (4,1295),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"macchwuo",	XO (4, 140,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"macchwuo.",	XO (4, 140,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"macchwuo",	XO (4, 140,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchwuo.",	XO (4, 140,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evmhegumiaa",	VX (4,1320),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhegsmiaa",	VX (4,1321),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhegsmfaa",	VX (4,1323),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2502,13 +2504,13 @@ const struct powerpc_opcode powerpc_opco
 {"evmwlumiaaw",	VX (4,1352),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwlsmiaaw",	VX (4,1353),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwssfaa",	VX (4,1363),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"macchwo",	XO (4, 172,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"macchwo",	XO (4, 172,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evmwumiaa",	VX (4,1368),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"macchwo.",	XO (4, 172,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"macchwo.",	XO (4, 172,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evmwsmiaa",	VX (4,1369),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwsmfaa",	VX (4,1371),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"nmacchwo",	XO (4, 174,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmacchwo.",	XO (4, 174,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"nmacchwo",	XO (4, 174,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmacchwo.",	XO (4, 174,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evmheusianw",	VX (4,1408),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"vsubcuw",	VX (4,1408),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"evmhessianw",	VX (4,1409),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2525,8 +2527,8 @@ const struct powerpc_opcode powerpc_opco
 {"evmhoumianw",	VX (4,1420),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhosmianw",	VX (4,1421),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhosmfanw",	VX (4,1423),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"macchwsuo",	XO (4, 204,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"macchwsuo.",	XO (4, 204,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"macchwsuo",	XO (4, 204,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"macchwsuo.",	XO (4, 204,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evmhegumian",	VX (4,1448),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhegsmian",	VX (4,1449),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhegsmfan",	VX (4,1451),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2541,13 +2543,13 @@ const struct powerpc_opcode powerpc_opco
 {"evmwlumianw",	VX (4,1480),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwlsmianw",	VX (4,1481),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwssfan",	VX (4,1491),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"macchwso",	XO (4, 236,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"macchwso",	XO (4, 236,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evmwumian",	VX (4,1496),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"macchwso.",	XO (4, 236,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"macchwso.",	XO (4, 236,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evmwsmian",	VX (4,1497),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwsmfan",	VX (4,1499),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"nmacchwso",	XO (4, 238,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmacchwso.",	XO (4, 238,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"nmacchwso",	XO (4, 238,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmacchwso.",	XO (4, 238,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vsububs",	VX (4,1536),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"mfvscr",	VX (4,1540),	VX_MASK,     PPCVEC,	PPCNONE,	{VD}},
 {"vcmpgtub.",	VXR(4, 518,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
@@ -2573,30 +2575,30 @@ const struct powerpc_opcode powerpc_opco
 {"udi12fcm.",	APU(4, 899,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"udi12fcm",	APU(4, 899,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"vsum4sbs",	VX (4,1800),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"maclhwuo",	XO (4, 396,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"maclhwuo.",	XO (4, 396,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"maclhwuo",	XO (4, 396,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"maclhwuo.",	XO (4, 396,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vsubshs",	VX (4,1856),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vcmpgtsh.",	VXR(4, 838,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"udi13fcm.",	APU(4, 931,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"udi13fcm",	APU(4, 931,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
-{"maclhwo",	XO (4, 428,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"maclhwo.",	XO (4, 428,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmaclhwo",	XO (4, 430,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmaclhwo.",	XO (4, 430,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"maclhwo",	XO (4, 428,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"maclhwo.",	XO (4, 428,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmaclhwo",	XO (4, 430,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmaclhwo.",	XO (4, 430,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vsubsws",	VX (4,1920),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"vcmpgtsw.",	VXR(4, 902,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"udi14fcm.",	APU(4, 963,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"udi14fcm",	APU(4, 963,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"vsumsws",	VX (4,1928),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"maclhwsuo",	XO (4, 460,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"maclhwsuo.",	XO (4, 460,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"maclhwsuo",	XO (4, 460,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"maclhwsuo.",	XO (4, 460,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"vcmpbfp.",	VXR(4, 966,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
 {"udi15fcm.",	APU(4, 995,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"udi15fcm",	APU(4, 995,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
-{"maclhwso",	XO (4, 492,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"maclhwso.",	XO (4, 492,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmaclhwso",	XO (4, 494,1,0),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
-{"nmaclhwso.",	XO (4, 494,1,1),XO_MASK, PPC405|PPC440,	PPCNONE,	{RT, RA, RB}},
+{"maclhwso",	XO (4, 492,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"maclhwso.",	XO (4, 492,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmaclhwso",	XO (4, 494,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
+{"nmaclhwso.",	XO (4, 494,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"dcbz_l",	X  (4,1014),	XRT_MASK,    PPCPS,	PPCNONE,	{RA, RB}},
 
 {"mulli",	OP(7),		OP_MASK,     PPCCOM,	PPCNONE,	{RT, RA, SI}},
@@ -3532,7 +3534,7 @@ const struct powerpc_opcode powerpc_opco
 
 {"iseleq",	X(31,79),	X_MASK,      PPCISEL,	PPCNONE,	{RT, RA, RB}},
 
-{"isel",	XISEL(31,15),	XISEL_MASK,  PPCISEL,	PPCNONE,	{RT, RA, RB, CRB}},
+{"isel",	XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, PPCNONE,	{RT, RA, RB, CRB}},
 
 {"subf",	XO(31,40,0,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
 {"sub",		XO(31,40,0,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RB, RA}},
@@ -3585,8 +3587,8 @@ const struct powerpc_opcode powerpc_opco
 {"mulhw",	XO(31,75,0,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
 {"mulhw.",	XO(31,75,0,1),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
 
-{"dlmzb",	XRC(31,78,0),	X_MASK,  PPC403|PPC440,	PPCNONE,	{RA, RS, RB}},
-{"dlmzb.",	XRC(31,78,1),	X_MASK,  PPC403|PPC440,	PPCNONE,	{RA, RS, RB}},
+{"dlmzb",	XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, PPCNONE,	{RA, RS, RB}},
+{"dlmzb.",	XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, PPCNONE,	{RA, RS, RB}},
 
 {"mtsrd",	X(31,82),  XRB_MASK|(1<<20), PPC64,	PPCNONE,	{SR, RS}},
 
@@ -3629,7 +3631,7 @@ const struct powerpc_opcode powerpc_opco
 
 {"wrtee",	X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RS}},
 
-{"dcbtstls",	X(31,134),	X_MASK, PPCCHLK|PPC476,	PPCNONE,	{CT, RA, RB}},
+{"dcbtstls",	X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,	{CT, RA, RB}},
 
 {"stvebx",	X(31,135),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
 {"stbfcmx",	APU(31,135,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
@@ -3676,7 +3678,7 @@ const struct powerpc_opcode powerpc_opco
 
 {"wrteei",	X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE,	{E}},
 
-{"dcbtls",	X(31,166),	X_MASK, PPCCHLK|PPC476,	PPCNONE,	{CT, RA, RB}},
+{"dcbtls",	X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,	{CT, RA, RB}},
 
 {"stvehx",	X(31,167),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
 {"sthfcmx",	APU(31,167,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
@@ -3714,7 +3716,7 @@ const struct powerpc_opcode powerpc_opco
 
 {"msgsnd",	XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2, PPCNONE,	{RB}},
 
-{"mtsr",	X(31,210), XRB_MASK|(1<<20), COM32,	PPCNONE,	{SR, RS}},
+{"mtsr",	X(31,210), XRB_MASK|(1<<20), COM32,	TITAN,  	{SR, RS}},
 
 {"eratwe",	X(31,211),	X_MASK,	     PPCA2,	PPCNONE,	{RS, RA, WS}},
 
@@ -3732,7 +3734,7 @@ const struct powerpc_opcode powerpc_opco
 
 {"stbepx",	X(31,223),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{RS, RA, RB}},
 
-{"icblc",	X(31,230),	X_MASK, PPCCHLK|PPC476,	PPCNONE,	{CT, RA, RB}},
+{"icblc",	X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,	{CT, RA, RB}},
 
 {"stvx",	X(31,231),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
 {"stqfcmx",	APU(31,231,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
@@ -3757,7 +3759,7 @@ const struct powerpc_opcode powerpc_opco
 
 {"icblce",	X(31,238),	X_MASK,      PPCCHLK,	E500MC|PPCA2,	{CT, RA, RB}},
 {"msgclr",	XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2, PPCNONE,	{RB}},
-{"mtsrin",	X(31,242),	XRA_MASK,    PPC32,	PPCNONE,	{RS, RB}},
+{"mtsrin",	X(31,242),	XRA_MASK,    PPC32,	TITAN,  	{RS, RB}},
 {"mtsri",	X(31,242),	XRA_MASK,    POWER32,	PPCNONE,	{RS, RB}},
 
 {"dcbtstt",	XRT(31,246,0x10), XRT_MASK,  POWER7,	PPCNONE,	{RA, RB}},
@@ -3773,7 +3775,7 @@ const struct powerpc_opcode powerpc_opco
 
 {"dcbtstep",	XRT(31,255,0),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{RT, RA, RB}},
 
-{"mfdcrx",	X(31,259),	X_MASK, BOOKE|PPCA2|PPC476, PPCNONE,	{RS, RA}},
+{"mfdcrx",	X(31,259),	X_MASK, BOOKE|PPCA2|PPC476, TITAN,	{RS, RA}},
 {"mfdcrx.",	XRC(31,259,1),	X_MASK,      PPCA2,	PPCNONE,	{RS, RA}},
 
 {"icbt",	X(31,262),	XRT_MASK,    PPC403,	PPCNONE,	{RA, RB}},
@@ -3791,7 +3793,7 @@ const struct powerpc_opcode powerpc_opco
 
 {"tlbiel",	X(31,274),	XRTLRA_MASK, POWER4,	PPC476,		{RB, L}},
 
-{"mfapidi",	X(31,275),	X_MASK,      BOOKE,	PPCNONE,	{RT, RA}},
+{"mfapidi",	X(31,275),	X_MASK,      BOOKE,	TITAN,  	{RT, RA}},
 
 {"lscbx",	XRC(31,277,0),	X_MASK,      M601,	PPCNONE,	{RT, RA, RB}},
 {"lscbx.",	XRC(31,277,1),	X_MASK,      M601,	PPCNONE,	{RT, RA, RB}},
@@ -3811,10 +3813,10 @@ const struct powerpc_opcode powerpc_opco
 
 {"mfdcrux",	X(31,291),	X_MASK,      PPC464,	PPCNONE,	{RS, RA}},
 
-{"tlbie",	X(31,306),	XRTLRA_MASK, PPC,	PPCNONE,	{RB, L}},
+{"tlbie",	X(31,306),	XRTLRA_MASK, PPC,	TITAN,  	{RB, L}},
 {"tlbi",	X(31,306),	XRT_MASK,    POWER,	PPCNONE,	{RA0, RB}},
 
-{"eciwx",	X(31,310),	X_MASK,      PPC,	PPCNONE,	{RT, RA, RB}},
+{"eciwx",	X(31,310),	X_MASK,      PPC,	TITAN,  	{RT, RA, RB}},
 
 {"lhzux",	X(31,311),	X_MASK,      COM,	PPCNONE,	{RT, RAL, RB}},
 
@@ -3859,10 +3861,10 @@ const struct powerpc_opcode powerpc_opco
 {"mfdmasa3",	XSPR(31,323,219), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfdmacc3",	XSPR(31,323,220), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfdmasr",	XSPR(31,323,224), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
-{"mfdcr",	X(31,323),	X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RT, SPR}},
+{"mfdcr",	X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN,	{RT, SPR}},
 {"mfdcr.",	XRC(31,323,1),	X_MASK,      PPCA2,	PPCNONE,	{RT, SPR}},
 
-{"dcread",	X(31,326),	X_MASK,      PPC476,	PPCNONE,	{RT, RA, RB}},
+{"dcread",	X(31,326),	X_MASK,  PPC476|TITAN,	PPCNONE,	{RT, RA, RB}},
 
 {"div",		XO(31,331,0,0),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
 {"div.",	XO(31,331,0,1),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
@@ -3873,17 +3875,17 @@ const struct powerpc_opcode powerpc_opco
 
 {"mfmq",	XSPR(31,339,  0), XSPR_MASK, M601,	PPCNONE,	{RT}},
 {"mfxer",	XSPR(31,339,  1), XSPR_MASK, COM,	PPCNONE,	{RT}},
-{"mfrtcu",	XSPR(31,339,  4), XSPR_MASK, COM,	PPCNONE,	{RT}},
-{"mfrtcl",	XSPR(31,339,  5), XSPR_MASK, COM,	PPCNONE,	{RT}},
+{"mfrtcu",	XSPR(31,339,  4), XSPR_MASK, COM,	TITAN,  	{RT}},
+{"mfrtcl",	XSPR(31,339,  5), XSPR_MASK, COM,	TITAN,  	{RT}},
 {"mfdec",	XSPR(31,339,  6), XSPR_MASK, MFDEC1,	PPCNONE,	{RT}},
 {"mflr",	XSPR(31,339,  8), XSPR_MASK, COM,	PPCNONE,	{RT}},
 {"mfctr",	XSPR(31,339,  9), XSPR_MASK, COM,	PPCNONE,	{RT}},
 {"mftid",	XSPR(31,339, 17), XSPR_MASK, POWER,	PPCNONE,	{RT}},
-{"mfdsisr",	XSPR(31,339, 18), XSPR_MASK, COM,	PPCNONE,	{RT}},
-{"mfdar",	XSPR(31,339, 19), XSPR_MASK, COM,	PPCNONE,	{RT}},
-{"mfdec",	XSPR(31,339, 22), XSPR_MASK, MFDEC2,	PPCNONE,	{RT}},
+{"mfdsisr",	XSPR(31,339, 18), XSPR_MASK, COM,	TITAN,  	{RT}},
+{"mfdar",	XSPR(31,339, 19), XSPR_MASK, COM,	TITAN,  	{RT}},
+{"mfdec",	XSPR(31,339, 22), XSPR_MASK, MFDEC2|TITAN, PPCNONE,	{RT}},
 {"mfsdr0",	XSPR(31,339, 24), XSPR_MASK, POWER,	PPCNONE,	{RT}},
-{"mfsdr1",	XSPR(31,339, 25), XSPR_MASK, COM,	PPCNONE,	{RT}},
+{"mfsdr1",	XSPR(31,339, 25), XSPR_MASK, COM,	TITAN,  	{RT}},
 {"mfsrr0",	XSPR(31,339, 26), XSPR_MASK, COM,	PPCNONE,	{RT}},
 {"mfsrr1",	XSPR(31,339, 27), XSPR_MASK, COM,	PPCNONE,	{RT}},
 {"mfcfar",	XSPR(31,339, 28), XSPR_MASK, POWER6,	PPCNONE,	{RT}},
@@ -3924,7 +3926,7 @@ const struct powerpc_opcode powerpc_opco
 {"mfsprg2",	XSPR(31,339,274), XSPR_MASK, PPC,	PPCNONE,	{RT}},
 {"mfsprg3",	XSPR(31,339,275), XSPR_MASK, PPC,	PPCNONE,	{RT}},
 {"mfasr",	XSPR(31,339,280), XSPR_MASK, PPC64,	PPCNONE,	{RT}},
-{"mfear",	XSPR(31,339,282), XSPR_MASK, PPC,	PPCNONE,	{RT}},
+{"mfear",	XSPR(31,339,282), XSPR_MASK, PPC,	TITAN,  	{RT}},
 {"mfpir",	XSPR(31,339,286), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
 {"mfpvr",	XSPR(31,339,287), XSPR_MASK, PPC,	PPCNONE,	{RT}},
 {"mfdbsr",	XSPR(31,339,304), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
@@ -3961,13 +3963,13 @@ const struct powerpc_opcode powerpc_opco
 {"mfbbear",	XSPR(31,339,513), XSPR_MASK, PPCBRLK,	PPCNONE,	{RT}},
 {"mfbbtar",	XSPR(31,339,514), XSPR_MASK, PPCBRLK,	PPCNONE,	{RT}},
 {"mfivor32",	XSPR(31,339,528), XSPR_MASK, PPCSPE,	PPCNONE,	{RT}},
-{"mfibatu",	XSPR(31,339,528), XSPRBAT_MASK, PPC,	PPCNONE,	{RT, SPRBAT}},
+{"mfibatu",	XSPR(31,339,528), XSPRBAT_MASK, PPC,	TITAN,  	{RT, SPRBAT}},
 {"mfivor33",	XSPR(31,339,529), XSPR_MASK, PPCSPE,	PPCNONE,	{RT}},
-{"mfibatl",	XSPR(31,339,529), XSPRBAT_MASK, PPC,	PPCNONE,	{RT, SPRBAT}},
+{"mfibatl",	XSPR(31,339,529), XSPRBAT_MASK, PPC,	TITAN,  	{RT, SPRBAT}},
 {"mfivor34",	XSPR(31,339,530), XSPR_MASK, PPCSPE,	PPCNONE,	{RT}},
 {"mfivor35",	XSPR(31,339,531), XSPR_MASK, PPCPMR,	PPCNONE,	{RT}},
-{"mfdbatu",	XSPR(31,339,536), XSPRBAT_MASK, PPC,	PPCNONE,	{RT, SPRBAT}},
-{"mfdbatl",	XSPR(31,339,537), XSPRBAT_MASK, PPC,	PPCNONE,	{RT, SPRBAT}},
+{"mfdbatu",	XSPR(31,339,536), XSPRBAT_MASK, PPC,	TITAN,  	{RT, SPRBAT}},
+{"mfdbatl",	XSPR(31,339,537), XSPRBAT_MASK, PPC,	TITAN,  	{RT, SPRBAT}},
 {"mfic_cst",	XSPR(31,339,560), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfic_adr",	XSPR(31,339,561), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfic_dat",	XSPR(31,339,562), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
@@ -3977,7 +3979,7 @@ const struct powerpc_opcode powerpc_opco
 {"mfmcsrr0",	XSPR(31,339,570), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RT}},
 {"mfmcsrr1",	XSPR(31,339,571), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RT}},
 {"mfmcsr",	XSPR(31,339,572), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RT}},
-{"mfmcar",	XSPR(31,339,573), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RT}},
+{"mfmcar",	XSPR(31,339,573), XSPR_MASK, PPCRFMCI,	TITAN,  	{RT}},
 {"mfdpdr",	XSPR(31,339,630), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfdpir",	XSPR(31,339,631), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfimmr",	XSPR(31,339,638), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
@@ -4000,6 +4002,16 @@ const struct powerpc_opcode powerpc_opco
 {"mfmd_dbcam",	XSPR(31,339,824), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfmd_dbram0",	XSPR(31,339,825), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfmd_dbram1",	XSPR(31,339,826), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
+{"mfivndx",	XSPR(31,339,880), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfdvndx",	XSPR(31,339,881), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfivlim",	XSPR(31,339,882), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfdvlim",	XSPR(31,339,883), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfclcsr",	XSPR(31,339,884), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfccr1",	XSPR(31,339,888), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfrstcfg",	XSPR(31,339,923), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfdcdbtrl",	XSPR(31,339,924), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfdcdbtrh",	XSPR(31,339,925), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mficdbtr",	XSPR(31,339,927), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
 {"mfummcr0",	XSPR(31,339,936), XSPR_MASK, PPC750,	PPCNONE,	{RT}},
 {"mfupmc1",	XSPR(31,339,937), XSPR_MASK, PPC750,	PPCNONE,	{RT}},
 {"mfupmc2",	XSPR(31,339,938), XSPR_MASK, PPC750,	PPCNONE,	{RT}},
@@ -4009,7 +4021,8 @@ const struct powerpc_opcode powerpc_opco
 {"mfupmc4",	XSPR(31,339,942), XSPR_MASK, PPC750,	PPCNONE,	{RT}},
 {"mfzpr",	XSPR(31,339,944), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfpid",	XSPR(31,339,945), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
-{"mfccr0",	XSPR(31,339,947), XSPR_MASK, PPC405,	PPCNONE,	{RT}},
+{"mfmmucr",	XSPR(31,339,946), XSPR_MASK, TITAN,	PPCNONE,	{RT}},
+{"mfccr0",	XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, PPCNONE,	{RT}},
 {"mfiac3",	XSPR(31,339,948), XSPR_MASK, PPC405,	PPCNONE,	{RT}},
 {"mfiac4",	XSPR(31,339,949), XSPR_MASK, PPC405,	PPCNONE,	{RT}},
 {"mfdvc1",	XSPR(31,339,950), XSPR_MASK, PPC405,	PPCNONE,	{RT}},
@@ -4026,7 +4039,7 @@ const struct powerpc_opcode powerpc_opco
 {"mfdbcr1",	XSPR(31,339,957), XSPR_MASK, PPC405,	PPCNONE,	{RT}},
 {"mfpmc3",	XSPR(31,339,957), XSPR_MASK, PPC750,	PPCNONE,	{RT}},
 {"mfpmc4",	XSPR(31,339,958), XSPR_MASK, PPC750,	PPCNONE,	{RT}},
-{"mficdbdr",	XSPR(31,339,979), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
+{"mficdbdr",	XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, PPCNONE,	{RT}},
 {"mfesr",	XSPR(31,339,980), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfdear",	XSPR(31,339,981), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfevpr",	XSPR(31,339,982), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
@@ -4040,6 +4053,7 @@ const struct powerpc_opcode powerpc_opco
 {"mfsrr3",	XSPR(31,339,991), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfdbsr",	XSPR(31,339,1008), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfdbcr0",	XSPR(31,339,1010), XSPR_MASK, PPC405,	PPCNONE,	{RT}},
+{"mfdbdr",	XSPR(31,339,1011), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
 {"mfiac1",	XSPR(31,339,1012), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfiac2",	XSPR(31,339,1013), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfdac1",	XSPR(31,339,1014), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
@@ -4071,7 +4085,7 @@ const struct powerpc_opcode powerpc_opco
 {"divs",	XO(31,363,0,0),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
 {"divs.",	XO(31,363,0,1),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
 
-{"tlbia",	X(31,370),	0xffffffff,  PPC,	PPCNONE,	{0}},
+{"tlbia",	X(31,370),	0xffffffff,  PPC,	TITAN,  	{0}},
 
 {"mftbl",	XSPR(31,371,268), XSPR_MASK, CLASSIC,	PPCNONE,	{RT}},
 {"mftbu",	XSPR(31,371,269), XSPR_MASK, CLASSIC,	PPCNONE,	{RT}},
@@ -4085,10 +4099,10 @@ const struct powerpc_opcode powerpc_opco
 
 {"popcntw",	X(31,378),	XRB_MASK, POWER7|PPCA2,	PPCNONE,	{RA, RS}},
 
-{"mtdcrx",	X(31,387),	X_MASK, BOOKE|PPCA2|PPC476, PPCNONE,	{RA, RS}},
+{"mtdcrx",	X(31,387),	X_MASK, BOOKE|PPCA2|PPC476, TITAN,	{RA, RS}},
 {"mtdcrx.",	XRC(31,387,1),	X_MASK,      PPCA2,	PPCNONE,	{RA, RS}},
 
-{"dcblc",	X(31,390),	X_MASK, PPCCHLK|PPC476,	PPCNONE,	{CT, RA, RB}},
+{"dcblc",	X(31,390),	X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,	{CT, RA, RB}},
 {"stdfcmx",	APU(31,391,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
 {"divdeu",	XO(31,393,0,0),	XO_MASK,     POWER7,	PPCNONE,	{RT, RA, RB}},
@@ -4119,7 +4133,7 @@ const struct powerpc_opcode powerpc_opco
 
 {"slbie",	X(31,434),	XRTRA_MASK,  PPC64,	PPCNONE,	{RB}},
 
-{"ecowx",	X(31,438),	X_MASK,      PPC,	PPCNONE,	{RT, RA, RB}},
+{"ecowx",	X(31,438),	X_MASK,      PPC,	TITAN,  	{RT, RA, RB}},
 
 {"sthux",	X(31,439),	X_MASK,      COM,	PPCNONE,	{RS, RAS, RB}},
 
@@ -4164,10 +4178,10 @@ const struct powerpc_opcode powerpc_opco
 {"mtdmasa3",	XSPR(31,451,219), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
 {"mtdmacc3",	XSPR(31,451,220), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
 {"mtdmasr",	XSPR(31,451,224), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
-{"mtdcr",	X(31,451),     X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {SPR, RS}},
+{"mtdcr",	X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN,	{SPR, RS}},
 {"mtdcr.",	XRC(31,451,1), X_MASK,       PPCA2,	PPCNONE,	{SPR, RS}},
 
-{"dccci",	X(31,454),     XRT_MASK, PPC403|PPC440,	PPCA2|PPC476,	{RA, RB}},
+{"dccci",	X(31,454), XRT_MASK, PPC403|PPC440|TITAN, PPCA2|PPC476,	{RA, RB}},
 {"dci",		X(31,454),	XRARB_MASK, PPCA2|PPC476, PPCNONE,	{CT}},
 
 {"divdu",	XO(31,457,0,0),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
@@ -4181,15 +4195,15 @@ const struct powerpc_opcode powerpc_opco
 {"mtmq",	XSPR(31,467,  0), XSPR_MASK, M601,	PPCNONE,	{RS}},
 {"mtxer",	XSPR(31,467,  1), XSPR_MASK, COM,	PPCNONE,	{RS}},
 {"mtlr",	XSPR(31,467,  8), XSPR_MASK, COM,	PPCNONE,	{RS}},
-{"mtctr",	XSPR(31,467,  9), XSPR_MASK, COM,	PPCNONE,	{RS}},
+{"mtctr", 	XSPR(31,467,  9), XSPR_MASK, COM,	PPCNONE,	{RS}},
 {"mttid",	XSPR(31,467, 17), XSPR_MASK, POWER,	PPCNONE,	{RS}},
-{"mtdsisr",	XSPR(31,467, 18), XSPR_MASK, COM,	PPCNONE,	{RS}},
-{"mtdar",	XSPR(31,467, 19), XSPR_MASK, COM,	PPCNONE,	{RS}},
-{"mtrtcu",	XSPR(31,467, 20), XSPR_MASK, COM,	PPCNONE,	{RS}},
-{"mtrtcl",	XSPR(31,467, 21), XSPR_MASK, COM,	PPCNONE,	{RS}},
+{"mtdsisr",	XSPR(31,467, 18), XSPR_MASK, COM,	TITAN,  	{RS}},
+{"mtdar",	XSPR(31,467, 19), XSPR_MASK, COM,	TITAN,  	{RS}},
+{"mtrtcu",	XSPR(31,467, 20), XSPR_MASK, COM,	TITAN,  	{RS}},
+{"mtrtcl",	XSPR(31,467, 21), XSPR_MASK, COM,	TITAN,  	{RS}},
 {"mtdec",	XSPR(31,467, 22), XSPR_MASK, COM,	PPCNONE,	{RS}},
 {"mtsdr0",	XSPR(31,467, 24), XSPR_MASK, POWER,	PPCNONE,	{RS}},
-{"mtsdr1",	XSPR(31,467, 25), XSPR_MASK, COM,	PPCNONE,	{RS}},
+{"mtsdr1",	XSPR(31,467, 25), XSPR_MASK, COM,	TITAN,  	{RS}},
 {"mtsrr0",	XSPR(31,467, 26), XSPR_MASK, COM,	PPCNONE,	{RS}},
 {"mtsrr1",	XSPR(31,467, 27), XSPR_MASK, COM,	PPCNONE,	{RS}},
 {"mtcfar",	XSPR(31,467, 28), XSPR_MASK, POWER6,	PPCNONE,	{RS}},
@@ -4228,7 +4242,7 @@ const struct powerpc_opcode powerpc_opco
 {"mtsprg6",	XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, PPCNONE,	{RS}},
 {"mtsprg7",	XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, PPCNONE,	{RS}},
 {"mtasr",	XSPR(31,467,280), XSPR_MASK, PPC64,	PPCNONE,	{RS}},
-{"mtear",	XSPR(31,467,282), XSPR_MASK, PPC,	PPCNONE,	{RS}},
+{"mtear",	XSPR(31,467,282), XSPR_MASK, PPC,	TITAN,  	{RS}},
 {"mttbl",	XSPR(31,467,284), XSPR_MASK, PPC,	PPCNONE,	{RS}},
 {"mttbu",	XSPR(31,467,285), XSPR_MASK, PPC,	PPCNONE,	{RS}},
 {"mtdbsr",	XSPR(31,467,304), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
@@ -4265,16 +4279,22 @@ const struct powerpc_opcode powerpc_opco
 {"mtbbear",	XSPR(31,467,513), XSPR_MASK, PPCBRLK,	PPCNONE,	{RS}},
 {"mtbbtar",	XSPR(31,467,514), XSPR_MASK, PPCBRLK,	PPCNONE,	{RS}},
 {"mtivor32",	XSPR(31,467,528), XSPR_MASK, PPCSPE,	PPCNONE,	{RS}},
-{"mtibatu",	XSPR(31,467,528), XSPRBAT_MASK, PPC,	PPCNONE,	{SPRBAT, RS}},
+{"mtibatu",	XSPR(31,467,528), XSPRBAT_MASK, PPC,	TITAN,  	{SPRBAT, RS}},
 {"mtivor33",	XSPR(31,467,529), XSPR_MASK, PPCSPE,	PPCNONE,	{RS}},
-{"mtibatl",	XSPR(31,467,529), XSPRBAT_MASK, PPC,	PPCNONE,	{SPRBAT, RS}},
+{"mtibatl",	XSPR(31,467,529), XSPRBAT_MASK, PPC,	TITAN,  	{SPRBAT, RS}},
 {"mtivor34",	XSPR(31,467,530), XSPR_MASK, PPCSPE,	PPCNONE,	{RS}},
 {"mtivor35",	XSPR(31,467,531), XSPR_MASK, PPCPMR,	PPCNONE,	{RS}},
-{"mtdbatu",	XSPR(31,467,536), XSPRBAT_MASK, PPC,	PPCNONE,	{SPRBAT, RS}},
-{"mtdbatl",	XSPR(31,467,537), XSPRBAT_MASK, PPC,	PPCNONE,	{SPRBAT, RS}},
+{"mtdbatu",	XSPR(31,467,536), XSPRBAT_MASK, PPC,	TITAN,  	{SPRBAT, RS}},
+{"mtdbatl",	XSPR(31,467,537), XSPRBAT_MASK, PPC,	TITAN,  	{SPRBAT, RS}},
 {"mtmcsrr0",	XSPR(31,467,570), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RS}},
 {"mtmcsrr1",	XSPR(31,467,571), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RS}},
 {"mtmcsr",	XSPR(31,467,572), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RS}},
+{"mtivndx",	XSPR(31,467,880), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
+{"mtdvndx",	XSPR(31,467,881), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
+{"mtivlim",	XSPR(31,467,882), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
+{"mtdvlim",	XSPR(31,467,883), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
+{"mtclcsr",	XSPR(31,467,884), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
+{"mtccr1",	XSPR(31,467,888), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
 {"mtummcr0",	XSPR(31,467,936), XSPR_MASK, PPC750,	PPCNONE,	{RS}},
 {"mtupmc1",	XSPR(31,467,937), XSPR_MASK, PPC750,	PPCNONE,	{RS}},
 {"mtupmc2",	XSPR(31,467,938), XSPR_MASK, PPC750,	PPCNONE,	{RS}},
@@ -4284,7 +4304,8 @@ const struct powerpc_opcode powerpc_opco
 {"mtupmc4",	XSPR(31,467,942), XSPR_MASK, PPC750,	PPCNONE,	{RS}},
 {"mtzpr",	XSPR(31,467,944), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
 {"mtpid",	XSPR(31,467,945), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
-{"mtccr0",	XSPR(31,467,947), XSPR_MASK, PPC405,	PPCNONE,	{RS}},
+{"mtrmmucr",	XSPR(31,467,946), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
+{"mtccr0",	XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, PPCNONE,	{RS}},
 {"mtiac3",	XSPR(31,467,948), XSPR_MASK, PPC405,	PPCNONE,	{RS}},
 {"mtiac4",	XSPR(31,467,949), XSPR_MASK, PPC405,	PPCNONE,	{RS}},
 {"mtdvc1",	XSPR(31,467,950), XSPR_MASK, PPC405,	PPCNONE,	{RS}},
@@ -4314,6 +4335,7 @@ const struct powerpc_opcode powerpc_opco
 {"mtsrr2",	XSPR(31,467,990), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
 {"mtsrr3",	XSPR(31,467,991), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
 {"mtdbsr",	XSPR(31,467,1008), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
+{"mtdbdr",	XSPR(31,467,1011), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
 {"mtdbcr0",	XSPR(31,467,1010), XSPR_MASK, PPC405,	PPCNONE,	{RS}},
 {"mtiac1",	XSPR(31,467,1012), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
 {"mtiac2",	XSPR(31,467,1013), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
@@ -4341,7 +4363,7 @@ const struct powerpc_opcode powerpc_opco
 
 {"dcread",	X(31,486),	X_MASK,  PPC403|PPC440,	PPCA2|PPC476,	{RT, RA, RB}},
 
-{"icbtls",	X(31,486),	X_MASK, PPCCHLK|PPC476,	PPCNONE,	{CT, RA, RB}},
+{"icbtls",	X(31,486),	X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,	{CT, RA, RB}},
 
 {"stvxl",	X(31,487),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
 
@@ -4433,7 +4455,7 @@ const struct powerpc_opcode powerpc_opco
 
 {"lxsdx",	X(31,588),	XX1_MASK,    PPCVSX,	PPCNONE,	{XT6, RA, RB}},
 
-{"mfsr",	X(31,595), XRB_MASK|(1<<20), COM32,	PPCNONE,	{RT, SR}},
+{"mfsr",	X(31,595), XRB_MASK|(1<<20), COM32,	TITAN,  	{RT, SR}},
 
 {"lswi",	X(31,597),	X_MASK,      PPCCOM,	PPCNONE,	{RT, RA0, NB}},
 {"lsi",		X(31,597),	X_MASK,      PWRCOM,	PPCNONE,	{RT, RA0, NB}},
@@ -4480,7 +4502,7 @@ const struct powerpc_opcode powerpc_opco
 {"addeo.",	XO(31,138,1,1),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
 {"aeo.",	XO(31,138,1,1),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
 
-{"mfsrin",	X(31,659),	XRA_MASK,    PPC32,	PPCNONE,	{RT, RB}},
+{"mfsrin",	X(31,659),	XRA_MASK,    PPC32,	TITAN,  	{RT, RB}},
 
 {"stdbrx",	X(31,660),	X_MASK, CELL|POWER7|PPCA2, PPCNONE,	{RS, RA0, RB}},
 
@@ -4711,7 +4733,7 @@ const struct powerpc_opcode powerpc_opco
 {"extsb",	XRC(31,954,0),	XRB_MASK,    PPC,	PPCNONE,	{RA, RS}},
 {"extsb.",	XRC(31,954,1),	XRB_MASK,    PPC,	PPCNONE,	{RA, RS}},
 
-{"iccci",	X(31,966),     XRT_MASK, PPC403|PPC440,	PPC476,		{RA, RB}},
+{"iccci",	X(31,966),     XRT_MASK, PPC403|PPC440|TITAN, PPC476,	{RA, RB}},
 {"ici",		X(31,966),	XRARB_MASK,  PPCA2|PPC476, PPCNONE,	{CT}},
 
 {"divduo",	XO(31,457,1,0),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
@@ -4738,7 +4760,7 @@ const struct powerpc_opcode powerpc_opco
 
 {"icbiep",	XRT(31,991,0),	XRT_MASK, E500MC|PPCA2,	PPCNONE,	{RA, RB}},
 
-{"icread",	X(31,998),     XRT_MASK, PPC403|PPC440|PPC476, PPCNONE,	{RA, RB}},
+{"icread",	X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, PPCNONE, {RA, RB}},
 
 {"nabso",	XO(31,488,1,0),	XORB_MASK,   M601,	PPCNONE,	{RT, RA}},
 {"nabso.",	XO(31,488,1,1),	XORB_MASK,   M601,	PPCNONE,	{RT, RA}},
@@ -4749,7 +4771,7 @@ const struct powerpc_opcode powerpc_opco
 {"divwo",	XO(31,491,1,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
 {"divwo.",	XO(31,491,1,1),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
 
-{"tlbli",	X(31,1010),	XRTRA_MASK,  PPC,	PPCNONE,	{RB}},
+{"tlbli",	X(31,1010),	XRTRA_MASK,  PPC,	TITAN,  	{RB}},
 
 {"stdcix",	X(31,1013),	X_MASK,      POWER6,	PPCNONE,	{RS, RA0, RB}},
 
@@ -4854,8 +4876,8 @@ const struct powerpc_opcode powerpc_opco
 {"fadds",	A(59,21,0),	AFRC_MASK,   PPC,	PPCNONE,	{FRT, FRA, FRB}},
 {"fadds.",	A(59,21,1),	AFRC_MASK,   PPC,	PPCNONE,	{FRT, FRA, FRB}},
 
-{"fsqrts",	A(59,22,0),    AFRAFRC_MASK, PPC,	PPCNONE,	{FRT, FRB}},
-{"fsqrts.",	A(59,22,1),    AFRAFRC_MASK, PPC,	PPCNONE,	{FRT, FRB}},
+{"fsqrts",	A(59,22,0),    AFRAFRC_MASK, PPC,	TITAN,  	{FRT, FRB}},
+{"fsqrts.",	A(59,22,1),    AFRAFRC_MASK, PPC,	TITAN,  	{FRT, FRB}},
 
 {"fres",	A(59,24,0),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
 {"fres",	A(59,24,0),   AFRALFRC_MASK, PPC,	POWER7,		{FRT, FRB, A_L}},
@@ -5141,8 +5163,8 @@ const struct powerpc_opcode powerpc_opco
 {"fadd.",	A(63,21,1),	AFRC_MASK,   PPCCOM,	PPCNONE,	{FRT, FRA, FRB}},
 {"fa.",		A(63,21,1),	AFRC_MASK,   PWRCOM,	PPCNONE,	{FRT, FRA, FRB}},
 
-{"fsqrt",	A(63,22,0),    AFRAFRC_MASK, PPCPWR2,	PPCNONE,	{FRT, FRB}},
-{"fsqrt.",	A(63,22,1),    AFRAFRC_MASK, PPCPWR2,	PPCNONE,	{FRT, FRB}},
+{"fsqrt",	A(63,22,0),    AFRAFRC_MASK, PPCPWR2,	TITAN,  	{FRT, FRB}},
+{"fsqrt.",	A(63,22,1),    AFRAFRC_MASK, PPCPWR2,	TITAN,  	{FRT, FRB}},
 
 {"fsel",	A(63,23,0),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
 {"fsel.",	A(63,23,1),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},

-- 
Alan Modra
Australia Development Lab, IBM

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2010-02-08  2:00 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2009-11-19 23:46 PATCH: Add AppliedMicro Titan (APM83xxx) support Philipp Tomsich
2009-11-20  4:12 ` Alan Modra
2009-11-20 16:04   ` PATCH [version 2]: " Philipp Tomsich
2010-02-08  2:00     ` Alan Modra

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