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Date: Mon, 26 Jul 2010 13:25:00 -0000
From: Nathan Froyd <froydnj@codesourcery.com>
To: "Maciej W. Rozycki" <macro@codesourcery.com>
Cc: Richard Sandiford <rdsandiford@googlemail.com>, binutils@sourceware.org,	Chao-ying Fu <fu@mips.com>, Rich Fuhler <rich@mips.com>,	David Lau <davidlau@mips.com>, Kevin Mills <kevinm@mips.com>,	Ilie Garbacea <ilie@mips.com>,	Catherine Moore <clm@codesourcery.com>,	Nathan Sidwell <nathan@codesourcery.com>,	Joseph Myers <joseph@codesourcery.com>
Subject: Re: [PATCH] MIPS: microMIPS ASE support
Message-ID: <20100726132543.GL9110@codesourcery.com>
References: <alpine.DEB.1.10.1005181806590.4023@tp.orcam.me.uk> <87y6fa9u3t.fsf@firetop.home> <alpine.DEB.1.10.1007112325020.2824@tp.orcam.me.uk>
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On Mon, Jul 26, 2010 at 11:55:20AM +0100, Maciej W. Rozycki wrote:
> > Did you actually test this with n64, say with a gcc bootstrap?  Same
> > comment goes for elfn32-mips.c.
> > 
> > Why only do the linker relaxation for elf32-mips.c (o32, o64 & EABI)?
> > Why not for n32 and n64 too?
> 
>  The answer to all the questions is negative.  There is no 64-bit 
> microMIPS hardware available at the moment.  The best bet might be QEMU -- 
> NathanF, have you implemented any of the 64-bit instructions in QEMU?  

I have implemented support for the 64-bit instructions in QEMU.  I
haven't really tested whether the instruction translation works
correctly for those instructions.  (It should; there's nothing unusual
about the codepaths the 64-bit instructions take vs. their 32-bit
counterparts...but you never know...)

-Nathan