* [PATCH] opcodes: blackfin: decode insns with invalid register as illegal
@ 2010-09-21 8:35 Mike Frysinger
2010-09-22 21:39 ` Mike Frysinger
0 siblings, 1 reply; 2+ messages in thread
From: Mike Frysinger @ 2010-09-21 8:35 UTC (permalink / raw)
To: binutils; +Cc: Robin Getz
From: Robin Getz <robin.getz@analog.com>
Sometimes the encoding in the opcode is a 4 bit field which defines a
register number. However, register numbers are only 0-7, so make sure
we call illegal for when the opcode register number is greater than 8.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-21 Robin Getz <robin.getz@analog.com>
* bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
register values greater than 8.
(IS_RESERVEDREG, allreg, mostreg): New helpers.
(decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
(decode_PushPopReg_0): Call mostreg/allreg as appropriate.
(decode_CC2dreg_0): Check valid CC register number.
---
opcodes/bfin-dis.c | 33 +++++++++++++++++++--------------
1 files changed, 19 insertions(+), 14 deletions(-)
diff --git a/opcodes/bfin-dis.c b/opcodes/bfin-dis.c
index e58917b..ef7c7b5 100644
--- a/opcodes/bfin-dis.c
+++ b/opcodes/bfin-dis.c
@@ -436,13 +436,18 @@ static enum machine_registers decode_allregs[] =
REG_LASTREG,
};
-#define IS_DREG(g,r) ((g) == 0)
-#define IS_PREG(g,r) ((g) == 1)
+#define IS_DREG(g,r) ((g) == 0 && (r) < 8)
+#define IS_PREG(g,r) ((g) == 1 && (r) < 8)
#define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
-#define IS_GENREG(g,r) ((g) == 0 || (g) == 1 || IS_AREG (g, r))
-#define IS_DAGREG(g,r) ((g) == 2 || (g) == 3)
+#define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
+#define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
#define IS_SYSREG(g,r) \
(((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
+#define IS_RESERVEDREG(g,r) \
+ (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
+
+#define allreg(r,g) (!IS_RESERVEDREG (g, r))
+#define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
#define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
#define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
@@ -773,35 +778,35 @@ decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
OUTS (outf, "SSYNC");
else if (prgfunc == 2 && poprnd == 5)
OUTS (outf, "EMUEXCPT");
- else if (prgfunc == 3)
+ else if (prgfunc == 3 && IS_DREG (0, poprnd))
{
OUTS (outf, "CLI ");
OUTS (outf, dregs (poprnd));
}
- else if (prgfunc == 4)
+ else if (prgfunc == 4 && IS_DREG (0, poprnd))
{
OUTS (outf, "STI ");
OUTS (outf, dregs (poprnd));
}
- else if (prgfunc == 5)
+ else if (prgfunc == 5 && IS_PREG (1, poprnd))
{
OUTS (outf, "JUMP (");
OUTS (outf, pregs (poprnd));
OUTS (outf, ")");
}
- else if (prgfunc == 6)
+ else if (prgfunc == 6 && IS_PREG (1, poprnd))
{
OUTS (outf, "CALL (");
OUTS (outf, pregs (poprnd));
OUTS (outf, ")");
}
- else if (prgfunc == 7)
+ else if (prgfunc == 7 && IS_PREG (1, poprnd))
{
OUTS (outf, "CALL (PC + ");
OUTS (outf, pregs (poprnd));
OUTS (outf, ")");
}
- else if (prgfunc == 8)
+ else if (prgfunc == 8 && IS_PREG (1, poprnd))
{
OUTS (outf, "JUMP (PC + ");
OUTS (outf, pregs (poprnd));
@@ -817,7 +822,7 @@ decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
OUTS (outf, "EXCPT ");
OUTS (outf, uimm4 (poprnd));
}
- else if (prgfunc == 11)
+ else if (prgfunc == 11 && IS_PREG (1, poprnd))
{
OUTS (outf, "TESTSET (");
OUTS (outf, pregs (poprnd));
@@ -903,12 +908,12 @@ decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
- if (W == 0)
+ if (W == 0 && mostreg (reg, grp))
{
OUTS (outf, allregs (reg, grp));
OUTS (outf, " = [SP++]");
}
- else if (W == 1)
+ else if (W == 1 && allreg (reg, grp))
{
OUTS (outf, "[--SP] = ");
OUTS (outf, allregs (reg, grp));
@@ -1203,7 +1208,7 @@ decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
OUTS (outf, "CC = ");
OUTS (outf, dregs (reg));
}
- else if (op == 3)
+ else if (op == 3 && reg == 0)
OUTS (outf, "CC = !CC");
else
return 0;
--
1.7.2
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] opcodes: blackfin: decode insns with invalid register as illegal
2010-09-21 8:35 [PATCH] opcodes: blackfin: decode insns with invalid register as illegal Mike Frysinger
@ 2010-09-22 21:39 ` Mike Frysinger
0 siblings, 0 replies; 2+ messages in thread
From: Mike Frysinger @ 2010-09-22 21:39 UTC (permalink / raw)
To: binutils; +Cc: Robin Getz
[-- Attachment #1: Type: Text/Plain, Size: 352 bytes --]
On Tuesday, September 21, 2010 04:34:48 Mike Frysinger wrote:
> From: Robin Getz <robin.getz@analog.com>
>
> Sometimes the encoding in the opcode is a 4 bit field which defines a
> register number. However, register numbers are only 0-7, so make sure
> we call illegal for when the opcode register number is greater than 8.
committed
-mike
[-- Attachment #2: This is a digitally signed message part. --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2010-09-22 21:39 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2010-09-21 8:35 [PATCH] opcodes: blackfin: decode insns with invalid register as illegal Mike Frysinger
2010-09-22 21:39 ` Mike Frysinger
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).