* [PATCH, ARM] MSR/MRS assembly and disassembly tweaks
@ 2011-04-04 14:07 Julian Brown
2011-04-08 16:25 ` Nick Clifton
` (2 more replies)
0 siblings, 3 replies; 14+ messages in thread
From: Julian Brown @ 2011-04-04 14:07 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 3569 bytes --]
Hi,
This patch improves handling of MSR and MRS instructions in GAS, and
also improves disassembly output in a couple of cases.
In more detail:
1. It should be possible to use APSR as a synonym for CPSR on e.g.
ARMv7-A and ARMv7-R cores, but the current implementation assembles an
MSR instruction with the "fc" fields set on such cores. I think this is
wrong: I fixed it to only set the "f" field in such cases.
2. Also in MSR instructions, "nzcvqg" bits can now be written in any
order, to bring them in line with other PSR instructions (e.g. "msr
CPSR_<fields>, rX", where <fields> can be in any order). You may only
write "g" if the selected processor for assembly supports the DSP
extension, else you will get an error.
3. Disassembling MSR instructions referring to IAPSR, EAPSR or XPSR now
shows bitfield syntax, "nzcvq" or "g". For APSR itself, the instruction
is still disassembled as CPSR_<fields> though, regardless of
architecture version.
4. BASEPRI_MASK is renamed to BASEPRI_MAX in disassembly (presumably
that was simply a typo).
5. Using plain "APSR" in MSR instructions (as an alias for "APSR_nzcvq")
is deprecated (DDI0403D_armv7m_arm.pdf, B5-799). I've implemented that
by emitting an assembler warning, but that might be a little too
aggressive.
6. VFP control registers are no longer accepted during parsing of
MSR/MRS. There's no testsuite coverage for that feature, and I'm not
sure what it was supposed to do. I didn't find any sign of it in the
ARM ARM, though I may have missed something.
I've added several new test cases to cover the modified functionality.
(Some may be a little redundant: I wrote this patch off an older branch
originally and didn't know about the new tests. They won't hurt though.)
OK to apply?
Thanks,
Julian
ChangeLog
gas/
* config/tc-arm.c (parse_psr): Add LHS argument. Improve support
for *APSR bitmasks.
(operand_parse_code): Replace OP_PSR with OP_wPSR and OP_rPSR.
Remove OP_RVC_PSR.
(parse_operands): Likewise.
(do_mrs): Tweak error message for constraint.
(do_t_mrs): Update constraints for changes to APSR support.
(do_t_msr): Likewise. Don't set PSR_f flag here.
(psrs): Remove "g", "nzcvq", "nzcvqg".
(insns): Tweak entries for msr and mrs instructions.
opcodes/
* arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
(print_insn_thumb32): Add APSR bitmask support.
gas/testsuite/
* gas/arm/mrs-msr-thumb-v7-m.s: New.
* gas/arm/mrs-msr-thumb-v7-m.d: New.
* gas/arm/mrs-msr-thumb-v7-m-bad.d: New.
* gas/arm/mrs-msr-thumb-v7-m-bad.l: New.
* gas/arm/mrs-msr-thumb-v7-m-bad.s: New.
* gas/arm/mrs-msr-thumb-v7e-m.d: New.
* gas/arm/mrs-msr-thumb-v7e-m.s: New.
* gas/arm/mrs-msr-arm-v7-a-bad.d: New.
* gas/arm/mrs-msr-arm-v7-a-bad.l: New.
* gas/arm/mrs-msr-arm-v7-a-bad.s: New.
* gas/arm/mrs-msr-arm-v7-a.d: New.
* gas/arm/mrs-msr-arm-v7-a.s: New.
* gas/arm/mrs-msr-arm-v6.d: New.
* gas/arm/mrs-msr-arm-v6.s: New.
* gas/arm/mrs-msr-thumb-v6t2.d: New.
* gas/arm/mrs-msr-thumb-v6t2.s: New.
* gas/arm/arch7.d: Fix typo in disassembly for BASEPRI_MAX,
bitmasks for IAPSR etc.
* gas/arm/arch7.s: Specify bitmask for APSR writes.
* gas/arm/archv6m.s: Likewise.
* msr-imm-bad.l: Tweak expected disassembly in error message.
* msr-reg-bad.l: Likewise.
* msr-imm.d: Tweak expected disassembly.
* msr-reg.d: Likewise.
* msr-reg-thumb.d: Likewise.
* msr-imm.s: Specify bitmask on APSR writes.
* msr-reg.s: Add comment about deprecated usage.
[-- Attachment #2: binutils-mrs-msr-fixes-fsf-6.diff --]
[-- Type: text/x-patch, Size: 38476 bytes --]
? gas/testsuite/gas/arm/a.out
Index: gas/config/tc-arm.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-arm.c,v
retrieving revision 1.478
diff -c -p -r1.478 tc-arm.c
*** gas/config/tc-arm.c 14 Mar 2011 16:04:12 -0000 1.478
--- gas/config/tc-arm.c 4 Apr 2011 13:57:22 -0000
*************** parse_half (char **str)
*** 5347,5385 ****
/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
or a bitmask suitable to be or-ed into the ARM msr instruction. */
static int
! parse_psr (char **str)
{
char *p;
unsigned long psr_field;
const struct asm_psr *psr;
char *start;
/* CPSR's and SPSR's can now be lowercase. This is just a convenience
feature for ease of use and backwards compatibility. */
p = *str;
if (strncasecmp (p, "SPSR", 4) == 0)
! psr_field = SPSR_BIT;
! else if (strncasecmp (p, "CPSR", 4) == 0
! || (strncasecmp (p, "APSR", 4) == 0
! && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)))
! psr_field = 0;
! else
{
start = p;
do
p++;
while (ISALNUM (*p) || *p == '_');
psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
p - start);
if (!psr)
return FAIL;
*str = p;
! return psr->field;
}
p += 4;
if (*p == '_')
{
/* A suffix follows. */
--- 5347,5425 ----
/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
or a bitmask suitable to be or-ed into the ARM msr instruction. */
static int
! parse_psr (char **str, bfd_boolean lhs)
{
char *p;
unsigned long psr_field;
const struct asm_psr *psr;
char *start;
+ bfd_boolean is_apsr = FALSE;
+ bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m);
/* CPSR's and SPSR's can now be lowercase. This is just a convenience
feature for ease of use and backwards compatibility. */
p = *str;
if (strncasecmp (p, "SPSR", 4) == 0)
! {
! if (m_profile)
! goto unsupported_psr;
!
! psr_field = SPSR_BIT;
! }
! else if (strncasecmp (p, "CPSR", 4) == 0)
! {
! if (m_profile)
! goto unsupported_psr;
!
! psr_field = 0;
! }
! else if (strncasecmp (p, "APSR", 4) == 0)
! {
! /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
! and ARMv7-R architecture CPUs. */
! is_apsr = TRUE;
! psr_field = 0;
! }
! else if (m_profile)
{
start = p;
do
p++;
while (ISALNUM (*p) || *p == '_');
+ if (strncasecmp (start, "iapsr", 5) == 0
+ || strncasecmp (start, "eapsr", 5) == 0
+ || strncasecmp (start, "xpsr", 4) == 0
+ || strncasecmp (start, "psr", 3) == 0)
+ p = start + strcspn (start, "rR") + 1;
+
psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
p - start);
+
if (!psr)
return FAIL;
+ /* If APSR is being written, a bitfield may be specified. Note that
+ APSR itself is handled above. */
+ if (psr->field <= 3)
+ {
+ psr_field = psr->field;
+ is_apsr = TRUE;
+ goto check_suffix;
+ }
+
*str = p;
! /* M-profile MSR instructions have the mask field set to "10", except
! *PSR variants which modify APSR, which may use a different mask (and
! have been handled already). Do that by setting the PSR_f field
! here. */
! return psr->field | (lhs ? PSR_f : 0);
}
+ else
+ goto unsupported_psr;
p += 4;
+ check_suffix:
if (*p == '_')
{
/* A suffix follows. */
*************** parse_psr (char **str)
*** 5390,5412 ****
p++;
while (ISALNUM (*p) || *p == '_');
! psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
! p - start);
! if (!psr)
! goto error;
! psr_field |= psr->field;
}
else
{
if (ISALNUM (*p))
goto error; /* Garbage after "[CS]PSR". */
! psr_field |= (PSR_c | PSR_f);
}
*str = p;
return psr_field;
error:
inst.error = _("flag for {c}psr instruction expected");
return FAIL;
--- 5430,5535 ----
p++;
while (ISALNUM (*p) || *p == '_');
! if (is_apsr)
! {
! /* APSR uses a notation for bits, rather than fields. */
! unsigned int nzcvq_bits = 0;
! unsigned int g_bit = 0;
! char *bit;
!
! for (bit = start; bit != p; bit++)
! {
! switch (TOLOWER (*bit))
! {
! case 'n':
! nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
! break;
!
! case 'z':
! nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
! break;
!
! case 'c':
! nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
! break;
!
! case 'v':
! nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
! break;
!
! case 'q':
! nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
! break;
!
! case 'g':
! g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
! break;
!
! default:
! inst.error = _("unexpected bit specified after APSR");
! return FAIL;
! }
! }
!
! if (nzcvq_bits == 0x1f)
! psr_field |= PSR_f;
!
! if (g_bit == 0x1)
! {
! if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
! {
! inst.error = _("selected processor does not "
! "support DSP extension");
! return FAIL;
! }
!
! psr_field |= PSR_s;
! }
!
! if ((nzcvq_bits & 0x20) != 0
! || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
! || (g_bit & 0x2) != 0)
! {
! inst.error = _("bad bitmask specified after APSR");
! return FAIL;
! }
! }
! else
! {
! psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
! p - start);
! if (!psr)
! goto error;
! psr_field |= psr->field;
! }
}
else
{
if (ISALNUM (*p))
goto error; /* Garbage after "[CS]PSR". */
! /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
! is deprecated, but allow it anyway. */
! if (is_apsr && lhs)
! {
! psr_field |= PSR_f;
! as_tsktsk (_("writing to APSR without specifying a bitmask is "
! "deprecated"));
! }
! else if (!m_profile)
! /* These bits are never right for M-profile devices: don't set them
! (only code paths which read/write APSR reach here). */
! psr_field |= (PSR_c | PSR_f);
}
*str = p;
return psr_field;
+ unsupported_psr:
+ inst.error = _("selected processor does not support requested special "
+ "purpose register");
+ return FAIL;
+
error:
inst.error = _("flag for {c}psr instruction expected");
return FAIL;
*************** enum operand_parse_code
*** 5932,5942 ****
OP_CPSF, /* CPS flags */
OP_ENDI, /* Endianness specifier */
! OP_PSR, /* CPSR/SPSR mask for msr */
OP_COND, /* conditional code */
OP_TB, /* Table branch. */
- OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */
OP_APSR_RR, /* ARM register or "APSR_nzcv". */
OP_RRnpc_I0, /* ARM register or literal 0 */
--- 6055,6065 ----
OP_CPSF, /* CPS flags */
OP_ENDI, /* Endianness specifier */
! OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
! OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
OP_COND, /* conditional code */
OP_TB, /* Table branch. */
OP_APSR_RR, /* ARM register or "APSR_nzcv". */
OP_RRnpc_I0, /* ARM register or literal 0 */
*************** parse_operands (char *str, const unsigne
*** 6402,6408 ****
case OP_CPSF: val = parse_cps_flags (&str); break;
case OP_ENDI: val = parse_endian_specifier (&str); break;
case OP_oROR: val = parse_ror (&str); break;
- case OP_PSR: val = parse_psr (&str); break;
case OP_COND: val = parse_cond (&str); break;
case OP_oBARRIER_I15:
po_barrier_or_imm (str); break;
--- 6525,6530 ----
*************** parse_operands (char *str, const unsigne
*** 6411,6421 ****
goto failure;
break;
! case OP_RVC_PSR:
! po_reg_or_goto (REG_TYPE_VFC, try_banked_reg);
! inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */
! break;
! try_banked_reg:
po_reg_or_goto (REG_TYPE_RNB, try_psr);
if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
{
--- 6533,6540 ----
goto failure;
break;
! case OP_wPSR:
! case OP_rPSR:
po_reg_or_goto (REG_TYPE_RNB, try_psr);
if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
{
*************** parse_operands (char *str, const unsigne
*** 6424,6432 ****
goto failure;
}
break;
! try_psr:
! val = parse_psr (&str);
! break;
case OP_APSR_RR:
po_reg_or_goto (REG_TYPE_RN, try_apsr);
--- 6543,6551 ----
goto failure;
}
break;
! try_psr:
! val = parse_psr (&str, op_parse_code == OP_wPSR);
! break;
case OP_APSR_RR:
po_reg_or_goto (REG_TYPE_RN, try_apsr);
*************** parse_operands (char *str, const unsigne
*** 6583,6590 ****
case OP_CPSF:
case OP_ENDI:
case OP_oROR:
! case OP_PSR:
! case OP_RVC_PSR:
case OP_COND:
case OP_oBARRIER_I15:
case OP_REGLST:
--- 6702,6709 ----
case OP_CPSF:
case OP_ENDI:
case OP_oROR:
! case OP_wPSR:
! case OP_rPSR:
case OP_COND:
case OP_oBARRIER_I15:
case OP_REGLST:
*************** do_mrs (void)
*** 7912,7918 ****
/* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
!= (PSR_c|PSR_f),
! _("'CPSR' or 'SPSR' expected"));
br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
}
--- 8031,8037 ----
/* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
!= (PSR_c|PSR_f),
! _("'APSR', 'CPSR' or 'SPSR' expected"));
br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
}
*************** do_t_mrs (void)
*** 10828,10848 ****
{
int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
! if (flags == 0)
! {
! constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m),
! _("selected processor does not support "
! "requested special purpose register"));
! }
! else
! {
! constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
! _("selected processor does not support "
! "requested special purpose register"));
! /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
! constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
! _("'CPSR' or 'SPSR' expected"));
! }
inst.instruction |= (flags & SPSR_BIT) >> 2;
inst.instruction |= inst.operands[1].imm & 0xff;
--- 10947,10960 ----
{
int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
! if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
! constraint (flags != 0, _("selected processor does not support "
! "requested special purpose register"));
! else
! /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
! devices). */
! constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
! _("'APSR', 'CPSR' or 'SPSR' expected"));
inst.instruction |= (flags & SPSR_BIT) >> 2;
inst.instruction |= inst.operands[1].imm & 0xff;
*************** do_t_msr (void)
*** 10867,10885 ****
else
flags = inst.operands[0].imm;
! if (flags & ~0xff)
{
! constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
! _("selected processor does not support "
! "requested special purpose register"));
}
else
! {
! constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m),
! _("selected processor does not support "
! "requested special purpose register"));
! flags |= PSR_f;
! }
Rn = inst.operands[1].reg;
reject_bad_reg (Rn);
--- 10979,10998 ----
else
flags = inst.operands[0].imm;
! if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
{
! int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
!
! constraint ((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
! && (bits & ~(PSR_s | PSR_f)) != 0)
! || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
! && bits != PSR_f),
! _("selected processor does not support requested special "
! "purpose register"));
}
else
! constraint ((flags & 0xff) != 0, _("selected processor does not support "
! "requested special purpose register"));
Rn = inst.operands[1].reg;
reject_bad_reg (Rn);
*************** static const struct asm_psr psrs[] =
*** 16440,16446 ****
{"c", PSR_c},
{"x", PSR_x},
{"s", PSR_s},
- {"g", PSR_s},
/* Combinations of flags. */
{"fs", PSR_f | PSR_s},
--- 16553,16558 ----
*************** static const struct asm_psr psrs[] =
*** 16503,16512 ****
{"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
{"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
{"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
-
- /* APSR flags */
- {"nzcvq", PSR_f},
- {"nzcvqg", PSR_s | PSR_f}
};
/* Table of V7M psr names. */
--- 16615,16620 ----
*************** static const struct asm_opcode insns[] =
*** 16955,16962 ****
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_msr
! TCE("mrs", 1000000, f3e08000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs),
! TCE("msr", 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr),
#undef ARM_VARIANT
#define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
--- 17063,17070 ----
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_msr
! TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
! TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
#undef ARM_VARIANT
#define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
Index: gas/testsuite/gas/arm/arch7.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/arch7.d,v
retrieving revision 1.6
diff -c -p -r1.6 arch7.d
*** gas/testsuite/gas/arm/arch7.d 17 Sep 2010 10:42:04 -0000 1.6
--- gas/testsuite/gas/arm/arch7.d 4 Apr 2011 13:57:22 -0000
*************** Disassembly of section .text:
*** 57,69 ****
0+0c0 <[^>]*> f3ef 8009 mrs r0, PSP
0+0c4 <[^>]*> f3ef 8010 mrs r0, PRIMASK
0+0c8 <[^>]*> f3ef 8011 mrs r0, BASEPRI
! 0+0cc <[^>]*> f3ef 8012 mrs r0, BASEPRI_MASK
0+0d0 <[^>]*> f3ef 8013 mrs r0, FAULTMASK
0+0d4 <[^>]*> f3ef 8014 mrs r0, CONTROL
! 0+0d8 <[^>]*> f380 8800 msr (CPSR_f|APSR), r0
! 0+0dc <[^>]*> f380 8801 msr IAPSR, r0
! 0+0e0 <[^>]*> f380 8802 msr EAPSR, r0
! 0+0e4 <[^>]*> f380 8803 msr PSR, r0
0+0e8 <[^>]*> f380 8805 msr IPSR, r0
0+0ec <[^>]*> f380 8806 msr EPSR, r0
0+0f0 <[^>]*> f380 8807 msr IEPSR, r0
--- 57,69 ----
0+0c0 <[^>]*> f3ef 8009 mrs r0, PSP
0+0c4 <[^>]*> f3ef 8010 mrs r0, PRIMASK
0+0c8 <[^>]*> f3ef 8011 mrs r0, BASEPRI
! 0+0cc <[^>]*> f3ef 8012 mrs r0, BASEPRI_MAX
0+0d0 <[^>]*> f3ef 8013 mrs r0, FAULTMASK
0+0d4 <[^>]*> f3ef 8014 mrs r0, CONTROL
! 0+0d8 <[^>]*> f380 8800 msr (CPSR_f|APSR_nzcvq), r0
! 0+0dc <[^>]*> f380 8801 msr IAPSR_nzcvq, r0
! 0+0e0 <[^>]*> f380 8802 msr EAPSR_nzcvq, r0
! 0+0e4 <[^>]*> f380 8803 msr PSR_nzcvq, r0
0+0e8 <[^>]*> f380 8805 msr IPSR, r0
0+0ec <[^>]*> f380 8806 msr EPSR, r0
0+0f0 <[^>]*> f380 8807 msr IEPSR, r0
*************** Disassembly of section .text:
*** 71,78 ****
0+0f8 <[^>]*> f380 8809 msr PSP, r0
0+0fc <[^>]*> f380 8810 msr PRIMASK, r0
0+100 <[^>]*> f380 8811 msr BASEPRI, r0
! 0+104 <[^>]*> f380 8812 msr BASEPRI_MASK, r0
0+108 <[^>]*> f380 8813 msr FAULTMASK, r0
0+10c <[^>]*> f380 8814 msr CONTROL, r0
0+110 <[^>]*> f3ef 8003 mrs r0, PSR
! 0+114 <[^>]*> f380 8803 msr PSR, r0
--- 71,78 ----
0+0f8 <[^>]*> f380 8809 msr PSP, r0
0+0fc <[^>]*> f380 8810 msr PRIMASK, r0
0+100 <[^>]*> f380 8811 msr BASEPRI, r0
! 0+104 <[^>]*> f380 8812 msr BASEPRI_MAX, r0
0+108 <[^>]*> f380 8813 msr FAULTMASK, r0
0+10c <[^>]*> f380 8814 msr CONTROL, r0
0+110 <[^>]*> f3ef 8003 mrs r0, PSR
! 0+114 <[^>]*> f380 8803 msr PSR_nzcvq, r0
Index: gas/testsuite/gas/arm/arch7.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/arch7.s,v
retrieving revision 1.2
diff -c -p -r1.2 arch7.s
*** gas/testsuite/gas/arm/arch7.s 17 Sep 2010 10:42:04 -0000 1.2
--- gas/testsuite/gas/arm/arch7.s 4 Apr 2011 13:57:22 -0000
*************** label2:
*** 63,72 ****
mrs r0, basepri_max
mrs r0, faultmask
mrs r0, control
! msr apsr, r0
! msr iapsr, r0
! msr eapsr, r0
! msr psr, r0
msr ipsr, r0
msr epsr, r0
msr iepsr, r0
--- 63,72 ----
mrs r0, basepri_max
mrs r0, faultmask
mrs r0, control
! msr apsr_nzcvq, r0
! msr iapsr_nzcvq, r0
! msr eapsr_nzcvq, r0
! msr psr_nzcvq, r0
msr ipsr, r0
msr epsr, r0
msr iepsr, r0
*************** label2:
*** 78,81 ****
msr faultmask, r0
msr control, r0
mrs r0, xpsr
! msr xpsr, r0
--- 78,81 ----
msr faultmask, r0
msr control, r0
mrs r0, xpsr
! msr xpsr_nzcvq, r0
Index: gas/testsuite/gas/arm/archv6m.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/archv6m.s,v
retrieving revision 1.2
diff -c -p -r1.2 archv6m.s
*** gas/testsuite/gas/arm/archv6m.s 2 Mar 2009 00:29:23 -0000 1.2
--- gas/testsuite/gas/arm/archv6m.s 4 Apr 2011 13:57:22 -0000
***************
*** 5,11 ****
.align 2
.global foo
foo:
! msr apsr,r6
msr epsr,r9
mrs r2, iapsr
yield
--- 5,11 ----
.align 2
.global foo
foo:
! msr apsr_nzcvq,r6
msr epsr,r9
mrs r2, iapsr
yield
Index: gas/testsuite/gas/arm/mrs-msr-arm-v6.d
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-arm-v6.d
diff -N gas/testsuite/gas/arm/mrs-msr-arm-v6.d
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-arm-v6.d 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,16 ----
+ #objdump: -dr --prefix-addresses --show-raw-insn
+ #name: MRS/MSR test, architecture v6, ARM mode
+
+ .*: file format .*
+
+
+ Disassembly of section .text:
+ 0+00 <[^>]*> e10f4000 mrs r4, CPSR
+ 0+04 <[^>]*> e10f5000 mrs r5, CPSR
+ 0+08 <[^>]*> e14f6000 mrs r6, SPSR
+ 0+0c <[^>]*> e328f101 msr CPSR_f, #1073741824 ; 0x40000000
+ 0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 ; 0x20000000
+ 0+14 <[^>]*> e369f201 msr SPSR_fc, #268435456 ; 0x10000000
+ 0+18 <[^>]*> e128f004 msr CPSR_f, r4
+ 0+1c <[^>]*> e128f005 msr CPSR_f, r5
+ 0+20 <[^>]*> e169f006 msr SPSR_fc, r6
Index: gas/testsuite/gas/arm/mrs-msr-arm-v6.s
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-arm-v6.s
diff -N gas/testsuite/gas/arm/mrs-msr-arm-v6.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-arm-v6.s 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,13 ----
+ .arch armv6
+ .text
+ .arm
+
+ mrs r4, apsr
+ mrs r5, cpsr
+ mrs r6, spsr
+ msr apsr_nzcvq, #0x40000000
+ msr cpsr_f, #0x20000000
+ msr spsr, #0x10000000
+ msr apsr_nzcvq, r4
+ msr cpsr_f, r5
+ msr spsr, r6
Index: gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.d
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.d
diff -N gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.d
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.d 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,2 ----
+ # name: MRS/MSR negative test, architecture v7-A, ARM mode
+ # error-output: mrs-msr-arm-v7-a-bad.l
Index: gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.l
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.l
diff -N gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.l
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.l 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,5 ----
+ [^:]*: Assembler messages:
+ [^:]*:5: Error: 'APSR', 'CPSR' or 'SPSR' expected -- `mrs r4,apsr_nzcvq'
+ [^:]*:6: Error: selected processor does not support requested special purpose register -- `mrs r5,iapsr'
+ [^:]*:7: Error: selected processor does not support requested special purpose register -- `msr iapsr,r4'
+ [^:]*:8: writing to APSR without specifying a bitmask is deprecated
Index: gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.s
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.s
diff -N gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.s 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,8 ----
+ .arch armv7-a
+ .text
+ .arm
+
+ mrs r4, apsr_nzcvq
+ mrs r5, iapsr
+ msr iapsr, r4
+ msr apsr, r5
Index: gas/testsuite/gas/arm/mrs-msr-arm-v7-a.d
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-arm-v7-a.d
diff -N gas/testsuite/gas/arm/mrs-msr-arm-v7-a.d
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-arm-v7-a.d 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,16 ----
+ #objdump: -dr --prefix-addresses --show-raw-insn
+ #name: MRS/MSR test, architecture v7-A, ARM mode
+
+ .*: file format .*
+
+
+ Disassembly of section .text:
+ 0+00 <[^>]*> e10f4000 mrs r4, CPSR
+ 0+04 <[^>]*> e10f5000 mrs r5, CPSR
+ 0+08 <[^>]*> e14f6000 mrs r6, SPSR
+ 0+0c <[^>]*> e32cf101 msr CPSR_fs, #1073741824 ; 0x40000000
+ 0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 ; 0x20000000
+ 0+14 <[^>]*> e369f201 msr SPSR_fc, #268435456 ; 0x10000000
+ 0+18 <[^>]*> e128f004 msr CPSR_f, r4
+ 0+1c <[^>]*> e128f005 msr CPSR_f, r5
+ 0+20 <[^>]*> e169f006 msr SPSR_fc, r6
Index: gas/testsuite/gas/arm/mrs-msr-arm-v7-a.s
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-arm-v7-a.s
diff -N gas/testsuite/gas/arm/mrs-msr-arm-v7-a.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-arm-v7-a.s 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,13 ----
+ .arch armv7-a
+ .text
+ .arm
+
+ mrs r4, apsr
+ mrs r5, cpsr
+ mrs r6, spsr
+ msr apsr_nzcvqg, #0x40000000
+ msr cpsr_f, #0x20000000
+ msr spsr, #0x10000000
+ msr apsr_nzcvq, r4
+ msr cpsr_f, r5
+ msr spsr, r6
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.d
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.d
diff -N gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.d
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.d 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,13 ----
+ #objdump: -dr --prefix-addresses --show-raw-insn
+ #name: MRS/MSR test, architecture v6t2, Thumb mode
+
+ .*: file format .*
+
+
+ Disassembly of section .text:
+ 0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
+ 0+04 <[^>]*> f3ef 8500 mrs r5, CPSR
+ 0+08 <[^>]*> f3ff 8600 mrs r6, SPSR
+ 0+0c <[^>]*> f384 8c00 msr CPSR_fs, r4
+ 0+10 <[^>]*> f385 8800 msr CPSR_f, r5
+ 0+14 <[^>]*> f396 8900 msr SPSR_fc, r6
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.s
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.s
diff -N gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.s 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,10 ----
+ .arch armv6t2
+ .text
+ .thumb
+
+ mrs r4, apsr
+ mrs r5, cpsr
+ mrs r6, spsr
+ msr apsr_nzcvqg, r4
+ msr cpsr_f, r5
+ msr spsr, r6
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.d
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.d
diff -N gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.d
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.d 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,2 ----
+ # name: MRS/MSR negative test, architecture v7-M, Thumb mode
+ # error-output: mrs-msr-thumb-v7-m-bad.l
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.l
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.l
diff -N gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.l
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.l 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,10 ----
+ [^:]*: Assembler messages:
+ [^:]*:5: Error: selected processor does not support requested special purpose register -- `mrs r4,cpsr'
+ [^:]*:6: Error: selected processor does not support requested special purpose register -- `mrs r5,spsr'
+ [^:]*:7: Error: selected processor does not support DSP extension -- `msr apsr_nzcvqg,r4'
+ [^:]*:8: Error: selected processor does not support DSP extension -- `msr iapsr_nzcvqg,r5'
+ [^:]*:9: Error: bad bitmask specified after APSR -- `msr xpsr_nncvq,r6'
+ [^:]*:10: Error: bad bitmask specified after APSR -- `msr xpsr_nzcv,r7'
+ [^:]*:11: Error: selected processor does not support requested special purpose register -- `msr cpsr_f,r7'
+ [^:]*:12: Error: selected processor does not support requested special purpose register -- `msr spsr,r8'
+ [^:]*:13: Error: syntax error -- `msr primask_nzcvq,r9'
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.s
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.s
diff -N gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.s 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,13 ----
+ .arch armv7-m
+ .text
+ .thumb
+
+ mrs r4, cpsr
+ mrs r5, spsr
+ msr apsr_nzcvqg, r4
+ msr iapsr_nzcvqg, r5
+ msr xpsr_nncvq, r6
+ msr xpsr_nzcv, r7
+ msr cpsr_f, r7
+ msr spsr, r8
+ msr primask_nzcvq, r9
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.d
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.d
diff -N gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.d
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.d 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,15 ----
+ #objdump: -dr --prefix-addresses --show-raw-insn
+ #name: MRS/MSR test, architecture v7-M, Thumb mode
+
+
+ .*: file format .*
+
+
+ Disassembly of section .text:
+ 0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
+ 0+04 <[^>]*> f3ef 8502 mrs r5, EAPSR
+ 0+08 <[^>]*> f3ef 8610 mrs r6, PRIMASK
+ 0+0c <[^>]*> f383 8803 msr PSR_nzcvq, r3
+ 0+10 <[^>]*> f384 8800 msr CPSR_f, r4
+ 0+14 <[^>]*> f385 8801 msr IAPSR_nzcvq, r5
+ 0+18 <[^>]*> f386 8810 msr PRIMASK, r6
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.s
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.s
diff -N gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.s 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,11 ----
+ .arch armv7-m
+ .text
+ .thumb
+
+ mrs r4, apsr
+ mrs r5, eapsr
+ mrs r6, primask
+ msr xpsr_nzcvq, r3
+ msr apsr_nzcvq, r4
+ msr iapsr_nzcvq, r5
+ msr primask, r6
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d
diff -N gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,13 ----
+ #objdump: -dr --prefix-addresses --show-raw-insn
+ #name: MRS/MSR test, architecture v7e-M, Thumb mode
+
+ .*: file format .*
+
+
+ Disassembly of section .text:
+ 0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
+ 0+04 <[^>]*> f3ef 8502 mrs r5, EAPSR
+ 0+08 <[^>]*> f3ef 8610 mrs r6, PRIMASK
+ 0+0c <[^>]*> f384 8c00 msr CPSR_fs, r4
+ 0+10 <[^>]*> f385 8401 msr IAPSR_g, r5
+ 0+14 <[^>]*> f386 8812 msr BASEPRI_MAX, r6
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s
diff -N gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,10 ----
+ .arch armv7e-m
+ .text
+ .thumb
+
+ mrs r4, apsr
+ mrs r5, eapsr
+ mrs r6, primask
+ msr apsr_nzcvqg, r4
+ msr iapsr_g, r5
+ msr basepri_max, r6
Index: gas/testsuite/gas/arm/msr-imm-bad.l
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/msr-imm-bad.l,v
retrieving revision 1.1
diff -c -p -r1.1 msr-imm-bad.l
*** gas/testsuite/gas/arm/msr-imm-bad.l 17 Sep 2010 10:42:04 -0000 1.1
--- gas/testsuite/gas/arm/msr-imm-bad.l 4 Apr 2011 13:57:22 -0000
***************
*** 1,5 ****
[^:]*: Assembler messages:
! [^:]*:9: Error: Thumb encoding does not support an immediate here -- `msr APSR,#0xc0000004'
[^:]*:10: Error: Thumb encoding does not support an immediate here -- `msr APSR_g,#0xc0000004'
[^:]*:11: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvq,#0xc0000004'
[^:]*:12: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvqg,#0xc0000004'
--- 1,5 ----
[^:]*: Assembler messages:
! [^:]*:9: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvq,#0xc0000004'
[^:]*:10: Error: Thumb encoding does not support an immediate here -- `msr APSR_g,#0xc0000004'
[^:]*:11: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvq,#0xc0000004'
[^:]*:12: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvqg,#0xc0000004'
Index: gas/testsuite/gas/arm/msr-imm.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/msr-imm.d,v
retrieving revision 1.1
diff -c -p -r1.1 msr-imm.d
*** gas/testsuite/gas/arm/msr-imm.d 17 Sep 2010 10:42:04 -0000 1.1
--- gas/testsuite/gas/arm/msr-imm.d 4 Apr 2011 13:57:22 -0000
***************
*** 5,11 ****
.*: +file format .*arm.*
Disassembly of section .text:
! 00000000 <[^>]*> e329f113 msr CPSR_fc, #-1073741820 ; 0xc0000004
00000004 <[^>]*> e324f113 msr CPSR_s, #-1073741820 ; 0xc0000004
00000008 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
0000000c <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 ; 0xc0000004
--- 5,11 ----
.*: +file format .*arm.*
Disassembly of section .text:
! 00000000 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
00000004 <[^>]*> e324f113 msr CPSR_s, #-1073741820 ; 0xc0000004
00000008 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
0000000c <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 ; 0xc0000004
Index: gas/testsuite/gas/arm/msr-imm.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/msr-imm.s,v
retrieving revision 1.1
diff -c -p -r1.1 msr-imm.s
*** gas/testsuite/gas/arm/msr-imm.s 17 Sep 2010 10:42:04 -0000 1.1
--- gas/testsuite/gas/arm/msr-imm.s 4 Apr 2011 13:57:22 -0000
***************
*** 6,12 ****
@ Write to Special Register from Immediate
@ Write to application status register
! msr APSR,#0xc0000004
msr APSR_g,#0xc0000004
msr APSR_nzcvq,#0xc0000004
msr APSR_nzcvqg,#0xc0000004
--- 6,12 ----
@ Write to Special Register from Immediate
@ Write to application status register
! msr APSR_nzcvq,#0xc0000004
msr APSR_g,#0xc0000004
msr APSR_nzcvq,#0xc0000004
msr APSR_nzcvqg,#0xc0000004
Index: gas/testsuite/gas/arm/msr-reg-bad.l
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/msr-reg-bad.l,v
retrieving revision 1.1
diff -c -p -r1.1 msr-reg-bad.l
*** gas/testsuite/gas/arm/msr-reg-bad.l 17 Sep 2010 10:42:04 -0000 1.1
--- gas/testsuite/gas/arm/msr-reg-bad.l 4 Apr 2011 13:57:22 -0000
***************
*** 1,7 ****
[^:]*: Assembler messages:
! [^:]*:9: Error: syntax error -- `msr APSR_g,r9'
! [^:]*:10: Error: syntax error -- `msr APSR_nzcvq,r9'
! [^:]*:11: Error: syntax error -- `msr APSR_nzcvqg,r9'
[^:]*:14: Error: selected processor does not support requested special purpose register -- `msr CPSR,r9'
[^:]*:15: Error: selected processor does not support requested special purpose register -- `msr CPSR_s,r9'
[^:]*:16: Error: selected processor does not support requested special purpose register -- `msr CPSR_f,r9'
--- 1,7 ----
[^:]*: Assembler messages:
! [^:]*:8: writing to APSR without specifying a bitmask is deprecated
! [^:]*:9: Error: selected processor does not support DSP extension -- `msr APSR_g,r9'
! [^:]*:11: Error: selected processor does not support DSP extension -- `msr APSR_nzcvqg,r9'
[^:]*:14: Error: selected processor does not support requested special purpose register -- `msr CPSR,r9'
[^:]*:15: Error: selected processor does not support requested special purpose register -- `msr CPSR_s,r9'
[^:]*:16: Error: selected processor does not support requested special purpose register -- `msr CPSR_f,r9'
Index: gas/testsuite/gas/arm/msr-reg-thumb.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/msr-reg-thumb.d,v
retrieving revision 1.2
diff -c -p -r1.2 msr-reg-thumb.d
*** gas/testsuite/gas/arm/msr-reg-thumb.d 22 Oct 2010 08:13:58 -0000 1.2
--- gas/testsuite/gas/arm/msr-reg-thumb.d 4 Apr 2011 13:57:22 -0000
***************
*** 2,13 ****
# as: -march=armv7-a -mthumb
# source: msr-reg.s
# objdump: -dr --prefix-addresses --show-raw-insn
# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
.*: +file format .*arm.*
Disassembly of section .text:
! 00000000 <[^>]*> f389 8900 msr CPSR_fc, r9
00000004 <[^>]*> f389 8400 msr CPSR_s, r9
00000008 <[^>]*> f389 8800 msr CPSR_f, r9
0000000c <[^>]*> f389 8c00 msr CPSR_fs, r9
--- 2,14 ----
# as: -march=armv7-a -mthumb
# source: msr-reg.s
# objdump: -dr --prefix-addresses --show-raw-insn
+ # warning: writing to APSR without specifying a bitmask is deprecated
# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
.*: +file format .*arm.*
Disassembly of section .text:
! 00000000 <[^>]*> f389 8800 msr CPSR_f, r9
00000004 <[^>]*> f389 8400 msr CPSR_s, r9
00000008 <[^>]*> f389 8800 msr CPSR_f, r9
0000000c <[^>]*> f389 8c00 msr CPSR_fs, r9
Index: gas/testsuite/gas/arm/msr-reg.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/msr-reg.d,v
retrieving revision 1.1
diff -c -p -r1.1 msr-reg.d
*** gas/testsuite/gas/arm/msr-reg.d 17 Sep 2010 10:42:04 -0000 1.1
--- gas/testsuite/gas/arm/msr-reg.d 4 Apr 2011 13:57:22 -0000
***************
*** 1,11 ****
# name: MSR register operands
# as: -march=armv7-a
# objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format .*arm.*
Disassembly of section .text:
! 00000000 <[^>]*> e129f009 msr CPSR_fc, r9
00000004 <[^>]*> e124f009 msr CPSR_s, r9
00000008 <[^>]*> e128f009 msr CPSR_f, r9
0000000c <[^>]*> e12cf009 msr CPSR_fs, r9
--- 1,12 ----
# name: MSR register operands
# as: -march=armv7-a
# objdump: -dr --prefix-addresses --show-raw-insn
+ # warning: writing to APSR without specifying a bitmask is deprecated
.*: +file format .*arm.*
Disassembly of section .text:
! 00000000 <[^>]*> e128f009 msr CPSR_f, r9
00000004 <[^>]*> e124f009 msr CPSR_s, r9
00000008 <[^>]*> e128f009 msr CPSR_f, r9
0000000c <[^>]*> e12cf009 msr CPSR_fs, r9
Index: gas/testsuite/gas/arm/msr-reg.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/msr-reg.s,v
retrieving revision 1.1
diff -c -p -r1.1 msr-reg.s
*** gas/testsuite/gas/arm/msr-reg.s 17 Sep 2010 10:42:04 -0000 1.1
--- gas/testsuite/gas/arm/msr-reg.s 4 Apr 2011 13:57:22 -0000
***************
*** 5,11 ****
.syntax unified
@ Write to Special Register from register
! msr APSR,r9
msr APSR_g,r9
msr APSR_nzcvq,r9
msr APSR_nzcvqg,r9
--- 5,11 ----
.syntax unified
@ Write to Special Register from register
! msr APSR,r9 @ deprecated usage.
msr APSR_g,r9
msr APSR_nzcvq,r9
msr APSR_nzcvqg,r9
Index: opcodes/arm-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/arm-dis.c,v
retrieving revision 1.138
diff -c -p -r1.138 arm-dis.c
*** opcodes/arm-dis.c 14 Mar 2011 16:04:08 -0000 1.138
--- opcodes/arm-dis.c 4 Apr 2011 13:57:22 -0000
*************** psr_name (int regno)
*** 3718,3724 ****
case 9: return "PSP";
case 16: return "PRIMASK";
case 17: return "BASEPRI";
! case 18: return "BASEPRI_MASK";
case 19: return "FAULTMASK";
case 20: return "CONTROL";
default: return "<unknown>";
--- 3718,3724 ----
case 9: return "PSP";
case 16: return "PRIMASK";
case 17: return "BASEPRI";
! case 18: return "BASEPRI_MAX";
case 19: return "FAULTMASK";
case 20: return "CONTROL";
default: return "<unknown>";
*************** print_insn_thumb32 (bfd_vma pc, struct d
*** 4188,4193 ****
--- 4188,4202 ----
else
func (stream, "(UNDEF: %lu)", sysm);
}
+ else if ((given & 0xff) <= 3)
+ {
+ func (stream, "%s_", psr_name (given & 0xff));
+
+ if (given & 0x800)
+ func (stream, "nzcvq");
+ if (given & 0x400)
+ func (stream, "g");
+ }
else
{
func (stream, psr_name (given & 0xff));
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH, ARM] MSR/MRS assembly and disassembly tweaks
2011-04-04 14:07 [PATCH, ARM] MSR/MRS assembly and disassembly tweaks Julian Brown
@ 2011-04-08 16:25 ` Nick Clifton
2011-04-12 16:41 ` Tejas Belagod
2011-04-12 19:59 ` Hans-Peter Nilsson
2 siblings, 0 replies; 14+ messages in thread
From: Nick Clifton @ 2011-04-08 16:25 UTC (permalink / raw)
To: Julian Brown; +Cc: binutils
Hi Julian,
> * config/tc-arm.c (parse_psr): Add LHS argument. Improve support
> for *APSR bitmasks.
> (operand_parse_code): Replace OP_PSR with OP_wPSR and OP_rPSR.
> Remove OP_RVC_PSR.
> (parse_operands): Likewise.
> (do_mrs): Tweak error message for constraint.
> (do_t_mrs): Update constraints for changes to APSR support.
> (do_t_msr): Likewise. Don't set PSR_f flag here.
> (psrs): Remove "g", "nzcvq", "nzcvqg".
> (insns): Tweak entries for msr and mrs instructions.
>
> opcodes/
> * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
> (print_insn_thumb32): Add APSR bitmask support.
>
> gas/testsuite/
> * gas/arm/mrs-msr-thumb-v7-m.s: New.
> * gas/arm/mrs-msr-thumb-v7-m.d: New.
> * gas/arm/mrs-msr-thumb-v7-m-bad.d: New.
> * gas/arm/mrs-msr-thumb-v7-m-bad.l: New.
> * gas/arm/mrs-msr-thumb-v7-m-bad.s: New.
> * gas/arm/mrs-msr-thumb-v7e-m.d: New.
> * gas/arm/mrs-msr-thumb-v7e-m.s: New.
> * gas/arm/mrs-msr-arm-v7-a-bad.d: New.
> * gas/arm/mrs-msr-arm-v7-a-bad.l: New.
> * gas/arm/mrs-msr-arm-v7-a-bad.s: New.
> * gas/arm/mrs-msr-arm-v7-a.d: New.
> * gas/arm/mrs-msr-arm-v7-a.s: New.
> * gas/arm/mrs-msr-arm-v6.d: New.
> * gas/arm/mrs-msr-arm-v6.s: New.
> * gas/arm/mrs-msr-thumb-v6t2.d: New.
> * gas/arm/mrs-msr-thumb-v6t2.s: New.
> * gas/arm/arch7.d: Fix typo in disassembly for BASEPRI_MAX,
> bitmasks for IAPSR etc.
> * gas/arm/arch7.s: Specify bitmask for APSR writes.
> * gas/arm/archv6m.s: Likewise.
> * msr-imm-bad.l: Tweak expected disassembly in error message.
> * msr-reg-bad.l: Likewise.
> * msr-imm.d: Tweak expected disassembly.
> * msr-reg.d: Likewise.
> * msr-reg-thumb.d: Likewise.
> * msr-imm.s: Specify bitmask on APSR writes.
> * msr-reg.s: Add comment about deprecated usage.
Approved - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH, ARM] MSR/MRS assembly and disassembly tweaks
2011-04-04 14:07 [PATCH, ARM] MSR/MRS assembly and disassembly tweaks Julian Brown
2011-04-08 16:25 ` Nick Clifton
@ 2011-04-12 16:41 ` Tejas Belagod
2011-04-13 4:33 ` Paul Carroll
2011-04-12 19:59 ` Hans-Peter Nilsson
2 siblings, 1 reply; 14+ messages in thread
From: Tejas Belagod @ 2011-04-12 16:41 UTC (permalink / raw)
To: Julian Brown; +Cc: binutils
On Mon, 2011-04-04 at 15:07 +0100, Julian Brown wrote:
> Hi,
>
> This patch improves handling of MSR and MRS instructions in GAS, and
> also improves disassembly output in a couple of cases.
>
> In more detail:
>
> 1. It should be possible to use APSR as a synonym for CPSR on e.g.
> ARMv7-A and ARMv7-R cores, but the current implementation assembles an
> MSR instruction with the "fc" fields set on such cores. I think this is
> wrong: I fixed it to only set the "f" field in such cases.
>
> 2. Also in MSR instructions, "nzcvqg" bits can now be written in any
> order, to bring them in line with other PSR instructions (e.g. "msr
> CPSR_<fields>, rX", where <fields> can be in any order). You may only
> write "g" if the selected processor for assembly supports the DSP
> extension, else you will get an error.
>
Hi Julian,
This patch seems to break one of the existing tests - msr-imm.s.
Basically it now thinks these instructions are illegal.
$ cat t.s
.syntax unified
msr APSR_nzcvqg, #0x00000004
msr APSR_g, #0x00000000
msr APSR_nzcvq, #0x00000004
$ as-new -march=armv7-a t.s
t.s: Assembler messages:
t.s:5: Error: syntax error -- `msr APSR_nzcvqg,#0x00000004'
t.s:6: Error: syntax error -- `msr APSR_g,#0x00000000'
t.s:7: Error: syntax error -- `msr APSR_nzcvq,#0x00000004'
Tejas.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH, ARM] MSR/MRS assembly and disassembly tweaks
2011-04-04 14:07 [PATCH, ARM] MSR/MRS assembly and disassembly tweaks Julian Brown
2011-04-08 16:25 ` Nick Clifton
2011-04-12 16:41 ` Tejas Belagod
@ 2011-04-12 19:59 ` Hans-Peter Nilsson
2011-04-13 14:42 ` Dave Martin
2011-04-13 14:52 ` Julian Brown
2 siblings, 2 replies; 14+ messages in thread
From: Hans-Peter Nilsson @ 2011-04-12 19:59 UTC (permalink / raw)
To: julian; +Cc: binutils
> Date: Mon, 4 Apr 2011 15:07:28 +0100
> From: Julian Brown <julian@codesourcery.com>
> This patch improves handling of MSR and MRS instructions in GAS, and
> also improves disassembly output in a couple of cases.
Please fix the resulting fallout from the src/sim testsuite for
arm-elf with the arm-sim board. It has regressed in the last
24h, like so:
Running /tmp/hpautotest-sim/src/sim/testsuite/sim/arm/allinsn.exp ...
Testing adc.cgs on machine xscale.
Executing on host: arm-elf-as /tmp/hpautotest-sim/src/sim/testsuite/sim/arm/adc.cgs -I/tmp/hpautotest-sim/src/sim/testsuite/sim/arm -o adc.cgs.o (timeout = 300)
/tmp/hpautotest-sim/src/sim/testsuite/sim/arm/adc.cgs: Assembler messages:
/tmp/hpautotest-sim/src/sim/testsuite/sim/arm/adc.cgs:15: Error: selected processor does not support requested special purpose register -- `mrs r1,cpsr'
I guess it could be Nick's recent patch, but...nah.
brgds, H-P
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: Re: [PATCH, ARM] MSR/MRS assembly and disassembly tweaks
2011-04-12 16:41 ` Tejas Belagod
@ 2011-04-13 4:33 ` Paul Carroll
2011-04-13 13:20 ` Julian Brown
0 siblings, 1 reply; 14+ messages in thread
From: Paul Carroll @ 2011-04-13 4:33 UTC (permalink / raw)
To: Tejas Belagod; +Cc: Julian Brown, binutils
On 12:59 PM, Tejas Belagod wrote:
> Hi Julian,
>
> This patch seems to break one of the existing tests - msr-imm.s.
> Basically it now thinks these instructions are illegal.
>
> $ as-new -march=mv7-a t.s
> t.s: Assembler messages:
> t.s:5: Error: syntax error -- `msr APSR_nzcvqg,#0x00000004'
> t.s:6: Error: syntax error -- `msr APSR_g,#0x00000000'
> t.s:7: Error: syntax error -- `msr APSR_nzcvq,#0x00000004'
Actually, I believe the 4 new gas test failures in the ARM toolkit arise
from changes for bug patch 12296, where include/opcode/arm.h was
modified to add ARM_EXT_OS to the ARM_AEXT_V7_ARM definition. I saw
this issue when comparing two source pulls, one from Saturday and one
from Monday.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH, ARM] MSR/MRS assembly and disassembly tweaks
2011-04-13 4:33 ` Paul Carroll
@ 2011-04-13 13:20 ` Julian Brown
0 siblings, 0 replies; 14+ messages in thread
From: Julian Brown @ 2011-04-13 13:20 UTC (permalink / raw)
To: Paul Carroll; +Cc: Tejas Belagod, binutils, Nick Clifton
On Tue, 12 Apr 2011 22:33:10 -0600
Paul Carroll <pcarroll@codesourcery.com> wrote:
> On 12:59 PM, Tejas Belagod wrote:
> > Hi Julian,
> >
> > This patch seems to break one of the existing tests - msr-imm.s.
> > Basically it now thinks these instructions are illegal.
> >
> > $ as-new -march=mv7-a t.s
> > t.s: Assembler messages:
> > t.s:5: Error: syntax error -- `msr APSR_nzcvqg,#0x00000004'
> > t.s:6: Error: syntax error -- `msr APSR_g,#0x00000000'
> > t.s:7: Error: syntax error -- `msr APSR_nzcvq,#0x00000004'
> Actually, I believe the 4 new gas test failures in the ARM toolkit
> arise from changes for bug patch 12296, where include/opcode/arm.h
> was modified to add ARM_EXT_OS to the ARM_AEXT_V7_ARM definition. I
> saw this issue when comparing two source pulls, one from Saturday and
> one from Monday.
Agreed -- AFAICT, adding ARM_EXT_OS to the ARM_AEXT_V7_ARM definition
was wrong. The "OS extension" bit only applies to V6M architecture
processors.
The syntax errors happen because the test in parse_psr:
bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m);
returns TRUE for e.g. ARMv7-A cores, since the feature arm_ext_m is
defined as:
static const arm_feature_set arm_ext_m =
ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
So: either ARM_EXT_OS is wrong for arm_ext_m, or ARM_EXT_OS must not be
set for non-M cores. I think the latter is true.
Thoughts?
Julian
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH, ARM] MSR/MRS assembly and disassembly tweaks
2011-04-12 19:59 ` Hans-Peter Nilsson
@ 2011-04-13 14:42 ` Dave Martin
2011-04-13 14:52 ` Julian Brown
1 sibling, 0 replies; 14+ messages in thread
From: Dave Martin @ 2011-04-13 14:42 UTC (permalink / raw)
To: Hans-Peter Nilsson; +Cc: julian, binutils
On Tue, Apr 12, 2011 at 8:59 PM, Hans-Peter Nilsson
<hans-peter.nilsson@axis.com> wrote:
>> Date: Mon, 4 Apr 2011 15:07:28 +0100
>> From: Julian Brown <julian@codesourcery.com>
>
>> This patch improves handling of MSR and MRS instructions in GAS, and
>> also improves disassembly output in a couple of cases.
>
> Please fix the resulting fallout from the src/sim testsuite for
> arm-elf with the arm-sim board. It has regressed in the last
> 24h, like so:
>
> Running /tmp/hpautotest-sim/src/sim/testsuite/sim/arm/allinsn.exp ...
> Testing adc.cgs on machine xscale.
> Executing on host: arm-elf-as /tmp/hpautotest-sim/src/sim/testsuite/sim/arm/adc.cgs -I/tmp/hpautotest-sim/src/sim/testsuite/sim/arm -o adc.cgs.o (timeout = 300)
> /tmp/hpautotest-sim/src/sim/testsuite/sim/arm/adc.cgs: Assembler messages:
> /tmp/hpautotest-sim/src/sim/testsuite/sim/arm/adc.cgs:15: Error: selected processor does not support requested special purpose register -- `mrs r1,cpsr'
>
> I guess it could be Nick's recent patch, but...nah.
>
> brgds, H-P
>
Further to this, it seems that most uses of mrs/msr, and all uses of
the name "cpsr" are now broken...
$ arm-linux-gnueabi-as -march=armv7-a -o tst.o
mrs r0, apsr
msr apsr_nzcvq, r0
mrs r0, cpsr
msr cpsr, r0
msr cpsr_c, r0
{standard input}: Assembler messages:
{standard input}:1: Error: 'APSR', 'CPSR' or 'SPSR' expected -- `mrs r0,apsr'
{standard input}:3: Error: selected processor does not support
requested special purpose register -- `mrs r0,cpsr'
{standard input}:4: Error: selected processor does not support
requested special purpose register -- `msr cpsr,r0'
{standard input}:5: Error: selected processor does not support
requested special purpose register -- `msr cpsr_c,r0'
---Dave
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH, ARM] MSR/MRS assembly and disassembly tweaks
2011-04-12 19:59 ` Hans-Peter Nilsson
2011-04-13 14:42 ` Dave Martin
@ 2011-04-13 14:52 ` Julian Brown
2011-04-15 7:20 ` Hans-Peter Nilsson
2011-04-18 13:29 ` Nick Clifton
1 sibling, 2 replies; 14+ messages in thread
From: Julian Brown @ 2011-04-13 14:52 UTC (permalink / raw)
To: Hans-Peter Nilsson; +Cc: binutils
[-- Attachment #1: Type: text/plain, Size: 1586 bytes --]
On Tue, 12 Apr 2011 21:59:37 +0200
Hans-Peter Nilsson <hans-peter.nilsson@axis.com> wrote:
> > Date: Mon, 4 Apr 2011 15:07:28 +0100
> > From: Julian Brown <julian@codesourcery.com>
>
> > This patch improves handling of MSR and MRS instructions in GAS, and
> > also improves disassembly output in a couple of cases.
>
> Please fix the resulting fallout from the src/sim testsuite for
> arm-elf with the arm-sim board. It has regressed in the last
> 24h, like so:
Hmm... I seem to have been a little confused by the difference between
"selected_cpu" and "cpu_variant" in tc-arm.c (in fact I still am!), and
I'd also not tested thoroughly enough what happens in "implied CPU
variant" mode, i.e. when no CPU or architecture is passed on the
command line or present as an .arch/.cpu directive in the input file.
So, anyway. The attached patch fixes the MRS/MSR tests, but causes some
further regressions regarding the SVC instruction on e.g. v7-A
architectures:
PASS -> FAIL: default/gas.sum:ARM V7 instructions
PASS -> FAIL: default/gas.sum:attributes for -march=armv7
.../arch7.s:83: Error: SVC is not permitted on this architecture
I'm not sure if I'll have time to investigate this further this week. I
could apply the attached if someone can investigate the SVC problem
further, or I can just revert my MRS/MSR patch for now. Anyone have any
preferences?
Thanks,
Julian
ChangeLog
gas/
* config/tc-arm.c (parse_psr): Use selected_cpu not cpu_variant to
detect M-profile targets.
include/
* opcode/arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
[-- Attachment #2: binutils-mrs-msr-fsf-tweaks-1.diff --]
[-- Type: text/x-patch, Size: 2204 bytes --]
? gas/testsuite/gas/arm/a.out
Index: gas/config/tc-arm.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-arm.c,v
retrieving revision 1.480
diff -c -p -r1.480 tc-arm.c
*** gas/config/tc-arm.c 12 Apr 2011 11:47:38 -0000 1.480
--- gas/config/tc-arm.c 13 Apr 2011 14:48:26 -0000
*************** parse_psr (char **str, bfd_boolean lhs)
*** 5354,5360 ****
const struct asm_psr *psr;
char *start;
bfd_boolean is_apsr = FALSE;
! bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m);
/* CPSR's and SPSR's can now be lowercase. This is just a convenience
feature for ease of use and backwards compatibility. */
--- 5354,5360 ----
const struct asm_psr *psr;
char *start;
bfd_boolean is_apsr = FALSE;
! bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
/* CPSR's and SPSR's can now be lowercase. This is just a convenience
feature for ease of use and backwards compatibility. */
Index: include/opcode/arm.h
===================================================================
RCS file: /cvs/src/src/include/opcode/arm.h,v
retrieving revision 1.25
diff -c -p -r1.25 arm.h
*** include/opcode/arm.h 11 Apr 2011 15:23:09 -0000 1.25
--- include/opcode/arm.h 13 Apr 2011 14:48:26 -0000
***************
*** 109,116 ****
#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K)
#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC)
#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC)
! #define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER \
! | ARM_EXT_OS)
#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A)
#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV)
#define ARM_AEXT_NOTM \
--- 109,115 ----
#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K)
#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC)
#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC)
! #define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER)
#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A)
#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV)
#define ARM_AEXT_NOTM \
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH, ARM] MSR/MRS assembly and disassembly tweaks
2011-04-13 14:52 ` Julian Brown
@ 2011-04-15 7:20 ` Hans-Peter Nilsson
2011-04-18 13:29 ` Nick Clifton
1 sibling, 0 replies; 14+ messages in thread
From: Hans-Peter Nilsson @ 2011-04-15 7:20 UTC (permalink / raw)
To: julian; +Cc: binutils
> Date: Wed, 13 Apr 2011 15:51:51 +0100
> From: Julian Brown <julian@codesourcery.com>
> I'm not sure if I'll have time to investigate this further this week. I
> could apply the attached if someone can investigate the SVC problem
> further, or I can just revert my MRS/MSR patch for now. Anyone have any
> preferences?
In the absence of any such takers, IMHO reverting is preferred.
brgds, H-P
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH, ARM] MSR/MRS assembly and disassembly tweaks
2011-04-13 14:52 ` Julian Brown
2011-04-15 7:20 ` Hans-Peter Nilsson
@ 2011-04-18 13:29 ` Nick Clifton
2011-04-18 13:54 ` Julian Brown
2011-04-19 2:53 ` Hans-Peter Nilsson
1 sibling, 2 replies; 14+ messages in thread
From: Nick Clifton @ 2011-04-18 13:29 UTC (permalink / raw)
To: Julian Brown; +Cc: Hans-Peter Nilsson, binutils
[-- Attachment #1: Type: text/plain, Size: 2356 bytes --]
Hi Julian,
> gas/
> * config/tc-arm.c (parse_psr): Use selected_cpu not cpu_variant to
> detect M-profile targets.
>
> include/
> * opcode/arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
Right - I have applied this patch together with some fixes of my own.
(Full patch attached). We now have zero unexpected failures in the GAS
testsuite for EABI, ELF and PE based ARM toolchains.
The problem with the SVC test was that removing ARM_EXT_OS from
ARM_AEXT_V7_ARM meant that -march=armv7 would select an architecture
that included v6m but which did not set ARM_EXT_OS. This is correct,
but the code in do_t_swi() did not allow for this and so triggered a
bogus error condition. I fixed this by extending the test in do_t_swi
to exclude all v7 and higher architectures.
One thing that I am not sure about is the correct name for V7M PSR
register 18. Is it BASEPRI_MASK or BASEPRI_MAX. Judging by the other
register names it is BASEPRI_MASK, but I could not find any
documentation to confirm this.
Cheers
Nick
gas/ChangeLog
2011-04-18 Julian Brown <julian@codesourcery.com>
Nick Clifton <nickc@redhat.com>
* config/tc-arm.c (parse_psr): Use selected_cpu not cpu_variant to
detect M-profile targets.
(do_t_swi): Exclude v7 and higher variants from arm_ext_os test.
(v7m_psrs): Fix typo: basepri_max should be basepri_mask.
gas/testsuite/ChangeLog
2011-04-18 Nick Clifton <nickc@redhat.com>
* gas/arm/arch7.s: Fix typo basepri_max should be basepri_mask.
* gas/arm/mrs-msr-thumb-v7e-m.s: Likewise.
* gas/arm/arch7.d: Update expected disassembly.
* gas/arm/attr-march-armv7.d: Remove Microcontroller tag.
* gas/arm/blx-bad.d: Only run for ELF based targets.
* gas/arm/mrs-msr-thumb-v6t2.d: Likewise.
* gas/arm/vldm-arm.d: Likewise.
* gas/arm/mrs-msr-thumb-v7-m.d: Likewise.
Remove qualifiers from PSR and IAPSR regsiter names.
* gas/arm/mrs-msr-thumb-v7e-m.d: Likewise.
* gas/arm/thumb2_bcond.d: Update expected disassembly to allow for
relaxing of branch insns.
* gas/arm/thumb32.d: Fix whitespace problems in disassembly.
opcodes/ChangeLog
2011-04-18 Nick Clifton <nickc@redhat.com>
* arm-dis.c (psr_name): Revert previous delta.
include/opcode/ChangeLog
2011-04-18 Julian Brown <julian@codesourcery.com>
* arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
[-- Attachment #2: arm.patch --]
[-- Type: text/x-diff, Size: 14185 bytes --]
Index: opcodes/arm-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/arm-dis.c,v
retrieving revision 1.141
diff -u -3 -p -r1.141 arm-dis.c
--- opcodes/arm-dis.c 12 Apr 2011 16:01:47 -0000 1.141
+++ opcodes/arm-dis.c 18 Apr 2011 13:11:50 -0000
@@ -3722,7 +3722,7 @@ psr_name (int regno)
case 9: return "PSP";
case 16: return "PRIMASK";
case 17: return "BASEPRI";
- case 18: return "BASEPRI_MAX";
+ case 18: return "BASEPRI_MASK";
case 19: return "FAULTMASK";
case 20: return "CONTROL";
default: return "<unknown>";
@@ -4192,15 +4192,6 @@ print_insn_thumb32 (bfd_vma pc, struct d
else
func (stream, "(UNDEF: %lu)", sysm);
}
- else if ((given & 0xff) <= 3)
- {
- func (stream, "%s_", psr_name (given & 0xff));
-
- if (given & 0x800)
- func (stream, "nzcvq");
- if (given & 0x400)
- func (stream, "g");
- }
else
{
func (stream, psr_name (given & 0xff));
Index: gas/config/tc-arm.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-arm.c,v
retrieving revision 1.480
diff -u -3 -p -r1.480 tc-arm.c
--- gas/config/tc-arm.c 12 Apr 2011 11:47:38 -0000 1.480
+++ gas/config/tc-arm.c 18 Apr 2011 13:11:52 -0000
@@ -5354,7 +5354,7 @@ parse_psr (char **str, bfd_boolean lhs)
const struct asm_psr *psr;
char *start;
bfd_boolean is_apsr = FALSE;
- bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m);
+ bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
/* CPSR's and SPSR's can now be lowercase. This is just a convenience
feature for ease of use and backwards compatibility. */
@@ -11760,7 +11760,9 @@ do_t_swi (void)
to ARM_EXT_V6M. */
if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
{
- if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os))
+ if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
+ /* This only applies to the v6m howver, not later architectures. */
+ && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
as_bad (_("SVC is not permitted on this architecture"));
ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
}
@@ -16632,7 +16634,8 @@ static const struct asm_psr v7m_psrs[] =
{"psp", 9 }, {"PSP", 9 },
{"primask", 16}, {"PRIMASK", 16},
{"basepri", 17}, {"BASEPRI", 17},
- {"basepri_max", 18}, {"BASEPRI_MAX", 18},
+ {"basepri_max", 18}, {"BASEPRI_MAX", 18}, /* Typo, preserved for backwards compatibility. */
+ {"basepri_mask",18}, {"BASEPRI_MASK", 18},
{"faultmask", 19}, {"FAULTMASK", 19},
{"control", 20}, {"CONTROL", 20}
};
Index: gas/testsuite/gas/arm/arch7.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/arch7.d,v
retrieving revision 1.8
diff -u -3 -p -r1.8 arch7.d
--- gas/testsuite/gas/arm/arch7.d 11 Apr 2011 18:49:05 -0000 1.8
+++ gas/testsuite/gas/arm/arch7.d 18 Apr 2011 13:11:52 -0000
@@ -57,13 +57,13 @@ Disassembly of section .text:
0+0c0 <[^>]*> f3ef 8009 mrs r0, PSP
0+0c4 <[^>]*> f3ef 8010 mrs r0, PRIMASK
0+0c8 <[^>]*> f3ef 8011 mrs r0, BASEPRI
-0+0cc <[^>]*> f3ef 8012 mrs r0, BASEPRI_MAX
+0+0cc <[^>]*> f3ef 8012 mrs r0, BASEPRI_MASK
0+0d0 <[^>]*> f3ef 8013 mrs r0, FAULTMASK
0+0d4 <[^>]*> f3ef 8014 mrs r0, CONTROL
0+0d8 <[^>]*> f380 8800 msr (CPSR_f|APSR_nzcvq), r0
-0+0dc <[^>]*> f380 8801 msr IAPSR_nzcvq, r0
-0+0e0 <[^>]*> f380 8802 msr EAPSR_nzcvq, r0
-0+0e4 <[^>]*> f380 8803 msr PSR_nzcvq, r0
+0+0dc <[^>]*> f380 8801 msr IAPSR, r0
+0+0e0 <[^>]*> f380 8802 msr EAPSR, r0
+0+0e4 <[^>]*> f380 8803 msr PSR, r0
0+0e8 <[^>]*> f380 8805 msr IPSR, r0
0+0ec <[^>]*> f380 8806 msr EPSR, r0
0+0f0 <[^>]*> f380 8807 msr IEPSR, r0
@@ -71,9 +71,10 @@ Disassembly of section .text:
0+0f8 <[^>]*> f380 8809 msr PSP, r0
0+0fc <[^>]*> f380 8810 msr PRIMASK, r0
0+100 <[^>]*> f380 8811 msr BASEPRI, r0
-0+104 <[^>]*> f380 8812 msr BASEPRI_MAX, r0
+0+104 <[^>]*> f380 8812 msr BASEPRI_MASK, r0
0+108 <[^>]*> f380 8813 msr FAULTMASK, r0
0+10c <[^>]*> f380 8814 msr CONTROL, r0
0+110 <[^>]*> f3ef 8003 mrs r0, PSR
-0+114 <[^>]*> f380 8803 msr PSR_nzcvq, r0
+0+114 <[^>]*> f380 8803 msr PSR, r0
0+118 <[^>]*> df00 svc 0
+#...
Index: gas/testsuite/gas/arm/arch7.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/arch7.s,v
retrieving revision 1.4
diff -u -3 -p -r1.4 arch7.s
--- gas/testsuite/gas/arm/arch7.s 11 Apr 2011 18:49:05 -0000 1.4
+++ gas/testsuite/gas/arm/arch7.s 18 Apr 2011 13:11:52 -0000
@@ -60,7 +60,7 @@ label2:
mrs r0, psp
mrs r0, primask
mrs r0, basepri
- mrs r0, basepri_max
+ mrs r0, basepri_mask
mrs r0, faultmask
mrs r0, control
msr apsr_nzcvq, r0
@@ -74,7 +74,7 @@ label2:
msr psp, r0
msr primask, r0
msr basepri, r0
- msr basepri_max, r0
+ msr BASEPRI_MASK, r0
msr faultmask, r0
msr control, r0
mrs r0, xpsr
Index: gas/testsuite/gas/arm/attr-march-armv7.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/attr-march-armv7.d,v
retrieving revision 1.4
diff -u -3 -p -r1.4 attr-march-armv7.d
--- gas/testsuite/gas/arm/attr-march-armv7.d 11 Apr 2011 15:23:08 -0000 1.4
+++ gas/testsuite/gas/arm/attr-march-armv7.d 18 Apr 2011 13:11:52 -0000
@@ -9,6 +9,5 @@ Attribute Section: aeabi
File Attributes
Tag_CPU_name: "7"
Tag_CPU_arch: v7
- Tag_CPU_arch_profile: Microcontroller
Tag_THUMB_ISA_use: Thumb-2
Tag_DIV_use: Not allowed
Index: gas/testsuite/gas/arm/blx-bad.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/blx-bad.d,v
retrieving revision 1.1
diff -u -3 -p -r1.1 blx-bad.d
--- gas/testsuite/gas/arm/blx-bad.d 6 Jan 2011 14:30:42 -0000 1.1
+++ gas/testsuite/gas/arm/blx-bad.d 18 Apr 2011 13:11:52 -0000
@@ -1,5 +1,7 @@
#objdump: -drw --show-raw-insn
#name: BLX encoding
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
.*: file format .*arm.*
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.d,v
retrieving revision 1.1
diff -u -3 -p -r1.1 mrs-msr-thumb-v6t2.d
--- gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.d 11 Apr 2011 18:49:05 -0000 1.1
+++ gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.d 18 Apr 2011 13:11:52 -0000
@@ -1,5 +1,7 @@
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MRS/MSR test, architecture v6t2, Thumb mode
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
.*: file format .*
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.d,v
retrieving revision 1.1
diff -u -3 -p -r1.1 mrs-msr-thumb-v7-m.d
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.d 11 Apr 2011 18:49:05 -0000 1.1
+++ gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.d 18 Apr 2011 13:11:52 -0000
@@ -1,6 +1,7 @@
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MRS/MSR test, architecture v7-M, Thumb mode
-
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
.*: file format .*
@@ -9,7 +10,7 @@ Disassembly of section .text:
0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
0+04 <[^>]*> f3ef 8502 mrs r5, EAPSR
0+08 <[^>]*> f3ef 8610 mrs r6, PRIMASK
-0+0c <[^>]*> f383 8803 msr PSR_nzcvq, r3
+0+0c <[^>]*> f383 8803 msr PSR, r3
0+10 <[^>]*> f384 8800 msr CPSR_f, r4
-0+14 <[^>]*> f385 8801 msr IAPSR_nzcvq, r5
+0+14 <[^>]*> f385 8801 msr IAPSR, r5
0+18 <[^>]*> f386 8810 msr PRIMASK, r6
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d,v
retrieving revision 1.1
diff -u -3 -p -r1.1 mrs-msr-thumb-v7e-m.d
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d 11 Apr 2011 18:49:05 -0000 1.1
+++ gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d 18 Apr 2011 13:11:52 -0000
@@ -1,5 +1,7 @@
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MRS/MSR test, architecture v7e-M, Thumb mode
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
.*: file format .*
@@ -9,5 +11,5 @@ Disassembly of section .text:
0+04 <[^>]*> f3ef 8502 mrs r5, EAPSR
0+08 <[^>]*> f3ef 8610 mrs r6, PRIMASK
0+0c <[^>]*> f384 8c00 msr CPSR_fs, r4
-0+10 <[^>]*> f385 8401 msr IAPSR_g, r5
-0+14 <[^>]*> f386 8812 msr BASEPRI_MAX, r6
+0+10 <[^>]*> f385 8401 msr IAPSR, r5
+0+14 <[^>]*> f386 8812 msr BASEPRI_MASK, r6
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s,v
retrieving revision 1.1
diff -u -3 -p -r1.1 mrs-msr-thumb-v7e-m.s
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s 11 Apr 2011 18:49:05 -0000 1.1
+++ gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s 18 Apr 2011 13:11:52 -0000
@@ -7,4 +7,4 @@
mrs r6, primask
msr apsr_nzcvqg, r4
msr iapsr_g, r5
- msr basepri_max, r6
+ msr basepri_mask, r6
Index: gas/testsuite/gas/arm/thumb2_bcond.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/thumb2_bcond.d,v
retrieving revision 1.7
diff -u -3 -p -r1.7 thumb2_bcond.d
--- gas/testsuite/gas/arm/thumb2_bcond.d 12 Apr 2011 15:44:36 -0000 1.7
+++ gas/testsuite/gas/arm/thumb2_bcond.d 18 Apr 2011 13:11:52 -0000
@@ -4,24 +4,24 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0+000 <[^>]+> bf18 it ne
-0+002 <[^>]+> f7ff bffd bne.w 0+0 <[^>]+>
-0+006 <[^>]+> bf38 it cc
-0+008 <[^>]+> f7ff bffa bcc.w 0+0 <[^>]+>
-0+00c <[^>]+> bf28 it cs
-0+00e <[^>]+> f7ff fff7 blcs 0+0 <[^>]+>
-0+012 <[^>]+> bfb8 it lt
-0+014 <[^>]+> 47a8 blxlt r5
-0+016 <[^>]+> bf08 it eq
-0+018 <[^>]+> 4740 bxeq r8
-0+01a <[^>]+> bfc8 it gt
-0+01c <[^>]+> e8d4 f001 tbbgt \[r4, r1\]
-0+020 <[^>]+> bfb8 it lt
-0+022 <[^>]+> df00 svclt 0
-0+024 <[^>]+> bf08 it eq
-0+026 <[^>]+> f8d0 f000 ldreq.w pc, \[r0\]
-0+02a <[^>]+> bfdc itt le
-0+02c <[^>]+> be00 bkpt 0x0000
-0+02e <[^>]+> bf00 nople
-0+030 <[^>]+> bf00 nop
+0+000 <[^>]+> bf18[ ]+it ne
+0+002 <[^>]+> [0-9a-f ]+[ ]+bne.[nw] 0+0 <[^>]+>
+0+00. <[^>]+> bf38[ ]+it cc
+0+00. <[^>]+> f7ff bff[ab][ ]+bcc.w 0+0 <[^>]+>
+0+00. <[^>]+> bf28[ ]+it cs
+0+0.. <[^>]+> f7ff fff[78][ ]+blcs 0+0 <[^>]+>
+0+0.. <[^>]+> bfb8[ ]+it lt
+0+0.. <[^>]+> 47a8[ ]+blxlt r5
+0+0.. <[^>]+> bf08[ ]+it eq
+0+0.. <[^>]+> 4740[ ]+bxeq r8
+0+0.. <[^>]+> bfc8[ ]+it gt
+0+0.. <[^>]+> e8d4 f001[ ]+tbbgt \[r4, r1\]
+0+0.. <[^>]+> bfb8[ ]+it lt
+0+0.. <[^>]+> df00[ ]+svclt 0
+0+0.. <[^>]+> bf08[ ]+it eq
+0+0.. <[^>]+> f8d0 f000[ ]+ldreq.w pc, \[r0\]
+0+0.. <[^>]+> bfdc[ ]+itt le
+0+0.. <[^>]+> be00[ ]+bkpt 0x0000
+0+0.. <[^>]+> bf00[ ]+nople
+0+0.. <[^>]+> bf00[ ]+nop
#...
Index: gas/testsuite/gas/arm/thumb32.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/thumb32.d,v
retrieving revision 1.41
diff -u -3 -p -r1.41 thumb32.d
--- gas/testsuite/gas/arm/thumb32.d 12 Apr 2011 16:01:48 -0000 1.41
+++ gas/testsuite/gas/arm/thumb32.d 18 Apr 2011 13:11:52 -0000
@@ -535,11 +535,11 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> e9d5 2300 ldrd r2, r3, \[r5\]
0[0-9a-f]+ <[^>]+> e9d5 230c ldrd r2, r3, \[r5, #48\].*
0[0-9a-f]+ <[^>]+> e955 230c ldrd r2, r3, \[r5, #-48\].*
-0[0-9a-f]+ <[^>]+> e95f 4505 ldrd r4, r5, \[pc, #-16\] ; 0+5f0 <^>]+>
+0[0-9a-f]+ <[^>]+> e95f 4504 ldrd r4, r5, \[pc, #-16\] ; 000005f0 <here>
0[0-9a-f]+ <[^>]+> e9c5 2300 strd r2, r3, \[r5\]
0[0-9a-f]+ <[^>]+> e9c5 230c strd r2, r3, \[r5, #48\].*
0[0-9a-f]+ <[^>]+> e945 230c strd r2, r3, \[r5, #-48\].*
-0[0-9a-f]+ <[^>]+> e94f 2308 strd r2, r3, \[pc, #-32\] ; 0+5f0 <^>]+>
+0[0-9a-f]+ <[^>]+> e94f 2308 strd r2, r3, \[pc, #-32\] ; 0+5f0 <here>
0[0-9a-f]+ <[^>]+> f815 1e00 ldrbt r1, \[r5\]
0[0-9a-f]+ <[^>]+> f815 1e30 ldrbt r1, \[r5, #48\].*
0[0-9a-f]+ <[^>]+> f915 1e00 ldrsbt r1, \[r5\]
@@ -1065,3 +1065,4 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> fa62 f103 ror.w r1, r2, r3
0[0-9a-f]+ <[^>]+> fa61 f103 ror.w r1, r1, r3
0[0-9a-f]+ <[^>]+> bf00 nop
+0[0-9a-f]+ <[^>]+> bf00 nop
Index: gas/testsuite/gas/arm/vldm-arm.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/vldm-arm.d,v
retrieving revision 1.1
diff -u -3 -p -r1.1 vldm-arm.d
--- gas/testsuite/gas/arm/vldm-arm.d 9 Jun 2010 15:11:51 -0000 1.1
+++ gas/testsuite/gas/arm/vldm-arm.d 18 Apr 2011 13:11:52 -0000
@@ -2,6 +2,8 @@
# as: -mfpu=vfp3
# source: vldm.s
# objdump: -dr --prefix-addresses --show-raw-insn
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
.*: +file format .*arm.*
Index: include/opcode/arm.h
===================================================================
RCS file: /cvs/src/src/include/opcode/arm.h,v
retrieving revision 1.25
diff -u -3 -p -r1.25 arm.h
--- include/opcode/arm.h 11 Apr 2011 15:23:09 -0000 1.25
+++ include/opcode/arm.h 18 Apr 2011 13:11:52 -0000
@@ -109,8 +109,7 @@
#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K)
#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC)
#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC)
-#define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER \
- | ARM_EXT_OS)
+#define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER)
#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A)
#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV)
#define ARM_AEXT_NOTM \
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH, ARM] MSR/MRS assembly and disassembly tweaks
2011-04-18 13:29 ` Nick Clifton
@ 2011-04-18 13:54 ` Julian Brown
2011-04-19 7:46 ` Nick Clifton
2011-04-19 2:53 ` Hans-Peter Nilsson
1 sibling, 1 reply; 14+ messages in thread
From: Julian Brown @ 2011-04-18 13:54 UTC (permalink / raw)
To: Nick Clifton; +Cc: Hans-Peter Nilsson, binutils
On Mon, 18 Apr 2011 14:29:33 +0100
Nick Clifton <nickc@redhat.com> wrote:
> Hi Julian,
>
> > gas/
> > * config/tc-arm.c (parse_psr): Use selected_cpu not
> > cpu_variant to detect M-profile targets.
> >
> > include/
> > * opcode/arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from
> > bitmask.
>
> Right - I have applied this patch together with some fixes of my own.
> (Full patch attached). We now have zero unexpected failures in the
> GAS testsuite for EABI, ELF and PE based ARM toolchains.
Thanks for this!
> The problem with the SVC test was that removing ARM_EXT_OS from
> ARM_AEXT_V7_ARM meant that -march=armv7 would select an architecture
> that included v6m but which did not set ARM_EXT_OS. This is correct,
> but the code in do_t_swi() did not allow for this and so triggered a
> bogus error condition. I fixed this by extending the test in do_t_swi
> to exclude all v7 and higher architectures.
I don't understand the subtleties of what ARM_EXT_OS is supposed to do
enough to comment on this, I don't think...
> One thing that I am not sure about is the correct name for V7M PSR
> register 18. Is it BASEPRI_MASK or BASEPRI_MAX. Judging by the
> other register names it is BASEPRI_MASK, but I could not find any
> documentation to confirm this.
> opcodes/ChangeLog
> 2011-04-18 Nick Clifton <nickc@redhat.com>
>
> * arm-dis.c (psr_name): Revert previous delta.
But I don't think this reversion is right. AFAICT IAPSR, etc. can have
bitmasks specified for the APSR parts. Also AFAICT the name of the
register is BASEPRI_MAX, and any use of BASEPRI_MASK is wrong. See e.g.:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489c/Cihjcedb.html
Cheers,
Julian
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH, ARM] MSR/MRS assembly and disassembly tweaks
2011-04-18 13:29 ` Nick Clifton
2011-04-18 13:54 ` Julian Brown
@ 2011-04-19 2:53 ` Hans-Peter Nilsson
1 sibling, 0 replies; 14+ messages in thread
From: Hans-Peter Nilsson @ 2011-04-19 2:53 UTC (permalink / raw)
To: nickc; +Cc: binutils
> Date: Mon, 18 Apr 2011 14:29:33 +0100
> From: Nick Clifton <nickc@redhat.com>
> Right - I have applied this patch together with some fixes of my own.
I don't see it on FSF binutils trunk; was there a missing commit
or the "wrong" repo?
> gas/ChangeLog
> 2011-04-18 Julian Brown <julian@codesourcery.com>
> Nick Clifton <nickc@redhat.com>
>
> * config/tc-arm.c (parse_psr): Use selected_cpu not cpu_variant to
> detect M-profile targets.
> (do_t_swi): Exclude v7 and higher variants from arm_ext_os test.
> (v7m_psrs): Fix typo: basepri_max should be basepri_mask.
brgds, H-P
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH, ARM] MSR/MRS assembly and disassembly tweaks
2011-04-18 13:54 ` Julian Brown
@ 2011-04-19 7:46 ` Nick Clifton
2011-04-19 22:29 ` Hans-Peter Nilsson
0 siblings, 1 reply; 14+ messages in thread
From: Nick Clifton @ 2011-04-19 7:46 UTC (permalink / raw)
To: Julian Brown; +Cc: Hans-Peter Nilsson, binutils
[-- Attachment #1: Type: text/plain, Size: 728 bytes --]
Hi Julian,
>> One thing that I am not sure about is the correct name for V7M PSR
>> register 18. Is it BASEPRI_MASK or BASEPRI_MAX.
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489c/Cihjcedb.html
Thanks - that was the reference I needed.
I have checked in this patch to revert the BASEPRI_MASK parts of my
previous patch.
Cheers
Nick
gas/ChangeLog
2011-04-19 Nick Clifton <nickc@redhat.com>
* config/tc-arm.c (v7m_psrs): Revert previous delta.
gas/testsuite/ChageLog
2011-04-19 Nick Clifton <nickc@redhat.com>
* gas/arm/mrs-msr-thumb-v7e-m.s: Restore name of basepri_max
register.
* gas/arm/mrs-msr-thumb-v7e-m.d: Likewise.
* gas/arm/arch7.d: Likewise.
* gas/arm/arch7.s: Likewise.
[-- Attachment #2: arm.patch --]
[-- Type: text/x-diff, Size: 4471 bytes --]
Index: gas/config/tc-arm.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-arm.c,v
retrieving revision 1.481
diff -u -3 -p -r1.481 tc-arm.c
--- gas/config/tc-arm.c 19 Apr 2011 07:27:28 -0000 1.481
+++ gas/config/tc-arm.c 19 Apr 2011 07:41:25 -0000
@@ -16634,8 +16634,8 @@ static const struct asm_psr v7m_psrs[] =
{"psp", 9 }, {"PSP", 9 },
{"primask", 16}, {"PRIMASK", 16},
{"basepri", 17}, {"BASEPRI", 17},
- {"basepri_max", 18}, {"BASEPRI_MAX", 18}, /* Typo, preserved for backwards compatibility. */
- {"basepri_mask",18}, {"BASEPRI_MASK", 18},
+ {"basepri_max", 18}, {"BASEPRI_MAX", 18},
+ {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
{"faultmask", 19}, {"FAULTMASK", 19},
{"control", 20}, {"CONTROL", 20}
};
Index: gas/testsuite/gas/arm/arch7.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/arch7.d,v
retrieving revision 1.9
diff -u -3 -p -r1.9 arch7.d
--- gas/testsuite/gas/arm/arch7.d 19 Apr 2011 07:27:30 -0000 1.9
+++ gas/testsuite/gas/arm/arch7.d 19 Apr 2011 07:41:25 -0000
@@ -57,7 +57,7 @@ Disassembly of section .text:
0+0c0 <[^>]*> f3ef 8009 mrs r0, PSP
0+0c4 <[^>]*> f3ef 8010 mrs r0, PRIMASK
0+0c8 <[^>]*> f3ef 8011 mrs r0, BASEPRI
-0+0cc <[^>]*> f3ef 8012 mrs r0, BASEPRI_MASK
+0+0cc <[^>]*> f3ef 8012 mrs r0, BASEPRI_MAX
0+0d0 <[^>]*> f3ef 8013 mrs r0, FAULTMASK
0+0d4 <[^>]*> f3ef 8014 mrs r0, CONTROL
0+0d8 <[^>]*> f380 8800 msr (CPSR_f|APSR_nzcvq), r0
@@ -71,7 +71,7 @@ Disassembly of section .text:
0+0f8 <[^>]*> f380 8809 msr PSP, r0
0+0fc <[^>]*> f380 8810 msr PRIMASK, r0
0+100 <[^>]*> f380 8811 msr BASEPRI, r0
-0+104 <[^>]*> f380 8812 msr BASEPRI_MASK, r0
+0+104 <[^>]*> f380 8812 msr BASEPRI_MAX, r0
0+108 <[^>]*> f380 8813 msr FAULTMASK, r0
0+10c <[^>]*> f380 8814 msr CONTROL, r0
0+110 <[^>]*> f3ef 8003 mrs r0, PSR
Index: gas/testsuite/gas/arm/arch7.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/arch7.s,v
retrieving revision 1.5
diff -u -3 -p -r1.5 arch7.s
--- gas/testsuite/gas/arm/arch7.s 19 Apr 2011 07:27:30 -0000 1.5
+++ gas/testsuite/gas/arm/arch7.s 19 Apr 2011 07:41:25 -0000
@@ -60,7 +60,7 @@ label2:
mrs r0, psp
mrs r0, primask
mrs r0, basepri
- mrs r0, basepri_mask
+ mrs r0, basepri_max
mrs r0, faultmask
mrs r0, control
msr apsr_nzcvq, r0
@@ -74,7 +74,7 @@ label2:
msr psp, r0
msr primask, r0
msr basepri, r0
- msr BASEPRI_MASK, r0
+ msr BASEPRI_MAX, r0
msr faultmask, r0
msr control, r0
mrs r0, xpsr
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d,v
retrieving revision 1.2
diff -u -3 -p -r1.2 mrs-msr-thumb-v7e-m.d
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d 19 Apr 2011 07:27:30 -0000 1.2
+++ gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d 19 Apr 2011 07:41:25 -0000
@@ -12,4 +12,4 @@ Disassembly of section .text:
0+08 <[^>]*> f3ef 8610 mrs r6, PRIMASK
0+0c <[^>]*> f384 8c00 msr CPSR_fs, r4
0+10 <[^>]*> f385 8401 msr IAPSR, r5
-0+14 <[^>]*> f386 8812 msr BASEPRI_MASK, r6
+0+14 <[^>]*> f386 8812 msr BASEPRI_MAX, r6
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s,v
retrieving revision 1.2
diff -u -3 -p -r1.2 mrs-msr-thumb-v7e-m.s
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s 19 Apr 2011 07:27:30 -0000 1.2
+++ gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s 19 Apr 2011 07:41:25 -0000
@@ -7,4 +7,4 @@
mrs r6, primask
msr apsr_nzcvqg, r4
msr iapsr_g, r5
- msr basepri_mask, r6
+ msr basepri_max, r6
Index: opcodes/arm-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/arm-dis.c,v
retrieving revision 1.142
diff -u -3 -p -r1.142 arm-dis.c
--- opcodes/arm-dis.c 19 Apr 2011 07:27:32 -0000 1.142
+++ opcodes/arm-dis.c 19 Apr 2011 07:41:26 -0000
@@ -3722,7 +3722,7 @@ psr_name (int regno)
case 9: return "PSP";
case 16: return "PRIMASK";
case 17: return "BASEPRI";
- case 18: return "BASEPRI_MASK";
+ case 18: return "BASEPRI_MAX";
case 19: return "FAULTMASK";
case 20: return "CONTROL";
default: return "<unknown>";
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH, ARM] MSR/MRS assembly and disassembly tweaks
2011-04-19 7:46 ` Nick Clifton
@ 2011-04-19 22:29 ` Hans-Peter Nilsson
0 siblings, 0 replies; 14+ messages in thread
From: Hans-Peter Nilsson @ 2011-04-19 22:29 UTC (permalink / raw)
To: nickc; +Cc: julian, binutils
> Date: Tue, 19 Apr 2011 08:46:48 +0100
> From: Nick Clifton <nickc@redhat.com>
> I have checked in this patch to revert the BASEPRI_MASK parts of my
> previous patch.
For closure: all now clear on the simulator front. Thanks.
brgds, H-P
^ permalink raw reply [flat|nested] 14+ messages in thread
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Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
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2011-04-04 14:07 [PATCH, ARM] MSR/MRS assembly and disassembly tweaks Julian Brown
2011-04-08 16:25 ` Nick Clifton
2011-04-12 16:41 ` Tejas Belagod
2011-04-13 4:33 ` Paul Carroll
2011-04-13 13:20 ` Julian Brown
2011-04-12 19:59 ` Hans-Peter Nilsson
2011-04-13 14:42 ` Dave Martin
2011-04-13 14:52 ` Julian Brown
2011-04-15 7:20 ` Hans-Peter Nilsson
2011-04-18 13:29 ` Nick Clifton
2011-04-18 13:54 ` Julian Brown
2011-04-19 7:46 ` Nick Clifton
2011-04-19 22:29 ` Hans-Peter Nilsson
2011-04-19 2:53 ` Hans-Peter Nilsson
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