From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 17547 invoked by alias); 13 Apr 2011 14:52:06 -0000 Received: (qmail 17534 invoked by uid 22791); 13 Apr 2011 14:52:05 -0000 X-SWARE-Spam-Status: No, hits=-1.7 required=5.0 tests=AWL,BAYES_00,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 13 Apr 2011 14:51:56 +0000 Received: (qmail 15693 invoked from network); 13 Apr 2011 14:51:55 -0000 Received: from unknown (HELO rex.config) (julian@127.0.0.2) by mail.codesourcery.com with ESMTPA; 13 Apr 2011 14:51:55 -0000 Date: Wed, 13 Apr 2011 14:52:00 -0000 From: Julian Brown To: Hans-Peter Nilsson Cc: binutils@sourceware.org Subject: Re: [PATCH, ARM] MSR/MRS assembly and disassembly tweaks Message-ID: <20110413155151.77dec560@rex.config> In-Reply-To: <201104121959.p3CJxbU3022379@ignucius.se.axis.com> References: <20110404150728.27eeeca9@rex.config> <201104121959.p3CJxbU3022379@ignucius.se.axis.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="MP_/OG7rfirQQR_wog6yz1KlskW" Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org X-SW-Source: 2011-04/txt/msg00200.txt.bz2 --MP_/OG7rfirQQR_wog6yz1KlskW Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Content-Disposition: inline Content-length: 1586 On Tue, 12 Apr 2011 21:59:37 +0200 Hans-Peter Nilsson wrote: > > Date: Mon, 4 Apr 2011 15:07:28 +0100 > > From: Julian Brown > > > This patch improves handling of MSR and MRS instructions in GAS, and > > also improves disassembly output in a couple of cases. > > Please fix the resulting fallout from the src/sim testsuite for > arm-elf with the arm-sim board. It has regressed in the last > 24h, like so: Hmm... I seem to have been a little confused by the difference between "selected_cpu" and "cpu_variant" in tc-arm.c (in fact I still am!), and I'd also not tested thoroughly enough what happens in "implied CPU variant" mode, i.e. when no CPU or architecture is passed on the command line or present as an .arch/.cpu directive in the input file. So, anyway. The attached patch fixes the MRS/MSR tests, but causes some further regressions regarding the SVC instruction on e.g. v7-A architectures: PASS -> FAIL: default/gas.sum:ARM V7 instructions PASS -> FAIL: default/gas.sum:attributes for -march=armv7 .../arch7.s:83: Error: SVC is not permitted on this architecture I'm not sure if I'll have time to investigate this further this week. I could apply the attached if someone can investigate the SVC problem further, or I can just revert my MRS/MSR patch for now. Anyone have any preferences? Thanks, Julian ChangeLog gas/ * config/tc-arm.c (parse_psr): Use selected_cpu not cpu_variant to detect M-profile targets. include/ * opcode/arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask. --MP_/OG7rfirQQR_wog6yz1KlskW Content-Type: text/x-patch Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=binutils-mrs-msr-fsf-tweaks-1.diff Content-length: 2204 ? gas/testsuite/gas/arm/a.out Index: gas/config/tc-arm.c =================================================================== RCS file: /cvs/src/src/gas/config/tc-arm.c,v retrieving revision 1.480 diff -c -p -r1.480 tc-arm.c *** gas/config/tc-arm.c 12 Apr 2011 11:47:38 -0000 1.480 --- gas/config/tc-arm.c 13 Apr 2011 14:48:26 -0000 *************** parse_psr (char **str, bfd_boolean lhs) *** 5354,5360 **** const struct asm_psr *psr; char *start; bfd_boolean is_apsr = FALSE; ! bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m); /* CPSR's and SPSR's can now be lowercase. This is just a convenience feature for ease of use and backwards compatibility. */ --- 5354,5360 ---- const struct asm_psr *psr; char *start; bfd_boolean is_apsr = FALSE; ! bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m); /* CPSR's and SPSR's can now be lowercase. This is just a convenience feature for ease of use and backwards compatibility. */ Index: include/opcode/arm.h =================================================================== RCS file: /cvs/src/src/include/opcode/arm.h,v retrieving revision 1.25 diff -c -p -r1.25 arm.h *** include/opcode/arm.h 11 Apr 2011 15:23:09 -0000 1.25 --- include/opcode/arm.h 13 Apr 2011 14:48:26 -0000 *************** *** 109,116 **** #define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K) #define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC) #define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC) ! #define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER \ ! | ARM_EXT_OS) #define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A) #define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV) #define ARM_AEXT_NOTM \ --- 109,115 ---- #define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K) #define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC) #define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC) ! #define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER) #define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A) #define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV) #define ARM_AEXT_NOTM \ --MP_/OG7rfirQQR_wog6yz1KlskW--