* [RFA] PowerPC VLE port - opcodes update
@ 2012-07-24 15:40 James Lemke
2012-07-25 4:47 ` Alan Modra
2012-08-31 10:40 ` Peter Bergner
0 siblings, 2 replies; 8+ messages in thread
From: James Lemke @ 2012-07-24 15:40 UTC (permalink / raw)
To: binutils; +Cc: Catherine Moore, Maciej W. Rozycki
[-- Attachment #1: Type: text/plain, Size: 439 bytes --]
My testing of the gcc port showed a problem with a 32-bit VLE insn.
I have gone through the PowerISA V2.06 for all of them. The attached
patch adds / removes the PPCVLE flag for a number of 32-bit insns.
A bootstrap was successful and I have run the dejagnu suite. There were no
regressions in any of binutils, gas, ld, gcc, g++, gfortran.
OK to commit?
--
Jim Lemke
Mentor Graphics / CodeSourcery
Orillia Ontario, +1-613-963-1073
[-- Attachment #2: vle-binutils-contrib-20120724b.diff --]
[-- Type: text/x-patch, Size: 17922 bytes --]
2012-07-24 James Lemke <jwlemke@codesourcery.com>
* ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
Index: opcodes/ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.146
diff -u -p -u -r1.146 ppc-opc.c
--- opcodes/ppc-opc.c 11 Jun 2012 08:20:43 -0000 1.146
+++ opcodes/ppc-opc.c 24 Jul 2012 15:14:02 -0000
@@ -2885,12 +2885,12 @@ const struct powerpc_opcode powerpc_opco
{"vrsqrtefp", VX (4, 330), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
{"vmrglh", VX (4, 332), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vpkswus", VX (4, 334), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
-{"mulchw", XRC(4, 168,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
-{"mulchw.", XRC(4, 168,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
-{"macchw", XO (4, 172,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
-{"macchw.", XO (4, 172,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
-{"nmacchw", XO (4, 174,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
-{"nmacchw.", XO (4, 174,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
+{"mulchw", XRC(4, 168,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"mulchw.", XRC(4, 168,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"macchw", XO (4, 172,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"macchw.", XO (4, 172,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"nmacchw", XO (4, 174,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"nmacchw.", XO (4, 174,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vslw", VX (4, 388), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
@@ -4212,8 +4212,8 @@ const struct powerpc_opcode powerpc_opco
{"tw", X(31,4), X_MASK, PPCCOM|PPCVLE, PPCNONE, {TO, RA, RB}},
{"t", X(31,4), X_MASK, PWRCOM, PPCNONE, {TO, RA, RB}},
-{"lvsl", X(31,6), X_MASK, PPCVEC, PPCNONE, {VD, RA0, RB}},
-{"lvebx", X(31,7), X_MASK, PPCVEC, PPCNONE, {VD, RA0, RB}},
+{"lvsl", X(31,6), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
+{"lvebx", X(31,7), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
@@ -4243,7 +4243,7 @@ const struct powerpc_opcode powerpc_opco
{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, PPCNONE, {RT, FXM4}},
{"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM|PPCVLE, POWER4, {RT}},
-{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, PPCNONE, {RT, FXM}},
+{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {RT, FXM}},
{"lwarx", X(31,20), XEH_MASK, PPC|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
@@ -4281,19 +4281,19 @@ const struct powerpc_opcode powerpc_opco
{"cmpl", X(31,32), XCMP_MASK, PPC|PPCVLE, PPCNONE, {BF, L, RA, RB}},
{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
-{"lvsr", X(31,38), X_MASK, PPCVEC, PPCNONE, {VD, RA0, RB}},
-{"lvehx", X(31,39), X_MASK, PPCVEC, PPCNONE, {VD, RA0, RB}},
+{"lvsr", X(31,38), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
+{"lvehx", X(31,39), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
{"iselgt", X(31,47), X_MASK, PPCISEL, PPCNONE, {RT, RA0, RB}},
-{"lvewx", X(31,71), X_MASK, PPCVEC, PPCNONE, {VD, RA0, RB}},
+{"lvewx", X(31,71), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, PPCNONE, {RT, RA, RB}},
{"iseleq", X(31,79), X_MASK, PPCISEL, PPCNONE, {RT, RA0, RB}},
-{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, PPCNONE, {RT, RA0, RB, CRB}},
+{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN|PPCVLE, PPCNONE, {RT, RA0, RB, CRB}},
{"subf", XO(31,40,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
{"sub", XO(31,40,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RB, RA}},
@@ -4302,7 +4302,7 @@ const struct powerpc_opcode powerpc_opco
{"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}},
-{"lbarx", X(31,52), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}},
+{"lbarx", X(31,52), XEH_MASK, POWER7|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
{"ldux", X(31,53), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}},
@@ -4346,8 +4346,8 @@ const struct powerpc_opcode powerpc_opco
{"mulhw", XO(31,75,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
{"mulhw.", XO(31,75,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
-{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, PPCNONE, {RA, RS, RB}},
-{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, PPCNONE, {RA, RS, RB}},
+{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN|PPCVLE, PPCNONE, {RA, RS, RB}},
+{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN|PPCVLE, PPCNONE, {RA, RS, RB}},
{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, PPCNONE, {SR, RS}},
@@ -4364,7 +4364,7 @@ const struct powerpc_opcode powerpc_opco
{"dni", XRC(31,97,1), XRB_MASK, E6500, PPCNONE, {DUI, DCTL}},
-{"lvx", X(31,103), X_MASK, PPCVEC, PPCNONE, {VD, RA0, RB}},
+{"lvx", X(31,103), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
{"neg", XO(31,104,0,0), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}},
@@ -4377,7 +4377,7 @@ const struct powerpc_opcode powerpc_opco
{"mtsrdin", X(31,114), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
-{"lharx", X(31,116), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}},
+{"lharx", X(31,116), XEH_MASK, POWER7|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
{"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}},
@@ -4414,8 +4414,8 @@ const struct powerpc_opcode powerpc_opco
{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, PPCNONE, {RS}},
-{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}},
-{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}},
+{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {FXM, RS}},
+{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {FXM, RS}},
{"mtmsr", X(31,146), XRLARB_MASK, COM|PPCVLE, PPCNONE, {RS, A_L}},
@@ -4503,7 +4503,7 @@ const struct powerpc_opcode powerpc_opco
{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
-{"stvx", X(31,231), X_MASK, PPCVEC, PPCNONE, {VS, RA0, RB}},
+{"stvx", X(31,231), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VS, RA0, RB}},
{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
@@ -4540,7 +4540,7 @@ const struct powerpc_opcode powerpc_opco
{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, PPCNONE, {RA, RS, RB}},
-{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA0, RB}},
+{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RS, RA}},
{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, PPCNONE, {RS, RA}},
@@ -4549,7 +4549,7 @@ const struct powerpc_opcode powerpc_opco
{"icbt", X(31,262), XRT_MASK, PPC403, PPCNONE, {RA, RB}},
-{"lvepxl", X(31,263), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
+{"lvepxl", X(31,263), X_MASK, PPCVEC2|PPCVLE, PPCNONE, {VD, RA0, RB}},
{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
{"doz", XO(31,264,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
@@ -4560,7 +4560,7 @@ const struct powerpc_opcode powerpc_opco
{"add.", XO(31,266,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
+{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2|PPCVLE, PPCNONE, {0}},
{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, PPC476, {RB, L}},
@@ -4580,12 +4580,12 @@ const struct powerpc_opcode powerpc_opco
{"eqv", XRC(31,284,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
{"eqv.", XRC(31,284,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
-{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA0, RB}},
+{"lhepx", X(31,287), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
{"mfdcrux", X(31,291), X_MASK, PPC464|PPCVLE, PPCNONE, {RS, RA}},
{"lvexhx", X(31,293), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
-{"lvepx", X(31,295), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
+{"lvepx", X(31,295), X_MASK, PPCVEC2|PPCVLE, PPCNONE, {VD, RA0, RB}},
{"tlbie", X(31,306), XRTLRA_MASK, PPC, TITAN, {RB, L}},
{"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}},
@@ -4599,7 +4599,7 @@ const struct powerpc_opcode powerpc_opco
{"xor", XRC(31,316,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
{"xor.", XRC(31,316,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
-{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA0, RB}},
+{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, PPCNONE, {RT}},
{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, PPCNONE, {RT}},
@@ -4854,7 +4854,7 @@ const struct powerpc_opcode powerpc_opco
{"lhax", X(31,343), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}},
-{"lvxl", X(31,359), X_MASK, PPCVEC, PPCNONE, {VD, RA0, RB}},
+{"lvxl", X(31,359), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
{"abs", XO(31,360,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
{"abs.", XO(31,360,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
@@ -4876,8 +4876,8 @@ const struct powerpc_opcode powerpc_opco
{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, PPCNONE, {RA, RS}},
-{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
-{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2|PPCVLE, PPCNONE, {RA, RS}},
+{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RA, RS}},
+{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, PPCNONE, {RA, RS}},
{"stvexbx", X(31,389), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
@@ -4974,10 +4974,10 @@ const struct powerpc_opcode powerpc_opco
{"divdu", XO(31,457,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
{"divdu.", XO(31,457,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
-{"divwu", XO(31,459,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-{"divwu.", XO(31,459,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
+{"divwu", XO(31,459,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"divwu.", XO(31,459,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
-{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, PPCNONE, {PMR, RS}},
+{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {PMR, RS}},
{"mttmr", X(31,494), X_MASK, PPCTMR|E6500, PPCNONE, {TMR, RS}},
{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, PPCNONE, {RS}},
@@ -5147,22 +5147,22 @@ const struct powerpc_opcode powerpc_opco
{"nand", XRC(31,476,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
{"nand.", XRC(31,476,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
-{"dsn", X(31,483), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
+{"dsn", X(31,483), XRT_MASK, E500MC|PPCVLE, PPCNONE, {RA, RB}},
-{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}},
+{"dcread", X(31,486), X_MASK, PPC403|PPC440|PPCVLE, PPCA2|PPC476, {RT, RA0, RB}},
{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
-{"stvxl", X(31,487), X_MASK, PPCVEC, PPCNONE, {VS, RA0, RB}},
+{"stvxl", X(31,487), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VS, RA0, RB}},
{"nabs", XO(31,488,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
{"nabs.", XO(31,488,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
-{"divd", XO(31,489,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-{"divd.", XO(31,489,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
+{"divd", XO(31,489,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"divd.", XO(31,489,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
-{"divw", XO(31,491,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-{"divw.", XO(31,491,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
+{"divw", XO(31,491,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"divw.", XO(31,491,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
{"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
@@ -5174,9 +5174,9 @@ const struct powerpc_opcode powerpc_opco
{"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS, RB}},
-{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, POWER7, {BF}},
+{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM|PPCVLE, POWER7, {BF}},
-{"lbdx", X(31,515), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
+{"lbdx", X(31,515), X_MASK, E500MC|PPCVLE, PPCNONE, {RT, RA, RB}},
{"bblels", X(31,518), X_MASK, PPCBRLK, PPCNONE, {0}},
@@ -5221,7 +5221,7 @@ const struct powerpc_opcode powerpc_opco
{"maskir", XRC(31,541,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
{"maskir.", XRC(31,541,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-{"lhdx", X(31,547), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
+{"lhdx", X(31,547), X_MASK, E500MC|PPCVLE, PPCNONE, {RT, RA, RB}},
{"lvtrx", X(31,549), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
@@ -5239,7 +5239,7 @@ const struct powerpc_opcode powerpc_opco
{"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
-{"lwdx", X(31,579), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
+{"lwdx", X(31,579), X_MASK, E500MC|PPCVLE, PPCNONE, {RT, RA, RB}},
{"lvtlx", X(31,581), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
@@ -5266,14 +5266,14 @@ const struct powerpc_opcode powerpc_opco
{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {FRT, RA0, RB}},
-{"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
+{"lddx", X(31,611), X_MASK, E500MC|PPCVLE, PPCNONE, {RT, RA, RB}},
{"lvswx", X(31,613), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-{"nego", XO(31,104,1,0), XORB_MASK, COM, PPCNONE, {RT, RA}},
-{"nego.", XO(31,104,1,1), XORB_MASK, COM, PPCNONE, {RT, RA}},
+{"nego", XO(31,104,1,0), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}},
+{"nego.", XO(31,104,1,1), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}},
{"mulo", XO(31,107,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
{"mulo.", XO(31,107,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
@@ -5379,17 +5379,17 @@ const struct powerpc_opcode powerpc_opco
{"mulldo", XO(31,233,1,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
-{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, PPCNONE, {RA0, RB}},
+{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}},
{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, PPCNONE, {RA0, RB}},
{"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
@@ -5416,7 +5416,7 @@ const struct powerpc_opcode powerpc_opco
{"lwzcix", X(31,789), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
-{"lhbrx", X(31,790), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
+{"lhbrx", X(31,790), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}},
{"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
{"lfqx", X(31,791), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}},
@@ -5429,7 +5429,7 @@ const struct powerpc_opcode powerpc_opco
{"srad", XRC(31,794,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
{"srad.", XRC(31,794,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
-{"lfddx", X(31,803), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}},
+{"lfddx", X(31,803), X_MASK, E500MC|PPCVLE, PPCNONE, {FRT, RA, RB}},
{"lvtrxl", X(31,805), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
{"stvepx", X(31,807), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
@@ -5570,7 +5570,7 @@ const struct powerpc_opcode powerpc_opco
{"stbcix", X(31,981), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
-{"icbi", X(31,982), XRT_MASK, PPC, PPCNONE, {RA0, RB}},
+{"icbi", X(31,982), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB}},
{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
@@ -5597,7 +5597,7 @@ const struct powerpc_opcode powerpc_opco
{"stdcix", X(31,1013), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
-{"dcbz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA0, RB}},
+{"dcbz", X(31,1014), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB}},
{"dclz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA0, RB}},
{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFA] PowerPC VLE port - opcodes update
2012-07-24 15:40 [RFA] PowerPC VLE port - opcodes update James Lemke
@ 2012-07-25 4:47 ` Alan Modra
2012-08-31 10:40 ` Peter Bergner
1 sibling, 0 replies; 8+ messages in thread
From: Alan Modra @ 2012-07-25 4:47 UTC (permalink / raw)
To: James Lemke; +Cc: binutils, Catherine Moore, Maciej W. Rozycki
On Tue, Jul 24, 2012 at 11:40:16AM -0400, James Lemke wrote:
> * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
OK.
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFA] PowerPC VLE port - opcodes update
2012-07-24 15:40 [RFA] PowerPC VLE port - opcodes update James Lemke
2012-07-25 4:47 ` Alan Modra
@ 2012-08-31 10:40 ` Peter Bergner
2012-08-31 11:03 ` Maciej W. Rozycki
2012-09-05 18:23 ` James Lemke
1 sibling, 2 replies; 8+ messages in thread
From: Peter Bergner @ 2012-08-31 10:40 UTC (permalink / raw)
To: James Lemke; +Cc: binutils, Catherine Moore, Maciej W. Rozycki, Alan Modra
On Tue, 24 Jul 2012 11:40:16 -0400 James Lemke wrote:
> My testing of the gcc port showed a problem with a 32-bit VLE insn.
> I have gone through the PowerISA V2.06 for all of them. The attached
> patch adds / removes the PPCVLE flag for a number of 32-bit insns.
While doing some clean ups, I've come across quite a few bugs and warts
due to the VLE patches. Hopefully you can clean these problems up.
First off, I see no documentation of the -mvle option, even though one
of the ChangeLog entries seems to imply it was added. Did that hunk get
dropped?
* doc/c-ppc.texi: Document -mvle.
I believe the option should also be added to the doc/as.texinfo file as well.
-{"mulchw", XRC(4, 168,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
-{"mulchw.", XRC(4, 168,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
-{"macchw", XO (4, 172,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
-{"macchw.", XO (4, 172,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
-{"nmacchw", XO (4, 174,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
-{"nmacchw.", XO (4, 174,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
+{"mulchw", XRC(4, 168,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"mulchw.", XRC(4, 168,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"macchw", XO (4, 172,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"macchw.", XO (4, 172,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"nmacchw", XO (4, 174,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"nmacchw.", XO (4, 174,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
Since the MULHW macro is defined as:
#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN | PPC_OPCODE_VLE
...this change is totally unneeded and just clutters up the opcode table.
Please remove all uses of PPCVLE on all of the instructions where PPCVLE is
used with MULHW...which is all of them.
Please do the same for all instructions that use PPCSPE, PPCEFS and PPCISEL
as well, since those macros also include PPCVLE. That assuming VLE should
have been enabled for all these MULHW, PPCSPE, PPCEFS and PPCISEL instructions
in the first place.
-{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}},
+{"dcread", X(31,486), X_MASK, PPC403|PPC440|PPCVLE, PPCA2|PPC476, {RT, RA0, RB}},
{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
This cannot possibly be correct. You've just enabled dcread for -mvle, but the icbtls
instruction which has the same major and minor opcodes is also enabled for -mvle.
This leads to bugs like:
bergner@bns:~/binutils/tests> cat vle-bugs.s
main:
dcread 3,4,5
icbtls 3,4,5
bergner@bns:~/binutils/tests> as -a32 -mvle vle-bugs.s
bergner@bns:~/binutils/tests> objdump -d -Mvle a.out
a.out: file format elf32-powerpc
Disassembly of section .text:
00000000 <main>:
0: 7c 64 2b cc dcread r3,r4,r5
4: 7c 64 2b cc dcread r3,r4,r5
So which is it?
Unfortunately, this isn't the only occurrence of two instructions with the same
major and minor opcodes that are enabled at the same time with -mvle. There are
actually quite a few of them. :( Doing a quick scan, I see these conflicting
instructions:
{"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evaddiw", VX (4, 514), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB, UIMM}},
{"vminub", VX (4, 514), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evsubfw", VX (4, 516), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evsubw", VX (4, 516), VX_MASK, PPCSPE, PPCNONE, {RS, RB, RA}},
{"vsrb", VX (4, 516), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evsubifw", VX (4, 518), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, UIMM, RB}},
{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, PPCNONE, {RS, RB, UIMM}},
{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evabs", VX (4, 520), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
{"vmuleub", VX (4, 520), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evextsb", VX (4, 522), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
{"vrfin", VX (4, 522), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
{"evrndw", VX (4, 524), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
{"vspltb", VX (4, 524), VXUIMM4_MASK,PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM4}},
{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
{"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
{"evfsadd", VX (4, 640), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vadduws", VX (4, 640), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evfsabs", VX (4, 644), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
{"vsrw", VX (4, 644), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evfsneg", VX (4, 646), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
{"vspltw", VX (4, 652), VXUIMM2_MASK,PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM2}},
{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
{"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
{"efsabs", VX (4, 708), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}},
{"vsr", VX (4, 708), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"efsneg", VX (4, 710), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}},
{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
{"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
{"evlddx", VX (4, 768), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evldwx", VX (4, 770), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vminsb", VX (4, 770), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evldhx", VX (4, 772), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vsrab", VX (4, 772), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vmulesb", VX (4, 776), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}},
{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vpkpx", VX (4, 782), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evmra", VX (4,1220), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
{"vxor", VX (4,1220), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vnor", VX (4,1284), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
These are not as easy to spot as identical, but they are:
{"evlwhex", VX (4, 784), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"mullhwu", XRC(4, 392,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"evlwhe", VX (4, 785), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
{"evmwumi", VX (4,1112), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"machhwo", XO (4, 44,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"machhwo.", XO (4, 44,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evdivws", VX (4,1222), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"macchwo", XO (4, 172,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"macchwo.", XO (4, 172,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evmwumian", VX (4,1496), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"macchwso", XO (4, 236,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"macchwso.", XO (4, 236,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
I can't even say whether this is an exhaustive list or not. I know I did not even
look at the VLE opcodes table itself, so you'll want to go through with a fine tooth
comb looking for duplicates.
Peter
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFA] PowerPC VLE port - opcodes update
2012-08-31 10:40 ` Peter Bergner
@ 2012-08-31 11:03 ` Maciej W. Rozycki
2012-09-02 4:37 ` Alan Modra
2012-09-05 18:23 ` James Lemke
1 sibling, 1 reply; 8+ messages in thread
From: Maciej W. Rozycki @ 2012-08-31 11:03 UTC (permalink / raw)
To: Peter Bergner; +Cc: James Lemke, binutils, Catherine Moore, Alan Modra
Peter,
> Unfortunately, this isn't the only occurrence of two instructions with the same
> major and minor opcodes that are enabled at the same time with -mvle. There are
> actually quite a few of them. :( Doing a quick scan, I see these conflicting
> instructions:
>
> {"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
> {"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
[etc...]
All these instructions are valid in the VLE mode depending on what a
given processor implements. The logic to interpret the PPCVLE
(PPC_OPCODE_VLE) flag should IMHO be changed such that in the VLE mode
(-mvle) it does not enable any instruction such marked unconditionally.
The flag should mean an instruction is merely permitted in the VLE mode
and then other flags would actually drive enabling the instruction -- an
extra opcode flag might be required to enable base set VLE instructions
that are always available with a lone -mvle option as I reckon they are a
superset of the base standard Power instruction set. That flag, say
PPC_OPCODE_VLE_BASE or PPCVLEB, would be ORed in the mask to match against
with -mvle itself. That flag would also be used for instructions valid in
the VLE mode only (E_* and SE_* mnemonics), that would otherwise never be
enabled.
So for example EVADDW would only be enabled whevener -mvle and -mspe are
used both at the same time, likewise VADDUBS would only work with -mvle
and -maltivec and with a lone -mvle neither of these instructions would be
enabled. The disassembler would work accordingly -- choosing the right
instruction to dump based on the architecture selected or inferred from
ELF object flags and the VLE section attribute.
Maciej
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFA] PowerPC VLE port - opcodes update
2012-08-31 11:03 ` Maciej W. Rozycki
@ 2012-09-02 4:37 ` Alan Modra
2012-09-04 14:41 ` Peter Bergner
0 siblings, 1 reply; 8+ messages in thread
From: Alan Modra @ 2012-09-02 4:37 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: Peter Bergner, James Lemke, binutils, Catherine Moore
On Fri, Aug 31, 2012 at 11:52:53AM +0100, Maciej W. Rozycki wrote:
> The logic to interpret the PPCVLE
> (PPC_OPCODE_VLE) flag should IMHO be changed such that in the VLE mode
> (-mvle) it does not enable any instruction such marked unconditionally.
Agreed.
> So for example EVADDW would only be enabled whevener -mvle and -mspe are
> used both at the same time, likewise VADDUBS would only work with -mvle
> and -maltivec and with a lone -mvle neither of these instructions would be
> enabled. The disassembler would work accordingly -- choosing the right
> instruction to dump based on the architecture selected or inferred from
> ELF object flags and the VLE section attribute.
Yes, and of course you can use other -m<cpu>/-M<cpu> options to select
the underlying flags.
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFA] PowerPC VLE port - opcodes update
2012-09-02 4:37 ` Alan Modra
@ 2012-09-04 14:41 ` Peter Bergner
2012-09-11 1:09 ` Alan Modra
0 siblings, 1 reply; 8+ messages in thread
From: Peter Bergner @ 2012-09-04 14:41 UTC (permalink / raw)
To: Alan Modra; +Cc: Maciej W. Rozycki, James Lemke, binutils, Catherine Moore
On Sun, 2 Sep 2012 14:07:05 +0930 Alan Modra wrote:
> On Fri, Aug 31, 2012 at 11:52:53AM +0100, Maciej W. Rozycki wrote:
> > The logic to interpret the PPCVLE
> > (PPC_OPCODE_VLE) flag should IMHO be changed such that in the VLE mode
> > (-mvle) it does not enable any instruction such marked unconditionally.
>
> Agreed.
Agreed here too, now that Maciej described how VLE works.
> > So for example EVADDW would only be enabled whevener -mvle and -mspe are
> > used both at the same time, likewise VADDUBS would only work with -mvle
> > and -maltivec and with a lone -mvle neither of these instructions would be
> > enabled. The disassembler would work accordingly -- choosing the right
> > instruction to dump based on the architecture selected or inferred from
> > ELF object flags and the VLE section attribute.
>
> Yes, and of course you can use other -m<cpu>/-M<cpu> options to select
> the underlying flags.
I can see two ways to accomplish this. The first method would be to remove
the PPCVLE flag from all of the instructions that are possibly valid VLE
instructions, and rather place the PPCVLE flag in the deprecated field
of those instructions that will never be valid VLE instructions. Then the
normal -mspe, -maltivec, -etc. options can enable the instructions you want.
This has one drawback, in that as people add new instructions, we may not
know or remember to add or not add PPCVLE to the deprecated field, so you
may get new instructions enabled when we shouldn't.
That leads me to the second option, and that is to copy all of the VLE
instructions in powerpc_opcodes into vle_opcodes and just use the -mvle
option to choose between the two structures. This should allow the
code to be cleaned up a bit, as we'll never have to look through both
tables like the code does now.
I think Alan probably has the final say on how this should be fixed though.
Peter
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFA] PowerPC VLE port - opcodes update
2012-08-31 10:40 ` Peter Bergner
2012-08-31 11:03 ` Maciej W. Rozycki
@ 2012-09-05 18:23 ` James Lemke
1 sibling, 0 replies; 8+ messages in thread
From: James Lemke @ 2012-09-05 18:23 UTC (permalink / raw)
To: Peter Bergner; +Cc: binutils, Catherine Moore, Maciej W. Rozycki, Alan Modra
On 08/31/2012 12:38 AM, Peter Bergner wrote:
> First off, I see no documentation of the -mvle option, even though one
> of the ChangeLog entries seems to imply it was added. Did that hunk get
> dropped?
>
> * doc/c-ppc.texi: Document -mvle.
>
> I believe the option should also be added to the doc/as.texinfo file as well.
Yes, I lost that hunk. Thanks for pointing this out.
Both changes have been committed as trivial.
--
Jim Lemke
Mentor Graphics / CodeSourcery
Orillia Ontario, +1-613-963-1073
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFA] PowerPC VLE port - opcodes update
2012-09-04 14:41 ` Peter Bergner
@ 2012-09-11 1:09 ` Alan Modra
0 siblings, 0 replies; 8+ messages in thread
From: Alan Modra @ 2012-09-11 1:09 UTC (permalink / raw)
To: Peter Bergner; +Cc: Maciej W. Rozycki, James Lemke, binutils, Catherine Moore
On Tue, Sep 04, 2012 at 09:35:19AM -0500, Peter Bergner wrote:
> On Sun, 2 Sep 2012 14:07:05 +0930 Alan Modra wrote:
> > On Fri, Aug 31, 2012 at 11:52:53AM +0100, Maciej W. Rozycki wrote:
> > > The logic to interpret the PPCVLE
> > > (PPC_OPCODE_VLE) flag should IMHO be changed such that in the VLE mode
> > > (-mvle) it does not enable any instruction such marked unconditionally.
> >
> > Agreed.
>
> Agreed here too, now that Maciej described how VLE works.
>
>
> > > So for example EVADDW would only be enabled whevener -mvle and -mspe are
> > > used both at the same time, likewise VADDUBS would only work with -mvle
> > > and -maltivec and with a lone -mvle neither of these instructions would be
> > > enabled. The disassembler would work accordingly -- choosing the right
> > > instruction to dump based on the architecture selected or inferred from
> > > ELF object flags and the VLE section attribute.
> >
> > Yes, and of course you can use other -m<cpu>/-M<cpu> options to select
> > the underlying flags.
>
> I can see two ways to accomplish this. The first method would be to remove
> the PPCVLE flag from all of the instructions that are possibly valid VLE
> instructions, and rather place the PPCVLE flag in the deprecated field
> of those instructions that will never be valid VLE instructions. Then the
> normal -mspe, -maltivec, -etc. options can enable the instructions you want.
> This has one drawback, in that as people add new instructions, we may not
> know or remember to add or not add PPCVLE to the deprecated field, so you
> may get new instructions enabled when we shouldn't.
>
> That leads me to the second option, and that is to copy all of the VLE
> instructions in powerpc_opcodes into vle_opcodes and just use the -mvle
> option to choose between the two structures. This should allow the
> code to be cleaned up a bit, as we'll never have to look through both
> tables like the code does now.
>
> I think Alan probably has the final say on how this should be fixed though.
I don't particularly care how this is fixed, but something should be
done. Peter's second proposal has all the disadvantages associated
with source duplication, but it might be more maintainable so I
slightly favour that idea. However, I'd be happy with a fix that
leaves the 32-bit insns in the main opcode table.
--
Alan Modra
Australia Development Lab, IBM
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-- links below jump to the message on this page --
2012-07-24 15:40 [RFA] PowerPC VLE port - opcodes update James Lemke
2012-07-25 4:47 ` Alan Modra
2012-08-31 10:40 ` Peter Bergner
2012-08-31 11:03 ` Maciej W. Rozycki
2012-09-02 4:37 ` Alan Modra
2012-09-04 14:41 ` Peter Bergner
2012-09-11 1:09 ` Alan Modra
2012-09-05 18:23 ` James Lemke
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