* PowerPC VLE sh_flags and p_flags
@ 2016-08-31 3:54 Alan Modra
2016-08-31 4:37 ` Adjust VLE testsuite Alan Modra
0 siblings, 1 reply; 2+ messages in thread
From: Alan Modra @ 2016-08-31 3:54 UTC (permalink / raw)
To: binutils
ELF section sh_flags SHF_PPC_VLE was being set based on arch/mach,
which meant all code sections in an object file has the flag or all
lacked it. We can do better than that. Only those code sections
where VLE is enabled ought to have the flag, allowing an object file
to contain both VLE and non-VLE code.
Also, ELF header p_flags PF_PPC_VLE wasn't being set, and the pr20531
testcase showed segments were being split unnecessarily.
Committed to master.
bfd/
* elf32-ppc.c (ppc_elf_section_processing): Delete.
(elf_backend_section_processing): Don't define.
(ppc_elf_modify_segment_map): Set p_flags and mark valid. Don't
split on non-exec sections differing in SHF_PPC_VLE. When
splitting segments, mark size invalid.
gas/
* config/tc-ppc.c (md_assemble): Set sh_flags for VLE. Test
ppc_cpu rather than calling ppc_mach to determine VLE mode.
(ppc_frag_check, ppc_handle_align): Likewise use ppc_cpu.
diff --git a/bfd/elf32-ppc.c b/bfd/elf32-ppc.c
index 1dd6d78..e808cb5 100644
--- a/bfd/elf32-ppc.c
+++ b/bfd/elf32-ppc.c
@@ -2444,18 +2444,6 @@ ppc_elf_lookup_section_flags (char *flag_name)
return 0;
}
-/* Add the VLE flag if required. */
-
-bfd_boolean
-ppc_elf_section_processing (bfd *abfd, Elf_Internal_Shdr *shdr)
-{
- if (bfd_get_mach (abfd) == bfd_mach_ppc_vle
- && (shdr->sh_flags & SHF_EXECINSTR) != 0)
- shdr->sh_flags |= SHF_PPC_VLE;
-
- return TRUE;
-}
-
/* Return address for Ith PLT stub in section PLT, for relocation REL
or (bfd_vma) -1 if it should not be included. */
@@ -2535,10 +2523,7 @@ bfd_boolean
ppc_elf_modify_segment_map (bfd *abfd,
struct bfd_link_info *info ATTRIBUTE_UNUSED)
{
- struct elf_segment_map *m, *n;
- bfd_size_type amt;
- unsigned int j, k;
- bfd_boolean sect0_vle, sectj_vle;
+ struct elf_segment_map *m;
/* At this point in the link, output sections have already been sorted by
LMA and assigned to segments. All that is left to do is to ensure
@@ -2548,25 +2533,59 @@ ppc_elf_modify_segment_map (bfd *abfd,
for (m = elf_seg_map (abfd); m != NULL; m = m->next)
{
- if (m->count == 0)
+ struct elf_segment_map *n;
+ bfd_size_type amt;
+ unsigned int j, k;
+ unsigned int p_flags;
+
+ if (m->p_type != PT_LOAD || m->count == 0)
continue;
- sect0_vle = (elf_section_flags (m->sections[0]) & SHF_PPC_VLE) != 0;
- for (j = 1; j < m->count; ++j)
+ for (p_flags = PF_R, j = 0; j != m->count; ++j)
{
- sectj_vle = (elf_section_flags (m->sections[j]) & SHF_PPC_VLE) != 0;
+ if ((m->sections[j]->flags & SEC_READONLY) == 0)
+ p_flags |= PF_W;
+ if ((m->sections[j]->flags & SEC_CODE) != 0)
+ {
+ p_flags |= PF_X;
+ if ((elf_section_flags (m->sections[j]) & SHF_PPC_VLE) != 0)
+ p_flags |= PF_PPC_VLE;
+ break;
+ }
+ }
+ if (j != m->count)
+ while (++j != m->count)
+ {
+ unsigned int p_flags1 = PF_R;
- if (sectj_vle != sect0_vle)
- break;
- }
- if (j >= m->count)
+ if ((m->sections[j]->flags & SEC_READONLY) == 0)
+ p_flags1 |= PF_W;
+ if ((m->sections[j]->flags & SEC_CODE) != 0)
+ {
+ p_flags1 |= PF_X;
+ if ((elf_section_flags (m->sections[j]) & SHF_PPC_VLE) != 0)
+ p_flags1 |= PF_PPC_VLE;
+ if (((p_flags1 ^ p_flags) & PF_PPC_VLE) != 0)
+ break;
+ }
+ p_flags |= p_flags1;
+ }
+ /* If we're splitting a segment which originally contained rw
+ sections then those sections might now only be in one of the
+ two parts. So always set p_flags if splitting, even if we
+ are being called for objcopy with p_flags_valid set. */
+ if (j != m->count || !m->p_flags_valid)
+ {
+ m->p_flags_valid = 1;
+ m->p_flags = p_flags;
+ }
+ if (j == m->count)
continue;
- /* sections 0..j-1 stay in this (current) segment,
+ /* Sections 0..j-1 stay in this (current) segment,
the remainder are put in a new segment.
The scan resumes with the new segment. */
- /* Fix the new segment. */
amt = sizeof (struct elf_segment_map);
amt += (m->count - j - 1) * sizeof (asection *);
n = (struct elf_segment_map *) bfd_zalloc (abfd, amt);
@@ -2574,20 +2593,13 @@ ppc_elf_modify_segment_map (bfd *abfd,
return FALSE;
n->p_type = PT_LOAD;
- n->p_flags = PF_X | PF_R;
- if (sectj_vle)
- n->p_flags |= PF_PPC_VLE;
n->count = m->count - j;
for (k = 0; k < n->count; ++k)
- {
- n->sections[k] = m->sections[j+k];
- m->sections[j+k] = NULL;
- }
+ n->sections[k] = m->sections[j + k];
+ m->count = j;
+ m->p_size_valid = 0;
n->next = m->next;
m->next = n;
-
- /* Fix the current segment */
- m->count = j;
}
return TRUE;
@@ -10860,7 +10872,6 @@ ppc_elf_finish_dynamic_sections (bfd *output_bfd,
#define elf_backend_action_discarded ppc_elf_action_discarded
#define elf_backend_init_index_section _bfd_elf_init_1_index_section
#define elf_backend_lookup_section_flags_hook ppc_elf_lookup_section_flags
-#define elf_backend_section_processing ppc_elf_section_processing
#include "elf32-target.h"
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index fc2a045..1417c26 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -3377,13 +3377,17 @@ md_assemble (char *str)
however it'll remain clear for dual-mode instructions on
dual-mode and, more importantly, standard-mode processors. */
if ((ppc_cpu & opcode->flags) == PPC_OPCODE_VLE)
- ppc_apuinfo_section_add (PPC_APUINFO_VLE, 1);
+ {
+ ppc_apuinfo_section_add (PPC_APUINFO_VLE, 1);
+ if (elf_section_data (now_seg) != NULL)
+ elf_section_data (now_seg)->this_hdr.sh_flags |= SHF_PPC_VLE;
+ }
}
#endif
/* Write out the instruction. */
/* Differentiate between two and four byte insns. */
- if (ppc_mach () == bfd_mach_ppc_vle)
+ if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
{
if (PPC_OP_SE_VLE (insn))
insn_length = 2;
@@ -3400,7 +3404,7 @@ md_assemble (char *str)
f = frag_more (insn_length);
if (frag_now->has_code && frag_now->insn_addr != addr_mod)
{
- if (ppc_mach() == bfd_mach_ppc_vle)
+ if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
as_bad (_("instruction address is not a multiple of 2"));
else
as_bad (_("instruction address is not a multiple of 4"));
@@ -6346,7 +6350,7 @@ ppc_frag_check (struct frag *fragP)
if (!fragP->has_code)
return;
- if (ppc_mach() == bfd_mach_ppc_vle)
+ if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
{
if (((fragP->fr_address + fragP->insn_addr) & 1) != 0)
as_bad (_("instruction address is not a multiple of 2"));
@@ -6367,7 +6371,7 @@ ppc_handle_align (struct frag *fragP)
valueT count = (fragP->fr_next->fr_address
- (fragP->fr_address + fragP->fr_fix));
- if (ppc_mach() == bfd_mach_ppc_vle && count != 0 && (count & 1) == 0)
+ if ((ppc_cpu & PPC_OPCODE_VLE) != 0 && count != 0 && (count & 1) == 0)
{
char *dest = fragP->fr_literal + fragP->fr_fix;
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 2+ messages in thread
* Adjust VLE testsuite
2016-08-31 3:54 PowerPC VLE sh_flags and p_flags Alan Modra
@ 2016-08-31 4:37 ` Alan Modra
0 siblings, 0 replies; 2+ messages in thread
From: Alan Modra @ 2016-08-31 4:37 UTC (permalink / raw)
To: binutils
To suit f7d69005.
* testsuite/ld-powerpc/vle-multiseg-1.d: Adjust to suit segment change.
* testsuite/ld-powerpc/vle-multiseg-2.d: Likewise.
* testsuite/ld-powerpc/vle-multiseg-3.d: Likewise.
* testsuite/ld-powerpc/vle-multiseg-6.d: Likewise.
* testsuite/ld-powerpc/vle-reloc-2.d: Likewise.
diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-1.d b/ld/testsuite/ld-powerpc/vle-multiseg-1.d
index d9554a1..17d22bd 100644
--- a/ld/testsuite/ld-powerpc/vle-multiseg-1.d
+++ b/ld/testsuite/ld-powerpc/vle-multiseg-1.d
@@ -1,14 +1,12 @@
Elf file type is EXEC.*
Entry point 0x0
-There are 2 program headers, starting at offset [0-9]+
+There are 1 program headers, starting at offset [0-9]+
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
- LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
- LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
+ LOAD ( +0x[0-9a-f]+){5} RWE 0x[0-f]+
Section to Segment mapping:
Segment Sections...
- 00 .data
- 01 .text_vle .text_iv .iv_handlers
+ 00 \.data \.text_vle \.text_iv \.iv_handlers
diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-2.d b/ld/testsuite/ld-powerpc/vle-multiseg-2.d
index 9d83bb5..2b0ca14 100644
--- a/ld/testsuite/ld-powerpc/vle-multiseg-2.d
+++ b/ld/testsuite/ld-powerpc/vle-multiseg-2.d
@@ -1,16 +1,12 @@
Elf file type is EXEC.*
Entry point 0x0
-There are 3 program headers, starting at offset [0-9]+
+There are 1 program headers, starting at offset [0-9]+
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
- LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
- LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
- LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
+ LOAD ( +0x[0-9a-f]+){5} RWE 0x[0-f]+
Section to Segment mapping:
Segment Sections...
- 00 .text_vle
- 01 .data
- 02 .text_iv .iv_handlers
+ 00 \.text_vle \.data \.text_iv \.iv_handlers
diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-3.d b/ld/testsuite/ld-powerpc/vle-multiseg-3.d
index 957b990..c283003 100644
--- a/ld/testsuite/ld-powerpc/vle-multiseg-3.d
+++ b/ld/testsuite/ld-powerpc/vle-multiseg-3.d
@@ -1,16 +1,12 @@
Elf file type is EXEC.*
Entry point 0x0
-There are 3 program headers, starting at offset [0-9]+
+There are 1 program headers, starting at offset [0-9]+
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
- LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
- LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
- LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
+ LOAD ( +0x[0-9a-f]+){5} RWE 0x[0-f]+
Section to Segment mapping:
Segment Sections...
- 00 .text_vle .text_iv
- 01 .data
- 02 .iv_handlers
+ 00 \.text_vle \.text_iv \.data \.iv_handlers
diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-6.d b/ld/testsuite/ld-powerpc/vle-multiseg-6.d
index 5c3c210..1a4af3e 100644
--- a/ld/testsuite/ld-powerpc/vle-multiseg-6.d
+++ b/ld/testsuite/ld-powerpc/vle-multiseg-6.d
@@ -12,14 +12,14 @@ There are 4 program headers, starting at offset [0-9]+
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
- LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
+ LOAD ( +0x[0-9a-f]+){5} RW 0x[0-f]+
LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
Section to Segment mapping:
Segment Sections...
- 00 .data
- 01 .text_vle
- 02 .text_iv
- 03 .text
+ 00 \.data
+ 01 \.text_vle
+ 02 \.text_iv
+ 03 \.text
diff --git a/ld/testsuite/ld-powerpc/vle-reloc-2.d b/ld/testsuite/ld-powerpc/vle-reloc-2.d
index 1e1c9d4..6baafdc 100644
--- a/ld/testsuite/ld-powerpc/vle-reloc-2.d
+++ b/ld/testsuite/ld-powerpc/vle-reloc-2.d
@@ -2,86 +2,86 @@
Disassembly of section .text:
-01800094 <sub1>:
- 1800094: 00 04 se_blr
-01800096 <sub2>:
- 1800096: 00 04 se_blr
-01800098 <vle_reloc_2>:
- 1800098: 70 20 c1 c2 e_or2i r1,450
- 180009c: 70 40 c1 81 e_or2i r2,385
- 18000a0: 70 60 c1 81 e_or2i r3,385
- 18000a4: 70 80 c1 ce e_or2i r4,462
- 18000a8: 70 a0 c1 80 e_or2i r5,384
- 18000ac: 70 40 c1 81 e_or2i r2,385
- 18000b0: 70 20 c9 c2 e_and2i. r1,450
- 18000b4: 70 40 c9 81 e_and2i. r2,385
- 18000b8: 70 60 c9 81 e_and2i. r3,385
- 18000bc: 70 80 c9 ce e_and2i. r4,462
- 18000c0: 70 a0 c9 80 e_and2i. r5,384
- 18000c4: 70 40 c9 81 e_and2i. r2,385
- 18000c8: 70 20 d1 c2 e_or2is r1,450
- 18000cc: 70 40 d1 81 e_or2is r2,385
- 18000d0: 70 60 d1 81 e_or2is r3,385
- 18000d4: 70 80 d1 ce e_or2is r4,462
- 18000d8: 70 a0 d1 80 e_or2is r5,384
- 18000dc: 70 40 d1 81 e_or2is r2,385
- 18000e0: 70 20 e1 c2 e_lis r1,450
- 18000e4: 70 40 e1 81 e_lis r2,385
- 18000e8: 70 60 e1 81 e_lis r3,385
- 18000ec: 70 80 e1 ce e_lis r4,462
- 18000f0: 70 a0 e1 80 e_lis r5,384
- 18000f4: 70 40 e1 81 e_lis r2,385
- 18000f8: 70 20 e9 c2 e_and2is. r1,450
- 18000fc: 70 40 e9 81 e_and2is. r2,385
- 1800100: 70 60 e9 81 e_and2is. r3,385
- 1800104: 70 80 e9 ce e_and2is. r4,462
- 1800108: 70 a0 e9 80 e_and2is. r5,384
- 180010c: 70 40 e9 81 e_and2is. r2,385
- 1800110: 70 01 99 c2 e_cmp16i r1,450
- 1800114: 70 02 99 81 e_cmp16i r2,385
- 1800118: 70 03 99 81 e_cmp16i r3,385
- 180011c: 70 04 99 ce e_cmp16i r4,462
- 1800120: 70 05 99 80 e_cmp16i r5,384
- 1800124: 70 02 99 81 e_cmp16i r2,385
- 1800128: 70 01 a9 c2 e_cmpl16i r1,450
- 180012c: 70 02 a9 81 e_cmpl16i r2,385
- 1800130: 70 03 a9 81 e_cmpl16i r3,385
- 1800134: 70 04 a9 ce e_cmpl16i r4,462
- 1800138: 70 05 a9 80 e_cmpl16i r5,384
- 180013c: 70 02 a9 81 e_cmpl16i r2,385
- 1800140: 70 01 b1 c2 e_cmph16i r1,450
- 1800144: 70 02 b1 81 e_cmph16i r2,385
- 1800148: 70 03 b1 81 e_cmph16i r3,385
- 180014c: 70 04 b1 ce e_cmph16i r4,462
- 1800150: 70 05 b1 80 e_cmph16i r5,384
- 1800154: 70 02 b1 81 e_cmph16i r2,385
- 1800158: 70 01 b9 c2 e_cmphl16i r1,450
- 180015c: 70 02 b9 81 e_cmphl16i r2,385
- 1800160: 70 03 b9 81 e_cmphl16i r3,385
- 1800164: 70 04 b9 ce e_cmphl16i r4,462
- 1800168: 70 05 b9 80 e_cmphl16i r5,384
- 180016c: 70 02 b9 81 e_cmphl16i r2,385
- 1800170: 70 01 89 c2 e_add2i. r1,450
- 1800174: 70 02 89 81 e_add2i. r2,385
- 1800178: 70 03 89 81 e_add2i. r3,385
- 180017c: 70 04 89 ce e_add2i. r4,462
- 1800180: 70 05 89 80 e_add2i. r5,384
- 1800184: 70 02 89 81 e_add2i. r2,385
- 1800188: 70 01 91 c2 e_add2is r1,450
- 180018c: 70 02 91 81 e_add2is r2,385
- 1800190: 70 03 91 81 e_add2is r3,385
- 1800194: 70 04 91 ce e_add2is r4,462
- 1800198: 70 05 91 80 e_add2is r5,384
- 180019c: 70 02 91 81 e_add2is r2,385
- 18001a0: 70 01 a1 c2 e_mull2i r1,450
- 18001a4: 70 02 a1 81 e_mull2i r2,385
- 18001a8: 70 03 a1 81 e_mull2i r3,385
- 18001ac: 70 04 a1 ce e_mull2i r4,462
- 18001b0: 70 05 a1 80 e_mull2i r5,384
- 18001b4: 70 02 a1 81 e_mull2i r2,385
-018001b8 <sub3>:
- 18001b8: 00 04 se_blr
-018001ba <sub4>:
- 18001ba: 00 04 se_blr
-018001bc <sub5>:
- 18001bc: 00 04 se_blr
+.* <sub1>:
+.*: 00 04 se_blr
+.* <sub2>:
+.*: 00 04 se_blr
+.* <vle_reloc_2>:
+.*: 70 20 c1 a2 e_or2i r1,418
+.*: 70 40 c1 81 e_or2i r2,385
+.*: 70 60 c1 81 e_or2i r3,385
+.*: 70 80 c1 ae e_or2i r4,430
+.*: 70 a0 c1 80 e_or2i r5,384
+.*: 70 40 c1 81 e_or2i r2,385
+.*: 70 20 c9 a2 e_and2i\. r1,418
+.*: 70 40 c9 81 e_and2i\. r2,385
+.*: 70 60 c9 81 e_and2i\. r3,385
+.*: 70 80 c9 ae e_and2i\. r4,430
+.*: 70 a0 c9 80 e_and2i\. r5,384
+.*: 70 40 c9 81 e_and2i\. r2,385
+.*: 70 20 d1 a2 e_or2is r1,418
+.*: 70 40 d1 81 e_or2is r2,385
+.*: 70 60 d1 81 e_or2is r3,385
+.*: 70 80 d1 ae e_or2is r4,430
+.*: 70 a0 d1 80 e_or2is r5,384
+.*: 70 40 d1 81 e_or2is r2,385
+.*: 70 20 e1 a2 e_lis r1,418
+.*: 70 40 e1 81 e_lis r2,385
+.*: 70 60 e1 81 e_lis r3,385
+.*: 70 80 e1 ae e_lis r4,430
+.*: 70 a0 e1 80 e_lis r5,384
+.*: 70 40 e1 81 e_lis r2,385
+.*: 70 20 e9 a2 e_and2is\. r1,418
+.*: 70 40 e9 81 e_and2is\. r2,385
+.*: 70 60 e9 81 e_and2is\. r3,385
+.*: 70 80 e9 ae e_and2is\. r4,430
+.*: 70 a0 e9 80 e_and2is\. r5,384
+.*: 70 40 e9 81 e_and2is\. r2,385
+.*: 70 01 99 a2 e_cmp16i r1,418
+.*: 70 02 99 81 e_cmp16i r2,385
+.*: 70 03 99 81 e_cmp16i r3,385
+.*: 70 04 99 ae e_cmp16i r4,430
+.*: 70 05 99 80 e_cmp16i r5,384
+.*: 70 02 99 81 e_cmp16i r2,385
+.*: 70 01 a9 a2 e_cmpl16i r1,418
+.*: 70 02 a9 81 e_cmpl16i r2,385
+.*: 70 03 a9 81 e_cmpl16i r3,385
+.*: 70 04 a9 ae e_cmpl16i r4,430
+.*: 70 05 a9 80 e_cmpl16i r5,384
+.*: 70 02 a9 81 e_cmpl16i r2,385
+.*: 70 01 b1 a2 e_cmph16i r1,418
+.*: 70 02 b1 81 e_cmph16i r2,385
+.*: 70 03 b1 81 e_cmph16i r3,385
+.*: 70 04 b1 ae e_cmph16i r4,430
+.*: 70 05 b1 80 e_cmph16i r5,384
+.*: 70 02 b1 81 e_cmph16i r2,385
+.*: 70 01 b9 a2 e_cmphl16i r1,418
+.*: 70 02 b9 81 e_cmphl16i r2,385
+.*: 70 03 b9 81 e_cmphl16i r3,385
+.*: 70 04 b9 ae e_cmphl16i r4,430
+.*: 70 05 b9 80 e_cmphl16i r5,384
+.*: 70 02 b9 81 e_cmphl16i r2,385
+.*: 70 01 89 a2 e_add2i\. r1,418
+.*: 70 02 89 81 e_add2i\. r2,385
+.*: 70 03 89 81 e_add2i\. r3,385
+.*: 70 04 89 ae e_add2i\. r4,430
+.*: 70 05 89 80 e_add2i\. r5,384
+.*: 70 02 89 81 e_add2i\. r2,385
+.*: 70 01 91 a2 e_add2is r1,418
+.*: 70 02 91 81 e_add2is r2,385
+.*: 70 03 91 81 e_add2is r3,385
+.*: 70 04 91 ae e_add2is r4,430
+.*: 70 05 91 80 e_add2is r5,384
+.*: 70 02 91 81 e_add2is r2,385
+.*: 70 01 a1 a2 e_mull2i r1,418
+.*: 70 02 a1 81 e_mull2i r2,385
+.*: 70 03 a1 81 e_mull2i r3,385
+.*: 70 04 a1 ae e_mull2i r4,430
+.*: 70 05 a1 80 e_mull2i r5,384
+.*: 70 02 a1 81 e_mull2i r2,385
+.* <sub3>:
+.*: 00 04 se_blr
+.* <sub4>:
+.*: 00 04 se_blr
+.* <sub5>:
+.*: 00 04 se_blr
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2016-08-31 4:37 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-08-31 3:54 PowerPC VLE sh_flags and p_flags Alan Modra
2016-08-31 4:37 ` Adjust VLE testsuite Alan Modra
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).