From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 88413 invoked by alias); 15 Feb 2017 00:55:09 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 88327 invoked by uid 89); 15 Feb 2017 00:55:09 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=1.3 required=5.0 tests=AWL,BAYES_50,RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_SPAM,SPF_PASS autolearn=no version=3.3.2 spammy=shorne@gmail.com, shornegmailcom, sk:shorne@, sk:shorne X-HELO: mail-it0-f65.google.com Received: from mail-it0-f65.google.com (HELO mail-it0-f65.google.com) (209.85.214.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 15 Feb 2017 00:54:58 +0000 Received: by mail-it0-f65.google.com with SMTP id r141so8274552ita.1 for ; Tue, 14 Feb 2017 16:54:58 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:to:cc:cc:subject:date:message-id :in-reply-to:references; bh=hB5QvKvjbDvaBTR8NNkV7knE/6Yz+hy+8o7mPp9NyxM=; b=r7TT1H/GAWkW6CergW8RMQYjgfYmykn1LFwN/qzVHN7+6vOKAUBJ1M9ZdnKiSsrn/4 jnNIDckxeAovQ588ZZWGjggi40N21C7ddeo/beS3zNduXGDUAWvhHL0L86+n9+csD6f3 YtBbbVOKqOcWhXHuN1c5CQlgghLuHvjldnjvV8TnlWGmdzYz6LJBGZavVJ5mA1iwsC+f 2I0Huclih/+V0mW97WDiw0y8E0ATKeoAlvsbNpfGQWCCbY0ILtxIUJXT6y2d2zAI6s9k qKIl8r/pI0sTPGphO1RaKoqmXj/N6O5+XdVCchV404PlF+zPiIV+5OjSa/7YH1jDO35C FIBQ== X-Gm-Message-State: AMke39mC4UaOHmXp8fVt9ECdQIVDz/7frVO/J2dsF7tH5BkR33EIZlHF0KCBWROqaO3UBg== X-Received: by 10.99.94.198 with SMTP id s189mr35665918pgb.211.1487120097299; Tue, 14 Feb 2017 16:54:57 -0800 (PST) Received: from localhost (dhcp-39-103.EECS.Berkeley.EDU. [128.32.39.103]) by smtp.gmail.com with ESMTPSA id n70sm3387107pfg.34.2017.02.14.16.54.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Feb 2017 16:54:56 -0800 (PST) From: Palmer Dabbelt To: binutils@sourceware.org To: Tristan Gingold Cc: Andrew Waterman Cc: Andrew Waterman Subject: [PATCH] Add SFENCE.VMA instruction Date: Wed, 15 Feb 2017 00:55:00 -0000 Message-Id: <20170215005445.31615-2-palmer@dabbelt.com> In-Reply-To: <20170215005445.31615-1-palmer@dabbelt.com> References: <20170215005445.31615-1-palmer@dabbelt.com> X-IsSubscribed: yes X-SW-Source: 2017-02/txt/msg00105.txt.bz2 From: Andrew Waterman include/ChangeLog: 2017-02-14 Andrew Waterman * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define. (MASK_SFENCE_VMA): Likewise. (sfence_vma): Declare instruction. opcodes/ChangeLog: 2017-02-14 Andrew Waterman * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and pseudoinstructions. --- include/ChangeLog | 6 ++++++ include/opcode/riscv-opc.h | 3 +++ opcodes/ChangeLog | 5 +++++ opcodes/riscv-opc.c | 3 +++ 4 files changed, 17 insertions(+) diff --git a/include/ChangeLog b/include/ChangeLog index 6a61d61..df14aca 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,9 @@ +2017-02-14 Andrew Waterman + + * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define. + (MASK_SFENCE_VMA): Likewise. + (sfence_vma): Declare instruction. + 2017-01-02 Alan Modra Update year range in copyright notice of all files. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index d10c7f8..cef2f3c 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -227,6 +227,8 @@ #define MASK_DRET 0xffffffff #define MATCH_SFENCE_VM 0x10400073 #define MASK_SFENCE_VM 0xfff07fff +#define MATCH_SFENCE_VMA 0x12000073 +#define MASK_SFENCE_VMA 0xfe007fff #define MATCH_WFI 0x10500073 #define MASK_WFI 0xffffffff #define MATCH_CSRRW 0x1073 @@ -815,6 +817,7 @@ DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index d096ce1..04822ad 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2017-02-14 Andrew Waterman + + * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and + pseudoinstructions. + 2017-02-11 Stafford Horne Alan Modra diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 0a6f36f..867a026 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -618,6 +618,9 @@ const struct riscv_opcode riscv_opcodes[] = {"dret", "I", "", MATCH_DRET, MASK_DRET, match_opcode, 0 }, {"sfence.vm", "I", "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 }, {"sfence.vm", "I", "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 }, +{"sfence.vma","I", "", MATCH_SFENCE_VMA, MASK_SFENCE_VMA | MASK_RS1 | MASK_RS2, match_opcode, INSN_ALIAS }, +{"sfence.vma","I", "s", MATCH_SFENCE_VMA, MASK_SFENCE_VMA | MASK_RS2, match_opcode, INSN_ALIAS }, +{"sfence.vma","I", "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 }, {"wfi", "I", "", MATCH_WFI, MASK_WFI, match_opcode, 0 }, /* Terminate the list. */ -- 2.10.2