From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 104924 invoked by alias); 24 Feb 2017 17:43:48 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 104812 invoked by uid 89); 24 Feb 2017 17:43:46 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.1 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_SPAM,SPF_PASS autolearn=ham version=3.3.2 spammy=HTo:U*andrew X-HELO: mail-pg0-f68.google.com Received: from mail-pg0-f68.google.com (HELO mail-pg0-f68.google.com) (74.125.83.68) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 24 Feb 2017 17:43:45 +0000 Received: by mail-pg0-f68.google.com with SMTP id z128so3766950pgb.3 for ; Fri, 24 Feb 2017 09:43:45 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:to:to:cc:subject:date:message-id :in-reply-to:references; bh=hB5QvKvjbDvaBTR8NNkV7knE/6Yz+hy+8o7mPp9NyxM=; b=eOYqTdNsQhx5SqVpqX+EDqn0fR6gFoAlDB7D9SmSbT4vJLaDhNx9DC2vLuYAAIhe9R qnDGCk2bzAR5Lb4KZ8l+XE93dzx6ZR5nNWU/ID9ceiI4+d4SU7PR3FQZcm+t3nBw2p6f joQwsdeaXwKNamMt/Cf6qki3bj/TkepaMenAVaYlg2WPXUI9WZGC3a9S8cYYHZOF8IhA 9VBsn+mkzrAAkncoCR2YlsIwQkamhM+3+PDKTklxa1UUxJAZFh505MyR8qQEta2bTR8r LYLyCv1ZZF2C9XRQsFdh08uMWb3+K85OIKZRi7jQxJCZ7VMRsfTLFj9U8AJbIy1eq9BY ngZg== X-Gm-Message-State: AMke39mZLR6/iIOu5STGeXc/TWcBYRUMf3fdFkHaClota0+cxXoAMzxYikPJ/PJ04Ts5Lg== X-Received: by 10.84.143.1 with SMTP id 1mr5360462ply.81.1487958224523; Fri, 24 Feb 2017 09:43:44 -0800 (PST) Received: from localhost (c-73-222-189-110.hsd1.ca.comcast.net. [73.222.189.110]) by smtp.gmail.com with ESMTPSA id w16sm16346261pgc.15.2017.02.24.09.43.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Feb 2017 09:43:44 -0800 (PST) From: Palmer Dabbelt To: Tristan Gingold To: binutils@sourceware.org To: Andrew Waterman Cc: Andrew Waterman Subject: [PATCH 1/3] Add SFENCE.VMA instruction Date: Fri, 24 Feb 2017 17:43:00 -0000 Message-Id: <20170224174232.13170-2-palmer@dabbelt.com> In-Reply-To: <20170224174232.13170-1-palmer@dabbelt.com> References: <20170224174232.13170-1-palmer@dabbelt.com> X-IsSubscribed: yes X-SW-Source: 2017-02/txt/msg00351.txt.bz2 From: Andrew Waterman include/ChangeLog: 2017-02-14 Andrew Waterman * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define. (MASK_SFENCE_VMA): Likewise. (sfence_vma): Declare instruction. opcodes/ChangeLog: 2017-02-14 Andrew Waterman * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and pseudoinstructions. --- include/ChangeLog | 6 ++++++ include/opcode/riscv-opc.h | 3 +++ opcodes/ChangeLog | 5 +++++ opcodes/riscv-opc.c | 3 +++ 4 files changed, 17 insertions(+) diff --git a/include/ChangeLog b/include/ChangeLog index 6a61d61..df14aca 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,9 @@ +2017-02-14 Andrew Waterman + + * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define. + (MASK_SFENCE_VMA): Likewise. + (sfence_vma): Declare instruction. + 2017-01-02 Alan Modra Update year range in copyright notice of all files. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index d10c7f8..cef2f3c 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -227,6 +227,8 @@ #define MASK_DRET 0xffffffff #define MATCH_SFENCE_VM 0x10400073 #define MASK_SFENCE_VM 0xfff07fff +#define MATCH_SFENCE_VMA 0x12000073 +#define MASK_SFENCE_VMA 0xfe007fff #define MATCH_WFI 0x10500073 #define MASK_WFI 0xffffffff #define MATCH_CSRRW 0x1073 @@ -815,6 +817,7 @@ DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index d096ce1..04822ad 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2017-02-14 Andrew Waterman + + * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and + pseudoinstructions. + 2017-02-11 Stafford Horne Alan Modra diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 0a6f36f..867a026 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -618,6 +618,9 @@ const struct riscv_opcode riscv_opcodes[] = {"dret", "I", "", MATCH_DRET, MASK_DRET, match_opcode, 0 }, {"sfence.vm", "I", "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 }, {"sfence.vm", "I", "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 }, +{"sfence.vma","I", "", MATCH_SFENCE_VMA, MASK_SFENCE_VMA | MASK_RS1 | MASK_RS2, match_opcode, INSN_ALIAS }, +{"sfence.vma","I", "s", MATCH_SFENCE_VMA, MASK_SFENCE_VMA | MASK_RS2, match_opcode, INSN_ALIAS }, +{"sfence.vma","I", "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 }, {"wfi", "I", "", MATCH_WFI, MASK_WFI, match_opcode, 0 }, /* Terminate the list. */ -- 2.10.2