From: Palmer Dabbelt <palmer@dabbelt.com>
To: Tristan Gingold <gingold@adacore.com>
To: binutils@sourceware.org
To: Andrew Waterman <andrew@sifive.com>
Cc: Andrew Waterman <andrew@sifive.com>
Subject: [PATCH 2/3] Add new counter-enable CSRs
Date: Fri, 24 Feb 2017 17:43:00 -0000 [thread overview]
Message-ID: <20170224174232.13170-3-palmer@dabbelt.com> (raw)
In-Reply-To: <20170224174232.13170-1-palmer@dabbelt.com>
From: Andrew Waterman <andrew@sifive.com>
include/ChangeLog:
2017-02-22 Andrew Waterman <andrew@sifive.com>
* opcode/riscv-opc.h (CSR_SCOUNTEREN): New define.
(CSR_MCOUNTEREN): Likewise.
(scounteren): Declare register.
(mcounteren): Likewise.
---
include/ChangeLog | 7 +++++++
include/opcode/riscv-opc.h | 4 ++++
2 files changed, 11 insertions(+)
diff --git a/include/ChangeLog b/include/ChangeLog
index df14aca..cd89358 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,10 @@
+2017-02-22 Andrew Waterman <andrew@sifive.com>
+
+ * opcode/riscv-opc.h (CSR_SCOUNTEREN): New define.
+ (CSR_MCOUNTEREN): Likewise.
+ (scounteren): Declare register.
+ (mcounteren): Likewise.
+
2017-02-14 Andrew Waterman <andrew@sifive.com>
* opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define.
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index cef2f3c..9269c6b 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -537,6 +537,7 @@
#define CSR_SSTATUS 0x100
#define CSR_SIE 0x104
#define CSR_STVEC 0x105
+#define CSR_SCOUNTEREN 0x106
#define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141
#define CSR_SCAUSE 0x142
@@ -549,6 +550,7 @@
#define CSR_MIDELEG 0x303
#define CSR_MIE 0x304
#define CSR_MTVEC 0x305
+#define CSR_MCOUNTEREN 0x306
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
@@ -993,6 +995,7 @@ DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
DECLARE_CSR(sstatus, CSR_SSTATUS)
DECLARE_CSR(sie, CSR_SIE)
DECLARE_CSR(stvec, CSR_STVEC)
+DECLARE_CSR(scounteren, CSR_SCOUNTEREN)
DECLARE_CSR(sscratch, CSR_SSCRATCH)
DECLARE_CSR(sepc, CSR_SEPC)
DECLARE_CSR(scause, CSR_SCAUSE)
@@ -1005,6 +1008,7 @@ DECLARE_CSR(medeleg, CSR_MEDELEG)
DECLARE_CSR(mideleg, CSR_MIDELEG)
DECLARE_CSR(mie, CSR_MIE)
DECLARE_CSR(mtvec, CSR_MTVEC)
+DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
DECLARE_CSR(mscratch, CSR_MSCRATCH)
DECLARE_CSR(mepc, CSR_MEPC)
DECLARE_CSR(mcause, CSR_MCAUSE)
--
2.10.2
next prev parent reply other threads:[~2017-02-24 17:43 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-24 17:43 binutils-2_28-branch: Various RISC-V Fixes Palmer Dabbelt
2017-02-24 17:43 ` Palmer Dabbelt [this message]
2017-02-24 17:43 ` [PATCH 1/3] Add SFENCE.VMA instruction Palmer Dabbelt
2017-02-24 17:43 ` [PATCH 3/3] bfd: RISC-V: relax to gp in more cases Palmer Dabbelt
2017-02-27 10:21 ` binutils-2_28-branch: Various RISC-V Fixes Tristan Gingold
2017-02-27 17:47 ` Palmer Dabbelt
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