* [PATCH 6/7] RISC-V: Fix assembler for c.li, c.andi and c.addiw
2017-03-22 23:04 binutils-2_28-branch: Assorted RISC-V Fixes Palmer Dabbelt
@ 2017-03-22 23:04 ` Palmer Dabbelt
2017-03-22 23:04 ` [PATCH 5/7] RISC-V: Fix assembler for c.addi, rd can be x0 Palmer Dabbelt
` (6 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Palmer Dabbelt @ 2017-03-22 23:04 UTC (permalink / raw)
To: binutils, Tristan Gingold; +Cc: Kito Cheng
From: Kito Cheng <kito.cheng@gmail.com>
- They can accept 0 in imm field
2017-03-14 Kito Cheng <kito.cheng@gmail.com>
* riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
<c.andi>: Likewise.
<c.addiw> Likewise.
---
gas/ChangeLog | 6 ++++++
gas/config/tc-riscv.c | 8 ++++++++
opcodes/ChangeLog | 6 ++++++
opcodes/riscv-opc.c | 6 +++---
4 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index b6ad1ee..f680ac6 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2017-03-14 Kito Cheng <kito.cheng@gmail.com>
+
+ * config/tc-riscv.c (validate_riscv_insn): Add 'o' RVC immediate
+ encoding format, which can accept 0-valued immediates.
+ (riscv_ip): Likewise.
+
2017-03-02 Kuan-Lin Chen <rufus@andestech.com>
* config/tc-riscv.h (HWARD2_USE_FIXED_ADVANCE_PC): New define.
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 4d28042..429ba2b 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -500,6 +500,7 @@ validate_riscv_insn (const struct riscv_opcode *opc)
case 'c': break; /* RS1, constrained to equal sp */
case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break;
+ case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break;
case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break;
case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break;
case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break;
@@ -1321,6 +1322,13 @@ rvc_imm_done:
ip->insn_opcode |=
ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number);
goto rvc_imm_done;
+ case 'o':
+ if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
+ || imm_expr->X_op != O_constant
+ || !VALID_RVC_IMM (imm_expr->X_add_number))
+ break;
+ ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
+ goto rvc_imm_done;
case 'K':
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|| imm_expr->X_op != O_constant
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 83f2cc1..8f7e44c 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,11 @@
2017-03-14 Kito Cheng <kito.cheng@gmail.com>
+ * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
+ <c.andi>: Likewise.
+ <c.addiw> Likewise.
+
+2017-03-14 Kito Cheng <kito.cheng@gmail.com>
+
* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
2017-03-13 Andrew Waterman <andrew@sifive.com>
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index edbf2f6..2b18a1e 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -562,7 +562,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"c.nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, 0 },
{"c.mv", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, 0 },
{"c.lui", "C", "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, 0 },
-{"c.li", "C", "d,Cj", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 },
+{"c.li", "C", "d,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 },
{"c.addi4spn","C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, 0 },
{"c.addi16sp","C", "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, 0 },
{"c.addi", "C", "d,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_opcode, 0 },
@@ -574,8 +574,8 @@ const struct riscv_opcode riscv_opcodes[] =
{"c.slli", "C", "d,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, 0 },
{"c.srli", "C", "Cs,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, 0 },
{"c.srai", "C", "Cs,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, 0 },
-{"c.andi", "C", "Cs,Cj", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 },
-{"c.addiw", "64C", "d,Cj", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 },
+{"c.andi", "C", "Cs,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 },
+{"c.addiw", "64C", "d,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 },
{"c.addw", "64C", "Cs,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 },
{"c.subw", "64C", "Cs,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, 0 },
{"c.ldsp", "64C", "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, 0 },
--
2.10.2
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 5/7] RISC-V: Fix assembler for c.addi, rd can be x0
2017-03-22 23:04 binutils-2_28-branch: Assorted RISC-V Fixes Palmer Dabbelt
2017-03-22 23:04 ` [PATCH 6/7] RISC-V: Fix assembler for c.li, c.andi and c.addiw Palmer Dabbelt
@ 2017-03-22 23:04 ` Palmer Dabbelt
2017-03-22 23:04 ` [PATCH 7/7] Sanitize RISC-V GAS help text, documentation Palmer Dabbelt
` (5 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Palmer Dabbelt @ 2017-03-22 23:04 UTC (permalink / raw)
To: binutils, Tristan Gingold; +Cc: Kito Cheng
From: Kito Cheng <kito.cheng@gmail.com>
opcodes/ChangeLog:
2017-03-14 Kito Cheng <kito.cheng@gmail.com>
* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
---
opcodes/ChangeLog | 4 ++++
opcodes/riscv-opc.c | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 969129b..83f2cc1 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2017-03-14 Kito Cheng <kito.cheng@gmail.com>
+
+ * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
+
2017-03-13 Andrew Waterman <andrew@sifive.com>
* riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index da33600..edbf2f6 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -565,7 +565,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"c.li", "C", "d,Cj", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 },
{"c.addi4spn","C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, 0 },
{"c.addi16sp","C", "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, 0 },
-{"c.addi", "C", "d,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, 0 },
+{"c.addi", "C", "d,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_opcode, 0 },
{"c.add", "C", "d,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, 0 },
{"c.sub", "C", "Cs,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 },
{"c.and", "C", "Cs,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, 0 },
--
2.10.2
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 7/7] Sanitize RISC-V GAS help text, documentation
2017-03-22 23:04 binutils-2_28-branch: Assorted RISC-V Fixes Palmer Dabbelt
2017-03-22 23:04 ` [PATCH 6/7] RISC-V: Fix assembler for c.li, c.andi and c.addiw Palmer Dabbelt
2017-03-22 23:04 ` [PATCH 5/7] RISC-V: Fix assembler for c.addi, rd can be x0 Palmer Dabbelt
@ 2017-03-22 23:04 ` Palmer Dabbelt
2017-03-22 23:04 ` [PATCH 2/7] RISC-V: Fix the offset of CFA relocation Palmer Dabbelt
` (4 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Palmer Dabbelt @ 2017-03-22 23:04 UTC (permalink / raw)
To: binutils, Tristan Gingold; +Cc: Palmer Dabbelt
It looks like I missed the GAS help text when going through all the
documentation last time, so it printed some of the old-format (never
upstream) arguments. I fixed this, and when I went to check doc/ I
noticed it was missing the '-fpic'/'-fno-pic' options.
---
gas/ChangeLog | 7 +++++++
gas/config/tc-riscv.c | 9 ++-------
gas/doc/c-riscv.texi | 8 ++++++++
3 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index f680ac6..1e45510 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2017-03-21 Palmer Dabbbelt <palmer@dabbelt.com>
+
+ * config/tc-riscv.c (md_show_usage): Remode defuct -m32, -m64,
+ -msoft-float, -mhard-float, -mno-rvc, and -mrvc options; and don't
+ print an invalid default ISA string.
+ * doc/c-riscv.texi (OPTIONS): Add -fpic and -fno-pic options.
+
2017-03-14 Kito Cheng <kito.cheng@gmail.com>
* config/tc-riscv.c (validate_riscv_insn): Add 'o' RVC immediate
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 429ba2b..649c3e8 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2465,15 +2465,10 @@ md_show_usage (FILE *stream)
{
fprintf (stream, _("\
RISC-V options:\n\
- -m32 assemble RV32 code\n\
- -m64 assemble RV64 code (default)\n\
-fpic generate position-independent code\n\
-fno-pic don't generate position-independent code (default)\n\
- -msoft-float don't use F registers for floating-point values\n\
- -mhard-float use F registers for floating-point values (default)\n\
- -mno-rvc disable the C extension for compressed instructions (default)\n\
- -mrvc enable the C extension for compressed instructions\n\
- -march=ISA set the RISC-V architecture, RV64IMAFD by default\n\
+ -march=ISA set the RISC-V architecture\n\
+ -mabi=ABI set the RISC-V ABI\n\
"));
}
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 0fa1b58..2efba4b 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -26,6 +26,14 @@ The following table lists all availiable RISC-V specific options
@c man begin OPTIONS
@table @gcctabopt
+@cindex @samp{-fpic} option, RISC-V
+@item -fpic
+Generate position-independent code
+
+@cindex @samp{-fno-pic} option, RISC-V
+@item -fno-pic
+Don't generate position-independent code (default)
+
@cindex @samp{-march=ISA} option, RISC-V
@item -march=ISA
Select the base isa, as specified by ISA. For example -march=rv32ima.
--
2.10.2
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 2/7] RISC-V: Fix the offset of CFA relocation.
2017-03-22 23:04 binutils-2_28-branch: Assorted RISC-V Fixes Palmer Dabbelt
` (2 preceding siblings ...)
2017-03-22 23:04 ` [PATCH 7/7] Sanitize RISC-V GAS help text, documentation Palmer Dabbelt
@ 2017-03-22 23:04 ` Palmer Dabbelt
2017-03-22 23:04 ` [PATCH 4/7] RISC-V: Define DWARF2_USE_FIXED_ADVANCE_PC Palmer Dabbelt
` (3 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Palmer Dabbelt @ 2017-03-22 23:04 UTC (permalink / raw)
To: binutils, Tristan Gingold; +Cc: Kuan-Lin Chen
From: Kuan-Lin Chen <rufus@andestech.com>
gas/ChangeLog:
2017-03-02 Kuan-Lin Chen <rufus@andestech.com>
* config/tc-riscv.c (md_apply_fix): Compute the correct offsets
for CFA relocations.
---
gas/ChangeLog | 5 +++++
gas/config/tc-riscv.c | 20 ++++++++++----------
2 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index d59472a..7639ec7 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2017-03-02 Kuan-Lin Chen <rufus@andestech.com>
+
+ * config/tc-riscv.c (md_apply_fix): Compute the correct offsets
+ for CFA relocations.
+
2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
Backport from mainline
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index ec5b0bb..c79f313 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1837,6 +1837,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
unsigned int subtype;
bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
bfd_boolean relaxable = FALSE;
+ offsetT loc;
/* Remember value for tc_gen_reloc. */
fixP->fx_addnumber = *valP;
@@ -1922,30 +1923,31 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
case BFD_RELOC_RISCV_CFA:
/* Load the byte to get the subtype. */
- subtype = bfd_get_8 (NULL, &fixP->fx_frag->fr_literal[fixP->fx_where]);
+ subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]);
+ loc = fixP->fx_frag->fr_fix - (subtype & 7);
switch (subtype)
{
case DW_CFA_advance_loc1:
- fixP->fx_where++;
- fixP->fx_next->fx_where++;
+ fixP->fx_where = loc + 1;
+ fixP->fx_next->fx_where = loc + 1;
fixP->fx_r_type = BFD_RELOC_RISCV_SET8;
fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
break;
case DW_CFA_advance_loc2:
fixP->fx_size = 2;
- fixP->fx_where++;
fixP->fx_next->fx_size = 2;
- fixP->fx_next->fx_where++;
+ fixP->fx_where = loc + 1;
+ fixP->fx_next->fx_where = loc + 1;
fixP->fx_r_type = BFD_RELOC_RISCV_SET16;
fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
break;
case DW_CFA_advance_loc4:
fixP->fx_size = 4;
- fixP->fx_where++;
fixP->fx_next->fx_size = 4;
- fixP->fx_next->fx_where++;
+ fixP->fx_where = loc;
+ fixP->fx_next->fx_where = loc;
fixP->fx_r_type = BFD_RELOC_RISCV_SET32;
fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
break;
@@ -2069,7 +2071,6 @@ riscv_pre_output_hook (void)
{
if (frag->fr_type == rs_cfa)
{
- fragS *loc4_frag;
expressionS exp;
symbolS *add_symbol = frag->fr_symbol->sy_value.X_add_symbol;
@@ -2080,8 +2081,7 @@ riscv_pre_output_hook (void)
exp.X_add_number = 0;
exp.X_op_symbol = op_symbol;
- loc4_frag = (fragS *) frag->fr_opcode;
- fix_new_exp (loc4_frag, (int) frag->fr_offset, 1, &exp, 0,
+ fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0,
BFD_RELOC_RISCV_CFA);
}
}
--
2.10.2
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 4/7] RISC-V: Define DWARF2_USE_FIXED_ADVANCE_PC.
2017-03-22 23:04 binutils-2_28-branch: Assorted RISC-V Fixes Palmer Dabbelt
` (3 preceding siblings ...)
2017-03-22 23:04 ` [PATCH 2/7] RISC-V: Fix the offset of CFA relocation Palmer Dabbelt
@ 2017-03-22 23:04 ` Palmer Dabbelt
2017-03-22 23:04 ` [PATCH 3/7] RISC-V: Fix DW_CFA_advance_loc relocation Palmer Dabbelt
` (2 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Palmer Dabbelt @ 2017-03-22 23:04 UTC (permalink / raw)
To: binutils, Tristan Gingold; +Cc: Kuan-Lin Chen
From: Kuan-Lin Chen <rufus@andestech.com>
gas/ChangeLog
2017-03-02 Kuan-Lin Chen <rufus@andestech.com>
* config/tc-riscv.h (HWARD2_USE_FIXED_ADVANCE_PC): New define.
---
gas/ChangeLog | 4 ++++
gas/config/tc-riscv.h | 3 +++
2 files changed, 7 insertions(+)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 0e80a25..b6ad1ee 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,9 @@
2017-03-02 Kuan-Lin Chen <rufus@andestech.com>
+ * config/tc-riscv.h (HWARD2_USE_FIXED_ADVANCE_PC): New define.
+
+2017-03-02 Kuan-Lin Chen <rufus@andestech.com>
+
* config/tc-riscv.c (md_apply_fix): Set fx_frag and
fx_next->fx_frag for CFA_advance_loc relocations.
diff --git a/gas/config/tc-riscv.h b/gas/config/tc-riscv.h
index ae8d60e..e92b387 100644
--- a/gas/config/tc-riscv.h
+++ b/gas/config/tc-riscv.h
@@ -112,4 +112,7 @@ extern int tc_riscv_regname_to_dw2regnum (char *);
#define elf_tc_final_processing riscv_elf_final_processing
extern void riscv_elf_final_processing (void);
+/* Adjust debug_line after relaxation. */
+#define DWARF2_USE_FIXED_ADVANCE_PC 1
+
#endif /* TC_RISCV */
--
2.10.2
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 3/7] RISC-V: Fix DW_CFA_advance_loc relocation.
2017-03-22 23:04 binutils-2_28-branch: Assorted RISC-V Fixes Palmer Dabbelt
` (4 preceding siblings ...)
2017-03-22 23:04 ` [PATCH 4/7] RISC-V: Define DWARF2_USE_FIXED_ADVANCE_PC Palmer Dabbelt
@ 2017-03-22 23:04 ` Palmer Dabbelt
2017-03-22 23:04 ` [PATCH 1/7] RISC-V: Fix [dis]assembly of srai/srli Palmer Dabbelt
2017-03-23 10:53 ` binutils-2_28-branch: Assorted RISC-V Fixes gingold
7 siblings, 0 replies; 10+ messages in thread
From: Palmer Dabbelt @ 2017-03-22 23:04 UTC (permalink / raw)
To: binutils, Tristan Gingold; +Cc: Kuan-Lin Chen
From: Kuan-Lin Chen <rufus@andestech.com>
gas/ChangeLog:
2017-03-02 Kuan-Lin Chen <rufus@andestech.com>
* config/tc-riscv.c (md_apply_fix): Set fx_frag and
fx_next->fx_frag for CFA_advance_loc relocations.
---
gas/ChangeLog | 5 +++++
gas/config/tc-riscv.c | 2 ++
2 files changed, 7 insertions(+)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 7639ec7..0e80a25 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,10 @@
2017-03-02 Kuan-Lin Chen <rufus@andestech.com>
+ * config/tc-riscv.c (md_apply_fix): Set fx_frag and
+ fx_next->fx_frag for CFA_advance_loc relocations.
+
+2017-03-02 Kuan-Lin Chen <rufus@andestech.com>
+
* config/tc-riscv.c (md_apply_fix): Compute the correct offsets
for CFA relocations.
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index c79f313..4d28042 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1956,6 +1956,8 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
if (subtype < 0x80 && (subtype & 0x40))
{
/* DW_CFA_advance_loc */
+ fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode;
+ fixP->fx_next->fx_frag = fixP->fx_frag;
fixP->fx_r_type = BFD_RELOC_RISCV_SET6;
fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6;
}
--
2.10.2
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 1/7] RISC-V: Fix [dis]assembly of srai/srli
2017-03-22 23:04 binutils-2_28-branch: Assorted RISC-V Fixes Palmer Dabbelt
` (5 preceding siblings ...)
2017-03-22 23:04 ` [PATCH 3/7] RISC-V: Fix DW_CFA_advance_loc relocation Palmer Dabbelt
@ 2017-03-22 23:04 ` Palmer Dabbelt
2017-03-23 10:53 ` binutils-2_28-branch: Assorted RISC-V Fixes gingold
7 siblings, 0 replies; 10+ messages in thread
From: Palmer Dabbelt @ 2017-03-22 23:04 UTC (permalink / raw)
To: binutils, Tristan Gingold; +Cc: Andrew Waterman
From: Andrew Waterman <andrew@sifive.com>
These were simple copy/paste errors from the compressed left shift
pattern, which can't have a 0-register.
---
opcodes/ChangeLog | 7 +++++++
opcodes/riscv-opc.c | 8 ++++----
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index bdc6266..969129b 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2017-03-13 Andrew Waterman <andrew@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
+ <srl> Likewise.
+ <srai> Likewise.
+ <sra> Likewise.
+
2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
Backport from mainline
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 867a026..da33600 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -210,14 +210,14 @@ const struct riscv_opcode riscv_opcodes[] =
{"sll", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS },
{"sll", "I", "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, 0 },
{"sll", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS },
-{"srli", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS },
+{"srli", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, INSN_ALIAS },
{"srli", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, 0 },
-{"srl", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS },
+{"srl", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, INSN_ALIAS },
{"srl", "I", "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, 0 },
{"srl", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS },
-{"srai", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS },
+{"srai", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, INSN_ALIAS },
{"srai", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, 0 },
-{"sra", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS },
+{"sra", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, INSN_ALIAS },
{"sra", "I", "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, 0 },
{"sra", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS },
{"sub", "C", "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS },
--
2.10.2
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: binutils-2_28-branch: Assorted RISC-V Fixes
2017-03-22 23:04 binutils-2_28-branch: Assorted RISC-V Fixes Palmer Dabbelt
` (6 preceding siblings ...)
2017-03-22 23:04 ` [PATCH 1/7] RISC-V: Fix [dis]assembly of srai/srli Palmer Dabbelt
@ 2017-03-23 10:53 ` gingold
2017-03-30 20:01 ` Palmer Dabbelt
7 siblings, 1 reply; 10+ messages in thread
From: gingold @ 2017-03-23 10:53 UTC (permalink / raw)
To: Palmer Dabbelt, binutils
On 23/03/2017 00:04, Palmer Dabbelt wrote:
> Since 2.28 was released a few fixes have landed on master that I think are sane
> for the 2.28 branch. The patches have better descriptions, but they are:
>
> * Fixes to allow assembly of a half dozen or so compressed instructions.
> * Debug info relocation fixes.
> * Help text/documentation.
>
> Are these OK for the 2.28 branch?
Yes, that's fine.
>
> [PATCH 1/7] RISC-V: Fix [dis]assembly of srai/srli
> [PATCH 2/7] RISC-V: Fix the offset of CFA relocation.
> [PATCH 3/7] RISC-V: Fix DW_CFA_advance_loc relocation.
> [PATCH 4/7] RISC-V: Define DWARF2_USE_FIXED_ADVANCE_PC.
> [PATCH 5/7] RISC-V: Fix assembler for c.addi, rd can be x0
> [PATCH 6/7] RISC-V: Fix assembler for c.li, c.andi and c.addiw
> [PATCH 7/7] Sanitize RISC-V GAS help text, documentation
>
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: binutils-2_28-branch: Assorted RISC-V Fixes
2017-03-23 10:53 ` binutils-2_28-branch: Assorted RISC-V Fixes gingold
@ 2017-03-30 20:01 ` Palmer Dabbelt
0 siblings, 0 replies; 10+ messages in thread
From: Palmer Dabbelt @ 2017-03-30 20:01 UTC (permalink / raw)
To: Tristan Gingold; +Cc: binutils
On Thu, 23 Mar 2017 03:53:51 PDT (-0700), Tristan Gingold wrote:
> On 23/03/2017 00:04, Palmer Dabbelt wrote:
>> Since 2.28 was released a few fixes have landed on master that I think are sane
>> for the 2.28 branch. The patches have better descriptions, but they are:
>>
>> * Fixes to allow assembly of a half dozen or so compressed instructions.
>> * Debug info relocation fixes.
>> * Help text/documentation.
>>
>> Are these OK for the 2.28 branch?
>
> Yes, that's fine.
Thanks, committed.
^ permalink raw reply [flat|nested] 10+ messages in thread