From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 48321 invoked by alias); 22 Mar 2017 23:04:39 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 48151 invoked by uid 89); 22 Mar 2017 23:04:38 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.5 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_SPAM,SPF_PASS autolearn=ham version=3.3.2 spammy=dC, sk:validat, constrained X-HELO: mail-pg0-f68.google.com Received: from mail-pg0-f68.google.com (HELO mail-pg0-f68.google.com) (74.125.83.68) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 22 Mar 2017 23:04:35 +0000 Received: by mail-pg0-f68.google.com with SMTP id w20so7918469pgc.1 for ; Wed, 22 Mar 2017 16:04:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:to:cc:subject:date:message-id :in-reply-to:references; bh=ZfUeFr00CZON8Eh9kNrdrsnuOOzyb9G6OuWK0X8rLoY=; b=SqH/oyZuzbWEIfYFaLXwG2dGRJHBO05t4mcS1UUT34+ohKOOj5QyXyI1Fejs586n6M vLPdZ01vrD5iw1rc0zCe2YqUFDwHYrQgObrMWCPhXtL+aryyddK3tsHYZi6qA3uOT0Ga t2f0Mh9QmFPKavBFNBVCI+BWxGhONzOROByFLIYSwUjdYAjTWV5y2amG7YNT4maPCHTt 7pjeYPXyqdZjBJJTxMOWsUH/jsSjneG7VC3CO63LvInX7mN9+g0VzofdvdVsRsordkGY 9LkszkhdgN3zkcHb1X7Q2LqJhTjeVNBk67QyvxllZNIh0zP81IkerItin5C5by112/55 Fv3Q== X-Gm-Message-State: AFeK/H2azJlZX2llnU2lkW5i0pZsZQbVWl06KWUJSbT5j+j6xiIK81RbETcfPVE0JM84ZA== X-Received: by 10.84.230.135 with SMTP id e7mr4116685plk.20.1490223874626; Wed, 22 Mar 2017 16:04:34 -0700 (PDT) Received: from localhost ([216.38.154.21]) by smtp.gmail.com with ESMTPSA id n185sm5939671pga.9.2017.03.22.16.04.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 22 Mar 2017 16:04:33 -0700 (PDT) From: Palmer Dabbelt To: binutils@sourceware.org To: Tristan Gingold Cc: Kito Cheng Subject: [PATCH 6/7] RISC-V: Fix assembler for c.li, c.andi and c.addiw Date: Wed, 22 Mar 2017 23:04:00 -0000 Message-Id: <20170322230408.8885-7-palmer@dabbelt.com> In-Reply-To: <20170322230408.8885-1-palmer@dabbelt.com> References: <20170322230408.8885-1-palmer@dabbelt.com> X-IsSubscribed: yes X-SW-Source: 2017-03/txt/msg00312.txt.bz2 From: Kito Cheng - They can accept 0 in imm field 2017-03-14 Kito Cheng * riscv-opc.c (riscv_opcodes> : Use the 'o' immediate encoding. : Likewise. Likewise. --- gas/ChangeLog | 6 ++++++ gas/config/tc-riscv.c | 8 ++++++++ opcodes/ChangeLog | 6 ++++++ opcodes/riscv-opc.c | 6 +++--- 4 files changed, 23 insertions(+), 3 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index b6ad1ee..f680ac6 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2017-03-14 Kito Cheng + + * config/tc-riscv.c (validate_riscv_insn): Add 'o' RVC immediate + encoding format, which can accept 0-valued immediates. + (riscv_ip): Likewise. + 2017-03-02 Kuan-Lin Chen * config/tc-riscv.h (HWARD2_USE_FIXED_ADVANCE_PC): New define. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 4d28042..429ba2b 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -500,6 +500,7 @@ validate_riscv_insn (const struct riscv_opcode *opc) case 'c': break; /* RS1, constrained to equal sp */ case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break; case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break; + case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break; case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break; case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break; case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break; @@ -1321,6 +1322,13 @@ rvc_imm_done: ip->insn_opcode |= ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number); goto rvc_imm_done; + case 'o': + if (my_getSmallExpression (imm_expr, imm_reloc, s, p) + || imm_expr->X_op != O_constant + || !VALID_RVC_IMM (imm_expr->X_add_number)) + break; + ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); + goto rvc_imm_done; case 'K': if (my_getSmallExpression (imm_expr, imm_reloc, s, p) || imm_expr->X_op != O_constant diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 83f2cc1..8f7e44c 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,11 @@ 2017-03-14 Kito Cheng + * riscv-opc.c (riscv_opcodes> : Use the 'o' immediate encoding. + : Likewise. + Likewise. + +2017-03-14 Kito Cheng + * riscv-opc.c (riscv_opcodes) : Use match_opcode. 2017-03-13 Andrew Waterman diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index edbf2f6..2b18a1e 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -562,7 +562,7 @@ const struct riscv_opcode riscv_opcodes[] = {"c.nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, 0 }, {"c.mv", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, 0 }, {"c.lui", "C", "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, 0 }, -{"c.li", "C", "d,Cj", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 }, +{"c.li", "C", "d,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 }, {"c.addi4spn","C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, 0 }, {"c.addi16sp","C", "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, 0 }, {"c.addi", "C", "d,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_opcode, 0 }, @@ -574,8 +574,8 @@ const struct riscv_opcode riscv_opcodes[] = {"c.slli", "C", "d,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, 0 }, {"c.srli", "C", "Cs,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, 0 }, {"c.srai", "C", "Cs,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, 0 }, -{"c.andi", "C", "Cs,Cj", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 }, -{"c.addiw", "64C", "d,Cj", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 }, +{"c.andi", "C", "Cs,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 }, +{"c.addiw", "64C", "d,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 }, {"c.addw", "64C", "Cs,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 }, {"c.subw", "64C", "Cs,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, 0 }, {"c.ldsp", "64C", "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, 0 }, -- 2.10.2