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From: Palmer Dabbelt <palmer@dabbelt.com>
To: binutils@sourceware.org
Cc: patches@groups.riscv.org
Cc: Michael Clark <michaeljclark@mac.com>
Subject: [PATCH] RISC-V: Change CALL macro to use ra as the temporary address register
Date: Mon, 01 May 2017 20:33:00 -0000	[thread overview]
Message-ID: <20170501203309.21781-1-palmer@dabbelt.com> (raw)

From: Michael Clark <michaeljclark@mac.com>

e.g.

    1:  auipc ra, %pcrel_hi(symbol)
        jalr  ra, %pcrel_lo(1b)(ra)

The use of ra instead of t1 for address construction provides an
opportunity for a microarchitecture to elide the write of the
destination address, and instead read the target address as an
immediate spread across the fused auipc+jalr pair. The link
register ra in the jalr overwrites the target address temporary.

2017-05-01  Michael Clark  <michaeljclark@mac.com>

	* riscv-opc.c (riscv_opcodes> <call>: Use RA not T1 as a temporary
	register.
---
 opcodes/ChangeLog   | 5 +++++
 opcodes/riscv-opc.c | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b9d67d2..6610242 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2017-05-01  Michael Clark  <michaeljclark@mac.com>
+
+	* riscv-opc.c (riscv_opcodes> <call>: Use RA not T1 as a temporary
+	register.
+
 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 
 	* arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index c629d2f..0188a65 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -147,7 +147,7 @@ const struct riscv_opcode riscv_opcodes[] =
 {"jal",       "32C", "Ca",  MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS },
 {"jal",       "I",   "a",  MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS },
 {"call",      "I",   "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL,  match_never, INSN_MACRO },
-{"call",      "I",   "c", (X_T1 << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL,  match_never, INSN_MACRO },
+{"call",      "I",   "c", (X_RA << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL,  match_never, INSN_MACRO },
 {"tail",      "I",   "c", (X_T1 << OP_SH_RS1), (int) M_CALL,  match_never, INSN_MACRO },
 {"jump",      "I",   "c,s", 0, (int) M_CALL,  match_never, INSN_MACRO },
 {"nop",       "C",   "",  MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS },
-- 
2.10.2

             reply	other threads:[~2017-05-01 20:33 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-01 20:33 Palmer Dabbelt [this message]
2017-05-01 20:37 ` Palmer Dabbelt
2017-05-02 15:36   ` Nick Clifton
2017-05-02 22:20     ` Palmer Dabbelt

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