From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12542 invoked by alias); 22 Feb 2018 12:20:09 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 12530 invoked by uid 89); 22 Feb 2018 12:20:08 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.8 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-pl0-f53.google.com Received: from mail-pl0-f53.google.com (HELO mail-pl0-f53.google.com) (209.85.160.53) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 22 Feb 2018 12:20:06 +0000 Received: by mail-pl0-f53.google.com with SMTP id w21so2767752plp.11 for ; Thu, 22 Feb 2018 04:20:06 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:mime-version :content-disposition:user-agent; bh=6w/ODCjWr5GueS89h8YVbnNFNAQlNAk/amyQv5pbh5Y=; b=C4O8wvm8sV1GzU0ADeQ1+y20XdTAAR9S1nLFkN+YB1Bey3Y2l4DiXl25TbOWtaMii0 irMqnbQ2siC1a2EjejnDOoPqzzqZO8murMwVwGdV6HgWm5G5rD9rcGGTMw7NdN6vGnmN qcbzG2fRP0fA633GC51hTMN8/ZsayGw7Q5JZpTG0DjEVSAhHmxsQr68S84zzfLliY/qP WxvaYNES8waOlUTD5DWC1ebqI7fujtNPr8pkYTvXehuAvVzhygBjB5E5bxyX2RTPG3/n VW+HXFR/XtM1lenufejqrzglwCttohDC7zISxz0EC1kDZAaephxRCm6OqnuAG3hhZyno 0pag== X-Gm-Message-State: APf1xPB/pZGXVNogCcZr/fxzA5sIIqh+anYqbMd6sYXA0dercZVQnWk8 s61mMxEW6zF25dY5ewAsP7w= X-Google-Smtp-Source: AH8x224Lea0r12bXghJh7FfBoxUPqBuGJIIvaqv4vG2baL5bCcGPkO0sD9W6ElcA1+sduWR5IjBUUg== X-Received: by 2002:a17:902:3303:: with SMTP id a3-v6mr6366087plc.399.1519302004697; Thu, 22 Feb 2018 04:20:04 -0800 (PST) Received: from gnu-tools-1.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id z125sm65961900pfz.27.2018.02.22.04.20.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 22 Feb 2018 04:20:04 -0800 (PST) Received: by gnu-tools-1.localdomain (Postfix, from userid 1000) id 1015622059; Thu, 22 Feb 2018 04:20:03 -0800 (PST) Date: Thu, 22 Feb 2018 12:20:00 -0000 From: "H.J. Lu" To: binutils@sourceware.org Cc: Linus Torvalds Subject: [PATCH] x86: Add {rex} pseudo prefix Message-ID: <20180222122003.GA10022@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.9.2 (2017-12-15) X-IsSubscribed: yes X-SW-Source: 2018-02/txt/msg00382.txt.bz2 Add {rex} pseudo prefix to generate a REX byte for integer and legacy vector instructions if possible. Any comments? H.J. --- gas/ * config/tc-i386.c (_i386_insn): Add rex_encoding. (md_assemble): When i.rex_encoding is true, generate a REX byte if possible. (parse_insn): Set i.rex_encoding for {rex}. * doc/c-i386.texi: Document {rex}. * testsuite/gas/i386/x86-64-pseudos.s: Add {rex} tests. * testsuite/gas/i386/x86-64-pseudos.d: Updated opcodes/ * i386-opc.tbl: Add {rex}, * i386-tbl.h: Regenerated. --- gas/config/tc-i386.c | 27 +++++++++++++++++++++++++++ gas/doc/c-i386.texi | 4 ++++ gas/testsuite/gas/i386/x86-64-pseudos.d | 26 ++++++++++++++++++++++++++ gas/testsuite/gas/i386/x86-64-pseudos.s | 26 ++++++++++++++++++++++++++ opcodes/i386-opc.tbl | 1 + opcodes/i386-tbl.h | 14 ++++++++++++++ 6 files changed, 98 insertions(+) diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index c67ea1f224..dff42bdb91 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -369,6 +369,9 @@ struct _i386_insn disp_encoding_32bit } disp_encoding; + /* Prefer the REX byte in encoding. */ + bfd_boolean rex_encoding; + /* How to encode vector instructions. */ enum { @@ -3992,6 +3995,26 @@ md_assemble (char *line) } } + if (i.rex == 0 && i.rex_encoding) + { + /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand + that uses legacy register. If it is "hi" register, don't add + the REX_OPCODE byte. */ + int x; + for (x = 0; x < 2; x++) + if (i.types[x].bitfield.reg + && i.types[x].bitfield.byte + && (i.op[x].regs->reg_flags & RegRex64) == 0 + && i.op[x].regs->reg_num > 3) + { + i.rex_encoding = FALSE; + break; + } + + if (i.rex_encoding) + i.rex = REX_OPCODE; + } + if (i.rex != 0) add_prefix (REX_OPCODE | i.rex); @@ -4104,6 +4127,10 @@ parse_insn (char *line, char *mnemonic) /* {evex} */ i.vec_encoding = vex_encoding_evex; break; + case 0x7: + /* {rex} */ + i.rex_encoding = TRUE; + break; default: abort (); } diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index e669c5f34f..dbbe61346c 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -642,6 +642,10 @@ Different encoding options can be specified via pseudo prefixes: @item @samp{@{evex@}} -- encode with EVEX prefix. + +@item +@samp{@{rex@}} -- prefer REX prefix for integer and legacy vector +instructions (x86-64 only). @end itemize @cindex conversion instructions, i386 diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.d b/gas/testsuite/gas/i386/x86-64-pseudos.d index c63a0a1150..de8c8eb46c 100644 --- a/gas/testsuite/gas/i386/x86-64-pseudos.d +++ b/gas/testsuite/gas/i386/x86-64-pseudos.d @@ -35,6 +35,19 @@ Disassembly of section .text: +[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%rax\),%xmm2 +[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%rax\),%xmm2 +[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%rax\),%xmm2 + +[a-f0-9]+: 88 c4 mov %al,%ah + +[a-f0-9]+: 40 89 c3 rex mov %eax,%ebx + +[a-f0-9]+: 41 89 c6 mov %eax,%r14d + +[a-f0-9]+: 41 89 00 mov %eax,\(%r8\) + +[a-f0-9]+: 40 0f 28 d7 rex movaps %xmm7,%xmm2 + +[a-f0-9]+: 44 0f 28 e7 movaps %xmm7,%xmm12 + +[a-f0-9]+: 40 0f 28 11 rex movaps \(%rcx\),%xmm2 + +[a-f0-9]+: 41 0f 28 10 movaps \(%r8\),%xmm2 + +[a-f0-9]+: 40 0f 38 01 01 rex phaddw \(%rcx\),%mm0 + +[a-f0-9]+: 41 0f 38 01 00 phaddw \(%r8\),%mm0 + +[a-f0-9]+: c5 f8 28 d7 vmovaps %xmm7,%xmm2 + +[a-f0-9]+: 62 b1 7c 08 28 d1 vmovaps %xmm17,%xmm2 + +[a-f0-9]+: c4 e3 7b f0 d8 07 rorx \$0x7,%eax,%ebx +[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2 +[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2 +[a-f0-9]+: c4 e1 78 29 fa vmovaps %xmm7,%xmm2 @@ -63,4 +76,17 @@ Disassembly of section .text: +[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%rax\),%xmm2 +[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%rax\),%xmm2 +[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%rax\),%xmm2 + +[a-f0-9]+: 88 c4 mov %al,%ah + +[a-f0-9]+: 40 89 c3 rex mov %eax,%ebx + +[a-f0-9]+: 41 89 c6 mov %eax,%r14d + +[a-f0-9]+: 41 89 00 mov %eax,\(%r8\) + +[a-f0-9]+: 40 0f 28 d7 rex movaps %xmm7,%xmm2 + +[a-f0-9]+: 44 0f 28 e7 movaps %xmm7,%xmm12 + +[a-f0-9]+: 40 0f 28 11 rex movaps \(%rcx\),%xmm2 + +[a-f0-9]+: 41 0f 28 10 movaps \(%r8\),%xmm2 + +[a-f0-9]+: 40 0f 38 01 01 rex phaddw \(%rcx\),%mm0 + +[a-f0-9]+: 41 0f 38 01 00 phaddw \(%r8\),%mm0 + +[a-f0-9]+: c5 f8 28 d7 vmovaps %xmm7,%xmm2 + +[a-f0-9]+: 62 b1 7c 08 28 d1 vmovaps %xmm17,%xmm2 + +[a-f0-9]+: c4 e3 7b f0 d8 07 rorx \$0x7,%eax,%ebx #pass diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.s b/gas/testsuite/gas/i386/x86-64-pseudos.s index c0ee8dcab9..c2137698ad 100644 --- a/gas/testsuite/gas/i386/x86-64-pseudos.s +++ b/gas/testsuite/gas/i386/x86-64-pseudos.s @@ -30,6 +30,19 @@ _start: movaps 128(%rax),%xmm2 {disp8} movaps 128(%rax),%xmm2 {disp32} movaps 128(%rax),%xmm2 + {rex} mov %al,%ah + {rex} movl %eax,%ebx + {rex} movl %eax,%r14d + {rex} movl %eax,(%r8) + {rex} movaps %xmm7,%xmm2 + {rex} movaps %xmm7,%xmm12 + {rex} movaps (%rcx),%xmm2 + {rex} movaps (%r8),%xmm2 + {rex} phaddw (%rcx),%mm0 + {rex} phaddw (%r8),%mm0 + {rex} vmovaps %xmm7,%xmm2 + {rex} vmovaps %xmm17,%xmm2 + {rex} rorx $7,%eax,%ebx .intel_syntax noprefix {vex3} vmovaps xmm2,xmm7 @@ -60,3 +73,16 @@ _start: movaps xmm2,XMMWORD PTR [rax+128] {disp8} movaps xmm2,XMMWORD PTR [rax+128] {disp32} movaps xmm2,XMMWORD PTR [rax+128] + {rex} mov ah,al + {rex} mov ebx,eax + {rex} mov r14d,eax + {rex} mov DWORD PTR [r8],eax + {rex} movaps xmm2,xmm7 + {rex} movaps xmm12,xmm7 + {rex} movaps xmm2,XMMWORD PTR [rcx] + {rex} movaps xmm2,XMMWORD PTR [r8] + {rex} phaddw mm0,QWORD PTR [rcx] + {rex} phaddw mm0,QWORD PTR [r8] + {rex} vmovaps xmm2,xmm7 + {rex} vmovaps xmm2,xmm17 + {rex} rorx ebx,eax,0x7 diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 481e99f097..450350556f 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -829,6 +829,7 @@ rex.wrxb, 0, 0x4f, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld {vex2}, 0, 0x4, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } {vex3}, 0, 0x5, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } {evex}, 0, 0x6, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +{rex}, 0, 0x7, None, 0, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } // 486 extensions. diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index f0b9241581..edb32fdaef 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -9293,6 +9293,20 @@ const insn_template i386_optab[] = { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, + { "{rex}", 0, 0x7, None, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 1, 0, 0 } }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, + 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 } } } }, { "bswap", 1, 0xfc8, None, 2, { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 2.14.3