From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 26682 invoked by alias); 9 Apr 2019 20:40:05 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 26672 invoked by uid 89); 9 Apr 2019 20:40:04 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.8 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.1 spammy=3078, HX-HELO:sk:NAM01-S, Extension, H*RU:sk:NAM01-S X-HELO: NAM01-SN1-obe.outbound.protection.outlook.com Received: from mail-eopbgr820094.outbound.protection.outlook.com (HELO NAM01-SN1-obe.outbound.protection.outlook.com) (40.107.82.94) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 09 Apr 2019 20:40:02 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=wavesemi.onmicrosoft.com; s=selector1-wavecomp-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=RFyACpRfkvGc5c7G9jVufTMa/d820SCH3wLwJKkVvT4=; b=o6BG9rslqP6wCCRkjusjYi6j7jDF4rZgwT1/ATOX5/LKtpwuGc7UMsmMN7vqFK8LmDKakLR/Vs++ZM3C4cy+346uwrwCqJmT5Covqt+g39AoPLQ4BUmRAom/aZzrrKL3KKHryayzOJwQuNXPDoGvNolGgd40mvVLdTV5ABwnqCE= Received: from CY4PR22MB0679.namprd22.prod.outlook.com (10.172.138.151) by CY4PR22MB0709.namprd22.prod.outlook.com (10.172.135.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1792.15; Tue, 9 Apr 2019 20:40:00 +0000 Received: from CY4PR22MB0679.namprd22.prod.outlook.com ([fe80::f081:5b3b:69eb:d550]) by CY4PR22MB0679.namprd22.prod.outlook.com ([fe80::f081:5b3b:69eb:d550%3]) with mapi id 15.20.1771.021; Tue, 9 Apr 2019 20:40:00 +0000 From: Faraz Shahbazker To: "binutils@sourceware.org" CC: Faraz Shahbazker , "paul.hua.gm@gmail.com" Subject: [PATCH 1/2] [MIPS] Apply ASE information for the selected processor Date: Tue, 09 Apr 2019 20:40:00 -0000 Message-ID: <20190409204029.98001-1-fshahbazker@wavecomp.com> authentication-results: spf=none (sender IP is ) smtp.mailfrom=fshahbazker@wavecomp.com; received-spf: None (protection.outlook.com: wavecomp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 Content-Type: text/plain; charset="us-ascii" Content-ID: <59B08BC2218C3C4092D412C46880B984@namprd22.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-SW-Source: 2019-04/txt/msg00086.txt.bz2 From: Matthew Fortune GAS does not enable implicit ASEs for most MIPS processors. The rework of option handling done as part of .module implementation left the implicit ASE logic broken and default enabled ASEs for most processors did not get applied. This patch ensures the ASE information is carried forward to the point where it is required. gas/ * config/tc-mips.c (mips_set_options) : New field. (file_mips_opts, mips_opts) : Initialize new field. (file_mips_check_options): Track and propagate the initial ASE settings for a CPU. * testsuite/gas/mips/elf_mach_p6600.d: New test. * testsuite/gas/mips/mips.exp: Run the new test. --- gas/config/tc-mips.c | 22 +++++++++++++++------- gas/testsuite/gas/mips/elf_mach_p6600.d | 23 +++++++++++++++++++++++ gas/testsuite/gas/mips/mips.exp | 1 + 3 files changed, 39 insertions(+), 7 deletions(-) create mode 100644 gas/testsuite/gas/mips/elf_mach_p6600.d diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 81b729a..45e8f38 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -268,6 +268,12 @@ struct mips_set_options /* 1 if single-precision operations on odd-numbered registers are allowed. */ int oddspreg; + + /* The set of ASEs that should be enabled for the user specified + architecture. This cannot be inferred from 'arch' for all cores + as processors only have a unique 'arch' if they add architecture + specific instructions (UDI). */ + int init_ase; }; =20 /* Specifies whether module level options have been checked yet. */ @@ -289,7 +295,8 @@ static struct mips_set_options file_mips_opts =3D /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, - /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 + /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1, + /* init_ase */ 0 }; =20 /* This is similar to file_mips_opts, but for the current set of options. = */ @@ -300,7 +307,8 @@ static struct mips_set_options mips_opts =3D /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, - /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 + /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1, + /* init_ase */ 0 }; =20 /* Which bits of file_ase were explicitly set or cleared by ASE options. = */ @@ -4086,8 +4094,6 @@ mips_check_options (struct mips_set_options *opts, bf= d_boolean abi_checks) static void file_mips_check_options (void) { - const struct mips_cpu_info *arch_info =3D 0; - if (file_mips_opts_checked) return; =20 @@ -4130,8 +4136,6 @@ file_mips_check_options (void) file_mips_opts.fp =3D 32; } =20 - arch_info =3D mips_cpu_info_from_arch (file_mips_opts.arch); - /* Disable operations on odd-numbered floating-point registers by default when using the FPXX ABI. */ if (file_mips_opts.oddspreg < 0) @@ -4175,7 +4179,7 @@ file_mips_check_options (void) =20 /* If the user didn't explicitly select or deselect a particular ASE, use the default setting for the CPU. */ - file_mips_opts.ase |=3D (arch_info->ase & ~file_ase_explicit); + file_mips_opts.ase |=3D (file_mips_opts.init_ase & ~file_ase_explicit); =20 /* Set up the current options. These may change throughout assembly. */ mips_opts =3D file_mips_opts; @@ -15189,6 +15193,7 @@ mips_after_parse_args (void) =20 file_mips_opts.arch =3D arch_info->cpu; file_mips_opts.isa =3D arch_info->isa; + file_mips_opts.init_ase =3D arch_info->ase; =20 /* Set up initial mips_opts state. */ mips_opts =3D file_mips_opts; @@ -16559,6 +16564,7 @@ parse_code_option (char * name) mips_opts.arch =3D p->cpu; mips_opts.isa =3D p->isa; isa_set =3D TRUE; + mips_opts.init_ase =3D p->ase; } } else if (strncmp (name, "mips", 4) =3D=3D 0) @@ -16573,6 +16579,7 @@ parse_code_option (char * name) mips_opts.arch =3D p->cpu; mips_opts.isa =3D p->isa; isa_set =3D TRUE; + mips_opts.init_ase =3D p->ase; } } else @@ -16646,6 +16653,7 @@ s_mipsset (int x ATTRIBUTE_UNUSED) { mips_opts.isa =3D file_mips_opts.isa; mips_opts.arch =3D file_mips_opts.arch; + mips_opts.init_ase =3D file_mips_opts.init_ase; mips_opts.gp =3D file_mips_opts.gp; mips_opts.fp =3D file_mips_opts.fp; } diff --git a/gas/testsuite/gas/mips/elf_mach_p6600.d b/gas/testsuite/gas/mi= ps/elf_mach_p6600.d new file mode 100644 index 0000000..a977d3b --- /dev/null +++ b/gas/testsuite/gas/mips/elf_mach_p6600.d @@ -0,0 +1,23 @@ +#readelf: -Ah +#name: ELF p6600 markings +#as: -64 -march=3Dp6600 +#source: empty.s + +ELF Header: +#... + Flags: +0xa......., .*mips64r6.* +#... + +MIPS ABI Flags Version: 0 + +ISA: MIPS64r6 +GPR size: 64 +CPR1 size: 128 +CPR2 size: 0 +FP ABI: .* +ISA Extension: None +ASEs: + VZ ASE + MSA ASE +FLAGS 1: .* +FLAGS 2: .* diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.= exp index a009c6e..5969c59 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -1151,6 +1151,7 @@ if { [istarget mips*-*-vxworks*] } { # Verify that machine markings are handled properly. run_dump_test "elf_mach_5900" run_dump_test "elf_mach_interaptiv-mr2" + run_dump_test "elf_mach_p6600" =20 run_dump_test "mips-gp32-fp32-pic" run_dump_test "mips-gp32-fp64-pic" --=20 2.9.5