From: Faraz Shahbazker <fshahbazker@wavecomp.com>
To: "binutils@sourceware.org" <binutils@sourceware.org>
Cc: Faraz Shahbazker <fshahbazker@wavecomp.com>,
"paul.hua.gm@gmail.com" <paul.hua.gm@gmail.com>
Subject: [PATCH 2/2] [MIPS] Add i6500 CPU and fix i6400 default ASEs
Date: Tue, 09 Apr 2019 20:40:00 -0000 [thread overview]
Message-ID: <20190409204029.98001-2-fshahbazker@wavecomp.com> (raw)
In-Reply-To: <20190409204029.98001-1-fshahbazker@wavecomp.com>
From: Matthew Fortune <matthew.fortune@mips.com>
gas/
* config/tc-mips.c (mips_cpu_info_table): Add i6500. Update
default ASEs for i6400.
* doc/c-mips.texi (-march): Document i6500.
* testsuite/gas/mips/elf_mach_i6400.d: New test.
* testsuite/gas/mips/elf_mach_i6500.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
---
gas/config/tc-mips.c | 4 +++-
gas/doc/c-mips.texi | 1 +
gas/testsuite/gas/mips/elf_mach_i6400.d | 23 +++++++++++++++++++++++
gas/testsuite/gas/mips/elf_mach_i6500.d | 25 +++++++++++++++++++++++++
gas/testsuite/gas/mips/mips.exp | 2 ++
5 files changed, 54 insertions(+), 1 deletion(-)
create mode 100644 gas/testsuite/gas/mips/elf_mach_i6400.d
create mode 100644 gas/testsuite/gas/mips/elf_mach_i6500.d
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 45e8f38..7eab392 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -20018,7 +20018,9 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
{ "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
/* MIPS 64 Release 6. */
- { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
+ { "i6400", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
+ { "i6500", 0, ASE_VIRT | ASE_MSA | ASE_CRC | ASE_GINV,
+ ISA_MIPS64R6, CPU_MIPS64R6},
{ "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
/* End marker. */
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 1ef289a..1df28c6 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -449,6 +449,7 @@ p5600,
sb1,
sb1a,
i6400,
+i6500,
p6600,
loongson2e,
loongson2f,
diff --git a/gas/testsuite/gas/mips/elf_mach_i6400.d b/gas/testsuite/gas/mips/elf_mach_i6400.d
new file mode 100644
index 0000000..ca1619a
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf_mach_i6400.d
@@ -0,0 +1,23 @@
+#readelf: -Ah
+#name: ELF i6400 markings
+#as: -64 -march=i6400
+#source: empty.s
+
+ELF Header:
+#...
+ Flags: +0xa......., .*mips64r6.*
+#...
+
+MIPS ABI Flags Version: 0
+
+ISA: MIPS64r6
+GPR size: 64
+CPR1 size: 128
+CPR2 size: 0
+FP ABI: .*
+ISA Extension: None
+ASEs:
+ VZ ASE
+ MSA ASE
+FLAGS 1: .*
+FLAGS 2: .*
diff --git a/gas/testsuite/gas/mips/elf_mach_i6500.d b/gas/testsuite/gas/mips/elf_mach_i6500.d
new file mode 100644
index 0000000..f1bb235
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf_mach_i6500.d
@@ -0,0 +1,25 @@
+#readelf: -Ah
+#name: ELF i6500 markings
+#as: -64 -march=i6500
+#source: empty.s
+
+ELF Header:
+#...
+ Flags: +0xa......., .*mips64r6.*
+#...
+
+MIPS ABI Flags Version: 0
+
+ISA: MIPS64r6
+GPR size: 64
+CPR1 size: 128
+CPR2 size: 0
+FP ABI: .*
+ISA Extension: None
+ASEs:
+ VZ ASE
+ MSA ASE
+ CRC ASE
+ GINV ASE
+FLAGS 1: .*
+FLAGS 2: .*
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 5969c59..635c7dc 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1152,6 +1152,8 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "elf_mach_5900"
run_dump_test "elf_mach_interaptiv-mr2"
run_dump_test "elf_mach_p6600"
+ run_dump_test "elf_mach_i6400"
+ run_dump_test "elf_mach_i6500"
run_dump_test "mips-gp32-fp32-pic"
run_dump_test "mips-gp32-fp64-pic"
--
2.9.5
next prev parent reply other threads:[~2019-04-09 20:40 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-09 20:40 [PATCH 1/2] [MIPS] Apply ASE information for the selected processor Faraz Shahbazker
2019-04-09 20:40 ` Faraz Shahbazker [this message]
2019-04-11 2:44 ` [PATCH 2/2] [MIPS] Add i6500 CPU and fix i6400 default ASEs Paul Hua
2019-04-11 16:52 ` Faraz Shahbazker
2019-04-12 1:14 ` Paul Hua
2019-04-12 2:09 ` Faraz Shahbazker
2019-04-13 2:06 ` Paul Hua
2019-04-13 4:55 ` Faraz Shahbazker
2019-04-13 8:35 ` Paul Hua
2019-04-13 8:32 ` [PATCH 1/2] [MIPS] Apply ASE information for the selected processor Paul Hua
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