From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 26971 invoked by alias); 9 Apr 2019 20:40:07 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 26859 invoked by uid 89); 9 Apr 2019 20:40:06 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.8 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.1 spammy=crc, CRC X-HELO: NAM01-SN1-obe.outbound.protection.outlook.com Received: from mail-eopbgr820094.outbound.protection.outlook.com (HELO NAM01-SN1-obe.outbound.protection.outlook.com) (40.107.82.94) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 09 Apr 2019 20:40:05 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=wavesemi.onmicrosoft.com; s=selector1-wavecomp-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6yHpLpEkS8usVR8RpEm7EQd67cV3dxHUv1jl3nQugSU=; b=r1rq+1Gezhgk0PVO+pksAgDbrtLcvVo7aZnG/tzzffuHYGNO8bkVK9vI6DE2fCESZDFiJ9sYGDM5jxhF3w5+MaUFE0jiUR1pHZZKqJ+dK/o3Dq8Xo32aHtisVzgo/1cQcfhUKRIcvAhghJjSZvWMjhFsW85oQxyrtvQnmtLVSo8= Received: from CY4PR22MB0679.namprd22.prod.outlook.com (10.172.138.151) by CY4PR22MB0709.namprd22.prod.outlook.com (10.172.135.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1792.15; Tue, 9 Apr 2019 20:40:01 +0000 Received: from CY4PR22MB0679.namprd22.prod.outlook.com ([fe80::f081:5b3b:69eb:d550]) by CY4PR22MB0679.namprd22.prod.outlook.com ([fe80::f081:5b3b:69eb:d550%3]) with mapi id 15.20.1771.021; Tue, 9 Apr 2019 20:40:01 +0000 From: Faraz Shahbazker To: "binutils@sourceware.org" CC: Faraz Shahbazker , "paul.hua.gm@gmail.com" Subject: [PATCH 2/2] [MIPS] Add i6500 CPU and fix i6400 default ASEs Date: Tue, 09 Apr 2019 20:40:00 -0000 Message-ID: <20190409204029.98001-2-fshahbazker@wavecomp.com> References: <20190409204029.98001-1-fshahbazker@wavecomp.com> In-Reply-To: <20190409204029.98001-1-fshahbazker@wavecomp.com> authentication-results: spf=none (sender IP is ) smtp.mailfrom=fshahbazker@wavecomp.com; received-spf: None (protection.outlook.com: wavecomp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 Content-Type: text/plain; charset="us-ascii" Content-ID: <31E59AB3C9CC5545ADFBB13BBCB1DD09@namprd22.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-SW-Source: 2019-04/txt/msg00087.txt.bz2 From: Matthew Fortune gas/ * config/tc-mips.c (mips_cpu_info_table): Add i6500. Update default ASEs for i6400. * doc/c-mips.texi (-march): Document i6500. * testsuite/gas/mips/elf_mach_i6400.d: New test. * testsuite/gas/mips/elf_mach_i6500.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests. --- gas/config/tc-mips.c | 4 +++- gas/doc/c-mips.texi | 1 + gas/testsuite/gas/mips/elf_mach_i6400.d | 23 +++++++++++++++++++++++ gas/testsuite/gas/mips/elf_mach_i6500.d | 25 +++++++++++++++++++++++++ gas/testsuite/gas/mips/mips.exp | 2 ++ 5 files changed, 54 insertions(+), 1 deletion(-) create mode 100644 gas/testsuite/gas/mips/elf_mach_i6400.d create mode 100644 gas/testsuite/gas/mips/elf_mach_i6500.d diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 45e8f38..7eab392 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -20018,7 +20018,9 @@ static const struct mips_cpu_info mips_cpu_info_tab= le[] =3D { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, =20 /* MIPS 64 Release 6. */ - { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, + { "i6400", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, + { "i6500", 0, ASE_VIRT | ASE_MSA | ASE_CRC | ASE_GINV, + ISA_MIPS64R6, CPU_MIPS64R6}, { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, =20 /* End marker. */ diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi index 1ef289a..1df28c6 100644 --- a/gas/doc/c-mips.texi +++ b/gas/doc/c-mips.texi @@ -449,6 +449,7 @@ p5600, sb1, sb1a, i6400, +i6500, p6600, loongson2e, loongson2f, diff --git a/gas/testsuite/gas/mips/elf_mach_i6400.d b/gas/testsuite/gas/mi= ps/elf_mach_i6400.d new file mode 100644 index 0000000..ca1619a --- /dev/null +++ b/gas/testsuite/gas/mips/elf_mach_i6400.d @@ -0,0 +1,23 @@ +#readelf: -Ah +#name: ELF i6400 markings +#as: -64 -march=3Di6400 +#source: empty.s + +ELF Header: +#... + Flags: +0xa......., .*mips64r6.* +#... + +MIPS ABI Flags Version: 0 + +ISA: MIPS64r6 +GPR size: 64 +CPR1 size: 128 +CPR2 size: 0 +FP ABI: .* +ISA Extension: None +ASEs: + VZ ASE + MSA ASE +FLAGS 1: .* +FLAGS 2: .* diff --git a/gas/testsuite/gas/mips/elf_mach_i6500.d b/gas/testsuite/gas/mi= ps/elf_mach_i6500.d new file mode 100644 index 0000000..f1bb235 --- /dev/null +++ b/gas/testsuite/gas/mips/elf_mach_i6500.d @@ -0,0 +1,25 @@ +#readelf: -Ah +#name: ELF i6500 markings +#as: -64 -march=3Di6500 +#source: empty.s + +ELF Header: +#... + Flags: +0xa......., .*mips64r6.* +#... + +MIPS ABI Flags Version: 0 + +ISA: MIPS64r6 +GPR size: 64 +CPR1 size: 128 +CPR2 size: 0 +FP ABI: .* +ISA Extension: None +ASEs: + VZ ASE + MSA ASE + CRC ASE + GINV ASE +FLAGS 1: .* +FLAGS 2: .* diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.= exp index 5969c59..635c7dc 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -1152,6 +1152,8 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "elf_mach_5900" run_dump_test "elf_mach_interaptiv-mr2" run_dump_test "elf_mach_p6600" + run_dump_test "elf_mach_i6400" + run_dump_test "elf_mach_i6500" =20 run_dump_test "mips-gp32-fp32-pic" run_dump_test "mips-gp32-fp64-pic" --=20 2.9.5