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From: Stafford Horne <shorne@gmail.com>
To: GDB patches <gdb-patches@sourceware.org>,
	GNU Binutils <binutils@sourceware.org>
Cc: Andrey Bacherov <bandvig@mail.ru>,
	Openrisc <openrisc@lists.librecores.org>,
	Stafford Horne <shorne@gmail.com>
Subject: [PATCH v2 6/6] sim/common: Fix issue with wrong byte order on BE targets
Date: Tue, 09 Apr 2019 21:40:00 -0000	[thread overview]
Message-ID: <20190409213925.32699-7-shorne@gmail.com> (raw)
In-Reply-To: <20190409213925.32699-1-shorne@gmail.com>

Currently only the OpenRISC sim uses this JOINSIDF() function to compose a
double float from 2 registers.  The old code doesn't seem to work as the
work order gets swapped when running on a x86_64 host.  This change
fixes that, but I am not sure if its the best thing to do.

On mips they do similar reg pair floating point operations composing
doubles from 2 32-bit registers in sim/mips/cp1.c value_fpr().

sim/common/ChangeLog:

	* cgen-ops.h (JOINSIDF): Fix big endian check.
---
 sim/common/cgen-ops.h | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/sim/common/cgen-ops.h b/sim/common/cgen-ops.h
index 841552066f..d718394723 100644
--- a/sim/common/cgen-ops.h
+++ b/sim/common/cgen-ops.h
@@ -431,12 +431,8 @@ JOINSIDI (SI x0, SI x1)
 SEMOPS_INLINE DF
 JOINSIDF (SI x0, SI x1)
 {
-  union { SI in[2]; DF out; } x;
-  if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
-    x.in[0] = x0, x.in[1] = x1;
-  else
-    x.in[1] = x0, x.in[0] = x1;
-  return x.out;
+  /* Making doubles is the same as making long longs.  */
+  return MAKEDI (x0, x1);
 }
 
 SEMOPS_INLINE XF
-- 
2.19.1

  parent reply	other threads:[~2019-04-09 21:40 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-09 21:39 [PATCH v2 0/6] OpenRISC orfpx64a32 support Stafford Horne
2019-04-09 21:39 ` [PATCH v2 1/6] cpu: Add support for orfp64a32 spec Stafford Horne
2019-04-09 21:39 ` [PATCH v2 4/6] sim/common: Wire in df/di conversion Stafford Horne
2019-04-13 21:59   ` Andrew Burgess
2019-04-09 21:40 ` [PATCH v2 3/6] sim/or1k: Regenerate sim for orfp64a32 spec Stafford Horne
2019-04-13 21:40   ` Andrew Burgess
2019-04-14  6:44     ` Stafford Horne
2019-04-09 21:40 ` [PATCH v2 2/6] opcodes: Regenerate opcodes " Stafford Horne
2019-04-11  8:45   ` Nick Clifton
2019-04-09 21:40 ` Stafford Horne [this message]
2019-04-11 22:27   ` [PATCH v2 6/6] sim/common: Fix issue with wrong byte order on BE targets Andrew Burgess
2019-04-12 20:21     ` Stafford Horne
2019-04-13 21:30       ` Andrew Burgess
2019-04-09 21:40 ` [PATCH v2 5/6] sim/or1k: Add test for 64-bit fpu operations Stafford Horne
2019-04-13 21:36   ` Andrew Burgess

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