* [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline
@ 2019-04-04 13:24 Andre Vieira (lists)
2019-04-04 13:28 ` [PATCH, binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI Andre Vieira (lists)
` (16 more replies)
0 siblings, 17 replies; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-04 13:24 UTC (permalink / raw)
To: binutils
Hello,
This is a patch series to implement support for Armv8.1-M Mainline. The
specifications for the Armv8.1-M Mainline can be found in
https://developer.arm.com/docs/ddi0553/latest
This patch series does not cover M-profile Vector Extension (MVE)
support, this will be implemented in a follow-up patch series.
Andre Vieira (16):
[PATCH, binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI
[PATCH, GAS, ARM, 2/16] Add architecture extension support for Armv8.1-M
Mainline
[PATCH, binutils, ARM, 3/16] BF insns infrastructure with new
bfd_reloc_code_real for fallback branch
[PATCH, binutils, ARM, 4/16] BF insns infrastructure with array of
relocs in struct arm_it
[PATCH, binutils, ARM, 5/16] BF insns infrastructure with new global
reloc R_ARM_THM_BF16
[PATCH, binutils, ARM, 6/16] New BF instruction for Armv8.1-M Mainline
[PATCH, binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8.1-M
Mainline
[PATCH, binutils, ARM, 8/16] BFL infrastructure with new global reloc
R_ARM_THM_BF18
[PATCH, binutils, ARM, 9/16] New BFL instruction for Armv8.1-M Mainline
[PATCH, binutils, ARM, 10/16] BFCSEL infrastructure with new global
reloc R_ARM_THM_BF12
[PATCH, binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M Mainline
[PATCH, binutils, ARM, 12/16] Scalar Low Overhead loop instructions for
Armv8.1-M Mainline
[PATCH, binutils, ARM, 13/16] Add support for CLRM
[PATCH, opcodes, ARM, 14/16] Add mode availability to coprocessor table
entries
[PATCH, binutils, ARM, 15/16] Add support for VSCCLRM
[PATCH, binutils, ARM, 16/16] Add support to VLDR and VSTR of system
registers
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH, GAS, ARM, 2/16] Add CLI extension support for Armv8.1-M Mainline
2019-04-04 13:24 [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Andre Vieira (lists)
2019-04-04 13:28 ` [PATCH, binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI Andre Vieira (lists)
@ 2019-04-04 13:28 ` Andre Vieira (lists)
2019-04-04 13:34 ` [PATCH, binutils, ARM, 4/16] BF insns infrastructure with array of relocs in struct arm_it Andre Vieira (lists)
` (14 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-04 13:28 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 778 bytes --]
Hi,
This patch implements the dsp, fp and fp.dp extensions for Armv8.1-M
Mainline.
This patch also removes the fp-armv8 check from the half-precision move
instructions 'do_neon_movhf', as checking that the FP16 instructions
extension feature bit is enabled 'ARM_EXT2_FP16_INST' is enough.
gas/ChangeLog:
2019-04-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_neon_movhf): Remove fp-armv8 check.
(armv8_1m_main_ext_table): New extension table.
(arm_archs): Use the new extension table.
* doc/c-arm.texi: Add missing arch and document new extensions.
* testsuite/gas/arm/armv8.1-m.main-fp.d: New.
* testsuite/gas/arm/armv8.1-m.main-fp-dp.d: New.
* testsuite/gas/arm/armv8.1-m.main-hp.d: New.
[-- Attachment #2: 2.patch --]
[-- Type: text/x-patch, Size: 31062 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 4f96066cc5f32b9a07d2f8b6a146ea2788f61f07..11d593c2626199d0dad4f4d81a276decb0300d3c 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -16809,9 +16809,6 @@ do_neon_movhf (void)
enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL);
constraint (rs != NS_HH, _("invalid suffix"));
- constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
- _(BAD_FPU));
-
if (inst.cond != COND_ALWAYS)
{
if (thumb_mode)
@@ -26503,6 +26500,20 @@ static const struct arm_ext_table armv8m_main_ext_table[] =
{ NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
};
+static const struct arm_ext_table armv8_1m_main_ext_table[] =
+{
+ ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
+ ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)),
+ ARM_EXT ("fp",
+ ARM_FEATURE (0, ARM_EXT2_FP16_INST,
+ FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
+ ALL_FP),
+ ARM_ADD ("fp.dp",
+ ARM_FEATURE (0, ARM_EXT2_FP16_INST,
+ FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
static const struct arm_ext_table armv8r_ext_table[] =
{
ARM_ADD ("crc", ARCH_CRC_ARMV8),
@@ -26570,7 +26581,8 @@ static const struct arm_arch_option_table arm_archs[] =
ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP),
ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP,
armv8m_main),
- ARM_ARCH_OPT ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN, FPU_ARCH_VFP),
+ ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN, FPU_ARCH_VFP,
+ armv8_1m_main),
ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP, armv8a),
ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP, armv81a),
ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP, armv82a),
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index 184d7160a887d3512de50255c17bcbb1ba661667..4c595d8bf0ee7a3b0ff77e1ddc6ab073c5c3e589 100644
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -250,6 +250,7 @@ names are recognized:
@code{armv8.5-a},
@code{armv8-m.base},
@code{armv8-m.main},
+@code{armv8.1-m.main},
@code{iwmmxt},
@code{iwmmxt2}
and
@@ -355,6 +356,16 @@ double-word registers.
@code{+nofp}: Disables all FPU instructions.
@code{+nodsp}: Disables DSP Extension.
+For @code{armv8.1-m.main}:
+
+@code{+dsp}: Enables DSP Extension.
+@code{+fp}: Enables single and half precision scalar Floating Point Extensions
+for Armv8.1-M Mainline with 16 double-word registers.
+@code{+fp.dp}: Enables double precision scalar Floating Point Extensions for
+Armv8.1-M Mainline, implies @code{+fp}.
+@code{+nofp}: Disables all FPU instructions.
+@code{+nodsp}: Disables DSP Extension.
+
For @code{armv8-a}:
@code{+crc}: Enables CRC32 Extension.
diff --git a/gas/testsuite/gas/arm/armv8.1-m.main-fp-dp.d b/gas/testsuite/gas/arm/armv8.1-m.main-fp-dp.d
new file mode 100644
index 0000000000000000000000000000000000000000..79c17da473350eca89703b864d2887178a3b9efe
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8.1-m.main-fp-dp.d
@@ -0,0 +1,203 @@
+# name: Double precision instructions for 'armv8.1-m.main'
+# source: vfp1_t2.s
+# as: -march=armv8.1-m.main+fp.dp
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]*> eeb4 0bc0 (vcmpe\.f64|fcmped) d0, d0
+0+004 <[^>]*> eeb5 0bc0 (vcmpe\.f64 d0, #0.0|fcmpezd d0)
+0+008 <[^>]*> eeb4 0b40 (vcmp\.f64|fcmpd) d0, d0
+0+00c <[^>]*> eeb5 0b40 (vcmp\.f64 d0, #0.0|fcmpzd d0)
+0+010 <[^>]*> eeb0 0bc0 (vabs\.f64|fabsd) d0, d0
+0+014 <[^>]*> eeb0 0b40 (vmov\.f64|fcpyd) d0, d0
+0+018 <[^>]*> eeb1 0b40 (vneg\.f64|fnegd) d0, d0
+0+01c <[^>]*> eeb1 0bc0 (vsqrt\.f64|fsqrtd) d0, d0
+0+020 <[^>]*> ee30 0b00 (vadd\.f64|faddd) d0, d0, d0
+0+024 <[^>]*> ee80 0b00 (vdiv\.f64|fdivd) d0, d0, d0
+0+028 <[^>]*> ee00 0b00 (vmla\.f64|fmacd) d0, d0, d0
+0+02c <[^>]*> ee10 0b00 (vnmls\.f64|fmscd) d0, d0, d0
+0+030 <[^>]*> ee20 0b00 (vmul\.f64|fmuld) d0, d0, d0
+0+034 <[^>]*> ee00 0b40 (vmls\.f64|fnmacd) d0, d0, d0
+0+038 <[^>]*> ee10 0b40 (vnmla\.f64|fnmscd) d0, d0, d0
+0+03c <[^>]*> ee20 0b40 (vnmul\.f64|fnmuld) d0, d0, d0
+0+040 <[^>]*> ee30 0b40 (vsub\.f64|fsubd) d0, d0, d0
+0+044 <[^>]*> ed90 0b00 vldr d0, \[r0\]
+0+048 <[^>]*> ed80 0b00 vstr d0, \[r0\]
+0+04c <[^>]*> ec90 0b02 vldmia r0, {d0}
+0+050 <[^>]*> ec90 0b02 vldmia r0, {d0}
+0+054 <[^>]*> ecb0 0b02 vldmia r0!, {d0}
+0+058 <[^>]*> ecb0 0b02 vldmia r0!, {d0}
+0+05c <[^>]*> ed30 0b02 vldmdb r0!, {d0}
+0+060 <[^>]*> ed30 0b02 vldmdb r0!, {d0}
+0+064 <[^>]*> ec80 0b02 vstmia r0, {d0}
+0+068 <[^>]*> ec80 0b02 vstmia r0, {d0}
+0+06c <[^>]*> eca0 0b02 vstmia r0!, {d0}
+0+070 <[^>]*> eca0 0b02 vstmia r0!, {d0}
+0+074 <[^>]*> ed20 0b02 vstmdb r0!, {d0}
+0+078 <[^>]*> ed20 0b02 vstmdb r0!, {d0}
+0+07c <[^>]*> eeb8 0bc0 (vcvt\.f64\.s32|fsitod) d0, s0
+0+080 <[^>]*> eeb8 0b40 (vcvt\.f64\.u32|fuitod) d0, s0
+0+084 <[^>]*> eebd 0b40 (vcvtr\.s32\.f64|ftosid) s0, d0
+0+088 <[^>]*> eebd 0bc0 (vcvt\.s32\.f64|ftosizd) s0, d0
+0+08c <[^>]*> eebc 0b40 (vcvtr\.u32\.f64|ftouid) s0, d0
+0+090 <[^>]*> eebc 0bc0 (vcvt\.u32\.f64|ftouizd) s0, d0
+0+094 <[^>]*> eeb7 0ac0 (vcvt\.f64\.f32|fcvtds) d0, s0
+0+098 <[^>]*> eeb7 0bc0 (vcvt\.f32\.f64|fcvtsd) s0, d0
+0+09c <[^>]*> ee30 0b10 vmov\.32 r0, d0\[1\]
+0+0a0 <[^>]*> ee10 0b10 vmov\.32 r0, d0\[0\]
+0+0a4 <[^>]*> ee20 0b10 vmov\.32 d0\[1\], r0
+0+0a8 <[^>]*> ee00 0b10 vmov\.32 d0\[0\], r0
+0+0ac <[^>]*> eeb5 1b40 (vcmp\.f64 d1, #0.0|fcmpzd d1)
+0+0b0 <[^>]*> eeb5 2b40 (vcmp\.f64 d2, #0.0|fcmpzd d2)
+0+0b4 <[^>]*> eeb5 fb40 (vcmp\.f64 d15, #0.0|fcmpzd d15)
+0+0b8 <[^>]*> eeb4 0b41 (vcmp\.f64|fcmpd) d0, d1
+0+0bc <[^>]*> eeb4 0b42 (vcmp\.f64|fcmpd) d0, d2
+0+0c0 <[^>]*> eeb4 0b4f (vcmp\.f64|fcmpd) d0, d15
+0+0c4 <[^>]*> eeb4 1b40 (vcmp\.f64|fcmpd) d1, d0
+0+0c8 <[^>]*> eeb4 2b40 (vcmp\.f64|fcmpd) d2, d0
+0+0cc <[^>]*> eeb4 fb40 (vcmp\.f64|fcmpd) d15, d0
+0+0d0 <[^>]*> eeb4 5b4c (vcmp\.f64|fcmpd) d5, d12
+0+0d4 <[^>]*> eeb1 0b41 (vneg\.f64|fnegd) d0, d1
+0+0d8 <[^>]*> eeb1 0b42 (vneg\.f64|fnegd) d0, d2
+0+0dc <[^>]*> eeb1 0b4f (vneg\.f64|fnegd) d0, d15
+0+0e0 <[^>]*> eeb1 1b40 (vneg\.f64|fnegd) d1, d0
+0+0e4 <[^>]*> eeb1 2b40 (vneg\.f64|fnegd) d2, d0
+0+0e8 <[^>]*> eeb1 fb40 (vneg\.f64|fnegd) d15, d0
+0+0ec <[^>]*> eeb1 cb45 (vneg\.f64|fnegd) d12, d5
+0+0f0 <[^>]*> ee30 0b01 (vadd\.f64|faddd) d0, d0, d1
+0+0f4 <[^>]*> ee30 0b02 (vadd\.f64|faddd) d0, d0, d2
+0+0f8 <[^>]*> ee30 0b0f (vadd\.f64|faddd) d0, d0, d15
+0+0fc <[^>]*> ee31 0b00 (vadd\.f64|faddd) d0, d1, d0
+0+100 <[^>]*> ee32 0b00 (vadd\.f64|faddd) d0, d2, d0
+0+104 <[^>]*> ee3f 0b00 (vadd\.f64|faddd) d0, d15, d0
+0+108 <[^>]*> ee30 1b00 (vadd\.f64|faddd) d1, d0, d0
+0+10c <[^>]*> ee30 2b00 (vadd\.f64|faddd) d2, d0, d0
+0+110 <[^>]*> ee30 fb00 (vadd\.f64|faddd) d15, d0, d0
+0+114 <[^>]*> ee39 cb05 (vadd\.f64|faddd) d12, d9, d5
+0+118 <[^>]*> eeb7 0ae0 (vcvt\.f64\.f32|fcvtds) d0, s1
+0+11c <[^>]*> eeb7 0ac1 (vcvt\.f64\.f32|fcvtds) d0, s2
+0+120 <[^>]*> eeb7 0aef (vcvt\.f64\.f32|fcvtds) d0, s31
+0+124 <[^>]*> eeb7 1ac0 (vcvt\.f64\.f32|fcvtds) d1, s0
+0+128 <[^>]*> eeb7 2ac0 (vcvt\.f64\.f32|fcvtds) d2, s0
+0+12c <[^>]*> eeb7 fac0 (vcvt\.f64\.f32|fcvtds) d15, s0
+0+130 <[^>]*> eef7 0bc0 (vcvt\.f32\.f64|fcvtsd) s1, d0
+0+134 <[^>]*> eeb7 1bc0 (vcvt\.f32\.f64|fcvtsd) s2, d0
+0+138 <[^>]*> eef7 fbc0 (vcvt\.f32\.f64|fcvtsd) s31, d0
+0+13c <[^>]*> eeb7 0bc1 (vcvt\.f32\.f64|fcvtsd) s0, d1
+0+140 <[^>]*> eeb7 0bc2 (vcvt\.f32\.f64|fcvtsd) s0, d2
+0+144 <[^>]*> eeb7 0bcf (vcvt\.f32\.f64|fcvtsd) s0, d15
+0+148 <[^>]*> ee30 1b10 vmov\.32 r1, d0\[1\]
+0+14c <[^>]*> ee30 eb10 vmov\.32 lr, d0\[1\]
+0+150 <[^>]*> ee31 0b10 vmov\.32 r0, d1\[1\]
+0+154 <[^>]*> ee32 0b10 vmov\.32 r0, d2\[1\]
+0+158 <[^>]*> ee3f 0b10 vmov\.32 r0, d15\[1\]
+0+15c <[^>]*> ee10 1b10 vmov\.32 r1, d0\[0\]
+0+160 <[^>]*> ee10 eb10 vmov\.32 lr, d0\[0\]
+0+164 <[^>]*> ee11 0b10 vmov\.32 r0, d1\[0\]
+0+168 <[^>]*> ee12 0b10 vmov\.32 r0, d2\[0\]
+0+16c <[^>]*> ee1f 0b10 vmov\.32 r0, d15\[0\]
+0+170 <[^>]*> ee20 1b10 vmov\.32 d0\[1\], r1
+0+174 <[^>]*> ee20 eb10 vmov\.32 d0\[1\], lr
+0+178 <[^>]*> ee21 0b10 vmov\.32 d1\[1\], r0
+0+17c <[^>]*> ee22 0b10 vmov\.32 d2\[1\], r0
+0+180 <[^>]*> ee2f 0b10 vmov\.32 d15\[1\], r0
+0+184 <[^>]*> ee00 1b10 vmov\.32 d0\[0\], r1
+0+188 <[^>]*> ee00 eb10 vmov\.32 d0\[0\], lr
+0+18c <[^>]*> ee01 0b10 vmov\.32 d1\[0\], r0
+0+190 <[^>]*> ee02 0b10 vmov\.32 d2\[0\], r0
+0+194 <[^>]*> ee0f 0b10 vmov\.32 d15\[0\], r0
+0+198 <[^>]*> ed91 0b00 vldr d0, \[r1\]
+0+19c <[^>]*> ed9e 0b00 vldr d0, \[lr\]
+0+1a0 <[^>]*> ed90 0b00 vldr d0, \[r0\]
+0+1a4 <[^>]*> ed90 0bff vldr d0, \[r0, #1020\].*
+0+1a8 <[^>]*> ed10 0bff vldr d0, \[r0, #-1020\].*
+0+1ac <[^>]*> ed90 1b00 vldr d1, \[r0\]
+0+1b0 <[^>]*> ed90 2b00 vldr d2, \[r0\]
+0+1b4 <[^>]*> ed90 fb00 vldr d15, \[r0\]
+0+1b8 <[^>]*> ed8c cbc9 vstr d12, \[ip, #804\].*
+0+1bc <[^>]*> ec90 1b02 vldmia r0, {d1}
+0+1c0 <[^>]*> ec90 2b02 vldmia r0, {d2}
+0+1c4 <[^>]*> ec90 fb02 vldmia r0, {d15}
+0+1c8 <[^>]*> ec90 0b04 vldmia r0, {d0-d1}
+0+1cc <[^>]*> ec90 0b06 vldmia r0, {d0-d2}
+0+1d0 <[^>]*> ec90 0b20 vldmia r0, {d0-d15}
+0+1d4 <[^>]*> ec90 1b1e vldmia r0, {d1-d15}
+0+1d8 <[^>]*> ec90 2b1c vldmia r0, {d2-d15}
+0+1dc <[^>]*> ec90 eb04 vldmia r0, {d14-d15}
+0+1e0 <[^>]*> ec91 0b02 vldmia r1, {d0}
+0+1e4 <[^>]*> ec9e 0b02 vldmia lr, {d0}
+0+1e8 <[^>]*> eeb5 0b40 (vcmp\.f64 d0, #0.0|fcmpzd d0)
+0+1ec <[^>]*> eeb5 1b40 (vcmp\.f64 d1, #0.0|fcmpzd d1)
+0+1f0 <[^>]*> eeb5 2b40 (vcmp\.f64 d2, #0.0|fcmpzd d2)
+0+1f4 <[^>]*> eeb5 3b40 (vcmp\.f64 d3, #0.0|fcmpzd d3)
+0+1f8 <[^>]*> eeb5 4b40 (vcmp\.f64 d4, #0.0|fcmpzd d4)
+0+1fc <[^>]*> eeb5 5b40 (vcmp\.f64 d5, #0.0|fcmpzd d5)
+0+200 <[^>]*> eeb5 6b40 (vcmp\.f64 d6, #0.0|fcmpzd d6)
+0+204 <[^>]*> eeb5 7b40 (vcmp\.f64 d7, #0.0|fcmpzd d7)
+0+208 <[^>]*> eeb5 8b40 (vcmp\.f64 d8, #0.0|fcmpzd d8)
+0+20c <[^>]*> eeb5 9b40 (vcmp\.f64 d9, #0.0|fcmpzd d9)
+0+210 <[^>]*> eeb5 ab40 (vcmp\.f64 d10, #0.0|fcmpzd d10)
+0+214 <[^>]*> eeb5 bb40 (vcmp\.f64 d11, #0.0|fcmpzd d11)
+0+218 <[^>]*> eeb5 cb40 (vcmp\.f64 d12, #0.0|fcmpzd d12)
+0+21c <[^>]*> eeb5 db40 (vcmp\.f64 d13, #0.0|fcmpzd d13)
+0+220 <[^>]*> eeb5 eb40 (vcmp\.f64 d14, #0.0|fcmpzd d14)
+0+224 <[^>]*> eeb5 fb40 (vcmp\.f64 d15, #0.0|fcmpzd d15)
+0+228 <[^>]*> bf01 itttt eq
+0+22a <[^>]*> eeb4 1bcf (vcmpeeq\.f64|fcmpedeq) d1, d15
+0+22e <[^>]*> eeb5 2bc0 (vcmpeeq\.f64 d2, #0.0|fcmpezdeq d2)
+0+232 <[^>]*> eeb4 3b4e (vcmpeq\.f64|fcmpdeq) d3, d14
+0+236 <[^>]*> eeb5 4b40 (vcmpeq\.f64 d4, #0.0|fcmpzdeq d4)
+0+23a <[^>]*> bf01 itttt eq
+0+23c <[^>]*> eeb0 5bcd (vabseq\.f64|fabsdeq) d5, d13
+0+240 <[^>]*> eeb0 6b4c (vmoveq\.f64|fcpydeq) d6, d12
+0+244 <[^>]*> eeb1 7b4b (vnegeq\.f64|fnegdeq) d7, d11
+0+248 <[^>]*> eeb1 8bca (vsqrteq\.f64|fsqrtdeq) d8, d10
+0+24c <[^>]*> bf01 itttt eq
+0+24e <[^>]*> ee31 9b0f (vaddeq\.f64|fadddeq) d9, d1, d15
+0+252 <[^>]*> ee83 2b0e (vdiveq\.f64|fdivdeq) d2, d3, d14
+0+256 <[^>]*> ee0d 4b0c (vmlaeq\.f64|fmacdeq) d4, d13, d12
+0+25a <[^>]*> ee16 5b0b (vnmlseq\.f64|fmscdeq) d5, d6, d11
+0+25e <[^>]*> bf01 itttt eq
+0+260 <[^>]*> ee2a 7b09 (vmuleq\.f64|fmuldeq) d7, d10, d9
+0+264 <[^>]*> ee09 8b4a (vmlseq\.f64|fnmacdeq) d8, d9, d10
+0+268 <[^>]*> ee16 7b4b (vnmlaeq\.f64|fnmscdeq) d7, d6, d11
+0+26c <[^>]*> ee24 5b4c (vnmuleq\.f64|fnmuldeq) d5, d4, d12
+0+270 <[^>]*> bf02 ittt eq
+0+272 <[^>]*> ee3d 3b4e (vsubeq\.f64|fsubdeq) d3, d13, d14
+0+276 <[^>]*> ed95 2b00 vldreq d2, \[r5\]
+0+27a <[^>]*> ed8c 1b00 vstreq d1, \[ip\]
+0+27e <[^>]*> bf01 itttt eq
+0+280 <[^>]*> ec91 1b02 vldmiaeq r1, {d1}
+0+284 <[^>]*> ec92 2b02 vldmiaeq r2, {d2}
+0+288 <[^>]*> ecb3 3b02 vldmiaeq r3!, {d3}
+0+28c <[^>]*> ecb4 4b02 vldmiaeq r4!, {d4}
+0+290 <[^>]*> bf01 itttt eq
+0+292 <[^>]*> ed35 5b02 vldmdbeq r5!, {d5}
+0+296 <[^>]*> ed36 6b02 vldmdbeq r6!, {d6}
+0+29a <[^>]*> ec87 fb02 vstmiaeq r7, {d15}
+0+29e <[^>]*> ec88 eb02 vstmiaeq r8, {d14}
+0+2a2 <[^>]*> bf01 itttt eq
+0+2a4 <[^>]*> eca9 db02 vstmiaeq r9!, {d13}
+0+2a8 <[^>]*> ecaa cb02 vstmiaeq sl!, {d12}
+0+2ac <[^>]*> ed2b bb02 vstmdbeq fp!, {d11}
+0+2b0 <[^>]*> ed2c ab02 vstmdbeq ip!, {d10}
+0+2b4 <[^>]*> bf01 itttt eq
+0+2b6 <[^>]*> eeb8 fbe0 (vcvteq\.f64\.s32|fsitodeq) d15, s1
+0+2ba <[^>]*> eeb8 1b6f (vcvteq\.f64\.u32|fuitodeq) d1, s31
+0+2be <[^>]*> eefd 0b4f (vcvtreq\.s32\.f64|ftosideq) s1, d15
+0+2c2 <[^>]*> eefd fbc2 (vcvteq\.s32\.f64|ftosizdeq) s31, d2
+0+2c6 <[^>]*> bf01 itttt eq
+0+2c8 <[^>]*> eefc 7b42 (vcvtreq\.u32\.f64|ftouideq) s15, d2
+0+2cc <[^>]*> eefc 5bc3 (vcvteq\.u32\.f64|ftouizdeq) s11, d3
+0+2d0 <[^>]*> eeb7 1ac5 (vcvteq\.f64\.f32|fcvtdseq) d1, s10
+0+2d4 <[^>]*> eef7 5bc1 (vcvteq\.f32\.f64|fcvtsdeq) s11, d1
+0+2d8 <[^>]*> bf01 itttt eq
+0+2da <[^>]*> ee31 8b10 vmoveq\.32 r8, d1\[1\]
+0+2de <[^>]*> ee1f 7b10 vmoveq\.32 r7, d15\[0\]
+0+2e2 <[^>]*> ee21 fb10 vmoveq\.32 d1\[1\], pc
+0+2e6 <[^>]*> ee0f 1b10 vmoveq\.32 d15\[0\], r1
+0+2ea <[^>]*> bf00 nop
+0+2ec <[^>]*> bf00 nop
+0+2ee <[^>]*> bf00 nop
diff --git a/gas/testsuite/gas/arm/armv8.1-m.main-fp.d b/gas/testsuite/gas/arm/armv8.1-m.main-fp.d
new file mode 100644
index 0000000000000000000000000000000000000000..dd69e0d5252b0b4994d723cc2c7d086987ee30a1
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8.1-m.main-fp.d
@@ -0,0 +1,270 @@
+# name: Single precision instructions for 'armv8.1-m.main'
+# source: vfp1xD_t2.s
+# as: -march=armv8.1-m.main+fp
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]*> eef1 fa10 (vmrs APSR_nzcv, fpscr|fmstat)
+0+004 <[^>]*> eeb4 0ac0 (vcmpe\.f32|fcmpes) s0, s0
+0+008 <[^>]*> eeb5 0ac0 (vcmpe\.f32 s0, #0.0|fcmpezs s0)
+0+00c <[^>]*> eeb4 0a40 (vcmp\.f32|fcmps) s0, s0
+0+010 <[^>]*> eeb5 0a40 (vcmp\.f32 s0, #0.0|fcmpzs s0)
+0+014 <[^>]*> eeb0 0ac0 (vabs\.f32|fabss) s0, s0
+0+018 <[^>]*> eeb0 0a40 (vmov\.f32|fcpys) s0, s0
+0+01c <[^>]*> eeb1 0a40 (vneg\.f32|fnegs) s0, s0
+0+020 <[^>]*> eeb1 0ac0 (vsqrt\.f32|fsqrts) s0, s0
+0+024 <[^>]*> ee30 0a00 (vadd\.f32|fadds) s0, s0, s0
+0+028 <[^>]*> ee80 0a00 (vdiv\.f32|fdivs) s0, s0, s0
+0+02c <[^>]*> ee00 0a00 (vmla\.f32|fmacs) s0, s0, s0
+0+030 <[^>]*> ee10 0a00 (vnmls\.f32|fmscs) s0, s0, s0
+0+034 <[^>]*> ee20 0a00 (vmul\.f32|fmuls) s0, s0, s0
+0+038 <[^>]*> ee00 0a40 (vmls\.f32|fnmacs) s0, s0, s0
+0+03c <[^>]*> ee10 0a40 (vnmla\.f32|fnmscs) s0, s0, s0
+0+040 <[^>]*> ee20 0a40 (vnmul\.f32|fnmuls) s0, s0, s0
+0+044 <[^>]*> ee30 0a40 (vsub\.f32|fsubs) s0, s0, s0
+0+048 <[^>]*> ed90 0a00 (vldr|flds) s0, \[r0\]
+0+04c <[^>]*> ed80 0a00 (vstr|fsts) s0, \[r0\]
+0+050 <[^>]*> ec90 0a01 (vldmia|fldmias) r0, {s0}
+0+054 <[^>]*> ec90 0a01 (vldmia|fldmias) r0, {s0}
+0+058 <[^>]*> ecb0 0a01 (vldmia|fldmias) r0!, {s0}
+0+05c <[^>]*> ecb0 0a01 (vldmia|fldmias) r0!, {s0}
+0+060 <[^>]*> ed30 0a01 (vldmdb|fldmdbs) r0!, {s0}
+0+064 <[^>]*> ed30 0a01 (vldmdb|fldmdbs) r0!, {s0}
+0+068 <[^>]*> ec90 0b03 fldmiax r0, {d0}( ;@ Deprecated|)
+0+06c <[^>]*> ec90 0b03 fldmiax r0, {d0}( ;@ Deprecated|)
+0+070 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}( ;@ Deprecated|)
+0+074 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}( ;@ Deprecated|)
+0+078 <[^>]*> ed30 0b03 fldmdbx r0!, {d0}( ;@ Deprecated|)
+0+07c <[^>]*> ed30 0b03 fldmdbx r0!, {d0}( ;@ Deprecated|)
+0+080 <[^>]*> ec80 0a01 (vstmia|fstmias) r0, {s0}
+0+084 <[^>]*> ec80 0a01 (vstmia|fstmias) r0, {s0}
+0+088 <[^>]*> eca0 0a01 (vstmia|fstmias) r0!, {s0}
+0+08c <[^>]*> eca0 0a01 (vstmia|fstmias) r0!, {s0}
+0+090 <[^>]*> ed20 0a01 (vstmdb|fstmdbs) r0!, {s0}
+0+094 <[^>]*> ed20 0a01 (vstmdb|fstmdbs) r0!, {s0}
+0+098 <[^>]*> ec80 0b03 fstmiax r0, {d0}( ;@ Deprecated|)
+0+09c <[^>]*> ec80 0b03 fstmiax r0, {d0}( ;@ Deprecated|)
+0+0a0 <[^>]*> eca0 0b03 fstmiax r0!, {d0}( ;@ Deprecated|)
+0+0a4 <[^>]*> eca0 0b03 fstmiax r0!, {d0}( ;@ Deprecated|)
+0+0a8 <[^>]*> ed20 0b03 fstmdbx r0!, {d0}( ;@ Deprecated|)
+0+0ac <[^>]*> ed20 0b03 fstmdbx r0!, {d0}( ;@ Deprecated|)
+0+0b0 <[^>]*> eeb8 0ac0 (vcvt\.f32\.s32|fsitos) s0, s0
+0+0b4 <[^>]*> eeb8 0a40 (vcvt\.f32\.u32|fuitos) s0, s0
+0+0b8 <[^>]*> eebd 0a40 (vcvtr\.s32\.f32|ftosis) s0, s0
+0+0bc <[^>]*> eebd 0ac0 (vcvt\.s32\.f32|ftosizs) s0, s0
+0+0c0 <[^>]*> eebc 0a40 (vcvtr\.u32\.f32|ftouis) s0, s0
+0+0c4 <[^>]*> eebc 0ac0 (vcvt\.u32\.f32|ftouizs) s0, s0
+0+0c8 <[^>]*> ee10 0a10 (vmov|fmrs) r0, s0
+0+0cc <[^>]*> eef0 0a10 (vmrs|fmrx) r0, fpsid
+0+0d0 <[^>]*> eef1 0a10 (vmrs|fmrx) r0, fpscr
+0+0d4 <[^>]*> eef8 0a10 (vmrs|fmrx) r0, fpexc
+0+0d8 <[^>]*> ee00 0a10 (vmov|fmsr) s0, r0
+0+0dc <[^>]*> eee0 0a10 (vmsr|fmxr) fpsid, r0
+0+0e0 <[^>]*> eee1 0a10 (vmsr|fmxr) fpscr, r0
+0+0e4 <[^>]*> eee8 0a10 (vmsr|fmxr) fpexc, r0
+0+0e8 <[^>]*> eef5 0a40 (vcmp\.f32 s1, #0.0|fcmpzs s1)
+0+0ec <[^>]*> eeb5 1a40 (vcmp\.f32 s2, #0.0|fcmpzs s2)
+0+0f0 <[^>]*> eef5 fa40 (vcmp\.f32 s31, #0.0|fcmpzs s31)
+0+0f4 <[^>]*> eeb4 0a60 (vcmp\.f32|fcmps) s0, s1
+0+0f8 <[^>]*> eeb4 0a41 (vcmp\.f32|fcmps) s0, s2
+0+0fc <[^>]*> eeb4 0a6f (vcmp\.f32|fcmps) s0, s31
+0+100 <[^>]*> eef4 0a40 (vcmp\.f32|fcmps) s1, s0
+0+104 <[^>]*> eeb4 1a40 (vcmp\.f32|fcmps) s2, s0
+0+108 <[^>]*> eef4 fa40 (vcmp\.f32|fcmps) s31, s0
+0+10c <[^>]*> eef4 aa46 (vcmp\.f32|fcmps) s21, s12
+0+110 <[^>]*> eeb1 0a60 (vneg\.f32|fnegs) s0, s1
+0+114 <[^>]*> eeb1 0a41 (vneg\.f32|fnegs) s0, s2
+0+118 <[^>]*> eeb1 0a6f (vneg\.f32|fnegs) s0, s31
+0+11c <[^>]*> eef1 0a40 (vneg\.f32|fnegs) s1, s0
+0+120 <[^>]*> eeb1 1a40 (vneg\.f32|fnegs) s2, s0
+0+124 <[^>]*> eef1 fa40 (vneg\.f32|fnegs) s31, s0
+0+128 <[^>]*> eeb1 6a6a (vneg\.f32|fnegs) s12, s21
+0+12c <[^>]*> ee30 0a20 (vadd\.f32|fadds) s0, s0, s1
+0+130 <[^>]*> ee30 0a01 (vadd\.f32|fadds) s0, s0, s2
+0+134 <[^>]*> ee30 0a2f (vadd\.f32|fadds) s0, s0, s31
+0+138 <[^>]*> ee30 0a80 (vadd\.f32|fadds) s0, s1, s0
+0+13c <[^>]*> ee31 0a00 (vadd\.f32|fadds) s0, s2, s0
+0+140 <[^>]*> ee3f 0a80 (vadd\.f32|fadds) s0, s31, s0
+0+144 <[^>]*> ee70 0a00 (vadd\.f32|fadds) s1, s0, s0
+0+148 <[^>]*> ee30 1a00 (vadd\.f32|fadds) s2, s0, s0
+0+14c <[^>]*> ee70 fa00 (vadd\.f32|fadds) s31, s0, s0
+0+150 <[^>]*> ee3a 6aa2 (vadd\.f32|fadds) s12, s21, s5
+0+154 <[^>]*> eeb8 0ae0 (vcvt\.f32\.s32|fsitos) s0, s1
+0+158 <[^>]*> eeb8 0ac1 (vcvt\.f32\.s32|fsitos) s0, s2
+0+15c <[^>]*> eeb8 0aef (vcvt\.f32\.s32|fsitos) s0, s31
+0+160 <[^>]*> eef8 0ac0 (vcvt\.f32\.s32|fsitos) s1, s0
+0+164 <[^>]*> eeb8 1ac0 (vcvt\.f32\.s32|fsitos) s2, s0
+0+168 <[^>]*> eef8 fac0 (vcvt\.f32\.s32|fsitos) s31, s0
+0+16c <[^>]*> eebd 0a60 (vcvtr\.s32\.f32|ftosis) s0, s1
+0+170 <[^>]*> eebd 0a41 (vcvtr\.s32\.f32|ftosis) s0, s2
+0+174 <[^>]*> eebd 0a6f (vcvtr\.s32\.f32|ftosis) s0, s31
+0+178 <[^>]*> eefd 0a40 (vcvtr\.s32\.f32|ftosis) s1, s0
+0+17c <[^>]*> eebd 1a40 (vcvtr\.s32\.f32|ftosis) s2, s0
+0+180 <[^>]*> eefd fa40 (vcvtr\.s32\.f32|ftosis) s31, s0
+0+184 <[^>]*> ee00 1a10 (vmov|fmsr) s0, r1
+0+188 <[^>]*> ee00 7a10 (vmov|fmsr) s0, r7
+0+18c <[^>]*> ee00 ea10 (vmov|fmsr) s0, lr
+0+190 <[^>]*> ee00 0a90 (vmov|fmsr) s1, r0
+0+194 <[^>]*> ee01 0a10 (vmov|fmsr) s2, r0
+0+198 <[^>]*> ee0f 0a90 (vmov|fmsr) s31, r0
+0+19c <[^>]*> ee0a 7a90 (vmov|fmsr) s21, r7
+0+1a0 <[^>]*> eee0 1a10 (vmsr|fmxr) fpsid, r1
+0+1a4 <[^>]*> eee0 ea10 (vmsr|fmxr) fpsid, lr
+0+1a8 <[^>]*> ee10 0a90 (vmov|fmrs) r0, s1
+0+1ac <[^>]*> ee11 0a10 (vmov|fmrs) r0, s2
+0+1b0 <[^>]*> ee1f 0a90 (vmov|fmrs) r0, s31
+0+1b4 <[^>]*> ee10 1a10 (vmov|fmrs) r1, s0
+0+1b8 <[^>]*> ee10 7a10 (vmov|fmrs) r7, s0
+0+1bc <[^>]*> ee10 ea10 (vmov|fmrs) lr, s0
+0+1c0 <[^>]*> ee15 9a90 (vmov|fmrs) r9, s11
+0+1c4 <[^>]*> eef0 1a10 (vmrs|fmrx) r1, fpsid
+0+1c8 <[^>]*> eef0 ea10 (vmrs|fmrx) lr, fpsid
+0+1cc <[^>]*> ed91 0a00 (vldr|flds) s0, \[r1\]
+0+1d0 <[^>]*> ed9e 0a00 (vldr|flds) s0, \[lr\]
+0+1d4 <[^>]*> ed90 0a00 (vldr|flds) s0, \[r0\]
+0+1d8 <[^>]*> ed90 0aff (vldr|flds) s0, \[r0, #1020\].*
+0+1dc <[^>]*> ed10 0aff (vldr|flds) s0, \[r0, #-1020\].*
+0+1e0 <[^>]*> edd0 0a00 (vldr|flds) s1, \[r0\]
+0+1e4 <[^>]*> ed90 1a00 (vldr|flds) s2, \[r0\]
+0+1e8 <[^>]*> edd0 fa00 (vldr|flds) s31, \[r0\]
+0+1ec <[^>]*> edcc aac9 (vstr|fsts) s21, \[ip, #804\].*
+0+1f0 <[^>]*> ecd0 0a01 (vldmia|fldmias) r0, {s1}
+0+1f4 <[^>]*> ec90 1a01 (vldmia|fldmias) r0, {s2}
+0+1f8 <[^>]*> ecd0 fa01 (vldmia|fldmias) r0, {s31}
+0+1fc <[^>]*> ec90 0a02 (vldmia|fldmias) r0, {s0-s1}
+0+200 <[^>]*> ec90 0a03 (vldmia|fldmias) r0, {s0-s2}
+0+204 <[^>]*> ec90 0a20 (vldmia|fldmias) r0, {s0-s31}
+0+208 <[^>]*> ecd0 0a1f (vldmia|fldmias) r0, {s1-s31}
+0+20c <[^>]*> ec90 1a1e (vldmia|fldmias) r0, {s2-s31}
+0+210 <[^>]*> ec90 fa02 (vldmia|fldmias) r0, {s30-s31}
+0+214 <[^>]*> ec91 0a01 (vldmia|fldmias) r1, {s0}
+0+218 <[^>]*> ec9e 0a01 (vldmia|fldmias) lr, {s0}
+0+21c <[^>]*> ec80 1b03 fstmiax r0, {d1}( ;@ Deprecated|)
+0+220 <[^>]*> ec80 2b03 fstmiax r0, {d2}( ;@ Deprecated|)
+0+224 <[^>]*> ec80 fb03 fstmiax r0, {d15}( ;@ Deprecated|)
+0+228 <[^>]*> ec80 0b05 fstmiax r0, {d0-d1}( ;@ Deprecated|)
+0+22c <[^>]*> ec80 0b07 fstmiax r0, {d0-d2}( ;@ Deprecated|)
+0+230 <[^>]*> ec80 0b21 fstmiax r0, {d0-d15}( ;@ Deprecated|)
+0+234 <[^>]*> ec80 1b1f fstmiax r0, {d1-d15}( ;@ Deprecated|)
+0+238 <[^>]*> ec80 2b1d fstmiax r0, {d2-d15}( ;@ Deprecated|)
+0+23c <[^>]*> ec80 eb05 fstmiax r0, {d14-d15}( ;@ Deprecated|)
+0+240 <[^>]*> ec81 0b03 fstmiax r1, {d0}( ;@ Deprecated|)
+0+244 <[^>]*> ec8e 0b03 fstmiax lr, {d0}( ;@ Deprecated|)
+0+248 <[^>]*> eeb5 0a40 (vcmp\.f32 s0, #0.0|fcmpzs s0)
+0+24c <[^>]*> eef5 0a40 (vcmp\.f32 s1, #0.0|fcmpzs s1)
+0+250 <[^>]*> eeb5 1a40 (vcmp\.f32 s2, #0.0|fcmpzs s2)
+0+254 <[^>]*> eef5 1a40 (vcmp\.f32 s3, #0.0|fcmpzs s3)
+0+258 <[^>]*> eeb5 2a40 (vcmp\.f32 s4, #0.0|fcmpzs s4)
+0+25c <[^>]*> eef5 2a40 (vcmp\.f32 s5, #0.0|fcmpzs s5)
+0+260 <[^>]*> eeb5 3a40 (vcmp\.f32 s6, #0.0|fcmpzs s6)
+0+264 <[^>]*> eef5 3a40 (vcmp\.f32 s7, #0.0|fcmpzs s7)
+0+268 <[^>]*> eeb5 4a40 (vcmp\.f32 s8, #0.0|fcmpzs s8)
+0+26c <[^>]*> eef5 4a40 (vcmp\.f32 s9, #0.0|fcmpzs s9)
+0+270 <[^>]*> eeb5 5a40 (vcmp\.f32 s10, #0.0|fcmpzs s10)
+0+274 <[^>]*> eef5 5a40 (vcmp\.f32 s11, #0.0|fcmpzs s11)
+0+278 <[^>]*> eeb5 6a40 (vcmp\.f32 s12, #0.0|fcmpzs s12)
+0+27c <[^>]*> eef5 6a40 (vcmp\.f32 s13, #0.0|fcmpzs s13)
+0+280 <[^>]*> eeb5 7a40 (vcmp\.f32 s14, #0.0|fcmpzs s14)
+0+284 <[^>]*> eef5 7a40 (vcmp\.f32 s15, #0.0|fcmpzs s15)
+0+288 <[^>]*> eeb5 8a40 (vcmp\.f32 s16, #0.0|fcmpzs s16)
+0+28c <[^>]*> eef5 8a40 (vcmp\.f32 s17, #0.0|fcmpzs s17)
+0+290 <[^>]*> eeb5 9a40 (vcmp\.f32 s18, #0.0|fcmpzs s18)
+0+294 <[^>]*> eef5 9a40 (vcmp\.f32 s19, #0.0|fcmpzs s19)
+0+298 <[^>]*> eeb5 aa40 (vcmp\.f32 s20, #0.0|fcmpzs s20)
+0+29c <[^>]*> eef5 aa40 (vcmp\.f32 s21, #0.0|fcmpzs s21)
+0+2a0 <[^>]*> eeb5 ba40 (vcmp\.f32 s22, #0.0|fcmpzs s22)
+0+2a4 <[^>]*> eef5 ba40 (vcmp\.f32 s23, #0.0|fcmpzs s23)
+0+2a8 <[^>]*> eeb5 ca40 (vcmp\.f32 s24, #0.0|fcmpzs s24)
+0+2ac <[^>]*> eef5 ca40 (vcmp\.f32 s25, #0.0|fcmpzs s25)
+0+2b0 <[^>]*> eeb5 da40 (vcmp\.f32 s26, #0.0|fcmpzs s26)
+0+2b4 <[^>]*> eef5 da40 (vcmp\.f32 s27, #0.0|fcmpzs s27)
+0+2b8 <[^>]*> eeb5 ea40 (vcmp\.f32 s28, #0.0|fcmpzs s28)
+0+2bc <[^>]*> eef5 ea40 (vcmp\.f32 s29, #0.0|fcmpzs s29)
+0+2c0 <[^>]*> eeb5 fa40 (vcmp\.f32 s30, #0.0|fcmpzs s30)
+0+2c4 <[^>]*> eef5 fa40 (vcmp\.f32 s31, #0.0|fcmpzs s31)
+0+2c8 <[^>]*> bf01 itttt eq
+0+2ca <[^>]*> eef1 fa10 (vmrseq APSR_nzcv, fpscr|fmstateq)
+0+2ce <[^>]*> eef4 1ae3 (vcmpeeq\.f32|fcmpeseq) s3, s7
+0+2d2 <[^>]*> eef5 2ac0 (vcmpeeq\.f32 s5, #0.0|fcmpezseq s5)
+0+2d6 <[^>]*> eef4 0a41 (vcmpeq\.f32|fcmpseq) s1, s2
+0+2da <[^>]*> bf01 itttt eq
+0+2dc <[^>]*> eef5 0a40 (vcmpeq\.f32 s1, #0.0|fcmpzseq s1)
+0+2e0 <[^>]*> eef0 0ae1 (vabseq\.f32|fabsseq) s1, s3
+0+2e4 <[^>]*> eef0 fa69 (vmoveq\.f32|fcpyseq) s31, s19
+0+2e8 <[^>]*> eeb1 aa44 (vnegeq\.f32|fnegseq) s20, s8
+0+2ec <[^>]*> bf01 itttt eq
+0+2ee <[^>]*> eef1 2ae3 (vsqrteq\.f32|fsqrtseq) s5, s7
+0+2f2 <[^>]*> ee32 3a82 (vaddeq\.f32|faddseq) s6, s5, s4
+0+2f6 <[^>]*> eec1 1a20 (vdiveq\.f32|fdivseq) s3, s2, s1
+0+2fa <[^>]*> ee4f fa2e (vmlaeq\.f32|fmacseq) s31, s30, s29
+0+2fe <[^>]*> bf01 itttt eq
+0+300 <[^>]*> ee1d ea8d (vnmlseq\.f32|fmscseq) s28, s27, s26
+0+304 <[^>]*> ee6c ca2b (vmuleq\.f32|fmulseq) s25, s24, s23
+0+308 <[^>]*> ee0a baca (vmlseq\.f32|fnmacseq) s22, s21, s20
+0+30c <[^>]*> ee59 9a68 (vnmlaeq\.f32|fnmscseq) s19, s18, s17
+0+310 <[^>]*> bf01 itttt eq
+0+312 <[^>]*> ee27 8ac7 (vnmuleq\.f32|fnmulseq) s16, s15, s14
+0+316 <[^>]*> ee76 6a65 (vsubeq\.f32|fsubseq) s13, s12, s11
+0+31a <[^>]*> ed98 5a00 (vldreq|fldseq) s10, \[r8\]
+0+31e <[^>]*> edc7 4a00 (vstreq|fstseq) s9, \[r7\]
+0+322 <[^>]*> bf01 itttt eq
+0+324 <[^>]*> ec91 4a01 (vldmiaeq|fldmiaseq) r1, {s8}
+0+328 <[^>]*> ecd2 3a01 (vldmiaeq|fldmiaseq) r2, {s7}
+0+32c <[^>]*> ecb3 3a01 (vldmiaeq|fldmiaseq) r3!, {s6}
+0+330 <[^>]*> ecf4 2a01 (vldmiaeq|fldmiaseq) r4!, {s5}
+0+334 <[^>]*> bf01 itttt eq
+0+336 <[^>]*> ed35 2a01 (vldmdbeq|fldmdbseq) r5!, {s4}
+0+33a <[^>]*> ed76 1a01 (vldmdbeq|fldmdbseq) r6!, {s3}
+0+33e <[^>]*> ec97 1b03 fldmiaxeq r7, {d1}( ;@ Deprecated|)
+0+342 <[^>]*> ec98 2b03 fldmiaxeq r8, {d2}( ;@ Deprecated|)
+0+346 <[^>]*> bf01 itttt eq
+0+348 <[^>]*> ecb9 3b03 fldmiaxeq r9!, {d3}( ;@ Deprecated|)
+0+34c <[^>]*> ecba 4b03 fldmiaxeq sl!, {d4}( ;@ Deprecated|)
+0+350 <[^>]*> ed3b 5b03 fldmdbxeq fp!, {d5}( ;@ Deprecated|)
+0+354 <[^>]*> ed3c 6b03 fldmdbxeq ip!, {d6}( ;@ Deprecated|)
+0+358 <[^>]*> bf01 itttt eq
+0+35a <[^>]*> ec8d 1a01 (vstmiaeq|fstmiaseq) sp, {s2}
+0+35e <[^>]*> ecce 0a01 (vstmiaeq|fstmiaseq) lr, {s1}
+0+362 <[^>]*> ece1 fa01 (vstmiaeq|fstmiaseq) r1!, {s31}
+0+366 <[^>]*> eca2 fa01 (vstmiaeq|fstmiaseq) r2!, {s30}
+0+36a <[^>]*> bf01 itttt eq
+0+36c <[^>]*> ed63 ea01 (vstmdbeq|fstmdbseq) r3!, {s29}
+0+370 <[^>]*> ed24 ea01 (vstmdbeq|fstmdbseq) r4!, {s28}
+0+374 <[^>]*> ec85 7b03 fstmiaxeq r5, {d7}( ;@ Deprecated|)
+0+378 <[^>]*> ec86 8b03 fstmiaxeq r6, {d8}( ;@ Deprecated|)
+0+37c <[^>]*> bf01 itttt eq
+0+37e <[^>]*> eca7 9b03 fstmiaxeq r7!, {d9}( ;@ Deprecated|)
+0+382 <[^>]*> eca8 ab03 fstmiaxeq r8!, {d10}( ;@ Deprecated|)
+0+386 <[^>]*> ed29 bb03 fstmdbxeq r9!, {d11}( ;@ Deprecated|)
+0+38a <[^>]*> ed2a cb03 fstmdbxeq sl!, {d12}( ;@ Deprecated|)
+0+38e <[^>]*> bf01 itttt eq
+0+390 <[^>]*> eef8 dac3 (vcvteq\.f32\.s32|fsitoseq) s27, s6
+0+394 <[^>]*> eefd ca62 (vcvtreq\.s32\.f32|ftosiseq) s25, s5
+0+398 <[^>]*> eefd bac2 (vcvteq\.s32\.f32|ftosizseq) s23, s4
+0+39c <[^>]*> eefc aa61 (vcvtreq\.u32\.f32|ftouiseq) s21, s3
+0+3a0 <[^>]*> bf01 itttt eq
+0+3a2 <[^>]*> eefc 9ac1 (vcvteq\.u32\.f32|ftouizseq) s19, s2
+0+3a6 <[^>]*> eef8 8a60 (vcvteq\.f32\.u32|fuitoseq) s17, s1
+0+3aa <[^>]*> ee11 ba90 (vmoveq|fmrseq) fp, s3
+0+3ae <[^>]*> eef0 9a10 (vmrseq|fmrxeq) r9, fpsid
+0+3b2 <[^>]*> bf04 itt eq
+0+3b4 <[^>]*> ee01 9a90 (vmoveq|fmsreq) s3, r9
+0+3b8 <[^>]*> eee0 8a10 (vmsreq|fmxreq) fpsid, r8
+0+3bc <[^>]*> eef9 0a10 (vmrs|fmrx) r0, fpinst @ Impl def
+0+3c0 <[^>]*> eefa 0a10 (vmrs|fmrx) r0, fpinst2 @ Impl def
+0+3c4 <[^>]*> eef7 0a10 (vmrs|fmrx) r0, mvfr0
+0+3c8 <[^>]*> eef6 0a10 (vmrs|fmrx) r0, mvfr1
+0+3cc <[^>]*> eefc 0a10 (vmrs|fmrx) r0, (<impl def 0xc>|vpr)
+0+3d0 <[^>]*> eee9 0a10 (vmsr|fmxr) fpinst, r0 @ Impl def
+0+3d4 <[^>]*> eeea 0a10 (vmsr|fmxr) fpinst2, r0 @ Impl def
+0+3d8 <[^>]*> eee7 0a10 (vmsr|fmxr) mvfr0, r0
+0+3dc <[^>]*> eee6 0a10 (vmsr|fmxr) mvfr1, r0
+0+3e0 <[^>]*> eeec 0a10 (vmsr|fmxr) (<impl def 0xc>|vpr), r0
+0+3e4 <[^>]*> bf00 nop
+0+3e6 <[^>]*> bf00 nop
+0+3e8 <[^>]*> bf00 nop
+0+3ea <[^>]*> bf00 nop
+0+3ec <[^>]*> bf00 nop
+0+3ee <[^>]*> bf00 nop
diff --git a/gas/testsuite/gas/arm/armv8.1-m.main-hp.d b/gas/testsuite/gas/arm/armv8.1-m.main-hp.d
new file mode 100644
index 0000000000000000000000000000000000000000..1743d1e19cdc943d24cdfc756e67c5a52ff8f435
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8.1-m.main-hp.d
@@ -0,0 +1,75 @@
+# name: Half precision instructions for 'armv8.1-m.main'
+# source: armv8-2-fp16-scalar.s
+# as: -march=armv8.1-m.main+fp
+# objdump: -d
+# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
+
+.*: +file format .*arm.*
+Disassembly of section .text:
+
+00000000 <label-0xc>:
+ 0: ee00 1910 vmov.f16 s0, r1
+ 4: ee10 0990 vmov.f16 r0, s1
+ 8: eeb0 0900 vmov.f16 s0, #0 ; 0x40000000 2.0
+
+0000000c <label>:
+ c: 00000ffe .word 0x00000ffe
+ 10: ed5f 1904 vldr.16 s3, \[pc, #-8\] ; c <label>
+ 14: ed1f 3902 vldr.16 s6, \[pc, #-4\] ; 14 <label\+0x8>
+ 18: eddf 1902 vldr.16 s3, \[pc, #4\] ; 20 <label\+0x14>
+ 1c: edd0 0902 vldr.16 s1, \[r0, #4\]
+ 20: ed10 1902 vldr.16 s2, \[r0, #-4\]
+ 24: ed80 3902 vstr.16 s6, \[r0, #4\]
+ 28: ed40 5902 vstr.16 s11, \[r0, #-4\]
+ 2c: eec6 298c vdiv.f16 s5, s13, s24
+ 30: eee6 298c vfma.f16 s5, s13, s24
+ 34: eee6 29cc vfms.f16 s5, s13, s24
+ 38: eed6 29cc vfnma.f16 s5, s13, s24
+ 3c: eed6 298c vfnms.f16 s5, s13, s24
+ 40: fec6 298c vmaxnm.f16 s5, s13, s24
+ 44: fec6 29cc vminnm.f16 s5, s13, s24
+ 48: ee46 298c vmla.f16 s5, s13, s24
+ 4c: ee46 29cc vmls.f16 s5, s13, s24
+ 50: ee66 298c vmul.f16 s5, s13, s24
+ 54: ee56 29cc vnmla.f16 s5, s13, s24
+ 58: ee56 298c vnmls.f16 s5, s13, s24
+ 5c: ee66 29cc vnmul.f16 s5, s13, s24
+ 60: ee76 29cc vsub.f16 s5, s13, s24
+ 64: eef0 29c6 vabs.f16 s5, s12
+ 68: ee72 2986 vadd.f16 s5, s5, s12
+ 6c: eef1 29c6 vsqrt.f16 s5, s12
+ 70: eef1 2946 vneg.f16 s5, s12
+ 74: eeb5 1940 vcmp.f16 s2, #0.0
+ 78: eeb5 19c0 vcmpe.f16 s2, #0.0
+ 7c: eef4 2966 vcmp.f16 s5, s13
+ 80: eef4 29e6 vcmpe.f16 s5, s13
+ 84: fe46 29ab vseleq.f16 s5, s13, s23
+ 88: fe66 29ab vselge.f16 s5, s13, s23
+ 8c: fe56 29ab vselvs.f16 s5, s13, s23
+ 90: eefd 19c4 vcvt.s32.f16 s3, s8
+ 94: eefc 19c4 vcvt.u32.f16 s3, s8
+ 98: eef8 19c4 vcvt.f16.s32 s3, s8
+ 9c: eef8 1944 vcvt.f16.u32 s3, s8
+ a0: eefa 39e1 vcvt.f16.s32 s7, s7, #29
+ a4: eefb 39e1 vcvt.f16.u32 s7, s7, #29
+ a8: eefe 39e1 vcvt.s32.f16 s7, s7, #29
+ ac: eeff 39e1 vcvt.u32.f16 s7, s7, #29
+ b0: fefc 29c5 vcvta.s32.f16 s5, s10
+ b4: fefc 2945 vcvta.u32.f16 s5, s10
+ b8: feff 29c5 vcvtm.s32.f16 s5, s10
+ bc: feff 2945 vcvtm.u32.f16 s5, s10
+ c0: fefd 29c5 vcvtn.s32.f16 s5, s10
+ c4: fefd 2945 vcvtn.u32.f16 s5, s10
+ c8: fefe 29c5 vcvtp.s32.f16 s5, s10
+ cc: fefe 2945 vcvtp.u32.f16 s5, s10
+ d0: eefc 2945 vcvtr.u32.f16 s5, s10
+ d4: eefd 2945 vcvtr.s32.f16 s5, s10
+ d8: fef8 1965 vrinta.f16 s3, s11
+ dc: fefb 1965 vrintm.f16 s3, s11
+ e0: fef9 1965 vrintn.f16 s3, s11
+ e4: fefa 1965 vrintp.f16 s3, s11
+ e8: eef6 1965 vrintr.f16 s3, s11
+ ec: eef7 1965 vrintx.f16 s3, s11
+ f0: eef6 19e5 vrintz.f16 s3, s11
+ f4: fef0 2ae4 vins.f16 s5, s9
+ f8: fef0 2a64 vmovx.f16 s5, s9
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH, binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI
2019-04-04 13:24 [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Andre Vieira (lists)
@ 2019-04-04 13:28 ` Andre Vieira (lists)
2019-04-04 13:28 ` [PATCH, GAS, ARM, 2/16] Add CLI extension support for Armv8.1-M Mainline Andre Vieira (lists)
` (15 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-04 13:28 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 2820 bytes --]
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline architecture. Its purpose is to add the command-line support to
assemble and link targeting Armv8.1-M Mainline architecture.
=== Patch description ===
The patch is straightforward, it does the following:
- support the new Tag_CPU_arch build attribute value, ie.:
+ declare the new value
+ update all the asserts forcing logic to be reviewed for new
architectures
+ create a corresponding bfd_mach_arm_8_1M_MAIN enumerator in bfd and
add mapping from Tag_CPU_arch to it
+ teach readelf about new Tag_CPU_arch value
- declare armv8.1-m.main as a supported architecture value
- define Armv8.1-M Mainline in terms of feature bits available
- tell objdump mapping from bfd_mach_arm_8_1M_MAIN enumerator to feature
bits available
- update architecture-specific logic in gas and bfd guarded by the
asserts mentioned above.
- tests for all the above
ChangeLog entries are as follows:
*** bfd/ChangeLog ***
2019-04-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
* archures.c (bfd_mach_arm_8_1M_MAIN): Define.
* bfd-in2.h: Regenerate.
* cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline.
* elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline
and update assert.
(using_thumb2): Likewise.
(using_thumb2_bl): Update assert.
(arch_has_arm_nop): Likewise.
(bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline.
(tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging.
*** binutils/ChangeLog ***
2019-04-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
* readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline.
*** gas/ChangeLog ***
2019-04-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline
Tag_CPU_arch build attribute value. Reindent.
(get_aeabi_cpu_arch_from_fset): Update assert.
(aeabi_set_public_attributes): Update assert for Tag_DIV_use logic.
* testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test.
*** include/ChangeLog ***
2019-04-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
* elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro.
(MAX_TAG_CPU_ARCH): Set value to above macro.
* opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro.
(ARM_AEXT_V8_1M_MAIN): Likewise.
(ARM_AEXT2_V8_1M_MAIN): Likewise.
(ARM_ARCH_V8_1M_MAIN): Likewise.
*** ld/ChangeLog ***
2019-04-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
* testsuite/ld-arm/attr-merge-13.attr: New test.
* testsuite/ld-arm/attr-merge-13a.s: New test.
* testsuite/ld-arm/attr-merge-13b.s: New test.
*** opcodes/ChangeLog ***
2019-04-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
[-- Attachment #2: 1.patch --]
[-- Type: text/x-patch, Size: 17384 bytes --]
diff --git a/bfd/archures.c b/bfd/archures.c
index 647cf0d8d4273651c211cb867bb7f1690e5c4937..aaf2e112cf9413aebd16484b0ab9fda87ea438c2 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -341,6 +341,7 @@ DESCRIPTION
.#define bfd_mach_arm_8R 24
.#define bfd_mach_arm_8M_BASE 25
.#define bfd_mach_arm_8M_MAIN 26
+.#define bfd_mach_arm_8_1M_MAIN 27
. bfd_arch_nds32, {* Andes NDS32. *}
.#define bfd_mach_n1 1
.#define bfd_mach_n1h 2
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 33a29406ae3f4786e1ccb727e29736c2179f122c..4f63fe50e6bf8003fb25beec9e64927a672e444b 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -2274,6 +2274,7 @@ enum bfd_architecture
#define bfd_mach_arm_8R 24
#define bfd_mach_arm_8M_BASE 25
#define bfd_mach_arm_8M_MAIN 26
+#define bfd_mach_arm_8_1M_MAIN 27
bfd_arch_nds32, /* Andes NDS32. */
#define bfd_mach_n1 1
#define bfd_mach_n1h 2
diff --git a/bfd/cpu-arm.c b/bfd/cpu-arm.c
index 568fdbfaeec4622e202f7451721bf851bbda640b..5a5da93cb4df61cc9bced426bb58622b5ef627c6 100644
--- a/bfd/cpu-arm.c
+++ b/bfd/cpu-arm.c
@@ -248,6 +248,7 @@ static const bfd_arch_info_type arch_info_struct[] =
N (bfd_mach_arm_8R, "armv8-r", FALSE, & arch_info_struct[24]),
N (bfd_mach_arm_8M_BASE, "armv8-m.base", FALSE, & arch_info_struct[25]),
N (bfd_mach_arm_8M_MAIN, "armv8-m.main", FALSE, & arch_info_struct[26]),
+ N (bfd_mach_arm_8_1M_MAIN, "armv8.1-m.main", FALSE, & arch_info_struct[27]),
N (bfd_mach_arm_unknown, "arm_any", FALSE, NULL)
};
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 28ee9d55a85cf8f998f1720d0f7d00304bae940b..735fe122880c59633b0083b78b9b1e686cfd91c5 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -3835,13 +3835,14 @@ using_thumb_only (struct elf32_arm_link_hash_table *globals)
arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
/* Force return logic to be reviewed for each new architecture. */
- BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
+ BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
if (arch == TAG_CPU_ARCH_V6_M
|| arch == TAG_CPU_ARCH_V6S_M
|| arch == TAG_CPU_ARCH_V7E_M
|| arch == TAG_CPU_ARCH_V8M_BASE
- || arch == TAG_CPU_ARCH_V8M_MAIN)
+ || arch == TAG_CPU_ARCH_V8M_MAIN
+ || arch == TAG_CPU_ARCH_V8_1M_MAIN)
return TRUE;
return FALSE;
@@ -3862,14 +3863,15 @@ using_thumb2 (struct elf32_arm_link_hash_table *globals)
arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
/* Force return logic to be reviewed for each new architecture. */
- BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
+ BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
return (arch == TAG_CPU_ARCH_V6T2
|| arch == TAG_CPU_ARCH_V7
|| arch == TAG_CPU_ARCH_V7E_M
|| arch == TAG_CPU_ARCH_V8
|| arch == TAG_CPU_ARCH_V8R
- || arch == TAG_CPU_ARCH_V8M_MAIN);
+ || arch == TAG_CPU_ARCH_V8M_MAIN
+ || arch == TAG_CPU_ARCH_V8_1M_MAIN);
}
/* Determine whether Thumb-2 BL instruction is available. */
@@ -3881,7 +3883,7 @@ using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
/* Force return logic to be reviewed for each new architecture. */
- BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
+ BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
/* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
return (arch == TAG_CPU_ARCH_V6T2
@@ -4101,7 +4103,7 @@ arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
Tag_CPU_arch);
/* Force return logic to be reviewed for each new architecture. */
- BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
+ BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
return (arch == TAG_CPU_ARCH_V6T2
|| arch == TAG_CPU_ARCH_V6K
@@ -13718,6 +13720,8 @@ bfd_arm_get_mach_from_attributes (bfd * abfd)
return bfd_mach_arm_8M_BASE;
case TAG_CPU_ARCH_V8M_MAIN:
return bfd_mach_arm_8M_MAIN;
+ case TAG_CPU_ARCH_V8_1M_MAIN:
+ return bfd_mach_arm_8_1M_MAIN;
default:
/* Force entry to be added for any new known Tag_CPU_arch value. */
@@ -14130,6 +14134,31 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
T(V8M_MAIN), /* V8-M BASELINE. */
T(V8M_MAIN) /* V8-M MAINLINE. */
};
+ const int v8_1m_mainline[] =
+ {
+ -1, /* PRE_V4. */
+ -1, /* V4. */
+ -1, /* V4T. */
+ -1, /* V5T. */
+ -1, /* V5TE. */
+ -1, /* V5TEJ. */
+ -1, /* V6. */
+ -1, /* V6KZ. */
+ -1, /* V6T2. */
+ -1, /* V6K. */
+ T(V8_1M_MAIN), /* V7. */
+ T(V8_1M_MAIN), /* V6_M. */
+ T(V8_1M_MAIN), /* V6S_M. */
+ T(V8_1M_MAIN), /* V7E_M. */
+ -1, /* V8. */
+ -1, /* V8R. */
+ T(V8_1M_MAIN), /* V8-M BASELINE. */
+ T(V8_1M_MAIN), /* V8-M MAINLINE. */
+ -1, /* Unused (18). */
+ -1, /* Unused (19). */
+ -1, /* Unused (20). */
+ T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
+ };
const int v4t_plus_v6_m[] =
{
-1, /* PRE_V4. */
@@ -14150,6 +14179,10 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
-1, /* V8R. */
T(V8M_BASE), /* V8-M BASELINE. */
T(V8M_MAIN), /* V8-M MAINLINE. */
+ -1, /* Unused (18). */
+ -1, /* Unused (19). */
+ -1, /* Unused (20). */
+ T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
};
const int *comb[] =
@@ -14164,6 +14197,10 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
v8r,
v8m_baseline,
v8m_mainline,
+ NULL,
+ NULL,
+ NULL,
+ v8_1m_mainline,
/* Pseudo-architecture. */
v4t_plus_v6_m
};
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 5a9d9ff433d5438e073e871b9c92d307d9f279d3..1fe71824776d979365ae936c6e35af8558da2683 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -14370,7 +14370,7 @@ typedef struct
static const char * arm_attr_tag_CPU_arch[] =
{"Pre-v4", "v4", "v4T", "v5T", "v5TE", "v5TEJ", "v6", "v6KZ", "v6T2",
"v6K", "v7", "v6-M", "v6S-M", "v7E-M", "v8", "v8-R", "v8-M.baseline",
- "v8-M.mainline"};
+ "v8-M.mainline", "", "", "", "v8.1-M.mainline"};
static const char * arm_attr_tag_ARM_ISA_use[] = {"No", "Yes"};
static const char * arm_attr_tag_THUMB_ISA_use[] =
{"No", "Thumb-1", "Thumb-2", "Yes"};
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 4218d059d6d4cbe922c4eb8215afaee5d39c18e3..4f96066cc5f32b9a07d2f8b6a146ea2788f61f07 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -26570,6 +26570,7 @@ static const struct arm_arch_option_table arm_archs[] =
ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP),
ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP,
armv8m_main),
+ ARM_ARCH_OPT ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN, FPU_ARCH_VFP),
ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP, armv8a),
ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP, armv81a),
ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP, armv82a),
@@ -27284,30 +27285,30 @@ typedef struct
stable when new architectures are added. */
static const cpu_arch_ver_table cpu_arch_ver[] =
{
- {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1},
- {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2},
- {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S},
- {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3},
- {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M},
- {TAG_CPU_ARCH_V4, ARM_ARCH_V4xM},
- {TAG_CPU_ARCH_V4, ARM_ARCH_V4},
- {TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM},
- {TAG_CPU_ARCH_V4T, ARM_ARCH_V4T},
- {TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM},
- {TAG_CPU_ARCH_V5T, ARM_ARCH_V5},
- {TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM},
- {TAG_CPU_ARCH_V5T, ARM_ARCH_V5T},
- {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP},
- {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE},
- {TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ},
- {TAG_CPU_ARCH_V6, ARM_ARCH_V6},
- {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z},
- {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ},
- {TAG_CPU_ARCH_V6K, ARM_ARCH_V6K},
- {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2},
- {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2},
- {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2},
- {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2},
+ {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1},
+ {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2},
+ {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S},
+ {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3},
+ {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M},
+ {TAG_CPU_ARCH_V4, ARM_ARCH_V4xM},
+ {TAG_CPU_ARCH_V4, ARM_ARCH_V4},
+ {TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM},
+ {TAG_CPU_ARCH_V4T, ARM_ARCH_V4T},
+ {TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM},
+ {TAG_CPU_ARCH_V5T, ARM_ARCH_V5},
+ {TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM},
+ {TAG_CPU_ARCH_V5T, ARM_ARCH_V5T},
+ {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP},
+ {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE},
+ {TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ},
+ {TAG_CPU_ARCH_V6, ARM_ARCH_V6},
+ {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z},
+ {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ},
+ {TAG_CPU_ARCH_V6K, ARM_ARCH_V6K},
+ {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2},
+ {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2},
+ {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2},
+ {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2},
/* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
always selected build attributes to match those of ARMv6-M
@@ -27316,25 +27317,26 @@ static const cpu_arch_ver_table cpu_arch_ver[] =
would be selected when fully respecting chronology of architectures.
It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
move them before ARMv7 architectures. */
- {TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M},
- {TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM},
-
- {TAG_CPU_ARCH_V7, ARM_ARCH_V7},
- {TAG_CPU_ARCH_V7, ARM_ARCH_V7A},
- {TAG_CPU_ARCH_V7, ARM_ARCH_V7R},
- {TAG_CPU_ARCH_V7, ARM_ARCH_V7M},
- {TAG_CPU_ARCH_V7, ARM_ARCH_V7VE},
- {TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8A},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A},
- {TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE},
- {TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN},
- {TAG_CPU_ARCH_V8R, ARM_ARCH_V8R},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A},
- {-1, ARM_ARCH_NONE}
+ {TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M},
+ {TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM},
+
+ {TAG_CPU_ARCH_V7, ARM_ARCH_V7},
+ {TAG_CPU_ARCH_V7, ARM_ARCH_V7A},
+ {TAG_CPU_ARCH_V7, ARM_ARCH_V7R},
+ {TAG_CPU_ARCH_V7, ARM_ARCH_V7M},
+ {TAG_CPU_ARCH_V7, ARM_ARCH_V7VE},
+ {TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM},
+ {TAG_CPU_ARCH_V8, ARM_ARCH_V8A},
+ {TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A},
+ {TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A},
+ {TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A},
+ {TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE},
+ {TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN},
+ {TAG_CPU_ARCH_V8R, ARM_ARCH_V8R},
+ {TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A},
+ {TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A},
+ {TAG_CPU_ARCH_V8_1M_MAIN, ARM_ARCH_V8_1M_MAIN},
+ {-1, ARM_ARCH_NONE}
};
/* Set an attribute if it has not already been set by the user. */
@@ -27417,7 +27419,7 @@ get_aeabi_cpu_arch_from_fset (const arm_feature_set *arch_ext_fset,
if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any))
{
/* Force revisiting of decision for each new architecture. */
- gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8M_MAIN);
+ gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8_1M_MAIN);
*profile = 'A';
return TAG_CPU_ARCH_V8;
}
@@ -27688,7 +27690,7 @@ aeabi_set_public_attributes (void)
by the base architecture.
For new architectures we will have to check these tests. */
- gas_assert (arch <= TAG_CPU_ARCH_V8M_MAIN);
+ gas_assert (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
|| ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
aeabi_set_attribute_int (Tag_DIV_use, 0);
diff --git a/gas/testsuite/gas/arm/attr-march-armv8_1-m.main.d b/gas/testsuite/gas/arm/attr-march-armv8_1-m.main.d
new file mode 100644
index 0000000000000000000000000000000000000000..acae2e31fe1afed95ee6a9466fbec13f45d05740
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-march-armv8_1-m.main.d
@@ -0,0 +1,13 @@
+# name: attributes for -march=armv8.1-m.main
+# source: blank.s
+# as: -march=armv8.1-m.main
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "8.1-M.MAIN"
+ Tag_CPU_arch: v8.1-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
diff --git a/include/elf/arm.h b/include/elf/arm.h
index 13f20002c25e126ad266b166c6e21125c57a4aaf..daf1d94391ea23c49cb646af430d2db8ef46c51e 100644
--- a/include/elf/arm.h
+++ b/include/elf/arm.h
@@ -111,7 +111,8 @@
#define TAG_CPU_ARCH_V8R 15
#define TAG_CPU_ARCH_V8M_BASE 16
#define TAG_CPU_ARCH_V8M_MAIN 17
-#define MAX_TAG_CPU_ARCH TAG_CPU_ARCH_V8M_MAIN
+#define TAG_CPU_ARCH_V8_1M_MAIN 21
+#define MAX_TAG_CPU_ARCH TAG_CPU_ARCH_V8_1M_MAIN
/* Pseudo-architecture to allow objects to be compatible with the subset of
armv4t and armv6-m. This value should never be stored in object files. */
#define TAG_CPU_ARCH_V4T_PLUS_V6_M (MAX_TAG_CPU_ARCH + 1)
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index 4f5c89f8383b419832fea1aca0335553cbe4221d..73fb2e3f43c5fd2d77dc796b7decb329c5a8a57f 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -72,6 +72,7 @@
#define ARM_EXT2_V8_5A 0x00001000 /* ARM V8.5A. */
#define ARM_EXT2_SB 0x00002000 /* Speculation Barrier instruction. */
#define ARM_EXT2_PREDRES 0x00004000 /* Prediction Restriction insns. */
+#define ARM_EXT2_V8_1M_MAIN 0x00008000 /* ARMv8.1-M Mainline. */
/* Co-processor space extensions. */
#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
@@ -175,6 +176,9 @@
#define ARM_AEXT2_V8M_MAIN_DSP ARM_AEXT2_V8M_MAIN
#define ARM_AEXT_V8R ARM_AEXT_V8A
#define ARM_AEXT2_V8R ARM_AEXT2_V8AR
+#define ARM_AEXT_V8_1M_MAIN ARM_AEXT_V8M_MAIN
+#define ARM_AEXT2_V8_1M_MAIN (ARM_AEXT2_V8M_MAIN | ARM_EXT2_V8_1M_MAIN \
+ | ARM_EXT2_FP16_INST)
/* Processors with specific extensions in the co-processor space. */
#define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
@@ -353,6 +357,8 @@
#define ARM_ARCH_V8M_MAIN_DSP ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN_DSP, \
ARM_AEXT2_V8M_MAIN_DSP)
#define ARM_ARCH_V8R ARM_FEATURE_CORE (ARM_AEXT_V8R, ARM_AEXT2_V8R)
+#define ARM_ARCH_V8_1M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8_1M_MAIN, \
+ ARM_AEXT2_V8_1M_MAIN)
/* Some useful combinations: */
#define ARM_ARCH_NONE ARM_FEATURE_LOW (0, 0)
diff --git a/ld/testsuite/ld-arm/attr-merge-13.attr b/ld/testsuite/ld-arm/attr-merge-13.attr
new file mode 100644
index 0000000000000000000000000000000000000000..9fabb5b88e5fbba01ce68d40597e69866e11d7f1
--- /dev/null
+++ b/ld/testsuite/ld-arm/attr-merge-13.attr
@@ -0,0 +1,6 @@
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "8.1-M.MAIN"
+ Tag_CPU_arch: v8.1-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
diff --git a/ld/testsuite/ld-arm/attr-merge-13a.s b/ld/testsuite/ld-arm/attr-merge-13a.s
new file mode 100644
index 0000000000000000000000000000000000000000..5349f7ff3b5ccb0bb5d226b8deed743335d93e44
--- /dev/null
+++ b/ld/testsuite/ld-arm/attr-merge-13a.s
@@ -0,0 +1,5 @@
+ .arch armv8-m.main
+
+ @ Tag_CPU_arch & Tag_CPU_arch_profile = v8-M.mainline
+ .eabi_attribute Tag_CPU_arch, 17
+ .eabi_attribute Tag_CPU_arch_profile, 'M'
diff --git a/ld/testsuite/ld-arm/attr-merge-13b.s b/ld/testsuite/ld-arm/attr-merge-13b.s
new file mode 100644
index 0000000000000000000000000000000000000000..20e075357a94edae8d649f034ab3e17efa3c06d2
--- /dev/null
+++ b/ld/testsuite/ld-arm/attr-merge-13b.s
@@ -0,0 +1,5 @@
+ .arch armv8.1-m.main
+
+ @ Tag_CPU_arch & Tag_CPU_arch_profile = v8.1-M.mainline
+ .eabi_attribute Tag_CPU_arch, 18
+ .eabi_attribute Tag_CPU_arch_profile, 'M'
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 71d7c524a22b0d93e5b0dd1573abbe158cd636e8..be9879da621c14e4dd8a816a371aaad6ccc4a696 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -6464,6 +6464,7 @@ select_arm_features (unsigned long mach,
case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
+ case bfd_mach_arm_8_1M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN); break;
/* If the machine type is unknown allow all architecture types and all
extensions. */
case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH, binutils, ARM, 4/16] BF insns infrastructure with array of relocs in struct arm_it
2019-04-04 13:24 [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Andre Vieira (lists)
2019-04-04 13:28 ` [PATCH, binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI Andre Vieira (lists)
2019-04-04 13:28 ` [PATCH, GAS, ARM, 2/16] Add CLI extension support for Armv8.1-M Mainline Andre Vieira (lists)
@ 2019-04-04 13:34 ` Andre Vieira (lists)
2019-04-04 13:34 ` [PATCH, binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real for fallback branch Andre Vieira (lists)
` (13 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-04 13:34 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 1149 bytes --]
Hi
This patch is part of a series of patches to add support for ARMv8.1-M
Mainline instructions to binutils.
This adds infrastructure for the Branch Future instructions (BF, BFX,
BFL, BFLX, BFCSEL). These are the first instructions in ARM that
have more than one relocations in them. Their external relocations can
be found in the 'ELF for the Arm Architecture - ABI 2019Q1' document on
developer.arm.com (see
https://developer.arm.com/docs/ihi0044/latest/elf-for-the-arm-architecture-abi-2019q1-documentation#aaelf32-table4-9)
This is the second infrastructure patch that adds support to allow up to
3 relocations in an instruction. This is done by changing the
reloc member of struct arm_it to an array instead (relocs[3]). All the
previous occurrences of reloc can now to referring to relocs[0].
Testing: Builds successfully and no regressions.
Thanks
Sudi
ChangeLog entries are as follows :
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (ARM_IT_MAX_RELOCS): New macro.
(arm_it): Member reloc renamed relocs and updated to an array.
Rest: Replace all occurrences of reloc to relocs[0].
[-- Attachment #2: 4.patch --]
[-- Type: text/x-patch, Size: 56125 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index a13baa603486623836977d4c8f68ac283d02cbab..14d114adbeec62b11fa3bc7d4f7cb3cdd030bf8f 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -463,6 +463,7 @@ enum it_instruction_type
/* The maximum number of operands we need. */
#define ARM_IT_MAX_OPERANDS 6
+#define ARM_IT_MAX_RELOCS 3
struct arm_it
{
@@ -487,7 +488,7 @@ struct arm_it
bfd_reloc_code_real_type type;
expressionS exp;
int pc_rel;
- } reloc;
+ } relocs[ARM_IT_MAX_RELOCS];
enum it_instruction_type it_insn_type;
@@ -1791,15 +1792,15 @@ parse_reg_list (char ** strp)
}
else
{
- if (inst.reloc.type != 0)
+ if (inst.relocs[0].type != 0)
{
inst.error = _("expression too complex");
return FAIL;
}
- memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
- inst.reloc.type = BFD_RELOC_ARM_MULTI;
- inst.reloc.pc_rel = 0;
+ memcpy (&inst.relocs[0].exp, &exp, sizeof (expressionS));
+ inst.relocs[0].type = BFD_RELOC_ARM_MULTI;
+ inst.relocs[0].pc_rel = 0;
}
}
@@ -3249,7 +3250,7 @@ add_to_lit_pool (unsigned int nbytes)
{
imm1 = inst.operands[1].imm;
imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg
- : inst.reloc.exp.X_unsigned ? 0
+ : inst.relocs[0].exp.X_unsigned ? 0
: ((bfd_int64_t) inst.operands[1].imm) >> 32);
if (target_big_endian)
{
@@ -3265,23 +3266,23 @@ add_to_lit_pool (unsigned int nbytes)
{
if (nbytes == 4)
{
- if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
- && (inst.reloc.exp.X_op == O_constant)
+ if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
+ && (inst.relocs[0].exp.X_op == O_constant)
&& (pool->literals[entry].X_add_number
- == inst.reloc.exp.X_add_number)
+ == inst.relocs[0].exp.X_add_number)
&& (pool->literals[entry].X_md == nbytes)
&& (pool->literals[entry].X_unsigned
- == inst.reloc.exp.X_unsigned))
+ == inst.relocs[0].exp.X_unsigned))
break;
- if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
- && (inst.reloc.exp.X_op == O_symbol)
+ if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
+ && (inst.relocs[0].exp.X_op == O_symbol)
&& (pool->literals[entry].X_add_number
- == inst.reloc.exp.X_add_number)
+ == inst.relocs[0].exp.X_add_number)
&& (pool->literals[entry].X_add_symbol
- == inst.reloc.exp.X_add_symbol)
+ == inst.relocs[0].exp.X_add_symbol)
&& (pool->literals[entry].X_op_symbol
- == inst.reloc.exp.X_op_symbol)
+ == inst.relocs[0].exp.X_op_symbol)
&& (pool->literals[entry].X_md == nbytes))
break;
}
@@ -3291,11 +3292,11 @@ add_to_lit_pool (unsigned int nbytes)
&& (pool->literals[entry].X_op == O_constant)
&& (pool->literals[entry].X_add_number == (offsetT) imm1)
&& (pool->literals[entry].X_unsigned
- == inst.reloc.exp.X_unsigned)
+ == inst.relocs[0].exp.X_unsigned)
&& (pool->literals[entry + 1].X_op == O_constant)
&& (pool->literals[entry + 1].X_add_number == (offsetT) imm2)
&& (pool->literals[entry + 1].X_unsigned
- == inst.reloc.exp.X_unsigned))
+ == inst.relocs[0].exp.X_unsigned))
break;
padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT);
@@ -3327,8 +3328,8 @@ add_to_lit_pool (unsigned int nbytes)
We also check to make sure the literal operand is a
constant number. */
- if (!(inst.reloc.exp.X_op == O_constant
- || inst.reloc.exp.X_op == O_big))
+ if (!(inst.relocs[0].exp.X_op == O_constant
+ || inst.relocs[0].exp.X_op == O_big))
{
inst.error = _("invalid type for literal pool");
return FAIL;
@@ -3341,7 +3342,7 @@ add_to_lit_pool (unsigned int nbytes)
return FAIL;
}
- pool->literals[entry] = inst.reloc.exp;
+ pool->literals[entry] = inst.relocs[0].exp;
pool->literals[entry].X_op = O_constant;
pool->literals[entry].X_add_number = 0;
pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4;
@@ -3354,22 +3355,22 @@ add_to_lit_pool (unsigned int nbytes)
return FAIL;
}
- pool->literals[entry] = inst.reloc.exp;
+ pool->literals[entry] = inst.relocs[0].exp;
pool->literals[entry].X_op = O_constant;
pool->literals[entry].X_add_number = imm1;
- pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned;
+ pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
pool->literals[entry++].X_md = 4;
- pool->literals[entry] = inst.reloc.exp;
+ pool->literals[entry] = inst.relocs[0].exp;
pool->literals[entry].X_op = O_constant;
pool->literals[entry].X_add_number = imm2;
- pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned;
+ pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
pool->literals[entry].X_md = 4;
pool->alignment = 3;
pool->next_free_entry += 1;
}
else
{
- pool->literals[entry] = inst.reloc.exp;
+ pool->literals[entry] = inst.relocs[0].exp;
pool->literals[entry].X_md = 4;
}
@@ -3385,13 +3386,13 @@ add_to_lit_pool (unsigned int nbytes)
}
else if (padding_slot_p)
{
- pool->literals[entry] = inst.reloc.exp;
+ pool->literals[entry] = inst.relocs[0].exp;
pool->literals[entry].X_md = nbytes;
}
- inst.reloc.exp.X_op = O_symbol;
- inst.reloc.exp.X_add_number = pool_size;
- inst.reloc.exp.X_add_symbol = pool->symbol;
+ inst.relocs[0].exp.X_op = O_symbol;
+ inst.relocs[0].exp.X_add_number = pool_size;
+ inst.relocs[0].exp.X_add_symbol = pool->symbol;
return SUCCESS;
}
@@ -5212,7 +5213,7 @@ parse_shift (char **str, int i, enum parse_shift_mode mode)
inst.operands[i].imm = reg;
inst.operands[i].immisreg = 1;
}
- else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
+ else if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
return FAIL;
}
inst.operands[i].shift_kind = shift;
@@ -5244,8 +5245,8 @@ parse_shifter_operand (char **str, int i)
inst.operands[i].isreg = 1;
/* parse_shift will override this if appropriate */
- inst.reloc.exp.X_op = O_constant;
- inst.reloc.exp.X_add_number = 0;
+ inst.relocs[0].exp.X_op = O_constant;
+ inst.relocs[0].exp.X_add_number = 0;
if (skip_past_comma (str) == FAIL)
return SUCCESS;
@@ -5254,7 +5255,7 @@ parse_shifter_operand (char **str, int i)
return parse_shift (str, i, NO_SHIFT_RESTRICT);
}
- if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
+ if (my_get_expression (&inst.relocs[0].exp, str, GE_IMM_PREFIX))
return FAIL;
if (skip_past_comma (str) == SUCCESS)
@@ -5263,7 +5264,7 @@ parse_shifter_operand (char **str, int i)
if (my_get_expression (&exp, str, GE_NO_PREFIX))
return FAIL;
- if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
+ if (exp.X_op != O_constant || inst.relocs[0].exp.X_op != O_constant)
{
inst.error = _("constant expression expected");
return FAIL;
@@ -5275,19 +5276,20 @@ parse_shifter_operand (char **str, int i)
inst.error = _("invalid rotation");
return FAIL;
}
- if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
+ if (inst.relocs[0].exp.X_add_number < 0
+ || inst.relocs[0].exp.X_add_number > 255)
{
inst.error = _("invalid constant");
return FAIL;
}
/* Encode as specified. */
- inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
+ inst.operands[i].imm = inst.relocs[0].exp.X_add_number | value << 7;
return SUCCESS;
}
- inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
- inst.reloc.pc_rel = 0;
+ inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
+ inst.relocs[0].pc_rel = 0;
return SUCCESS;
}
@@ -5458,12 +5460,12 @@ parse_shifter_operand_group_reloc (char **str, int i)
/* We now have the group relocation table entry corresponding to
the name in the assembler source. Next, we parse the expression. */
- if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
+ if (my_get_expression (&inst.relocs[0].exp, str, GE_NO_PREFIX))
return PARSE_OPERAND_FAIL_NO_BACKTRACK;
/* Record the relocation type (always the ALU variant here). */
- inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
- gas_assert (inst.reloc.type != 0);
+ inst.relocs[0].type = (bfd_reloc_code_real_type) entry->alu_code;
+ gas_assert (inst.relocs[0].type != 0);
return PARSE_OPERAND_SUCCESS;
}
@@ -5502,23 +5504,23 @@ parse_neon_alignment (char **str, int i)
}
/* Parse all forms of an ARM address expression. Information is written
- to inst.operands[i] and/or inst.reloc.
+ to inst.operands[i] and/or inst.relocs[0].
Preindexed addressing (.preind=1):
- [Rn, #offset] .reg=Rn .reloc.exp=offset
+ [Rn, #offset] .reg=Rn .relocs[0].exp=offset
[Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
[Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
- .shift_kind=shift .reloc.exp=shift_imm
+ .shift_kind=shift .relocs[0].exp=shift_imm
These three may have a trailing ! which causes .writeback to be set also.
Postindexed addressing (.postind=1, .writeback=1):
- [Rn], #offset .reg=Rn .reloc.exp=offset
+ [Rn], #offset .reg=Rn .relocs[0].exp=offset
[Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
[Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
- .shift_kind=shift .reloc.exp=shift_imm
+ .shift_kind=shift .relocs[0].exp=shift_imm
Unindexed addressing (.preind=0, .postind=0):
@@ -5527,11 +5529,11 @@ parse_neon_alignment (char **str, int i)
Other:
[Rn]{!} shorthand for [Rn,#0]{!}
- =immediate .isreg=0 .reloc.exp=immediate
- label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
+ =immediate .isreg=0 .relocs[0].exp=immediate
+ label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
It is the caller's responsibility to check for addressing modes not
- supported by the instruction, and to set inst.reloc.type. */
+ supported by the instruction, and to set inst.relocs[0].type. */
static parse_operand_result
parse_address_main (char **str, int i, int group_relocations,
@@ -5545,15 +5547,15 @@ parse_address_main (char **str, int i, int group_relocations,
if (skip_past_char (&p, '=') == FAIL)
{
/* Bare address - translate to PC-relative offset. */
- inst.reloc.pc_rel = 1;
+ inst.relocs[0].pc_rel = 1;
inst.operands[i].reg = REG_PC;
inst.operands[i].isreg = 1;
inst.operands[i].preind = 1;
- if (my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX_BIG))
+ if (my_get_expression (&inst.relocs[0].exp, &p, GE_OPT_PREFIX_BIG))
return PARSE_OPERAND_FAIL;
}
- else if (parse_big_immediate (&p, i, &inst.reloc.exp,
+ else if (parse_big_immediate (&p, i, &inst.relocs[0].exp,
/*allow_symbol_p=*/TRUE))
return PARSE_OPERAND_FAIL;
@@ -5628,29 +5630,32 @@ parse_address_main (char **str, int i, int group_relocations,
/* We now have the group relocation table entry corresponding to
the name in the assembler source. Next, we parse the
expression. */
- if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
+ if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
return PARSE_OPERAND_FAIL_NO_BACKTRACK;
/* Record the relocation type. */
switch (group_type)
{
case GROUP_LDR:
- inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
+ inst.relocs[0].type
+ = (bfd_reloc_code_real_type) entry->ldr_code;
break;
case GROUP_LDRS:
- inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
+ inst.relocs[0].type
+ = (bfd_reloc_code_real_type) entry->ldrs_code;
break;
case GROUP_LDC:
- inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
+ inst.relocs[0].type
+ = (bfd_reloc_code_real_type) entry->ldc_code;
break;
default:
gas_assert (0);
}
- if (inst.reloc.type == 0)
+ if (inst.relocs[0].type == 0)
{
inst.error = _("this group relocation is not allowed on this instruction");
return PARSE_OPERAND_FAIL_NO_BACKTRACK;
@@ -5660,11 +5665,11 @@ parse_address_main (char **str, int i, int group_relocations,
{
char *q = p;
- if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
+ if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
return PARSE_OPERAND_FAIL;
/* If the offset is 0, find out if it's a +0 or -0. */
- if (inst.reloc.exp.X_op == O_constant
- && inst.reloc.exp.X_add_number == 0)
+ if (inst.relocs[0].exp.X_op == O_constant
+ && inst.relocs[0].exp.X_add_number == 0)
{
skip_whitespace (q);
if (*q == '#')
@@ -5756,11 +5761,11 @@ parse_address_main (char **str, int i, int group_relocations,
inst.operands[i].negative = 0;
p--;
}
- if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
+ if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
return PARSE_OPERAND_FAIL;
/* If the offset is 0, find out if it's a +0 or -0. */
- if (inst.reloc.exp.X_op == O_constant
- && inst.reloc.exp.X_add_number == 0)
+ if (inst.relocs[0].exp.X_op == O_constant
+ && inst.relocs[0].exp.X_add_number == 0)
{
skip_whitespace (q);
if (*q == '#')
@@ -5780,8 +5785,8 @@ parse_address_main (char **str, int i, int group_relocations,
if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
{
inst.operands[i].preind = 1;
- inst.reloc.exp.X_op = O_constant;
- inst.reloc.exp.X_add_number = 0;
+ inst.relocs[0].exp.X_op = O_constant;
+ inst.relocs[0].exp.X_add_number = 0;
}
*str = p;
return PARSE_OPERAND_SUCCESS;
@@ -5809,28 +5814,28 @@ parse_half (char **str)
p = *str;
skip_past_char (&p, '#');
if (strncasecmp (p, ":lower16:", 9) == 0)
- inst.reloc.type = BFD_RELOC_ARM_MOVW;
+ inst.relocs[0].type = BFD_RELOC_ARM_MOVW;
else if (strncasecmp (p, ":upper16:", 9) == 0)
- inst.reloc.type = BFD_RELOC_ARM_MOVT;
+ inst.relocs[0].type = BFD_RELOC_ARM_MOVT;
- if (inst.reloc.type != BFD_RELOC_UNUSED)
+ if (inst.relocs[0].type != BFD_RELOC_UNUSED)
{
p += 9;
skip_whitespace (p);
}
- if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
+ if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
return FAIL;
- if (inst.reloc.type == BFD_RELOC_UNUSED)
+ if (inst.relocs[0].type == BFD_RELOC_UNUSED)
{
- if (inst.reloc.exp.X_op != O_constant)
+ if (inst.relocs[0].exp.X_op != O_constant)
{
inst.error = _("constant expression expected");
return FAIL;
}
- if (inst.reloc.exp.X_add_number < 0
- || inst.reloc.exp.X_add_number > 0xffff)
+ if (inst.relocs[0].exp.X_add_number < 0
+ || inst.relocs[0].exp.X_add_number > 0xffff)
{
inst.error = _("immediate value out of range");
return FAIL;
@@ -6257,7 +6262,7 @@ parse_tb (char **str)
{
if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
return FAIL;
- if (inst.reloc.exp.X_add_number != 1)
+ if (inst.relocs[0].exp.X_add_number != 1)
{
inst.error = _("invalid shift");
return FAIL;
@@ -6587,6 +6592,7 @@ enum operand_parse_code
OP_EXP, /* arbitrary expression */
OP_EXPi, /* same, with optional immediate prefix */
OP_EXPr, /* same, with optional relocation suffix */
+ OP_EXPs, /* same, with optional non-first operand relocation suffix */
OP_HALF, /* 0 .. 65535 or low/high reloc. */
OP_IROT1, /* VCADD rotate immediate: 90, 270. */
OP_IROT2, /* VCMLA rotate immediate: 0, 90, 180, 270. */
@@ -6995,19 +7001,19 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
/* Expressions */
case OP_EXPi: EXPi:
- po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
+ po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
GE_OPT_PREFIX));
break;
case OP_EXP:
- po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
+ po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
GE_NO_PREFIX));
break;
case OP_EXPr: EXPr:
- po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
+ po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
GE_NO_PREFIX));
- if (inst.reloc.exp.X_op == O_symbol)
+ if (inst.relocs[0].exp.X_op == O_symbol)
{
val = parse_reloc (&str);
if (val == -1)
@@ -7023,6 +7029,20 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
}
break;
+ case OP_EXPs:
+ po_misc_or_fail (my_get_expression (&inst.relocs[i].exp, &str,
+ GE_NO_PREFIX));
+ if (inst.relocs[i].exp.X_op == O_symbol)
+ {
+ inst.operands[i].hasreloc = 1;
+ }
+ else if (inst.relocs[i].exp.X_op == O_constant)
+ {
+ inst.operands[i].imm = inst.relocs[i].exp.X_add_number;
+ inst.operands[i].hasreloc = 0;
+ }
+ break;
+
/* Operand for MOVW or MOVT. */
case OP_HALF:
po_misc_or_fail (parse_half (&str));
@@ -7543,7 +7563,7 @@ encode_arm_shift (int i)
inst.instruction |= inst.operands[i].imm << 8;
}
else
- inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
+ inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
}
}
@@ -7558,7 +7578,7 @@ encode_arm_shifter_operand (int i)
else
{
inst.instruction |= INST_IMMEDIATE;
- if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
+ if (inst.relocs[0].type != BFD_RELOC_ARM_IMMEDIATE)
inst.instruction |= inst.operands[i].imm;
}
}
@@ -7633,13 +7653,13 @@ encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
else
{
inst.instruction |= inst.operands[i].shift_kind << 5;
- inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
+ inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
}
}
}
- else /* immediate offset in inst.reloc */
+ else /* immediate offset in inst.relocs[0] */
{
- if (is_pc && !inst.reloc.pc_rel)
+ if (is_pc && !inst.relocs[0].pc_rel)
{
const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
@@ -7656,12 +7676,12 @@ encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
as_tsktsk (_("use of PC in this instruction is deprecated"));
}
- if (inst.reloc.type == BFD_RELOC_UNUSED)
+ if (inst.relocs[0].type == BFD_RELOC_UNUSED)
{
/* Prefer + for zero encoded value. */
if (!inst.operands[i].negative)
inst.instruction |= INDEX_UP;
- inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
+ inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM;
}
}
}
@@ -7693,19 +7713,19 @@ encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
if (!inst.operands[i].negative)
inst.instruction |= INDEX_UP;
}
- else /* immediate offset in inst.reloc */
+ else /* immediate offset in inst.relocs[0] */
{
- constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
+ constraint ((inst.operands[i].reg == REG_PC && !inst.relocs[0].pc_rel
&& inst.operands[i].writeback),
BAD_PC_WRITEBACK);
inst.instruction |= HWOFFSET_IMM;
- if (inst.reloc.type == BFD_RELOC_UNUSED)
+ if (inst.relocs[0].type == BFD_RELOC_UNUSED)
{
/* Prefer + for zero encoded value. */
if (!inst.operands[i].negative)
inst.instruction |= INDEX_UP;
- inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
+ inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM8;
}
}
}
@@ -7958,7 +7978,7 @@ enum lit_type
static void do_vfp_nsyn_opcode (const char *);
-/* inst.reloc.exp describes an "=expr" load pseudo-operation.
+/* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
Determine whether it can be performed with a move instruction; if
it can, convert inst.instruction to that move instruction and
return TRUE; if it can't, convert inst.instruction to a literal-pool
@@ -7985,28 +8005,28 @@ move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
return TRUE;
}
- if (inst.reloc.exp.X_op != O_constant
- && inst.reloc.exp.X_op != O_symbol
- && inst.reloc.exp.X_op != O_big)
+ if (inst.relocs[0].exp.X_op != O_constant
+ && inst.relocs[0].exp.X_op != O_symbol
+ && inst.relocs[0].exp.X_op != O_big)
{
inst.error = _("constant expression expected");
return TRUE;
}
- if (inst.reloc.exp.X_op == O_constant
- || inst.reloc.exp.X_op == O_big)
+ if (inst.relocs[0].exp.X_op == O_constant
+ || inst.relocs[0].exp.X_op == O_big)
{
#if defined BFD_HOST_64_BIT
bfd_int64_t v;
#else
offsetT v;
#endif
- if (inst.reloc.exp.X_op == O_big)
+ if (inst.relocs[0].exp.X_op == O_big)
{
LITTLENUM_TYPE w[X_PRECISION];
LITTLENUM_TYPE * l;
- if (inst.reloc.exp.X_add_number == -1)
+ if (inst.relocs[0].exp.X_add_number == -1)
{
gen_to_words (w, X_PRECISION, E_PRECISION);
l = w;
@@ -8030,7 +8050,7 @@ move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
#endif
}
else
- v = inst.reloc.exp.X_add_number;
+ v = inst.relocs[0].exp.X_add_number;
if (!inst.operands[i].issingle)
{
@@ -8119,7 +8139,7 @@ move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
unsigned immlo = inst.operands[1].imm;
unsigned immhi = inst.operands[1].regisimm
? inst.operands[1].reg
- : inst.reloc.exp.X_unsigned
+ : inst.relocs[0].exp.X_unsigned
? 0
: ((bfd_int64_t)((int) immlo)) >> 32;
int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
@@ -8194,8 +8214,8 @@ move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
inst.operands[1].reg = REG_PC;
inst.operands[1].isreg = 1;
inst.operands[1].preind = 1;
- inst.reloc.pc_rel = 1;
- inst.reloc.type = (thumb_p
+ inst.relocs[0].pc_rel = 1;
+ inst.relocs[0].type = (thumb_p
? BFD_RELOC_ARM_THUMB_OFFSET
: (mode_3
? BFD_RELOC_ARM_HWLITERAL
@@ -8262,15 +8282,15 @@ encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
}
if (reloc_override)
- inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
- else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
- || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
- && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
+ inst.relocs[0].type = (bfd_reloc_code_real_type) reloc_override;
+ else if ((inst.relocs[0].type < BFD_RELOC_ARM_ALU_PC_G0_NC
+ || inst.relocs[0].type > BFD_RELOC_ARM_LDC_SB_G2)
+ && inst.relocs[0].type != BFD_RELOC_ARM_LDR_PC_G0)
{
if (thumb_mode)
- inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
+ inst.relocs[0].type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
else
- inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
+ inst.relocs[0].type = BFD_RELOC_ARM_CP_OFF_IMM;
}
/* Prefer + for zero encoded value. */
@@ -8389,9 +8409,9 @@ static void
do_rm_rd_rn (void)
{
constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
- constraint (((inst.reloc.exp.X_op != O_constant
- && inst.reloc.exp.X_op != O_illegal)
- || inst.reloc.exp.X_add_number != 0),
+ constraint (((inst.relocs[0].exp.X_op != O_constant
+ && inst.relocs[0].exp.X_op != O_illegal)
+ || inst.relocs[0].exp.X_add_number != 0),
BAD_ADDR_MODE);
inst.instruction |= inst.operands[0].reg;
inst.instruction |= inst.operands[1].reg << 12;
@@ -8425,16 +8445,16 @@ do_adr (void)
/* Frag hacking will turn this into a sub instruction if the offset turns
out to be negative. */
- inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
- inst.reloc.pc_rel = 1;
- inst.reloc.exp.X_add_number -= 8;
+ inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
+ inst.relocs[0].pc_rel = 1;
+ inst.relocs[0].exp.X_add_number -= 8;
if (support_interwork
- && inst.reloc.exp.X_op == O_symbol
- && inst.reloc.exp.X_add_symbol != NULL
- && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
- && THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
- inst.reloc.exp.X_add_number |= 1;
+ && inst.relocs[0].exp.X_op == O_symbol
+ && inst.relocs[0].exp.X_add_symbol != NULL
+ && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
+ && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
+ inst.relocs[0].exp.X_add_number |= 1;
}
/* This is a pseudo-op of the form "adrl rd, label" to be converted
@@ -8449,24 +8469,24 @@ do_adrl (void)
/* Frag hacking will turn this into a sub instruction if the offset turns
out to be negative. */
- inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
- inst.reloc.pc_rel = 1;
+ inst.relocs[0].type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
+ inst.relocs[0].pc_rel = 1;
inst.size = INSN_SIZE * 2;
- inst.reloc.exp.X_add_number -= 8;
+ inst.relocs[0].exp.X_add_number -= 8;
if (support_interwork
- && inst.reloc.exp.X_op == O_symbol
- && inst.reloc.exp.X_add_symbol != NULL
- && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
- && THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
- inst.reloc.exp.X_add_number |= 1;
+ && inst.relocs[0].exp.X_op == O_symbol
+ && inst.relocs[0].exp.X_add_symbol != NULL
+ && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
+ && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
+ inst.relocs[0].exp.X_add_number |= 1;
}
static void
do_arit (void)
{
- constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
- && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
+ constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
+ && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
THUMB1_RELOC_ONLY);
if (!inst.operands[1].present)
inst.operands[1].reg = inst.operands[0].reg;
@@ -8551,13 +8571,13 @@ encode_branch (int default_reloc)
constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
&& inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
_("the only valid suffixes here are '(plt)' and '(tlscall)'"));
- inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
+ inst.relocs[0].type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
? BFD_RELOC_ARM_PLT32
: thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
}
else
- inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
- inst.reloc.pc_rel = 1;
+ inst.relocs[0].type = (bfd_reloc_code_real_type) default_reloc;
+ inst.relocs[0].pc_rel = 1;
}
static void
@@ -8641,7 +8661,7 @@ do_bx (void)
want_reloc = FALSE;
if (want_reloc)
- inst.reloc.type = BFD_RELOC_ARM_V4BX;
+ inst.relocs[0].type = BFD_RELOC_ARM_V4BX;
}
@@ -9010,15 +9030,15 @@ do_ldrex (void)
|| (inst.operands[1].reg == REG_PC),
BAD_ADDR_MODE);
- constraint (inst.reloc.exp.X_op != O_constant
- || inst.reloc.exp.X_add_number != 0,
+ constraint (inst.relocs[0].exp.X_op != O_constant
+ || inst.relocs[0].exp.X_add_number != 0,
_("offset must be zero in ARM encoding"));
constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
inst.instruction |= inst.operands[0].reg << 12;
inst.instruction |= inst.operands[1].reg << 16;
- inst.reloc.type = BFD_RELOC_UNUSED;
+ inst.relocs[0].type = BFD_RELOC_UNUSED;
}
static void
@@ -9045,7 +9065,7 @@ check_ldr_r15_aligned (void)
constraint (!(inst.operands[1].immisreg)
&& (inst.operands[0].reg == REG_PC
&& inst.operands[1].reg == REG_PC
- && (inst.reloc.exp.X_add_number & 0x3)),
+ && (inst.relocs[0].exp.X_add_number & 0x3)),
_("ldr to register 15 must be 4-byte aligned"));
}
@@ -9067,8 +9087,8 @@ do_ldstt (void)
reject [Rn,...]. */
if (inst.operands[1].preind)
{
- constraint (inst.reloc.exp.X_op != O_constant
- || inst.reloc.exp.X_add_number != 0,
+ constraint (inst.relocs[0].exp.X_op != O_constant
+ || inst.relocs[0].exp.X_add_number != 0,
_("this instruction requires a post-indexed address"));
inst.operands[1].preind = 0;
@@ -9099,8 +9119,8 @@ do_ldsttv4 (void)
reject [Rn,...]. */
if (inst.operands[1].preind)
{
- constraint (inst.reloc.exp.X_op != O_constant
- || inst.reloc.exp.X_add_number != 0,
+ constraint (inst.relocs[0].exp.X_op != O_constant
+ || inst.relocs[0].exp.X_add_number != 0,
_("this instruction requires a post-indexed address"));
inst.operands[1].preind = 0;
@@ -9139,8 +9159,8 @@ do_mlas (void)
static void
do_mov (void)
{
- constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
- && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
+ constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
+ && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
THUMB1_RELOC_ONLY);
inst.instruction |= inst.operands[0].reg << 12;
encode_arm_shifter_operand (1);
@@ -9154,14 +9174,14 @@ do_mov16 (void)
bfd_boolean top;
top = (inst.instruction & 0x00400000) != 0;
- constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
+ constraint (top && inst.relocs[0].type == BFD_RELOC_ARM_MOVW,
_(":lower16: not allowed in this instruction"));
- constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
+ constraint (!top && inst.relocs[0].type == BFD_RELOC_ARM_MOVT,
_(":upper16: not allowed in this instruction"));
inst.instruction |= inst.operands[0].reg << 12;
- if (inst.reloc.type == BFD_RELOC_UNUSED)
+ if (inst.relocs[0].type == BFD_RELOC_UNUSED)
{
- imm = inst.reloc.exp.X_add_number;
+ imm = inst.relocs[0].exp.X_add_number;
/* The value is in two pieces: 0:11, 16:19. */
inst.instruction |= (imm & 0x00000fff);
inst.instruction |= (imm & 0x0000f000) << 4;
@@ -9296,8 +9316,8 @@ do_msr (void)
else
{
inst.instruction |= INST_IMMEDIATE;
- inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
- inst.reloc.pc_rel = 0;
+ inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
+ inst.relocs[0].pc_rel = 0;
}
}
@@ -9537,28 +9557,28 @@ do_shift (void)
_("extraneous shift as part of operand to shift insn"));
}
else
- inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
+ inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
}
static void
do_smc (void)
{
- inst.reloc.type = BFD_RELOC_ARM_SMC;
- inst.reloc.pc_rel = 0;
+ inst.relocs[0].type = BFD_RELOC_ARM_SMC;
+ inst.relocs[0].pc_rel = 0;
}
static void
do_hvc (void)
{
- inst.reloc.type = BFD_RELOC_ARM_HVC;
- inst.reloc.pc_rel = 0;
+ inst.relocs[0].type = BFD_RELOC_ARM_HVC;
+ inst.relocs[0].pc_rel = 0;
}
static void
do_swi (void)
{
- inst.reloc.type = BFD_RELOC_ARM_SWI;
- inst.reloc.pc_rel = 0;
+ inst.relocs[0].type = BFD_RELOC_ARM_SWI;
+ inst.relocs[0].pc_rel = 0;
}
static void
@@ -9660,14 +9680,14 @@ do_strex (void)
constraint (inst.operands[0].reg == inst.operands[1].reg
|| inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
- constraint (inst.reloc.exp.X_op != O_constant
- || inst.reloc.exp.X_add_number != 0,
+ constraint (inst.relocs[0].exp.X_op != O_constant
+ || inst.relocs[0].exp.X_add_number != 0,
_("offset must be zero in ARM encoding"));
inst.instruction |= inst.operands[0].reg << 12;
inst.instruction |= inst.operands[1].reg;
inst.instruction |= inst.operands[2].reg << 16;
- inst.reloc.type = BFD_RELOC_UNUSED;
+ inst.relocs[0].type = BFD_RELOC_UNUSED;
}
static void
@@ -10054,15 +10074,15 @@ do_fpa_ldmstm (void)
[Rn]{!}. The instruction does not really support stacking or
unstacking, so we have to emulate these by setting appropriate
bits and offsets. */
- constraint (inst.reloc.exp.X_op != O_constant
- || inst.reloc.exp.X_add_number != 0,
+ constraint (inst.relocs[0].exp.X_op != O_constant
+ || inst.relocs[0].exp.X_add_number != 0,
_("this instruction does not support indexing"));
if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
- inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
+ inst.relocs[0].exp.X_add_number = 12 * inst.operands[1].imm;
if (!(inst.instruction & INDEX_UP))
- inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
+ inst.relocs[0].exp.X_add_number = -inst.relocs[0].exp.X_add_number;
if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
{
@@ -10182,7 +10202,7 @@ do_iwmmxt_wldstd (void)
if (inst.operands[1].writeback)
inst.instruction |= WRITE_BACK;
inst.instruction |= inst.operands[1].reg << 16;
- inst.instruction |= inst.reloc.exp.X_add_number << 4;
+ inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
inst.instruction |= inst.operands[1].imm;
}
else
@@ -10354,7 +10374,7 @@ do_xsc_mra (void)
static void
encode_thumb32_shifted_operand (int i)
{
- unsigned int value = inst.reloc.exp.X_add_number;
+ unsigned int value = inst.relocs[0].exp.X_add_number;
unsigned int shift = inst.operands[i].shift_kind;
constraint (inst.operands[i].immisreg,
@@ -10364,7 +10384,7 @@ encode_thumb32_shifted_operand (int i)
inst.instruction |= SHIFT_ROR << 4;
else
{
- constraint (inst.reloc.exp.X_op != O_constant,
+ constraint (inst.relocs[0].exp.X_op != O_constant,
_("expression too complex"));
constraint (value > 32
@@ -10416,14 +10436,14 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
inst.instruction |= inst.operands[i].imm;
if (inst.operands[i].shifted)
{
- constraint (inst.reloc.exp.X_op != O_constant,
+ constraint (inst.relocs[0].exp.X_op != O_constant,
_("expression too complex"));
- constraint (inst.reloc.exp.X_add_number < 0
- || inst.reloc.exp.X_add_number > 3,
+ constraint (inst.relocs[0].exp.X_add_number < 0
+ || inst.relocs[0].exp.X_add_number > 3,
_("shift out of range"));
- inst.instruction |= inst.reloc.exp.X_add_number << 4;
+ inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
}
- inst.reloc.type = BFD_RELOC_UNUSED;
+ inst.relocs[0].type = BFD_RELOC_UNUSED;
}
else if (inst.operands[i].preind)
{
@@ -10445,7 +10465,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
if (inst.operands[i].writeback)
inst.instruction |= 0x00000100;
}
- inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
+ inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
}
else if (inst.operands[i].postind)
{
@@ -10457,7 +10477,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
inst.instruction |= 0x00200000;
else
inst.instruction |= 0x00000900;
- inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
+ inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
}
else /* unindexed - only for coprocessor */
inst.error = _("instruction does not accept unindexed addressing");
@@ -10589,7 +10609,7 @@ do_t_add_sub_w (void)
reject_bad_reg (Rd);
inst.instruction |= (Rn << 16) | (Rd << 8);
- inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
+ inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
}
/* Parse an add or subtract instruction. We get here with inst.instruction
@@ -10651,11 +10671,12 @@ do_t_add_sub (void)
{
inst.instruction = THUMB_OP16(opcode);
inst.instruction |= (Rd << 4) | Rs;
- if (inst.reloc.type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
- || inst.reloc.type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
+ if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
+ || (inst.relocs[0].type
+ > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC))
{
if (inst.size_req == 2)
- inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
+ inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
else
inst.relax = opcode;
}
@@ -10666,29 +10687,31 @@ do_t_add_sub (void)
if (inst.size_req == 4
|| (inst.size_req != 2 && !opcode))
{
- constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
- && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
+ constraint ((inst.relocs[0].type
+ >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC)
+ && (inst.relocs[0].type
+ <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) ,
THUMB1_RELOC_ONLY);
if (Rd == REG_PC)
{
constraint (add, BAD_PC);
constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
_("only SUBS PC, LR, #const allowed"));
- constraint (inst.reloc.exp.X_op != O_constant,
+ constraint (inst.relocs[0].exp.X_op != O_constant,
_("expression too complex"));
- constraint (inst.reloc.exp.X_add_number < 0
- || inst.reloc.exp.X_add_number > 0xff,
+ constraint (inst.relocs[0].exp.X_add_number < 0
+ || inst.relocs[0].exp.X_add_number > 0xff,
_("immediate value out of range"));
inst.instruction = T2_SUBS_PC_LR
- | inst.reloc.exp.X_add_number;
- inst.reloc.type = BFD_RELOC_UNUSED;
+ | inst.relocs[0].exp.X_add_number;
+ inst.relocs[0].type = BFD_RELOC_UNUSED;
return;
}
else if (Rs == REG_PC)
{
/* Always use addw/subw. */
inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
- inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
+ inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
}
else
{
@@ -10696,9 +10719,9 @@ do_t_add_sub (void)
inst.instruction = (inst.instruction & 0xe1ffffff)
| 0x10000000;
if (flags)
- inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+ inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
else
- inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
+ inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_IMM;
}
inst.instruction |= Rd << 8;
inst.instruction |= Rs << 16;
@@ -10706,7 +10729,7 @@ do_t_add_sub (void)
}
else
{
- unsigned int value = inst.reloc.exp.X_add_number;
+ unsigned int value = inst.relocs[0].exp.X_add_number;
unsigned int shift = inst.operands[2].shift_kind;
Rn = inst.operands[2].reg;
@@ -10782,7 +10805,7 @@ do_t_add_sub (void)
inst.instruction = (inst.instruction == T_MNEM_add
? 0x0000 : 0x8000);
inst.instruction |= (Rd << 4) | Rs;
- inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
+ inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
return;
}
@@ -10833,24 +10856,24 @@ do_t_adr (void)
/* Generate a 32-bit opcode. */
inst.instruction = THUMB_OP32 (inst.instruction);
inst.instruction |= Rd << 8;
- inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
- inst.reloc.pc_rel = 1;
+ inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_PC12;
+ inst.relocs[0].pc_rel = 1;
}
else
{
/* Generate a 16-bit opcode. */
inst.instruction = THUMB_OP16 (inst.instruction);
- inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
- inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
- inst.reloc.pc_rel = 1;
+ inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
+ inst.relocs[0].exp.X_add_number -= 4; /* PC relative adjust. */
+ inst.relocs[0].pc_rel = 1;
inst.instruction |= Rd << 4;
}
- if (inst.reloc.exp.X_op == O_symbol
- && inst.reloc.exp.X_add_symbol != NULL
- && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
- && THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
- inst.reloc.exp.X_add_number += 1;
+ if (inst.relocs[0].exp.X_op == O_symbol
+ && inst.relocs[0].exp.X_add_symbol != NULL
+ && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
+ && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
+ inst.relocs[0].exp.X_add_number += 1;
}
/* Arithmetic instructions for which there is just one 16-bit
@@ -10885,7 +10908,7 @@ do_t_arit3 (void)
inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
inst.instruction |= Rd << 8;
inst.instruction |= Rs << 16;
- inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+ inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
}
else
{
@@ -10973,7 +10996,7 @@ do_t_arit3c (void)
inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
inst.instruction |= Rd << 8;
inst.instruction |= Rs << 16;
- inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+ inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
}
else
{
@@ -11166,7 +11189,7 @@ do_t_branch (void)
&& (inst.size_req == 4
|| (inst.size_req != 2
&& (inst.operands[0].hasreloc
- || inst.reloc.exp.X_op == O_constant))))
+ || inst.relocs[0].exp.X_op == O_constant))))
{
inst.instruction = THUMB_OP32(opcode);
if (cond == COND_ALWAYS)
@@ -11196,8 +11219,8 @@ do_t_branch (void)
if (unified_syntax && inst.size_req != 2)
inst.relax = opcode;
}
- inst.reloc.type = reloc;
- inst.reloc.pc_rel = 1;
+ inst.relocs[0].type = reloc;
+ inst.relocs[0].pc_rel = 1;
}
/* Actually do the work for Thumb state bkpt and hlt. The only difference
@@ -11241,20 +11264,20 @@ do_t_branch23 (void)
the branch encoding is now needed to deal with TLSCALL relocs.
So if we see a PLT reloc now, put it back to how it used to be to
keep the preexisting behaviour. */
- if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
- inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
+ if (inst.relocs[0].type == BFD_RELOC_ARM_PLT32)
+ inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH23;
#if defined(OBJ_COFF)
/* If the destination of the branch is a defined symbol which does not have
the THUMB_FUNC attribute, then we must be calling a function which has
the (interfacearm) attribute. We look for the Thumb entry point to that
function and change the branch to refer to that function instead. */
- if ( inst.reloc.exp.X_op == O_symbol
- && inst.reloc.exp.X_add_symbol != NULL
- && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
- && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
- inst.reloc.exp.X_add_symbol =
- find_real_start (inst.reloc.exp.X_add_symbol);
+ if ( inst.relocs[0].exp.X_op == O_symbol
+ && inst.relocs[0].exp.X_add_symbol != NULL
+ && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
+ && ! THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
+ inst.relocs[0].exp.X_add_symbol
+ = find_real_start (inst.relocs[0].exp.X_add_symbol);
#endif
}
@@ -11362,8 +11385,8 @@ do_t_cbz (void)
set_it_insn_type (OUTSIDE_IT_INSN);
constraint (inst.operands[0].reg > 7, BAD_HIREG);
inst.instruction |= inst.operands[0].reg;
- inst.reloc.pc_rel = 1;
- inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
+ inst.relocs[0].pc_rel = 1;
+ inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH7;
}
static void
@@ -11511,7 +11534,7 @@ static void
do_t_ldmstm (void)
{
/* This really doesn't seem worth it. */
- constraint (inst.reloc.type != BFD_RELOC_UNUSED,
+ constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
_("expression too complex"));
constraint (inst.operands[1].writeback,
_("Thumb load/store multiple does not support {reglist}^"));
@@ -11648,7 +11671,7 @@ do_t_ldrex (void)
inst.instruction |= inst.operands[0].reg << 12;
inst.instruction |= inst.operands[1].reg << 16;
- inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
+ inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
}
static void
@@ -11718,7 +11741,7 @@ do_t_ldst (void)
{
if (Rn == REG_PC)
{
- if (inst.reloc.pc_rel)
+ if (inst.relocs[0].pc_rel)
opcode = T_MNEM_ldr_pc2;
else
opcode = T_MNEM_ldr_pc;
@@ -11739,7 +11762,7 @@ do_t_ldst (void)
}
inst.instruction |= THUMB_OP16 (opcode);
if (inst.size_req == 2)
- inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
+ inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
else
inst.relax = opcode;
return;
@@ -11818,7 +11841,7 @@ do_t_ldst (void)
inst.instruction = T_OPCODE_STR_SP;
inst.instruction |= inst.operands[0].reg << 8;
- inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
+ inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
return;
}
@@ -11828,7 +11851,7 @@ do_t_ldst (void)
/* Immediate offset. */
inst.instruction |= inst.operands[0].reg;
inst.instruction |= inst.operands[1].reg << 3;
- inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
+ inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
return;
}
@@ -12026,25 +12049,27 @@ do_t_mov_cmp (void)
{
inst.instruction = THUMB_OP16 (opcode);
inst.instruction |= Rn << 8;
- if (inst.reloc.type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
- || inst.reloc.type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
+ if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
+ || inst.relocs[0].type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
{
if (inst.size_req == 2)
- inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
+ inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
else
inst.relax = opcode;
}
}
else
{
- constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
- && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
+ constraint ((inst.relocs[0].type
+ >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC)
+ && (inst.relocs[0].type
+ <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) ,
THUMB1_RELOC_ONLY);
inst.instruction = THUMB_OP32 (inst.instruction);
inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
inst.instruction |= Rn << r0off;
- inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+ inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
}
}
else if (inst.operands[1].shifted && inst.operands[1].immisreg
@@ -12131,7 +12156,7 @@ do_t_mov_cmp (void)
{
inst.instruction |= Rn;
inst.instruction |= Rm << 3;
- inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
+ inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
}
else
{
@@ -12222,7 +12247,7 @@ do_t_mov_cmp (void)
constraint (Rn > 7,
_("only lo regs allowed with immediate"));
inst.instruction |= Rn << 8;
- inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
+ inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
}
}
@@ -12234,24 +12259,24 @@ do_t_mov16 (void)
bfd_boolean top;
top = (inst.instruction & 0x00800000) != 0;
- if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
+ if (inst.relocs[0].type == BFD_RELOC_ARM_MOVW)
{
constraint (top, _(":lower16: not allowed in this instruction"));
- inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
+ inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVW;
}
- else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
+ else if (inst.relocs[0].type == BFD_RELOC_ARM_MOVT)
{
constraint (!top, _(":upper16: not allowed in this instruction"));
- inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
+ inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVT;
}
Rd = inst.operands[0].reg;
reject_bad_reg (Rd);
inst.instruction |= Rd << 8;
- if (inst.reloc.type == BFD_RELOC_UNUSED)
+ if (inst.relocs[0].type == BFD_RELOC_UNUSED)
{
- imm = inst.reloc.exp.X_add_number;
+ imm = inst.relocs[0].exp.X_add_number;
inst.instruction |= (imm & 0xf000) << 4;
inst.instruction |= (imm & 0x0800) << 15;
inst.instruction |= (imm & 0x0700) << 4;
@@ -12301,7 +12326,7 @@ do_t_mvn_tst (void)
inst.instruction = THUMB_OP32 (inst.instruction);
inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
inst.instruction |= Rn << r0off;
- inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+ inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
}
else
{
@@ -12613,7 +12638,7 @@ do_t_orn (void)
if (!inst.operands[2].isreg)
{
inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
- inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+ inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
}
else
{
@@ -12647,8 +12672,8 @@ do_t_pkhbt (void)
inst.instruction |= Rm;
if (inst.operands[3].present)
{
- unsigned int val = inst.reloc.exp.X_add_number;
- constraint (inst.reloc.exp.X_op != O_constant,
+ unsigned int val = inst.relocs[0].exp.X_add_number;
+ constraint (inst.relocs[0].exp.X_op != O_constant,
_("expression too complex"));
inst.instruction |= (val & 0x1c) << 10;
inst.instruction |= (val & 0x03) << 6;
@@ -12688,7 +12713,7 @@ do_t_push_pop (void)
constraint (inst.operands[0].writeback,
_("push/pop do not support {reglist}^"));
- constraint (inst.reloc.type != BFD_RELOC_UNUSED,
+ constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
_("expression too complex"));
mask = inst.operands[0].imm;
@@ -12806,15 +12831,15 @@ do_t_rsb (void)
if (inst.size_req == 4 || !unified_syntax)
narrow = FALSE;
- if (inst.reloc.exp.X_op != O_constant
- || inst.reloc.exp.X_add_number != 0)
+ if (inst.relocs[0].exp.X_op != O_constant
+ || inst.relocs[0].exp.X_add_number != 0)
narrow = FALSE;
/* Turn rsb #0 into 16-bit neg. We should probably do this via
relaxation, but it doesn't seem worth the hassle. */
if (narrow)
{
- inst.reloc.type = BFD_RELOC_UNUSED;
+ inst.relocs[0].type = BFD_RELOC_UNUSED;
inst.instruction = THUMB_OP16 (T_MNEM_negs);
inst.instruction |= Rs << 3;
inst.instruction |= Rd;
@@ -12822,7 +12847,7 @@ do_t_rsb (void)
else
{
inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
- inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+ inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
}
}
else
@@ -12906,7 +12931,7 @@ do_t_shift (void)
inst.instruction |= inst.operands[0].reg << 8;
encode_thumb32_shifted_operand (1);
/* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
- inst.reloc.type = BFD_RELOC_UNUSED;
+ inst.relocs[0].type = BFD_RELOC_UNUSED;
}
}
else
@@ -12938,7 +12963,7 @@ do_t_shift (void)
case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
default: abort ();
}
- inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
+ inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
inst.instruction |= inst.operands[0].reg;
inst.instruction |= inst.operands[1].reg << 3;
}
@@ -12982,7 +13007,7 @@ do_t_shift (void)
case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
default: abort ();
}
- inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
+ inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
inst.instruction |= inst.operands[0].reg;
inst.instruction |= inst.operands[1].reg << 3;
}
@@ -13028,12 +13053,12 @@ do_t_simd2 (void)
static void
do_t_smc (void)
{
- unsigned int value = inst.reloc.exp.X_add_number;
+ unsigned int value = inst.relocs[0].exp.X_add_number;
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
_("SMC is not permitted on this architecture"));
- constraint (inst.reloc.exp.X_op != O_constant,
+ constraint (inst.relocs[0].exp.X_op != O_constant,
_("expression too complex"));
- inst.reloc.type = BFD_RELOC_UNUSED;
+ inst.relocs[0].type = BFD_RELOC_UNUSED;
inst.instruction |= (value & 0xf000) >> 12;
inst.instruction |= (value & 0x0ff0);
inst.instruction |= (value & 0x000f) << 16;
@@ -13044,9 +13069,9 @@ do_t_smc (void)
static void
do_t_hvc (void)
{
- unsigned int value = inst.reloc.exp.X_add_number;
+ unsigned int value = inst.relocs[0].exp.X_add_number;
- inst.reloc.type = BFD_RELOC_UNUSED;
+ inst.relocs[0].type = BFD_RELOC_UNUSED;
inst.instruction |= (value & 0x0fff);
inst.instruction |= (value & 0xf000) << 4;
}
@@ -13068,11 +13093,11 @@ do_t_ssat_usat (int bias)
if (inst.operands[3].present)
{
- offsetT shift_amount = inst.reloc.exp.X_add_number;
+ offsetT shift_amount = inst.relocs[0].exp.X_add_number;
- inst.reloc.type = BFD_RELOC_UNUSED;
+ inst.relocs[0].type = BFD_RELOC_UNUSED;
- constraint (inst.reloc.exp.X_op != O_constant,
+ constraint (inst.relocs[0].exp.X_op != O_constant,
_("expression too complex"));
if (shift_amount != 0)
@@ -13125,7 +13150,7 @@ do_t_strex (void)
inst.instruction |= inst.operands[0].reg << 8;
inst.instruction |= inst.operands[1].reg << 12;
inst.instruction |= inst.operands[2].reg << 16;
- inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
+ inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
}
static void
@@ -13203,7 +13228,7 @@ do_t_sxth (void)
static void
do_t_swi (void)
{
- inst.reloc.type = BFD_RELOC_ARM_SWI;
+ inst.relocs[0].type = BFD_RELOC_ARM_SWI;
}
static void
@@ -17360,8 +17385,8 @@ do_neon_ldx_stx (void)
else
{
constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
- constraint (inst.reloc.exp.X_op != O_constant
- || inst.reloc.exp.X_add_number != 0,
+ constraint (inst.relocs[0].exp.X_op != O_constant
+ || inst.relocs[0].exp.X_add_number != 0,
BAD_ADDR_MODE);
if (inst.operands[1].writeback)
@@ -17584,8 +17609,9 @@ do_vcmla (void)
{
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
_(BAD_FPU));
- constraint (inst.reloc.exp.X_op != O_constant, _("expression too complex"));
- unsigned rot = inst.reloc.exp.X_add_number;
+ constraint (inst.relocs[0].exp.X_op != O_constant,
+ _("expression too complex"));
+ unsigned rot = inst.relocs[0].exp.X_add_number;
constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
_("immediate out of range"));
rot /= 90;
@@ -17625,8 +17651,9 @@ do_vcadd (void)
{
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
_(BAD_FPU));
- constraint (inst.reloc.exp.X_op != O_constant, _("expression too complex"));
- unsigned rot = inst.reloc.exp.X_add_number;
+ constraint (inst.relocs[0].exp.X_op != O_constant,
+ _("expression too complex"));
+ unsigned rot = inst.relocs[0].exp.X_add_number;
constraint (rot != 90 && rot != 270, _("immediate out of range"));
enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
@@ -17976,18 +18003,18 @@ output_relax_insn (void)
start of the instruction. */
dwarf2_emit_insn (0);
- switch (inst.reloc.exp.X_op)
+ switch (inst.relocs[0].exp.X_op)
{
case O_symbol:
- sym = inst.reloc.exp.X_add_symbol;
- offset = inst.reloc.exp.X_add_number;
+ sym = inst.relocs[0].exp.X_add_symbol;
+ offset = inst.relocs[0].exp.X_add_number;
break;
case O_constant:
sym = NULL;
- offset = inst.reloc.exp.X_add_number;
+ offset = inst.relocs[0].exp.X_add_number;
break;
default:
- sym = make_expr_symbol (&inst.reloc.exp);
+ sym = make_expr_symbol (&inst.relocs[0].exp);
offset = 0;
break;
}
@@ -18043,10 +18070,14 @@ output_inst (const char * str)
else
md_number_to_chars (to, inst.instruction, inst.size);
- if (inst.reloc.type != BFD_RELOC_UNUSED)
- fix_new_arm (frag_now, to - frag_now->fr_literal,
- inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
- inst.reloc.type);
+ int r;
+ for (r = 0; r < ARM_IT_MAX_RELOCS; r++)
+ {
+ if (inst.relocs[r].type != BFD_RELOC_UNUSED)
+ fix_new_arm (frag_now, to - frag_now->fr_literal,
+ inst.size, & inst.relocs[r].exp, inst.relocs[r].pc_rel,
+ inst.relocs[r].type);
+ }
dwarf2_emit_insn (inst.size);
}
@@ -18771,7 +18802,9 @@ md_assemble (char *str)
}
memset (&inst, '\0', sizeof (inst));
- inst.reloc.type = BFD_RELOC_UNUSED;
+ int r;
+ for (r = 0; r < ARM_IT_MAX_RELOCS; r++)
+ inst.relocs[r].type = BFD_RELOC_UNUSED;
opcode = opcode_lookup (&p);
if (!opcode)
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH, binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real for fallback branch
2019-04-04 13:24 [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Andre Vieira (lists)
` (2 preceding siblings ...)
2019-04-04 13:34 ` [PATCH, binutils, ARM, 4/16] BF insns infrastructure with array of relocs in struct arm_it Andre Vieira (lists)
@ 2019-04-04 13:34 ` Andre Vieira (lists)
2019-04-04 13:36 ` [PATCH, binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM_BF16 Andre Vieira (lists)
` (12 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-04 13:34 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 1240 bytes --]
Hi
This patch is part of a series of patches to add support for Armv8.1-M
Mainline instructions to binutils.
This adds infrastructure for the Branch Future instructions (BF, BFX,
BFL, BFLX, BFCSEL). These are the first instructions in ARM that
have more than one relocations in them.
This is the first infrastructure patch that adds a new
bfd_reloc_code_real enum for the fallback branch offset.
This is common for all such instructions and needs to be resolvable by
the assembler.
Testing: Builds successfully and no regressions.
Thanks
Sudi
ChangeLog entries are as follows :
*** bfd/ChnageLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_THUMB_PCREL_BRANCH5): New enum.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case
for BFD_RELOC_THUMB_PCREL_BRANCH5.
(v8_1_branch_value_check): New function to check branch
offsets.
(md_appdy_fix): New switch case for
BFD_RELOC_THUMB_PCREL_BRANCH5.
(tc_gen_reloc): Likewise.
*** opcodes/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
[-- Attachment #2: 3.patch --]
[-- Type: text/x-patch, Size: 6219 bytes --]
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 4f63fe50e6bf8003fb25beec9e64927a672e444b..3493d4f0de41cb184710248ce6664700bca78cca 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -3564,6 +3564,9 @@ field in the instruction. */
/* ARM 26-bit pc-relative branch for B or conditional BL instruction. */
BFD_RELOC_ARM_PCREL_JUMP,
+/* ARM 5-bit pc-relative branch for Branch Future instructions. */
+ BFD_RELOC_THUMB_PCREL_BRANCH5,
+
/* Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
The lowest bit must be zero and is not stored in the instruction.
Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index 36284d71a9bdb0237ad678027441ccf0fe880430..02daa29b433e390507fe91e7a045f43eb85d548d 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -1529,6 +1529,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_THUMB_PCREL_BLX",
"BFD_RELOC_ARM_PCREL_CALL",
"BFD_RELOC_ARM_PCREL_JUMP",
+ "BFD_RELOC_THUMB_PCREL_BRANCH5",
"BFD_RELOC_THUMB_PCREL_BRANCH7",
"BFD_RELOC_THUMB_PCREL_BRANCH9",
"BFD_RELOC_THUMB_PCREL_BRANCH12",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index e6446a78098602d91d3c7f4a0b20807b805bb829..a071dc75c0499192077da30aba8ee7fc3d62dacb 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -3014,6 +3014,11 @@ ENUM
ENUMDOC
ARM 26-bit pc-relative branch for B or conditional BL instruction.
+ENUM
+ BFD_RELOC_THUMB_PCREL_BRANCH5
+ENUMDOC
+ ARM 5-bit pc-relative branch for Branch Future instructions.
+
ENUM
BFD_RELOC_THUMB_PCREL_BRANCH7
ENUMX
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 11d593c2626199d0dad4f4d81a276decb0300d3c..a13baa603486623836977d4c8f68ac283d02cbab 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -235,6 +235,8 @@ static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN);
static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M);
static const arm_feature_set arm_ext_v8m_main =
ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN);
+static const arm_feature_set arm_ext_v8_1m_main =
+ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
/* Instructions in ARMv8-M only found in M profile architectures. */
static const arm_feature_set arm_ext_v8m_m_only =
ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
@@ -843,6 +845,7 @@ struct asm_opcode
#define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
#define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
#define BAD_BRANCH _("branch must be last instruction in IT block")
+#define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
#define BAD_NOT_IT _("instruction not allowed in IT block")
#define BAD_FPU _("selected FPU does not support instruction")
#define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
@@ -13272,6 +13275,26 @@ do_t_usat16 (void)
inst.instruction |= Rn << 16;
}
+/* Checking the range of the branch offset (VAL) with NBITS bits
+ and IS_SIGNED signedness. Also checks the LSB to be 0. */
+static int
+v8_1_branch_value_check (int val, int nbits, int is_signed)
+{
+ gas_assert (nbits > 0 && nbits <= 32);
+ if (is_signed)
+ {
+ int cmp = (1 << (nbits - 1));
+ if ((val < -cmp) || (val >= cmp) || (val & 0x01))
+ return FAIL;
+ }
+ else
+ {
+ if ((val <= 0) || (val >= (1 << nbits)) || (val & 0x1))
+ return FAIL;
+ }
+ return SUCCESS;
+}
+
/* Neon instruction encoder helpers. */
/* Encodings for the different types for various Neon opcodes. */
@@ -22791,6 +22814,7 @@ md_pcrel_from_section (fixS * fixP, segT seg)
return (base + 4) & ~3;
/* Thumb branches are simply offset by +4. */
+ case BFD_RELOC_THUMB_PCREL_BRANCH5:
case BFD_RELOC_THUMB_PCREL_BRANCH7:
case BFD_RELOC_THUMB_PCREL_BRANCH9:
case BFD_RELOC_THUMB_PCREL_BRANCH12:
@@ -24669,6 +24693,30 @@ md_apply_fix (fixS * fixP,
}
break;
+ case BFD_RELOC_THUMB_PCREL_BRANCH5:
+ if (fixP->fx_addsy
+ && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
+ && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && ARM_IS_FUNC (fixP->fx_addsy)
+ && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
+ {
+ /* Force a relocation for a branch 5 bits wide. */
+ fixP->fx_done = 0;
+ }
+ if (v8_1_branch_value_check (value, 5, FALSE) == FAIL)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ BAD_BRANCH_OFF);
+
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ addressT boff = value >> 1;
+
+ newval = md_chars_to_number (buf, THUMB_SIZE);
+ newval |= (boff << 7);
+ md_number_to_chars (buf, newval, THUMB_SIZE);
+ }
+ break;
+
case BFD_RELOC_ARM_V4BX:
/* This will need to go in the object file. */
fixP->fx_done = 0;
@@ -24880,6 +24928,12 @@ tc_gen_reloc (asection *section, fixS *fixp)
_("ADRL used for a symbol not defined in the same file"));
return NULL;
+ case BFD_RELOC_THUMB_PCREL_BRANCH5:
+ as_bad_where (fixp->fx_file, fixp->fx_line,
+ _("%s used for a symbol not defined in the same file"),
+ bfd_get_reloc_code_name (fixp->fx_r_type));
+ return NULL;
+
case BFD_RELOC_ARM_OFFSET_IMM:
if (section->use_rela_p)
{
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index be9879da621c14e4dd8a816a371aaad6ccc4a696..0fe44877db243b8cbce50fed451e65fcacf9fabc 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2714,6 +2714,7 @@ static const struct opcode16 thumb_opcodes[] =
%E print the lsb and width fields of a bfc/bfi instruction
%F print the lsb and width fields of a sbfx/ubfx instruction
+ %G print a fallback offset for Branch Future instructions
%b print a conditional branch offset
%B print an unconditional branch offset
%s print the shift field of an SSAT instruction
@@ -5863,6 +5864,13 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
}
break;
+ case 'G':
+ {
+ unsigned int boff = (((given & 0x07800000) >> 23) << 1);
+ func (stream, "%x", boff);
+ }
+ break;
+
case 'b':
{
unsigned int S = (given & 0x04000000u) >> 26;
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH, binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM_BF16
2019-04-04 13:24 [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Andre Vieira (lists)
` (3 preceding siblings ...)
2019-04-04 13:34 ` [PATCH, binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real for fallback branch Andre Vieira (lists)
@ 2019-04-04 13:36 ` Andre Vieira (lists)
2019-04-04 13:37 ` [PATCH, binutils, ARM, 6/16] New BF instruction for Armv8.1-M Mainline Andre Vieira (lists)
` (11 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-04 13:36 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 1848 bytes --]
Hi
This patch is part of a series of patches to add support for Armv8.1-M
Mainline instructions to binutils.
This adds infrastructure for the BF instructions which is one of the
first instructions in Arm that
have more than one relocations in them.
This is the third infrastructure patch that adds a new relocation
R_ARM_THM_BF16. Relocation specified in
https://developer.arm.com/docs/ihi0044/latest/elf-for-the-arm-architecture-abi-2019q1-documentation#aaelf32-table4-9
The inconsistency between external R_ARM_THM_BF16 and internal
BFD_RELOC_ARM_THUMB_BF17 is because internally we count the static bit-0
of the immediate and we don't externally.
Testing: Builds successfully and no regressions.
Thanks
Sudi
ChangeLog entries are as follows :
*** bfd/ChnageLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF16.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF17
and R_ARM_THM_BF16 together.
(get_value_helper): New reloc helper.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF16.
*** elfcpp/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF16): New relocation code.
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF17.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16.
*** opcodes/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 5.patch --]
[-- Type: text/x-patch; name="5.patch", Size: 10716 bytes --]
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 3493d4f0de41cb184710248ce6664700bca78cca..b5922ff222b48e0699a814c9742e0a61cdca9cb8 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -3567,6 +3567,9 @@ field in the instruction. */
/* ARM 5-bit pc-relative branch for Branch Future instructions. */
BFD_RELOC_THUMB_PCREL_BRANCH5,
+/* ARM 17-bit pc-relative branch for Branch Future instructions. */
+ BFD_RELOC_ARM_THUMB_BF17,
+
/* Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
The lowest bit must be zero and is not stored in the instruction.
Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 735fe122880c59633b0083b78b9b1e686cfd91c5..abdc2bbdac6f00e7ce631bcb1dfa477edf480063 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -1742,6 +1742,20 @@ static reloc_howto_type elf32_arm_howto_table_1[] =
0x00000000, /* src_mask. */
0x00000000, /* dst_mask. */
FALSE), /* pcrel_offset. */
+ /* Relocations for Armv8.1-M Mainline. */
+ HOWTO (R_ARM_THM_BF16, /* type. */
+ 0, /* rightshift. */
+ 1, /* size (0 = byte, 1 = short, 2 = long). */
+ 16, /* bitsize. */
+ TRUE, /* pc_relative. */
+ 0, /* bitpos. */
+ complain_overflow_dont,/* do not complain_on_overflow. */
+ bfd_elf_generic_reloc, /* special_function. */
+ "R_ARM_THM_BF16", /* name. */
+ FALSE, /* partial_inplace. */
+ 0x001f0ffe, /* src_mask. */
+ 0x001f0ffe, /* dst_mask. */
+ TRUE), /* pcrel_offset. */
};
/* 160 onwards: */
@@ -2053,7 +2067,8 @@ static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
{BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
{BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
{BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
- {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
+ {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
+ {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16}
};
static reloc_howto_type *
@@ -10250,6 +10265,59 @@ identify_add_or_sub (bfd_vma insn)
return 0;
}
+/* Helper function to compute the Addend for Armv8.1-M Mainline relocations. */
+static bfd_vma
+get_value_helper (bfd_vma plt_offset,
+ asection *splt,
+ asection *input_section,
+ asection *sym_sec,
+ struct elf_link_hash_entry * h,
+ struct bfd_link_info *info,
+ bfd *input_bfd,
+ Elf_Internal_Rela *rel,
+ const char *sym_name,
+ unsigned char st_type,
+ struct elf32_arm_link_hash_table *globals,
+ bfd_boolean *unresolved_reloc_p)
+{
+ bfd_vma value = 0;
+ enum arm_st_branch_type branch_type;
+ enum elf32_arm_stub_type stub_type = arm_stub_none;
+ struct elf32_arm_stub_hash_entry *stub_entry;
+ struct elf32_arm_link_hash_entry *hash
+ = (struct elf32_arm_link_hash_entry *)h;
+
+
+ if (plt_offset != (bfd_vma) -1)
+ {
+ value = (splt->output_section->vma
+ + splt->output_offset
+ + plt_offset);
+ value -= PLT_THUMB_STUB_SIZE;
+ *unresolved_reloc_p = FALSE;
+ }
+
+ stub_type = arm_type_of_stub (info, input_section, rel,
+ st_type, &branch_type,
+ hash, value, sym_sec,
+ input_bfd, sym_name);
+
+ if (stub_type != arm_stub_none)
+ {
+ stub_entry = elf32_arm_get_stub_entry (input_section,
+ sym_sec, h,
+ rel, globals,
+ stub_type);
+ if (stub_entry != NULL)
+ {
+ value = (stub_entry->stub_offset
+ + stub_entry->stub_sec->output_offset
+ + stub_entry->stub_sec->output_section->vma);
+ }
+ }
+ return value;
+}
+
/* Perform a relocation as part of a final link. */
static bfd_reloc_status_type
@@ -12855,6 +12923,51 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
*unresolved_reloc_p = FALSE;
return bfd_reloc_ok;
+ case R_ARM_THM_BF16:
+ {
+ bfd_vma relocation;
+ bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
+ bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
+
+ if (globals->use_rel)
+ {
+ bfd_vma immA = (upper_insn & 0x001f);
+ bfd_vma immB = (lower_insn & 0x07fe) >> 1;
+ bfd_vma immC = (lower_insn & 0x0800) >> 11;
+ addend = (immA << 12);
+ addend |= (immB << 2);
+ addend |= (immC << 1);
+ addend |= 1;
+ /* Sign extend. */
+ addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
+ }
+
+ value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
+ info, input_bfd, rel, sym_name, st_type,
+ globals, unresolved_reloc_p);
+
+ relocation = value + addend;
+ relocation -= (input_section->output_section->vma
+ + input_section->output_offset
+ + rel->r_offset);
+
+ /* Put RELOCATION back into the insn. */
+ {
+ bfd_vma immA = (relocation & 0x0001f000) >> 12;
+ bfd_vma immB = (relocation & 0x00000ffc) >> 2;
+ bfd_vma immC = (relocation & 0x00000002) >> 1;
+
+ upper_insn = (upper_insn & 0xffe0) | immA;
+ lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
+ }
+
+ /* Put the relocated value back in the object file: */
+ bfd_put_16 (input_bfd, upper_insn, hit_data);
+ bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
+
+ return bfd_reloc_ok;
+ }
+
default:
return bfd_reloc_notsupported;
}
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index 02daa29b433e390507fe91e7a045f43eb85d548d..4a3fa144ad25b5a800501c352e6f0aa79509bb27 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -1530,6 +1530,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_ARM_PCREL_CALL",
"BFD_RELOC_ARM_PCREL_JUMP",
"BFD_RELOC_THUMB_PCREL_BRANCH5",
+ "BFD_RELOC_ARM_THUMB_BF17",
"BFD_RELOC_THUMB_PCREL_BRANCH7",
"BFD_RELOC_THUMB_PCREL_BRANCH9",
"BFD_RELOC_THUMB_PCREL_BRANCH12",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index a071dc75c0499192077da30aba8ee7fc3d62dacb..b351d120d1d1894ba64a3eb2d32e21884648fd6a 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -3019,6 +3019,11 @@ ENUM
ENUMDOC
ARM 5-bit pc-relative branch for Branch Future instructions.
+ENUM
+ BFD_RELOC_ARM_THUMB_BF17
+ENUMDOC
+ ARM 17-bit pc-relative branch for Branch Future instructions.
+
ENUM
BFD_RELOC_THUMB_PCREL_BRANCH7
ENUMX
diff --git a/elfcpp/arm.h b/elfcpp/arm.h
index fb5cc25f0695fb62e398c6c9a26b7e2c59e40be0..b4cd67f87ce49288ee40adb7653443b493774267 100644
--- a/elfcpp/arm.h
+++ b/elfcpp/arm.h
@@ -194,7 +194,10 @@ enum
R_ARM_ME_TOO = 128, // Obsolete
R_ARM_THM_TLS_DESCSEQ16 = 129,// Static Thumb16
R_ARM_THM_TLS_DESCSEQ32 = 130,// Static Thumb32
- // 131 - 139 Unallocated
+ // 131 - 135 Unallocated
+ // Relocations for Armv8.1-M Mainline (BF/BFL)
+ R_ARM_THM_BF16 = 136, // Static Thumb32 ((S + A) | T) – P
+ // 139 Unallocated
// 140 - 159 Dynamic Reserved for future allocation
R_ARM_IRELATIVE = 160, // Dynamic
// 161 - 255 Unallocated
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 14d114adbeec62b11fa3bc7d4f7cb3cdd030bf8f..d3a21d63575c194051606bb723a224d3c10334e9 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -22853,6 +22853,7 @@ md_pcrel_from_section (fixS * fixP, segT seg)
case BFD_RELOC_THUMB_PCREL_BRANCH12:
case BFD_RELOC_THUMB_PCREL_BRANCH20:
case BFD_RELOC_THUMB_PCREL_BRANCH25:
+ case BFD_RELOC_ARM_THUMB_BF17:
return base + 4;
case BFD_RELOC_THUMB_PCREL_BRANCH23:
@@ -24750,6 +24751,39 @@ md_apply_fix (fixS * fixP,
}
break;
+ case BFD_RELOC_ARM_THUMB_BF17:
+ if (fixP->fx_addsy
+ && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
+ && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && ARM_IS_FUNC (fixP->fx_addsy)
+ && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
+ {
+ /* Force a relocation for a branch 17 bits wide. */
+ fixP->fx_done = 0;
+ }
+
+ if (v8_1_branch_value_check (value, 17, TRUE) == FAIL)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ BAD_BRANCH_OFF);
+
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ offsetT newval2;
+ addressT immA, immB, immC;
+
+ immA = (value & 0x0001f000) >> 12;
+ immB = (value & 0x00000ffc) >> 2;
+ immC = (value & 0x00000002) >> 1;
+
+ newval = md_chars_to_number (buf, THUMB_SIZE);
+ newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
+ newval |= immA;
+ newval2 |= (immC << 11) | (immB << 1);
+ md_number_to_chars (buf, newval, THUMB_SIZE);
+ md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
+ }
+ break;
+
case BFD_RELOC_ARM_V4BX:
/* This will need to go in the object file. */
fixP->fx_done = 0;
@@ -24932,6 +24966,7 @@ tc_gen_reloc (asection *section, fixS *fixp)
case BFD_RELOC_ARM_GOTFUNCDESC:
case BFD_RELOC_ARM_GOTOFFFUNCDESC:
case BFD_RELOC_ARM_FUNCDESC:
+ case BFD_RELOC_ARM_THUMB_BF17:
code = fixp->fx_r_type;
break;
diff --git a/include/elf/arm.h b/include/elf/arm.h
index daf1d94391ea23c49cb646af430d2db8ef46c51e..2c6d4ef18a96e10fb206248df151c44a67757042 100644
--- a/include/elf/arm.h
+++ b/include/elf/arm.h
@@ -241,6 +241,7 @@ START_RELOC_NUMBERS (elf_arm_reloc_type)
RELOC_NUMBER (R_ARM_THM_ALU_ABS_G1_NC,133)
RELOC_NUMBER (R_ARM_THM_ALU_ABS_G2_NC,134)
RELOC_NUMBER (R_ARM_THM_ALU_ABS_G3_NC,135)
+ RELOC_NUMBER (R_ARM_THM_BF16, 136)
RELOC_NUMBER (R_ARM_IRELATIVE, 160)
RELOC_NUMBER (R_ARM_GOTFUNCDESC, 161)
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 0fe44877db243b8cbce50fed451e65fcacf9fabc..71443d3ea41966309d4516754eb8f2e38e3e6df0 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2715,6 +2715,7 @@ static const struct opcode16 thumb_opcodes[] =
%E print the lsb and width fields of a bfc/bfi instruction
%F print the lsb and width fields of a sbfx/ubfx instruction
%G print a fallback offset for Branch Future instructions
+ %W print an offset for BF instruction
%b print a conditional branch offset
%B print an unconditional branch offset
%s print the shift field of an SSAT instruction
@@ -5871,6 +5872,23 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
}
break;
+ case 'W':
+ {
+ unsigned int immA = (given & 0x001f0000u) >> 16;
+ unsigned int immB = (given & 0x000007feu) >> 1;
+ unsigned int immC = (given & 0x00000800u) >> 11;
+ bfd_vma offset = 0;
+
+ offset |= immA << 12;
+ offset |= immB << 2;
+ offset |= immC << 1;
+ /* Sign extend. */
+ offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
+
+ info->print_address_func (pc + 4 + offset, info);
+ }
+ break;
+
case 'b':
{
unsigned int S = (given & 0x04000000u) >> 26;
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH, binutils, ARM, 6/16] New BF instruction for Armv8.1-M Mainline
2019-04-04 13:24 [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Andre Vieira (lists)
` (4 preceding siblings ...)
2019-04-04 13:36 ` [PATCH, binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM_BF16 Andre Vieira (lists)
@ 2019-04-04 13:37 ` Andre Vieira (lists)
2019-04-12 10:41 ` Andre Vieira (lists)
2019-04-04 13:38 ` [PATCH, binutils, ARM, 7/16] New BFX and BFLX " Andre Vieira (lists)
` (10 subsequent siblings)
16 siblings, 1 reply; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-04 13:37 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 1049 bytes --]
Hi
This patch is part of a series of patches to add support for Armv8.1-M
Mainline instructions to binutils.
This patch adds the BF instruction.
Testing: Added new tests for the valid instructions operands. Testsuite
shows no regression when run for arm-none-eabi targets.
Thanks
Sudi
ChangeLog entries are as follows :
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (T16_32_TAB): New entries for bf.
(do_t_branch_future): New.
(insns): New instruction for bf.
* testsuite/gas/arm/armv8_1-m-bf.d: New.
* testsuite/gas/arm/armv8_1-m-bf.s: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.s: New
* testsuite/gas/arm/armv8_1-m-bf-bad.l: New
* testsuite/gas/arm/armv8_1-m-bf-bad.d: New
*** ld/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bf.s: New.
* testsuite/ld-arm/bf.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instructions for bf.
[-- Attachment #2: 6.patch --]
[-- Type: text/x-patch, Size: 8532 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index d3a21d63575c194051606bb723a224d3c10334e9..04bd9b0e612b2e88db275effeec2749a4ba3605f 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -10505,6 +10505,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
X(_asrs, 1000, fa50f000), \
X(_b, e000, f000b000), \
X(_bcond, d000, f0008000), \
+ X(_bf, 0000, f040e001), \
X(_bic, 4380, ea200000), \
X(_bics, 4380, ea300000), \
X(_cmn, 42c0, eb100f00), \
@@ -13320,6 +13321,51 @@ v8_1_branch_value_check (int val, int nbits, int is_signed)
return SUCCESS;
}
+/* For branches in Armv8.1-M Mainline. */
+static void
+do_t_branch_future (void)
+{
+ unsigned long insn = inst.instruction;
+
+ inst.instruction = THUMB_OP32 (inst.instruction);
+ if (inst.operands[0].hasreloc == 0)
+ {
+ if (v8_1_branch_value_check (inst.operands[0].imm, 5, FALSE) == FAIL)
+ as_bad (BAD_BRANCH_OFF);
+
+ inst.instruction |= ((inst.operands[0].imm & 0x1f) >> 1) << 23;
+ }
+ else
+ {
+ inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH5;
+ inst.relocs[0].pc_rel = 1;
+ }
+
+ switch (insn)
+ {
+ case T_MNEM_bf:
+ if (inst.operands[1].hasreloc == 0)
+ {
+ int val = inst.operands[1].imm;
+ if (v8_1_branch_value_check (inst.operands[1].imm, 17, TRUE) == FAIL)
+ as_bad (BAD_BRANCH_OFF);
+
+ int immA = (val & 0x0001f000) >> 12;
+ int immB = (val & 0x00000ffc) >> 2;
+ int immC = (val & 0x00000002) >> 1;
+ inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
+ }
+ else
+ {
+ inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF17;
+ inst.relocs[1].pc_rel = 1;
+ }
+ break;
+
+ default: abort ();
+ }
+}
+
/* Neon instruction encoder helpers. */
/* Encodings for the different types for various Neon opcodes. */
@@ -19538,6 +19584,11 @@ static struct asm_barrier_opt barrier_opt_names[] =
{ mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
NULL, do_##te }
+/* T_MNEM_xyz enumerator variants of ToC. */
+#define toC(mnem, top, nops, ops, te) \
+ { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
+ do_##te }
+
/* Legacy mnemonics that always have conditional infix after the third
character. */
#define CL(mnem, op, nops, ops, ae) \
@@ -21623,6 +21674,11 @@ static const struct asm_opcode insns[] =
#define THUMB_VARIANT & arm_ext_v8m_main
ToC("vlldm", ec300a00, 1, (RRnpc), rn),
ToC("vlstm", ec200a00, 1, (RRnpc), rn),
+
+ /* Armv8.1-M Mainline instructions. */
+#undef THUMB_VARIANT
+#define THUMB_VARIANT & arm_ext_v8_1m_main
+ toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
};
#undef ARM_VARIANT
#undef THUMB_VARIANT
@@ -21633,8 +21689,10 @@ static const struct asm_opcode insns[] =
#undef cCE
#undef cCL
#undef C3E
+#undef C3
#undef CE
#undef CM
+#undef CL
#undef UE
#undef UF
#undef UT
@@ -21650,6 +21708,10 @@ static const struct asm_opcode insns[] =
#undef OPS5
#undef OPS6
#undef do_0
+#undef ToC
+#undef toC
+#undef ToU
+#undef
\f
/* MD interface: bits in the object file. */
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-bad.d b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..d61aad79e9a6faa26a733245b3769b867f5e126d
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.d
@@ -0,0 +1,4 @@
+#name: Invalid Armv8.1-M Mainline BF instructions
+#source: armv8_1-m-bf-bad.s
+#as: -march=armv8.1-m.main
+#error_output: armv8_1-m-bf-bad.l
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-bad.l b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..3f7ed80a6d07a4a2c05e8968e95c26d66eae2fab
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.l
@@ -0,0 +1,9 @@
+.*: Assembler messages:
+.*:6: Error: branch out of range or not a multiple of 2
+.*:7: Error: branch out of range or not a multiple of 2
+.*:8: Error: branch out of range or not a multiple of 2
+.*:9: Error: branch out of range or not a multiple of 2
+.*:11: Error: branch out of range or not a multiple of 2
+.*:12: Error: branch out of range or not a multiple of 2
+.*:13: Error: branch out of range or not a multiple of 2
+.*:14: Error: branch out of range or not a multiple of 2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-bad.s b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..43ef4b1bf92fa42956f2fdabd29eeec7bcf168fb
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.s
@@ -0,0 +1,14 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+ # OP0 : Unsigned, 5-bit, even
+ bf 0, 36
+ bf -2, 36
+ bf 3, 36
+ bf 32, 36
+ # OP1 : signed, 17-bit, even
+ bf 2, -5
+ bf 2, 5
+ bf 2, 65536
+ bf 2, -65538
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf.d b/gas/testsuite/gas/arm/armv8_1-m-bf.d
new file mode 100644
index 0000000000000000000000000000000000000000..9e721ed290d1291c27c210768ebf0358c038a105
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf.d
@@ -0,0 +1,17 @@
+#name: Valid Armv8.1-M Mainline BF instruction
+#source: armv8_1-m-bf.s
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f0c0 e803 bf 2, 0000000a <foo\+0xa>
+0[0-9a-f]+ <[^>]+> 4608 mov r0, r1
+0[0-9a-f]+ <[^>]+> f0df e7ff bf 2, 00000000 <.target>
+ 6: R_ARM_THM_BF16 .target
+0[0-9a-f]+ <[^>]+> 4609 mov r1, r1
+0[0-9a-f]+ <[^>]+> f140 e801 bf 4, 00000012 <foo\+0x12>
+0[0-9a-f]+ <[^>]+> 460a mov r2, r1
+0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
+0[0-9a-f]+ <[^>]+> 4614 mov r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf.s b/gas/testsuite/gas/arm/armv8_1-m-bf.s
new file mode 100644
index 0000000000000000000000000000000000000000..cafc34bf5de4d54ef3db6139b8c997fa22608a2f
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf.s
@@ -0,0 +1,14 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+ bf 2, 6
+ mov r0, r1
+ bf 2, .target
+ mov r1, r1
+ bf .LBranch, .LB2
+ mov r2, r1
+.LB2:
+ mov r3, r2
+.LBranch:
+ mov r4, r2
diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp
index 450a76b7082be883d0bbc818420edd2d6a762e6e..ef3a49c23742f4c43c78e73aa692928ba3d56123 100644
--- a/ld/testsuite/ld-arm/arm-elf.exp
+++ b/ld/testsuite/ld-arm/arm-elf.exp
@@ -667,6 +667,10 @@ set armeabitests_nonacl {
{{objdump -d armv4-bx.d}}
"armv4-bx"}
+ {"Armv8.1-M Mainline BF" "-r -Ttext 0x1000 --section-start .foo=0x1001000" "" "-march=armv8.1-m.main" {bf.s}
+ {{objdump -dr bf.d}}
+ "bf"}
+
{"R_ARM_THM_JUMP24 Relocation veneers: Short 1"
"--no-fix-arm1176 --section-start destsect=0x00009000 --section-start .text=0x8000" ""
"-march=armv7-a -mthumb"
diff --git a/ld/testsuite/ld-arm/bf.d b/ld/testsuite/ld-arm/bf.d
new file mode 100644
index 0000000000000000000000000000000000000000..190383f93af81e6c9ba023b07d1bfa3771e29a97
--- /dev/null
+++ b/ld/testsuite/ld-arm/bf.d
@@ -0,0 +1,14 @@
+
+.*: file format elf32-littlearm
+
+
+Disassembly of section .text:
+
+00001000 <_start>:
+ 1000: f0df e7ff bf 2, 1001000 <bar>
+ 1000: R_ARM_THM_BF16 bar
+
+Disassembly of section .foo:
+
+01001000 <bar>:
+ 1001000: 4770 bx lr
diff --git a/ld/testsuite/ld-arm/bf.s b/ld/testsuite/ld-arm/bf.s
new file mode 100644
index 0000000000000000000000000000000000000000..164a90d04b4e995add2c54beee31e63fbdc5c12d
--- /dev/null
+++ b/ld/testsuite/ld-arm/bf.s
@@ -0,0 +1,19 @@
+ .global _start
+ .syntax unified
+
+@ We will place the section .text at 0x1000.
+
+ .text
+ .thumb_func
+
+_start:
+ bf 2, bar
+
+@ We will place the section .foo at 0x1001000.
+
+ .section .foo, "xa"
+ .thumb_func
+
+bar:
+ bx lr
+
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 71443d3ea41966309d4516754eb8f2e38e3e6df0..966a4d4d92fa660b1754c4c703648ec008efcfb0 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2747,6 +2747,11 @@ static const struct opcode16 thumb_opcodes[] =
makes heavy use of special-case bit patterns. */
static const struct opcode32 thumb32_opcodes[] =
{
+ /* Armv8.1-M Mainline instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
+
+
/* ARMv8-M and ARMv8-M Security Extensions instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH, binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8.1-M Mainline
2019-04-04 13:24 [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Andre Vieira (lists)
` (5 preceding siblings ...)
2019-04-04 13:37 ` [PATCH, binutils, ARM, 6/16] New BF instruction for Armv8.1-M Mainline Andre Vieira (lists)
@ 2019-04-04 13:38 ` Andre Vieira (lists)
2019-04-04 13:38 ` [PATCH, binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18 Andre Vieira (lists)
` (9 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-04 13:38 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 1092 bytes --]
Hi
This patch is part of a series of patches to add support for Armv8.1-M
Mainline instructions to binutils.
This patch adds the BFX and BFLX instructions.
Testing: Added new test for the valid and invalid instructions operands.
Testsuite shows no regression when run for arm-none-eabi targets.
Thanks
Sudi
ChangeLog entries are as follows :
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (T16_32_TAB): New entries for bfx and bflx.
(do_t_v8_1_branch): New switch cases for bfx and bflx.
(insns): New instruction for bfx and bflx.
* testsuite/gas/arm/armv8_1-m-bf-exchange.d: New.
* testsuite/gas/arm/armv8_1-m-bf-exchange.s: New.
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s: New
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l: New
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d: New
*** opcodes/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
Arm register with r13 and r15 unpredictable.
(thumb32_opcodes): New instructions for bfx and bflx.
[-- Attachment #2: 7.patch --]
[-- Type: text/x-patch, Size: 5584 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 04bd9b0e612b2e88db275effeec2749a4ba3605f..c7c1a82a998ce08330e05f3f2b3e34e453b87b2c 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -10506,6 +10506,8 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
X(_b, e000, f000b000), \
X(_bcond, d000, f0008000), \
X(_bf, 0000, f040e001), \
+ X(_bfx, 0000, f060e001), \
+ X(_bflx, 0000, f070e001), \
X(_bic, 4380, ea200000), \
X(_bics, 4380, ea300000), \
X(_cmn, 42c0, eb100f00), \
@@ -13362,6 +13364,11 @@ do_t_branch_future (void)
}
break;
+ case T_MNEM_bfx:
+ case T_MNEM_bflx:
+ inst.instruction |= inst.operands[1].reg << 16;
+ break;
+
default: abort ();
}
}
@@ -21679,6 +21686,8 @@ static const struct asm_opcode insns[] =
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_v8_1m_main
toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
+ toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future),
+ toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future),
};
#undef ARM_VARIANT
#undef THUMB_VARIANT
@@ -21711,7 +21720,6 @@ static const struct asm_opcode insns[] =
#undef ToC
#undef toC
#undef ToU
-#undef
\f
/* MD interface: bits in the object file. */
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..3ee7df81610c45f68aced3982cb04589104d6873
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d
@@ -0,0 +1,4 @@
+#name: Invalid Armv8.1-M Mainline BF-exchange instructions
+#source: armv8_1-m-bf-exchange-bad.s
+#as: -march=armv8.1-m.main
+#error_output: armv8_1-m-bf-exchange-bad.l
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..1033b71e6ea2ad7a6886ba1d45e34537ea650a04
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l
@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*:6: Error: branch out of range or not a multiple of 2
+.*:7: Error: branch out of range or not a multiple of 2
+.*:8: Error: branch out of range or not a multiple of 2
+.*:9: Error: branch out of range or not a multiple of 2
+.*:11: Error: r15 not allowed here -- `bfx 2,PC'
+.*:12: Error: r13 not allowed here -- `bflx 2,SP'
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..ca06eaf3d4fa6cf692b78b0dee87c6c75a888f71
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s
@@ -0,0 +1,12 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+ # OP0 : Unsigned, 5-bit, even
+ bfx 0, r3
+ bfx -2, r3
+ bflx 3, r3
+ bflx 32, r3
+ # OP1 : no SP or PC
+ bfx 2, PC
+ bflx 2, SP
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-exchange.d b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange.d
new file mode 100644
index 0000000000000000000000000000000000000000..e88bb941acd7ebe29867dba940a69992932e6ada
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange.d
@@ -0,0 +1,14 @@
+#name: Valid Armv8.1-M Mainline BF-exchange instructions
+#source: armv8_1-m-bf-exchange.s
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f265 e001 bfx 8, r5
+0[0-9a-f]+ <[^>]+> 4609 mov r1, r1
+0[0-9a-f]+ <[^>]+> f173 e001 bflx 4, r3
+0[0-9a-f]+ <[^>]+> 460a mov r2, r1
+0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
+0[0-9a-f]+ <[^>]+> 4614 mov r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-exchange.s b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange.s
new file mode 100644
index 0000000000000000000000000000000000000000..e3d9dfcdc7a2f518a10c4e71568b32dc6694aaba
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange.s
@@ -0,0 +1,12 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+ bfx .LB1, r5
+ mov r1, r1
+ bflx .LB2, r3
+ mov r2, r1
+.LB1:
+ mov r3, r2
+.LB2:
+ mov r4, r2
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 966a4d4d92fa660b1754c4c703648ec008efcfb0..2929522fa359bd55305d50da84598a17813c2510 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2731,6 +2731,7 @@ static const struct opcode16 thumb_opcodes[] =
%<bitfield>W print bitfield*4 in decimal
%<bitfield>r print bitfield as an ARM register
%<bitfield>R as %<>r but r15 is UNPREDICTABLE
+ %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
%<bitfield>c print bitfield as a condition code
%<bitfield>'c print specified char iff bitfield is all ones
@@ -2750,6 +2751,10 @@ static const struct opcode32 thumb32_opcodes[] =
/* Armv8.1-M Mainline instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
/* ARMv8-M and ARMv8-M Security Extensions instructions. */
@@ -6057,6 +6062,10 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
value_in_comment = val * 4;
break;
+ case 'S':
+ if (val == 13)
+ is_unpredictable = TRUE;
+ /* Fall through. */
case 'R':
if (val == 15)
is_unpredictable = TRUE;
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH, binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18
2019-04-04 13:24 [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Andre Vieira (lists)
` (6 preceding siblings ...)
2019-04-04 13:38 ` [PATCH, binutils, ARM, 7/16] New BFX and BFLX " Andre Vieira (lists)
@ 2019-04-04 13:38 ` Andre Vieira (lists)
2019-04-04 13:39 ` [PATCH, binutils, ARM, 9/16] New BFL instruction for Armv8.1-M Mainline Andre Vieira (lists)
` (8 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-04 13:38 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 1764 bytes --]
Hi
This patch is part of a series of patches to add support for Armv8.1-M
Mainline instructions to binutils.
This adds infrastructure for the BFL instructions which is one of the
first instructions in Arm that
have more than one relocations in them.
This adds a new relocation R_ARM_THM_BF18. Relocation specified in
https://developer.arm.com/docs/ihi0044/latest/elf-for-the-arm-architecture-abi-2019q1-documentation#aaelf32-table4-9
The inconsistency between external R_ARM_THM_BF18 and internal
BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0
of the immediate and we don't externally.
Testing: Builds successfully and no regressions.
Thanks
Sudi
ChangeLog entries are as follows :
*** bfd/ChnageLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF19): New
* libbfd.h: Regenerated.
* bfd-in2.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19
and R_ARM_THM_BF18 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19.
*** elfcpp/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF18): New relocation code.
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF19.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18.
*** opcodes/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 8.patch --]
[-- Type: text/x-patch; name="8.patch", Size: 8829 bytes --]
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index b5922ff222b48e0699a814c9742e0a61cdca9cb8..99b0db4ec6d6ddfde74f47215510e0905b910e95 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -3570,6 +3570,9 @@ field in the instruction. */
/* ARM 17-bit pc-relative branch for Branch Future instructions. */
BFD_RELOC_ARM_THUMB_BF17,
+/* ARM 19-bit pc-relative branch for Branch Future Link instruction. */
+ BFD_RELOC_ARM_THUMB_BF19,
+
/* Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
The lowest bit must be zero and is not stored in the instruction.
Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index f5dc61b79ed2c6f5eb5800c3807f79438d1e3f1c..744d92515e81f558d5aacdeff53ef74cc2749437 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -1756,6 +1756,20 @@ static reloc_howto_type elf32_arm_howto_table_1[] =
0x001f0ffe, /* src_mask. */
0x001f0ffe, /* dst_mask. */
TRUE), /* pcrel_offset. */
+ EMPTY_HOWTO (137),
+ HOWTO (R_ARM_THM_BF18, /* type. */
+ 0, /* rightshift. */
+ 1, /* size (0 = byte, 1 = short, 2 = long). */
+ 18, /* bitsize. */
+ TRUE, /* pc_relative. */
+ 0, /* bitpos. */
+ complain_overflow_dont,/* do not complain_on_overflow. */
+ bfd_elf_generic_reloc, /* special_function. */
+ "R_ARM_THM_BF18", /* name. */
+ FALSE, /* partial_inplace. */
+ 0x007f0ffe, /* src_mask. */
+ 0x007f0ffe, /* dst_mask. */
+ TRUE), /* pcrel_offset. */
};
/* 160 onwards: */
@@ -2068,7 +2082,8 @@ static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
{BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
{BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
{BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
- {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16}
+ {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16},
+ {BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18}
};
static reloc_howto_type *
@@ -12968,6 +12983,51 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
return bfd_reloc_ok;
}
+ case R_ARM_THM_BF18:
+ {
+ bfd_vma relocation;
+ bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
+ bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
+
+ if (globals->use_rel)
+ {
+ bfd_vma immA = (upper_insn & 0x007f);
+ bfd_vma immB = (lower_insn & 0x07fe) >> 1;
+ bfd_vma immC = (lower_insn & 0x0800) >> 11;
+ addend = (immA << 12);
+ addend |= (immB << 2);
+ addend |= (immC << 1);
+ addend |= 1;
+ /* Sign extend. */
+ addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
+ }
+
+ value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
+ info, input_bfd, rel, sym_name, st_type,
+ globals, unresolved_reloc_p);
+
+ relocation = value + addend;
+ relocation -= (input_section->output_section->vma
+ + input_section->output_offset
+ + rel->r_offset);
+
+ /* Put RELOCATION back into the insn. */
+ {
+ bfd_vma immA = (relocation & 0x0007f000) >> 12;
+ bfd_vma immB = (relocation & 0x00000ffc) >> 2;
+ bfd_vma immC = (relocation & 0x00000002) >> 1;
+
+ upper_insn = (upper_insn & 0xff80) | immA;
+ lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
+ }
+
+ /* Put the relocated value back in the object file: */
+ bfd_put_16 (input_bfd, upper_insn, hit_data);
+ bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
+
+ return bfd_reloc_ok;
+ }
+
default:
return bfd_reloc_notsupported;
}
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index 4a3fa144ad25b5a800501c352e6f0aa79509bb27..7f775acf9178d70ad8351064f2e2291dd79c73a0 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -1531,6 +1531,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_ARM_PCREL_JUMP",
"BFD_RELOC_THUMB_PCREL_BRANCH5",
"BFD_RELOC_ARM_THUMB_BF17",
+ "BFD_RELOC_ARM_THUMB_BF19",
"BFD_RELOC_THUMB_PCREL_BRANCH7",
"BFD_RELOC_THUMB_PCREL_BRANCH9",
"BFD_RELOC_THUMB_PCREL_BRANCH12",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index b351d120d1d1894ba64a3eb2d32e21884648fd6a..9e3899ab4e7f3485cc2bd0f0953f652e0b28f48a 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -3024,6 +3024,11 @@ ENUM
ENUMDOC
ARM 17-bit pc-relative branch for Branch Future instructions.
+ENUM
+ BFD_RELOC_ARM_THUMB_BF19
+ENUMDOC
+ ARM 19-bit pc-relative branch for Branch Future Link instruction.
+
ENUM
BFD_RELOC_THUMB_PCREL_BRANCH7
ENUMX
diff --git a/elfcpp/arm.h b/elfcpp/arm.h
index e70f8bb01cc24b4445147d76c8a9bd28c562e017..a505a1ba37568c8b82d1ccc6dfebb63bf2595e75 100644
--- a/elfcpp/arm.h
+++ b/elfcpp/arm.h
@@ -197,6 +197,7 @@ enum
// 131 - 135 Unallocated
// New relocations for Armv8.1-M Mainline (BF/BFL)
R_ARM_THM_BF16 = 136, // Static Thumb32 ((S + A) | T) – P
+ R_ARM_THM_BF18 = 138, // Static Thumb32 ((S + A) | T) – P
// 139 Unallocated
// 140 - 159 Dynamic Reserved for future allocation
R_ARM_IRELATIVE = 160, // Dynamic
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index c7c1a82a998ce08330e05f3f2b3e34e453b87b2c..177d90f1c6fdc9ad99a395b479b16e5b9f8ae0b6 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -22924,6 +22924,7 @@ md_pcrel_from_section (fixS * fixP, segT seg)
case BFD_RELOC_THUMB_PCREL_BRANCH20:
case BFD_RELOC_THUMB_PCREL_BRANCH25:
case BFD_RELOC_ARM_THUMB_BF17:
+ case BFD_RELOC_ARM_THUMB_BF19:
return base + 4;
case BFD_RELOC_THUMB_PCREL_BRANCH23:
@@ -24854,6 +24855,39 @@ md_apply_fix (fixS * fixP,
}
break;
+ case BFD_RELOC_ARM_THUMB_BF19:
+ if (fixP->fx_addsy
+ && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
+ && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && ARM_IS_FUNC (fixP->fx_addsy)
+ && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
+ {
+ /* Force a relocation for a branch 19 bits wide. */
+ fixP->fx_done = 0;
+ }
+
+ if (v8_1_branch_value_check (value, 19, TRUE) == FAIL)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ BAD_BRANCH_OFF);
+
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ offsetT newval2;
+ addressT immA, immB, immC;
+
+ immA = (value & 0x0007f000) >> 12;
+ immB = (value & 0x00000ffc) >> 2;
+ immC = (value & 0x00000002) >> 1;
+
+ newval = md_chars_to_number (buf, THUMB_SIZE);
+ newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
+ newval |= immA;
+ newval2 |= (immC << 11) | (immB << 1);
+ md_number_to_chars (buf, newval, THUMB_SIZE);
+ md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
+ }
+ break;
+
case BFD_RELOC_ARM_V4BX:
/* This will need to go in the object file. */
fixP->fx_done = 0;
@@ -25037,6 +25071,7 @@ tc_gen_reloc (asection *section, fixS *fixp)
case BFD_RELOC_ARM_GOTOFFFUNCDESC:
case BFD_RELOC_ARM_FUNCDESC:
case BFD_RELOC_ARM_THUMB_BF17:
+ case BFD_RELOC_ARM_THUMB_BF19:
code = fixp->fx_r_type;
break;
diff --git a/include/elf/arm.h b/include/elf/arm.h
index 2c6d4ef18a96e10fb206248df151c44a67757042..b8f2d2fa416e4516860ec049b642d331e0a3600e 100644
--- a/include/elf/arm.h
+++ b/include/elf/arm.h
@@ -242,6 +242,7 @@ START_RELOC_NUMBERS (elf_arm_reloc_type)
RELOC_NUMBER (R_ARM_THM_ALU_ABS_G2_NC,134)
RELOC_NUMBER (R_ARM_THM_ALU_ABS_G3_NC,135)
RELOC_NUMBER (R_ARM_THM_BF16, 136)
+ RELOC_NUMBER (R_ARM_THM_BF18, 138)
RELOC_NUMBER (R_ARM_IRELATIVE, 160)
RELOC_NUMBER (R_ARM_GOTFUNCDESC, 161)
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 2929522fa359bd55305d50da84598a17813c2510..a70ed814fb1177132df1d5121cc68b2fef876b0c 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2716,6 +2716,7 @@ static const struct opcode16 thumb_opcodes[] =
%F print the lsb and width fields of a sbfx/ubfx instruction
%G print a fallback offset for Branch Future instructions
%W print an offset for BF instruction
+ %Y print an offset for BFL instruction
%b print a conditional branch offset
%B print an unconditional branch offset
%s print the shift field of an SSAT instruction
@@ -5899,6 +5900,23 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
}
break;
+ case 'Y':
+ {
+ unsigned int immA = (given & 0x007f0000u) >> 16;
+ unsigned int immB = (given & 0x000007feu) >> 1;
+ unsigned int immC = (given & 0x00000800u) >> 11;
+ bfd_vma offset = 0;
+
+ offset |= immA << 12;
+ offset |= immB << 2;
+ offset |= immC << 1;
+ /* Sign extend. */
+ offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
+
+ info->print_address_func (pc + 4 + offset, info);
+ }
+ break;
+
case 'b':
{
unsigned int S = (given & 0x04000000u) >> 26;
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH, binutils, ARM, 9/16] New BFL instruction for Armv8.1-M Mainline
2019-04-04 13:24 [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Andre Vieira (lists)
` (7 preceding siblings ...)
2019-04-04 13:38 ` [PATCH, binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18 Andre Vieira (lists)
@ 2019-04-04 13:39 ` Andre Vieira (lists)
2019-04-12 10:40 ` Andre Vieira (lists)
2019-04-04 13:40 ` [PATCH, binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_BF12 Andre Vieira (lists)
` (7 subsequent siblings)
16 siblings, 1 reply; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-04 13:39 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 1085 bytes --]
Hi
This patch is part of a series of patches to add support for Armv8.1-M
Mainline instructions to binutils.
This patch adds the BFL instruction.
Testing: Added new test for the valid and invalid instruction operands.
Testsuite shows no regression when run for arm-none-eabi targets.
Thanks
Sudi
ChangeLog entries are as follows :
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (T16_32_TAB): New entrie for bfl.
(do_t_v8_1_branch): New switch case for bfl.
(insns): New instruction for bfl.
* testsuite/gas/arm/armv8_1-m-bfl.d: New.
* testsuite/gas/arm/armv8_1-m-bfl.s: New.
* testsuite/gas/arm/armv8_1-m-bfl-bad.s: New.
* testsuite/gas/arm/armv8_1-m-bfl-bad.d: New.
* testsuite/gas/arm/armv8_1-m-bfl-bad.l: New.
*** ld/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bfl.s: New.
* testsuite/ld-arm/bfl.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instruction bfl.
[-- Attachment #2: 9.patch --]
[-- Type: text/x-patch, Size: 7022 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 177d90f1c6fdc9ad99a395b479b16e5b9f8ae0b6..5643e3f6bcafe95816c666ad3ed9844ad458c54e 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -10507,6 +10507,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
X(_bcond, d000, f0008000), \
X(_bf, 0000, f040e001), \
X(_bfx, 0000, f060e001), \
+ X(_bfl, 0000, f000c001), \
X(_bflx, 0000, f070e001), \
X(_bic, 4380, ea200000), \
X(_bics, 4380, ea300000), \
@@ -13364,6 +13365,25 @@ do_t_branch_future (void)
}
break;
+ case T_MNEM_bfl:
+ if (inst.operands[1].hasreloc == 0)
+ {
+ int val = inst.operands[1].imm;
+ if (v8_1_branch_value_check (inst.operands[1].imm, 19, TRUE) == FAIL)
+ as_bad (BAD_BRANCH_OFF);
+
+ int immA = (val & 0x0007f000) >> 12;
+ int immB = (val & 0x00000ffc) >> 2;
+ int immC = (val & 0x00000002) >> 1;
+ inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
+ }
+ else
+ {
+ inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF19;
+ inst.relocs[1].pc_rel = 1;
+ }
+ break;
+
case T_MNEM_bfx:
case T_MNEM_bflx:
inst.instruction |= inst.operands[1].reg << 16;
@@ -21687,6 +21707,7 @@ static const struct asm_opcode insns[] =
#define THUMB_VARIANT & arm_ext_v8_1m_main
toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future),
+ toC("bfl", _bfl, 2, (EXPs, EXPs), t_branch_future),
toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future),
};
#undef ARM_VARIANT
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl-bad.d b/gas/testsuite/gas/arm/armv8_1-m-bfl-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..6a8f6f3cfd74d2f068048c39eab29eb70d165350
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl-bad.d
@@ -0,0 +1,4 @@
+#name: Invalid Armv8.1-M Mainline BFL instructions
+#source: armv8_1-m-bfl-bad.s
+#as: -march=armv8.1-m.main
+#error_output: armv8_1-m-bfl-bad.l
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl-bad.l b/gas/testsuite/gas/arm/armv8_1-m-bfl-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..3f7ed80a6d07a4a2c05e8968e95c26d66eae2fab
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl-bad.l
@@ -0,0 +1,9 @@
+.*: Assembler messages:
+.*:6: Error: branch out of range or not a multiple of 2
+.*:7: Error: branch out of range or not a multiple of 2
+.*:8: Error: branch out of range or not a multiple of 2
+.*:9: Error: branch out of range or not a multiple of 2
+.*:11: Error: branch out of range or not a multiple of 2
+.*:12: Error: branch out of range or not a multiple of 2
+.*:13: Error: branch out of range or not a multiple of 2
+.*:14: Error: branch out of range or not a multiple of 2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl-bad.s b/gas/testsuite/gas/arm/armv8_1-m-bfl-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..2af310820c39231978b50a8b5728b0f1f40e9efe
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl-bad.s
@@ -0,0 +1,14 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+ # OP0 : Unsigned, 5-bit, even
+ bfl 0, 36
+ bfl -2, 36
+ bfl 3, 36
+ bfl 32, 36
+ # OP1 : signed, 19-bit, even
+ bf 2, -5
+ bf 2, 5
+ bf 2, 262144
+ bf 2, -262146
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl.d b/gas/testsuite/gas/arm/armv8_1-m-bfl.d
new file mode 100644
index 0000000000000000000000000000000000000000..f5fff51ab2e906ea4b9e2703340da573fd694609
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl.d
@@ -0,0 +1,17 @@
+#name: Valid Armv8.1-M Mainline BFL instruction
+#source: armv8_1-m-bfl.s
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f080 c803 bfl 2, 0000000a <foo\+0xa>
+0[0-9a-f]+ <[^>]+> 4608 mov r0, r1
+0[0-9a-f]+ <[^>]+> f0ff c7ff bfl 2, 00000000 <.target>
+ 6: R_ARM_THM_BF18 .target
+0[0-9a-f]+ <[^>]+> 4609 mov r1, r1
+0[0-9a-f]+ <[^>]+> f100 c801 bfl 4, 00000012 <foo\+0x12>
+0[0-9a-f]+ <[^>]+> 460a mov r2, r1
+0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
+0[0-9a-f]+ <[^>]+> 4614 mov r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl.s b/gas/testsuite/gas/arm/armv8_1-m-bfl.s
new file mode 100644
index 0000000000000000000000000000000000000000..06afa7cdbffd27a57453b1d9ac2719798cc2163b
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl.s
@@ -0,0 +1,14 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+ bfl 2, 6
+ mov r0, r1
+ bfl 2, .target
+ mov r1, r1
+ bfl .LBranch, .LB2
+ mov r2, r1
+.LB2:
+ mov r3, r2
+.LBranch:
+ mov r4, r2
diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp
index ef3a49c23742f4c43c78e73aa692928ba3d56123..528565e97bee829c193ad54ab21e2f9a7071a718 100644
--- a/ld/testsuite/ld-arm/arm-elf.exp
+++ b/ld/testsuite/ld-arm/arm-elf.exp
@@ -670,6 +670,9 @@ set armeabitests_nonacl {
{"Armv8.1-M Mainline BF" "-r -Ttext 0x1000 --section-start .foo=0x1001000" "" "-march=armv8.1-m.main" {bf.s}
{{objdump -dr bf.d}}
"bf"}
+ {"Armv8.1-M Mainline BFL" "-r -Ttext 0x1000 --section-start .foo=0x1001000" "" "-march=armv8.1-m.main" {bfl.s}
+ {{objdump -dr bfl.d}}
+ "bfl"}
{"R_ARM_THM_JUMP24 Relocation veneers: Short 1"
"--no-fix-arm1176 --section-start destsect=0x00009000 --section-start .text=0x8000" ""
diff --git a/ld/testsuite/ld-arm/bfl.d b/ld/testsuite/ld-arm/bfl.d
new file mode 100644
index 0000000000000000000000000000000000000000..32903504bd02bee217a0dc27af127a28d36a83ee
--- /dev/null
+++ b/ld/testsuite/ld-arm/bfl.d
@@ -0,0 +1,14 @@
+
+.*: file format elf32-littlearm
+
+
+Disassembly of section .text:
+
+00001000 <_start>:
+ 1000: f0ff c7ff bfl 2, 1001000 <bar>
+ 1000: R_ARM_THM_BF18 bar
+
+Disassembly of section .foo:
+
+01001000 <bar>:
+ 1001000: 4770 bx lr
diff --git a/ld/testsuite/ld-arm/bfl.s b/ld/testsuite/ld-arm/bfl.s
new file mode 100644
index 0000000000000000000000000000000000000000..e9fb0a70f6c6c6ee802b0bd91dfcd608c94a0d30
--- /dev/null
+++ b/ld/testsuite/ld-arm/bfl.s
@@ -0,0 +1,19 @@
+ .global _start
+ .syntax unified
+
+@ We will place the section .text at 0x1000.
+
+ .text
+ .thumb_func
+
+_start:
+ bfl 2, bar
+
+@ We will place the section .foo at 0x1001000.
+
+ .section .foo, "xa"
+ .thumb_func
+
+bar:
+ bx lr
+
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index a70ed814fb1177132df1d5121cc68b2fef876b0c..12e28c3df6d79df7e1ae3a69e61b8c07b0e7c4e3 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2754,6 +2754,8 @@ static const struct opcode32 thumb32_opcodes[] =
0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH, binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_BF12
2019-04-04 13:24 [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Andre Vieira (lists)
` (8 preceding siblings ...)
2019-04-04 13:39 ` [PATCH, binutils, ARM, 9/16] New BFL instruction for Armv8.1-M Mainline Andre Vieira (lists)
@ 2019-04-04 13:40 ` Andre Vieira (lists)
2019-04-04 13:41 ` [PATCH, binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Mainline Andre Vieira (lists)
` (6 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-04 13:40 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 1765 bytes --]
Hi
This patch is part of a series of patches to add support for Armv8.1-M
Mainline instructions to binutils.
This adds infrastructure for the BFCSEL instructions which is one of the
first instructions in Arm that
have more than one relocations in them.
This adds a new relocation R_ARM_THM_BF12. Relocation specified in
https://developer.arm.com/docs/ihi0044/latest/elf-for-the-arm-architecture-abi-2019q1-documentation#aaelf32-table4-9
The inconsistency between external R_ARM_THM_BF12 and internal
BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0
of the immediate and we don't externally.
Testing: Builds successfully and no regressions.
Thanks
Sudi
ChangeLog entries are as follows :
*** bfd/ChnageLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF13): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13
and R_ARM_THM_BF12 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13.
*** elfcpp/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF12): New relocation code.
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF13.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12.
*** opcodes/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 10.patch --]
[-- Type: text/x-patch; name="10.patch", Size: 8719 bytes --]
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 99b0db4ec6d6ddfde74f47215510e0905b910e95..95d66b586d608ea397121f9124f24b0f2e9a9307 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -3570,6 +3570,9 @@ field in the instruction. */
/* ARM 17-bit pc-relative branch for Branch Future instructions. */
BFD_RELOC_ARM_THUMB_BF17,
+/* ARM 13-bit pc-relative branch for BFCSEL instruction. */
+ BFD_RELOC_ARM_THUMB_BF13,
+
/* ARM 19-bit pc-relative branch for Branch Future Link instruction. */
BFD_RELOC_ARM_THUMB_BF19,
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index cac652d1d3247107c0cba8c95ed36e280b3674fe..4b64dd4688cbec3638a89cc0e4150f52414269c4 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -1756,7 +1756,19 @@ static reloc_howto_type elf32_arm_howto_table_1[] =
0x001f0ffe, /* src_mask. */
0x001f0ffe, /* dst_mask. */
TRUE), /* pcrel_offset. */
- EMPTY_HOWTO (137),
+ HOWTO (R_ARM_THM_BF12, /* type. */
+ 0, /* rightshift. */
+ 1, /* size (0 = byte, 1 = short, 2 = long). */
+ 12, /* bitsize. */
+ TRUE, /* pc_relative. */
+ 0, /* bitpos. */
+ complain_overflow_dont,/* do not complain_on_overflow. */
+ bfd_elf_generic_reloc, /* special_function. */
+ "R_ARM_THM_BF12", /* name. */
+ FALSE, /* partial_inplace. */
+ 0x00010ffe, /* src_mask. */
+ 0x00010ffe, /* dst_mask. */
+ TRUE), /* pcrel_offset. */
HOWTO (R_ARM_THM_BF18, /* type. */
0, /* rightshift. */
1, /* size (0 = byte, 1 = short, 2 = long). */
@@ -2083,6 +2095,7 @@ static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
{BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
{BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
{BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16},
+ {BFD_RELOC_ARM_THUMB_BF13, R_ARM_THM_BF12},
{BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18}
};
@@ -12983,6 +12996,51 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
return bfd_reloc_ok;
}
+ case R_ARM_THM_BF12:
+ {
+ bfd_vma relocation;
+ bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
+ bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
+
+ if (globals->use_rel)
+ {
+ bfd_vma immA = (upper_insn & 0x0001);
+ bfd_vma immB = (lower_insn & 0x07fe) >> 1;
+ bfd_vma immC = (lower_insn & 0x0800) >> 11;
+ addend = (immA << 12);
+ addend |= (immB << 2);
+ addend |= (immC << 1);
+ addend |= 1;
+ /* Sign extend. */
+ addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
+ }
+
+ value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
+ info, input_bfd, rel, sym_name, st_type,
+ globals, unresolved_reloc_p);
+
+ relocation = value + addend;
+ relocation -= (input_section->output_section->vma
+ + input_section->output_offset
+ + rel->r_offset);
+
+ /* Put RELOCATION back into the insn. */
+ {
+ bfd_vma immA = (relocation & 0x00001000) >> 12;
+ bfd_vma immB = (relocation & 0x00000ffc) >> 2;
+ bfd_vma immC = (relocation & 0x00000002) >> 1;
+
+ upper_insn = (upper_insn & 0xfffe) | immA;
+ lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
+ }
+
+ /* Put the relocated value back in the object file: */
+ bfd_put_16 (input_bfd, upper_insn, hit_data);
+ bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
+
+ return bfd_reloc_ok;
+ }
+
case R_ARM_THM_BF18:
{
bfd_vma relocation;
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index 7f775acf9178d70ad8351064f2e2291dd79c73a0..b3d71d976a437454593dde7afb7c0d8e368c56ca 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -1531,6 +1531,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_ARM_PCREL_JUMP",
"BFD_RELOC_THUMB_PCREL_BRANCH5",
"BFD_RELOC_ARM_THUMB_BF17",
+ "BFD_RELOC_ARM_THUMB_BF13",
"BFD_RELOC_ARM_THUMB_BF19",
"BFD_RELOC_THUMB_PCREL_BRANCH7",
"BFD_RELOC_THUMB_PCREL_BRANCH9",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index 9e3899ab4e7f3485cc2bd0f0953f652e0b28f48a..c41b2fe75d10e9441cd38861b2f6f02f546f6a64 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -3024,6 +3024,11 @@ ENUM
ENUMDOC
ARM 17-bit pc-relative branch for Branch Future instructions.
+ENUM
+ BFD_RELOC_ARM_THUMB_BF13
+ENUMDOC
+ ARM 13-bit pc-relative branch for BFCSEL instruction.
+
ENUM
BFD_RELOC_ARM_THUMB_BF19
ENUMDOC
diff --git a/elfcpp/arm.h b/elfcpp/arm.h
index 44dfca2b86efc9c0c5abe3022f52b70440253011..6972df4186d7044523a24203ca4cfc7ca10d4e5c 100644
--- a/elfcpp/arm.h
+++ b/elfcpp/arm.h
@@ -197,6 +197,7 @@ enum
// 131 - 135 Unallocated
// New relocations for ARMv8.1-M Mainline (BF/BFL)
R_ARM_THM_BF16 = 136, // Static Thumb32 ((S + A) | T) – P
+ R_ARM_THM_BF12 = 137, // Static Thumb32 ((S + A) | T) – P
R_ARM_THM_BF18 = 138, // Static Thumb32 ((S + A) | T) – P
// 139 Unallocated
// 140 - 159 Dynamic Reserved for future allocation
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 2b3dd16092e0296e4a8e471692bd725b253f7085..e5ea88c81ea2116f54f0bbbdf50ca1feef606428 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -22946,6 +22946,7 @@ md_pcrel_from_section (fixS * fixP, segT seg)
case BFD_RELOC_THUMB_PCREL_BRANCH25:
case BFD_RELOC_ARM_THUMB_BF17:
case BFD_RELOC_ARM_THUMB_BF19:
+ case BFD_RELOC_ARM_THUMB_BF13:
return base + 4;
case BFD_RELOC_THUMB_PCREL_BRANCH23:
@@ -24909,6 +24910,39 @@ md_apply_fix (fixS * fixP,
}
break;
+ case BFD_RELOC_ARM_THUMB_BF13:
+ if (fixP->fx_addsy
+ && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
+ && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && ARM_IS_FUNC (fixP->fx_addsy)
+ && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
+ {
+ /* Force a relocation for a branch 13 bits wide. */
+ fixP->fx_done = 0;
+ }
+
+ if (v8_1_branch_value_check (value, 13, TRUE) == FAIL)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ BAD_BRANCH_OFF);
+
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ offsetT newval2;
+ addressT immA, immB, immC;
+
+ immA = (value & 0x00001000) >> 12;
+ immB = (value & 0x00000ffc) >> 2;
+ immC = (value & 0x00000002) >> 1;
+
+ newval = md_chars_to_number (buf, THUMB_SIZE);
+ newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
+ newval |= immA;
+ newval2 |= (immC << 11) | (immB << 1);
+ md_number_to_chars (buf, newval, THUMB_SIZE);
+ md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
+ }
+ break;
+
case BFD_RELOC_ARM_V4BX:
/* This will need to go in the object file. */
fixP->fx_done = 0;
@@ -25093,6 +25127,7 @@ tc_gen_reloc (asection *section, fixS *fixp)
case BFD_RELOC_ARM_FUNCDESC:
case BFD_RELOC_ARM_THUMB_BF17:
case BFD_RELOC_ARM_THUMB_BF19:
+ case BFD_RELOC_ARM_THUMB_BF13:
code = fixp->fx_r_type;
break;
diff --git a/include/elf/arm.h b/include/elf/arm.h
index b8f2d2fa416e4516860ec049b642d331e0a3600e..9f22ffed2b5c664c72ff53fafdf9c074d1e126b9 100644
--- a/include/elf/arm.h
+++ b/include/elf/arm.h
@@ -242,6 +242,7 @@ START_RELOC_NUMBERS (elf_arm_reloc_type)
RELOC_NUMBER (R_ARM_THM_ALU_ABS_G2_NC,134)
RELOC_NUMBER (R_ARM_THM_ALU_ABS_G3_NC,135)
RELOC_NUMBER (R_ARM_THM_BF16, 136)
+ RELOC_NUMBER (R_ARM_THM_BF12, 137)
RELOC_NUMBER (R_ARM_THM_BF18, 138)
RELOC_NUMBER (R_ARM_IRELATIVE, 160)
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 0ff06d300cfc28c4e02eb815a8744fd0a5feaeb4..90c4822e5f476c343d003c0e5024a44a0e8f8576 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2717,6 +2717,7 @@ static const struct opcode16 thumb_opcodes[] =
%G print a fallback offset for Branch Future instructions
%W print an offset for BF instruction
%Y print an offset for BFL instruction
+ %Z print an offset for BFCSEL instruction
%b print a conditional branch offset
%B print an unconditional branch offset
%s print the shift field of an SSAT instruction
@@ -5919,6 +5920,23 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
}
break;
+ case 'Z':
+ {
+ unsigned int immA = (given & 0x00010000u) >> 16;
+ unsigned int immB = (given & 0x000007feu) >> 1;
+ unsigned int immC = (given & 0x00000800u) >> 11;
+ bfd_vma offset = 0;
+
+ offset |= immA << 12;
+ offset |= immB << 2;
+ offset |= immC << 1;
+ /* Sign extend. */
+ offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
+
+ info->print_address_func (pc + 4 + offset, info);
+ }
+ break;
+
case 'b':
{
unsigned int S = (given & 0x04000000u) >> 26;
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH, binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M Mainline
2019-04-04 13:24 [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Andre Vieira (lists)
` (10 preceding siblings ...)
2019-04-04 13:41 ` [PATCH, binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Mainline Andre Vieira (lists)
@ 2019-04-04 13:41 ` Andre Vieira (lists)
2019-04-12 10:39 ` Andre Vieira (lists)
2019-04-04 13:42 ` [PATCH, binutils, ARM, 13/16] Add support for CLRM Andre Vieira (lists)
` (4 subsequent siblings)
16 siblings, 1 reply; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-04 13:41 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 1407 bytes --]
Hi
This patch is part of a series of patches to add support for Armv8.1-M
Mainline instructions to binutils.
This patch adds the BFCSEL instruction. It also adds a local relocation
with a new bfd_reloc_code_real enum.
Testing: Added new test for the valid instruction operands. Testsuite
shows no regression when run for arm-none-eabi targets.
Thanks
Sudi
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation.
* bfd-in2.h: Regenerated.
* libbfd.h: Likewise.
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (T16_32_TAB): New entriy for bfcsel.
(do_t_v8_1_branch): New switch case for bfcsel.
(toU): Define.
(insns): New instruction for bfcsel.
(md_pcrel_from_section): New switch case
for BFD_RELOC_THUMB_PCREL_BFCSEL.
(md_appdy_fix): Likewise
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/armv8_1-m-bfcsel.d: New.
* testsuite/gas/arm/armv8_1-m-bfcsel.s: New.
*** ld/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bfcsel.s: New.
* testsuite/ld-arm/bfcsel.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instruction bfcsel.
(print_insn_thumb32): Edit the switch case for %Z.
[-- Attachment #2: 11.patch --]
[-- Type: text/x-patch, Size: 10513 bytes --]
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 95d66b586d608ea397121f9124f24b0f2e9a9307..4a3fa75867c814f082ba3ab3079cf60c30ad2b62 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -3567,6 +3567,9 @@ field in the instruction. */
/* ARM 5-bit pc-relative branch for Branch Future instructions. */
BFD_RELOC_THUMB_PCREL_BRANCH5,
+/* ARM 6-bit pc-relative branch for BFCSEL instruction. */
+ BFD_RELOC_THUMB_PCREL_BFCSEL,
+
/* ARM 17-bit pc-relative branch for Branch Future instructions. */
BFD_RELOC_ARM_THUMB_BF17,
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index b3d71d976a437454593dde7afb7c0d8e368c56ca..32080db8c3f6141ae9aa9674c8776694db29905a 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -1530,6 +1530,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_ARM_PCREL_CALL",
"BFD_RELOC_ARM_PCREL_JUMP",
"BFD_RELOC_THUMB_PCREL_BRANCH5",
+ "BFD_RELOC_THUMB_PCREL_BFCSEL",
"BFD_RELOC_ARM_THUMB_BF17",
"BFD_RELOC_ARM_THUMB_BF13",
"BFD_RELOC_ARM_THUMB_BF19",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index c41b2fe75d10e9441cd38861b2f6f02f546f6a64..c0e413cd19dbfaf5100143c8879d84cb63ba4a17 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -3019,6 +3019,11 @@ ENUM
ENUMDOC
ARM 5-bit pc-relative branch for Branch Future instructions.
+ENUM
+ BFD_RELOC_THUMB_PCREL_BFCSEL
+ENUMDOC
+ ARM 6-bit pc-relative branch for BFCSEL instruction.
+
ENUM
BFD_RELOC_ARM_THUMB_BF17
ENUMDOC
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 5d7f2c0a6d4d7834038b92d6c4256cee7e69ed4c..5e59078890752b0580ae443c7b330e32baecccf6 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -10506,6 +10506,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
X(_b, e000, f000b000), \
X(_bcond, d000, f0008000), \
X(_bf, 0000, f040e001), \
+ X(_bfcsel,0000, f000e001), \
X(_bfx, 0000, f060e001), \
X(_bfl, 0000, f000c001), \
X(_bflx, 0000, f070e001), \
@@ -13384,6 +13385,46 @@ do_t_branch_future (void)
}
break;
+ case T_MNEM_bfcsel:
+ /* Operand 1. */
+ if (inst.operands[1].hasreloc == 0)
+ {
+ int val = inst.operands[1].imm;
+ int immA = (val & 0x00001000) >> 12;
+ int immB = (val & 0x00000ffc) >> 2;
+ int immC = (val & 0x00000002) >> 1;
+ inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
+ }
+ else
+ {
+ inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF13;
+ inst.relocs[1].pc_rel = 1;
+ }
+
+ /* Operand 2. */
+ if (inst.operands[2].hasreloc == 0)
+ {
+ constraint ((inst.operands[0].hasreloc != 0), BAD_ARGS);
+ int val2 = inst.operands[2].imm;
+ int val0 = inst.operands[0].imm & 0x1f;
+ int diff = val2 - val0;
+ if (diff == 4)
+ inst.instruction |= 1 << 17; /* T bit. */
+ else if (diff != 2)
+ as_bad (_("out of range label-relative fixup value"));
+ }
+ else
+ {
+ constraint ((inst.operands[0].hasreloc == 0), BAD_ARGS);
+ inst.relocs[2].type = BFD_RELOC_THUMB_PCREL_BFCSEL;
+ inst.relocs[2].pc_rel = 1;
+ }
+
+ /* Operand 3. */
+ constraint (inst.cond != COND_ALWAYS, BAD_COND);
+ inst.instruction |= (inst.operands[3].imm & 0xf) << 18;
+ break;
+
case T_MNEM_bfx:
case T_MNEM_bflx:
inst.instruction |= inst.operands[1].reg << 16;
@@ -19616,6 +19657,11 @@ static struct asm_barrier_opt barrier_opt_names[] =
{ mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
do_##te }
+/* T_MNEM_xyz enumerator variants of ToU. */
+#define toU(mnem, top, nops, ops, te) \
+ { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
+ NULL, do_##te }
+
/* Legacy mnemonics that always have conditional infix after the third
character. */
#define CL(mnem, op, nops, ops, ae) \
@@ -21706,6 +21752,7 @@ static const struct asm_opcode insns[] =
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_v8_1m_main
toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
+ toU("bfcsel", _bfcsel, 4, (EXPs, EXPs, EXPs, COND), t_branch_future),
toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future),
toC("bfl", _bfl, 2, (EXPs, EXPs), t_branch_future),
toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future),
@@ -21741,6 +21788,7 @@ static const struct asm_opcode insns[] =
#undef ToC
#undef toC
#undef ToU
+#undef toU
\f
/* MD interface: bits in the object file. */
@@ -22944,6 +22992,7 @@ md_pcrel_from_section (fixS * fixP, segT seg)
case BFD_RELOC_THUMB_PCREL_BRANCH12:
case BFD_RELOC_THUMB_PCREL_BRANCH20:
case BFD_RELOC_THUMB_PCREL_BRANCH25:
+ case BFD_RELOC_THUMB_PCREL_BFCSEL:
case BFD_RELOC_ARM_THUMB_BF17:
case BFD_RELOC_ARM_THUMB_BF19:
case BFD_RELOC_ARM_THUMB_BF13:
@@ -24844,6 +24893,39 @@ md_apply_fix (fixS * fixP,
}
break;
+ case BFD_RELOC_THUMB_PCREL_BFCSEL:
+ if (fixP->fx_addsy
+ && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
+ && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && ARM_IS_FUNC (fixP->fx_addsy)
+ && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
+ {
+ fixP->fx_done = 0;
+ }
+ if ((value & ~0x7f) && ((value & ~0x3f) != ~0x3f))
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("branch out of range"));
+
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ newval = md_chars_to_number (buf, THUMB_SIZE);
+
+ addressT boff = ((newval & 0x0780) >> 7) << 1;
+ addressT diff = value - boff;
+
+ if (diff == 4)
+ {
+ newval |= 1 << 1; /* T bit. */
+ }
+ else if (diff != 2)
+ {
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("out of range label-relative fixup value"));
+ }
+ md_number_to_chars (buf, newval, THUMB_SIZE);
+ }
+ break;
+
case BFD_RELOC_ARM_THUMB_BF17:
if (fixP->fx_addsy
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
@@ -25158,6 +25240,7 @@ tc_gen_reloc (asection *section, fixS *fixp)
return NULL;
case BFD_RELOC_THUMB_PCREL_BRANCH5:
+ case BFD_RELOC_THUMB_PCREL_BFCSEL:
as_bad_where (fixp->fx_file, fixp->fx_line,
_("%s used for a symbol not defined in the same file"),
bfd_get_reloc_code_name (fixp->fx_r_type));
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d b/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d
new file mode 100644
index 0000000000000000000000000000000000000000..7e2599bc37bd4b0ac631c972c6e08c899ad59aa6
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d
@@ -0,0 +1,14 @@
+#name: Valid Armv8.1-M Mainline BFCSEL instruction
+#source: armv8_1-m-bfcsel.s
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f082 e005 bfcsel 2, 0000000c <foo\+0xc>, 6, eq
+0[0-9a-f]+ <[^>]+> 4609 mov r1, r1
+0[0-9a-f]+ <[^>]+> f43f affe beq.w 00000000 <.target>
+ 6: R_ARM_THM_JUMP19 .target
+0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
+0[0-9a-f]+ <[^>]+> 4614 mov r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfcsel.s b/gas/testsuite/gas/arm/armv8_1-m-bfcsel.s
new file mode 100644
index 0000000000000000000000000000000000000000..f9bb30292400ef40b09b243053fedc0a47e3d088
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfcsel.s
@@ -0,0 +1,12 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+ bfcsel .LB1, .LBranch, .LB2, eq
+ mov r1, r1
+.LB1:
+ beq .target
+.LB2:
+ mov r3, r2
+.LBranch:
+ mov r4, r2
diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp
index 528565e97bee829c193ad54ab21e2f9a7071a718..5471895e63a68c0ee5e9c9644564e7b9235a4184 100644
--- a/ld/testsuite/ld-arm/arm-elf.exp
+++ b/ld/testsuite/ld-arm/arm-elf.exp
@@ -673,6 +673,9 @@ set armeabitests_nonacl {
{"Armv8.1-M Mainline BFL" "-r -Ttext 0x1000 --section-start .foo=0x1001000" "" "-march=armv8.1-m.main" {bfl.s}
{{objdump -dr bfl.d}}
"bfl"}
+ {"Armv8.1-M Mainline BFCSEL" "-r -Ttext 0x1000 --section-start .foo=0x1001000" "" "-march=armv8.1-m.main" {bfcsel.s}
+ {{objdump -dr bfcsel.d}}
+ "bfcsel"}
{"R_ARM_THM_JUMP24 Relocation veneers: Short 1"
"--no-fix-arm1176 --section-start destsect=0x00009000 --section-start .text=0x8000" ""
diff --git a/ld/testsuite/ld-arm/bfcsel.d b/ld/testsuite/ld-arm/bfcsel.d
new file mode 100644
index 0000000000000000000000000000000000000000..d9e8527d9594a9bbc41822fbe740ed507f0b9b84
--- /dev/null
+++ b/ld/testsuite/ld-arm/bfcsel.d
@@ -0,0 +1,18 @@
+
+.*: file format elf32-littlearm
+
+
+Disassembly of section .text:
+
+00001000 <_start>:
+ 1000: f101 e7ff bfcsel 4, 1001000 <bar>, 6, eq
+ 1000: R_ARM_THM_BF12 bar
+ 1004: 4623 mov r3, r4
+ 1006: 4611 mov r1, r2
+ 1008: d0ff beq.n 100a <_start\+0xa>
+ 100a: 4613 mov r3, r2
+
+Disassembly of section .foo:
+
+01001000 <bar>:
+ 1001000: 4770 bx lr
diff --git a/ld/testsuite/ld-arm/bfcsel.s b/ld/testsuite/ld-arm/bfcsel.s
new file mode 100644
index 0000000000000000000000000000000000000000..675e2ea1ae28b64663cd02411550670112dd91a2
--- /dev/null
+++ b/ld/testsuite/ld-arm/bfcsel.s
@@ -0,0 +1,25 @@
+ .global _start
+ .syntax unified
+
+@ We will place the section .text at 0x1000.
+
+ .text
+ .thumb_func
+
+_start:
+ bfcsel .LB1, bar, .LB2, eq
+ mov r3, r4
+ mov r1, r2
+.LB1:
+ beq .LB2
+.LB2:
+ mov r3, r2
+
+@ We will place the section .foo at 0x1001000.
+
+ .section .foo, "xa"
+ .thumb_func
+
+bar:
+ bx lr
+
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index f53afc584cfdd271fde85d86ecab219a87c77bd3..b4865c1a42a04bb6a9b156d7369c065ca351efb4 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2759,6 +2759,8 @@ static const struct opcode32 thumb32_opcodes[] =
0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
/* ARMv8-M and ARMv8-M Security Extensions instructions. */
@@ -5934,6 +5936,12 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
info->print_address_func (pc + 4 + offset, info);
+
+ unsigned int T = (given & 0x00020000u) >> 17;
+ unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
+ unsigned int boffset = (T == 1) ? 4 : 2;
+ func (stream, ", ");
+ func (stream, "%x", endoffset + boffset);
}
break;
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH, binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Mainline
2019-04-04 13:24 [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Andre Vieira (lists)
` (9 preceding siblings ...)
2019-04-04 13:40 ` [PATCH, binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_BF12 Andre Vieira (lists)
@ 2019-04-04 13:41 ` Andre Vieira (lists)
2019-04-12 10:40 ` Andre Vieira (lists)
2019-04-04 13:41 ` [PATCH, binutils, ARM, 11/16] New BFCSEL instruction " Andre Vieira (lists)
` (5 subsequent siblings)
16 siblings, 1 reply; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-04 13:41 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 1791 bytes --]
Hi
This patch is part of a series of patches to add support for Armv8.1-M
Mainline instructions to binutils.
This patch adds support to the Scalar low overhead loop instructions:
LE
WLS
DLS
We also add a new assembler resolvable relocation bfd_reloc_code_real
enum for the 12-bit branch offset used in these instructions.
Testing: Builds successfully and no regressions. Added new tests for the
valid and invalid instructions operands. Testsuite shows no regression
when run for arm-none-eabi targets.
Thanks
Sudi
ChangeLog entries are as follows :
*** bfd/ChnageLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR
for the LR operand and optional LR operand.
(parse_operands): Add switch cases for OP_LR and OP_oLR for
both type checking and value checking.
(encode_thumb32_addr_mode): New entries for DLS, WLS and LE.
(v8_1_loop_reloc): New helper function for handling labels
for the low overhead loop instructions.
(do_t_loloop): New function to encode DLS, WLS and LE.
(insns): New entries for WLS, DLS and LE.
(md_pcrel_from_section): New switch case
for BFD_RELOC_ARM_THUMB_LOOP12.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/armv8_1-m-tloop.s: New.
* testsuite/gas/arm/armv8_1-m-tloop.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.s: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.l: New.
*** opcodes/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %P
and %Q patterns.
[-- Attachment #2: 12.patch --]
[-- Type: text/x-patch, Size: 13169 bytes --]
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 4a3fa75867c814f082ba3ab3079cf60c30ad2b62..540b9f71c181841ea782c63d87d0d5271c864966 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -3579,6 +3579,9 @@ field in the instruction. */
/* ARM 19-bit pc-relative branch for Branch Future Link instruction. */
BFD_RELOC_ARM_THUMB_BF19,
+/* ARM 12-bit pc-relative branch for Low Overhead Loop instructions. */
+ BFD_RELOC_ARM_THUMB_LOOP12,
+
/* Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
The lowest bit must be zero and is not stored in the instruction.
Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index 32080db8c3f6141ae9aa9674c8776694db29905a..f64a8f3892ad3aff5c4570f0281875bce35846a6 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -1534,6 +1534,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_ARM_THUMB_BF17",
"BFD_RELOC_ARM_THUMB_BF13",
"BFD_RELOC_ARM_THUMB_BF19",
+ "BFD_RELOC_ARM_THUMB_LOOP12",
"BFD_RELOC_THUMB_PCREL_BRANCH7",
"BFD_RELOC_THUMB_PCREL_BRANCH9",
"BFD_RELOC_THUMB_PCREL_BRANCH12",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index c0e413cd19dbfaf5100143c8879d84cb63ba4a17..e6ba9e265027a6c34a8ad183dd5825a9af9c1f82 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -3039,6 +3039,11 @@ ENUM
ENUMDOC
ARM 19-bit pc-relative branch for Branch Future Link instruction.
+ENUM
+ BFD_RELOC_ARM_THUMB_LOOP12
+ENUMDOC
+ ARM 12-bit pc-relative branch for Low Overhead Loop instructions.
+
ENUM
BFD_RELOC_THUMB_PCREL_BRANCH7
ENUMX
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 592d658efbe7bb8169353f49e8faf6dd396647b0..ca143a9c7d1ffd0c73dafc972f2c50aed631665c 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -6543,6 +6543,10 @@ enum operand_parse_code
OP_RIWG, /* iWMMXt wCG register */
OP_RXA, /* XScale accumulator register */
+ /* New operands for Armv8.1-M Mainline. */
+ OP_LR, /* ARM LR register */
+ OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */
+
OP_REGLST, /* ARM register list */
OP_VRSLST, /* VFP single-precision register list */
OP_VRDLST, /* VFP double-precision register list */
@@ -6622,6 +6626,7 @@ enum operand_parse_code
OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
OP_oRR, /* ARM register */
+ OP_oLR, /* ARM LR register */
OP_oRRnpc, /* ARM register, not the PC */
OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
OP_oRRw, /* ARM register, not r15, optional trailing ! */
@@ -6790,6 +6795,8 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
case OP_RRnpc:
case OP_RRnpcsp:
case OP_oRR:
+ case OP_LR:
+ case OP_oLR:
case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
@@ -7307,6 +7314,12 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
inst.operands[i].imm = val;
break;
+ case OP_LR:
+ case OP_oLR:
+ if (inst.operands[i].reg != REG_LR)
+ inst.error = _("operand must be LR register");
+ break;
+
default:
break;
}
@@ -10518,6 +10531,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
X(_cpsid, b670, f3af8600), \
X(_cpy, 4600, ea4f0000), \
X(_dec_sp,80dd, f1ad0d00), \
+ X(_dls, 0000, f040e001), \
X(_eor, 4040, ea800000), \
X(_eors, 4040, ea900000), \
X(_inc_sp,00dd, f10d0d00), \
@@ -10530,6 +10544,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
X(_ldr_pc,4800, f85f0000), \
X(_ldr_pc2,4800, f85f0000), \
X(_ldr_sp,9800, f85d0000), \
+ X(_le, 0000, f00fc001), \
X(_lsl, 0000, fa00f000), \
X(_lsls, 0000, fa10f000), \
X(_lsr, 0800, fa20f000), \
@@ -10571,6 +10586,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
X(_yield, bf10, f3af8001), \
X(_wfe, bf20, f3af8002), \
X(_wfi, bf30, f3af8003), \
+ X(_wls, 0000, f040c001), \
X(_sev, bf40, f3af8004), \
X(_sevl, bf50, f3af8005), \
X(_udf, de00, f7f0a000)
@@ -13434,6 +13450,64 @@ do_t_branch_future (void)
}
}
+/* Helper function for do_t_loloop to handle relocations. */
+static void
+v8_1_loop_reloc (int is_le)
+{
+ if (inst.relocs[0].exp.X_op == O_constant)
+ {
+ int value = inst.relocs[0].exp.X_add_number;
+ value = (is_le) ? -value : value;
+
+ if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
+ as_bad (BAD_BRANCH_OFF);
+
+ int imml, immh;
+
+ immh = (value & 0x00000ffc) >> 2;
+ imml = (value & 0x00000002) >> 1;
+
+ inst.instruction |= (imml << 11) | (immh << 1);
+ }
+ else
+ {
+ inst.relocs[0].type = BFD_RELOC_ARM_THUMB_LOOP12;
+ inst.relocs[0].pc_rel = 1;
+ }
+}
+
+/* To handle the Scalar Low Overhead Loop instructions
+ in Armv8.1-M Mainline. */
+static void
+do_t_loloop (void)
+{
+ unsigned long insn = inst.instruction;
+
+ set_it_insn_type (OUTSIDE_IT_INSN);
+ inst.instruction = THUMB_OP32 (inst.instruction);
+
+ switch (insn)
+ {
+ case T_MNEM_le:
+ /* le <label>. */
+ if (!inst.operands[0].present)
+ inst.instruction |= 1 << 21;
+
+ v8_1_loop_reloc (TRUE);
+ break;
+
+ case T_MNEM_wls:
+ v8_1_loop_reloc (FALSE);
+ /* Fall through. */
+ case T_MNEM_dls:
+ constraint (inst.operands[1].isreg != 1, BAD_ARGS);
+ inst.instruction |= (inst.operands[1].reg << 16);
+ break;
+
+ default: abort();
+ }
+}
+
/* Neon instruction encoder helpers. */
/* Encodings for the different types for various Neon opcodes. */
@@ -21756,6 +21830,10 @@ static const struct asm_opcode insns[] =
toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future),
toC("bfl", _bfl, 2, (EXPs, EXPs), t_branch_future),
toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future),
+
+ toU("dls", _dls, 2, (LR, RRnpcsp), t_loloop),
+ toU("wls", _wls, 3, (LR, RRnpcsp, EXP), t_loloop),
+ toU("le", _le, 2, (oLR, EXP), t_loloop),
};
#undef ARM_VARIANT
#undef THUMB_VARIANT
@@ -22996,6 +23074,7 @@ md_pcrel_from_section (fixS * fixP, segT seg)
case BFD_RELOC_ARM_THUMB_BF17:
case BFD_RELOC_ARM_THUMB_BF19:
case BFD_RELOC_ARM_THUMB_BF13:
+ case BFD_RELOC_ARM_THUMB_LOOP12:
return base + 4;
case BFD_RELOC_THUMB_PCREL_BRANCH23:
@@ -25025,6 +25104,39 @@ md_apply_fix (fixS * fixP,
}
break;
+ case BFD_RELOC_ARM_THUMB_LOOP12:
+ if (fixP->fx_addsy
+ && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
+ && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && ARM_IS_FUNC (fixP->fx_addsy)
+ && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
+ {
+ /* Force a relocation for a branch 12 bits wide. */
+ fixP->fx_done = 0;
+ }
+
+ bfd_vma insn = md_chars_to_number (buf, INSN_SIZE);
+ /* le lr, <label> or le <label> */
+ if (((insn & 0xffffffff) == 0xc001f00f)
+ || ((insn & 0xffffffff) == 0xc001f02f))
+ value = -value;
+
+ if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ BAD_BRANCH_OFF);
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ addressT imml, immh;
+
+ immh = (value & 0x00000ffc) >> 2;
+ imml = (value & 0x00000002) >> 1;
+
+ newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
+ newval |= (imml << 11) | (immh << 1);
+ md_number_to_chars (buf + THUMB_SIZE, newval, THUMB_SIZE);
+ }
+ break;
+
case BFD_RELOC_ARM_V4BX:
/* This will need to go in the object file. */
fixP->fx_done = 0;
@@ -25241,6 +25353,7 @@ tc_gen_reloc (asection *section, fixS *fixp)
case BFD_RELOC_THUMB_PCREL_BRANCH5:
case BFD_RELOC_THUMB_PCREL_BFCSEL:
+ case BFD_RELOC_ARM_THUMB_LOOP12:
as_bad_where (fixp->fx_file, fixp->fx_line,
_("%s used for a symbol not defined in the same file"),
bfd_get_reloc_code_name (fixp->fx_r_type));
diff --git a/gas/testsuite/gas/arm/armv8_1-m-loloop-bad.d b/gas/testsuite/gas/arm/armv8_1-m-loloop-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..d1f2a8dfae4fdcb7ca031f8d198d3e5091697391
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-loloop-bad.d
@@ -0,0 +1,4 @@
+#name: Invalid Armv8.1-M Mainline Low Overhead Loop instructions
+#source: armv8_1-m-loloop-bad.s
+#as: -march=armv8.1-m.main
+#error_output: armv8_1-m-loloop-bad.l
diff --git a/gas/testsuite/gas/arm/armv8_1-m-loloop-bad.l b/gas/testsuite/gas/arm/armv8_1-m-loloop-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..691917ebdcefb33aadf8e25314a2aaa4dbc13f86
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-loloop-bad.l
@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*:5: Error: operand must be LR register -- `wls r1,r2,.LB1'
+.*:6: Error: operand must be LR register -- `dls r2,r2'
+.*:7: Error: r15 not allowed here -- `dls lr,pc'
+.*:8: Error: branch out of range or not a multiple of 2
+.*:9: Error: branch out of range or not a multiple of 2
+.*:10: Error: branch out of range or not a multiple of 2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-loloop-bad.s b/gas/testsuite/gas/arm/armv8_1-m-loloop-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..b4f19625db1406e503c2d80ef19162c2d0c1f27e
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-loloop-bad.s
@@ -0,0 +1,12 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+ wls r1, r2, .LB1
+ dls r2, r2
+ dls lr, pc
+ le lr, #4096
+ le #-4098
+ le #-4095
+.LB1:
+ mov r3, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-loloop.d b/gas/testsuite/gas/arm/armv8_1-m-loloop.d
new file mode 100644
index 0000000000000000000000000000000000000000..25661738a338c0054da0ba212e2e3388b966d2b2
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-loloop.d
@@ -0,0 +1,16 @@
+#name: Valid Armv8.1-M Mainline Low Overhead loop instructions
+#source: armv8_1-m-loloop.s
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f042 c00d wls lr, r2, 0000001c <foo\+0x1c>
+0[0-9a-f]+ <[^>]+> f042 e001 dls lr, r2
+0[0-9a-f]+ <[^>]+> f04e e001 dls lr, lr
+0[0-9a-f]+ <[^>]+> f00f c009 le lr, 00000000 <foo>
+0[0-9a-f]+ <[^>]+> f02f c00b le 00000000 <foo>
+0[0-9a-f]+ <[^>]+> f00f c24b le lr, fffffb84 <foo\+0xfffffb84>
+0[0-9a-f]+ <[^>]+> f02f c007 le 00000010 <foo\+0x10>
+0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-loloop.s b/gas/testsuite/gas/arm/armv8_1-m-loloop.s
new file mode 100644
index 0000000000000000000000000000000000000000..8fb87e40aa5d17955903ff473e55c0f37eac50bb
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-loloop.s
@@ -0,0 +1,14 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+.Lstart:
+ wls lr, r2, .LB1
+ dls lr, r2
+ dls lr, lr
+ le lr, .Lstart
+ le .Lstart
+ le lr, #-1172
+ le #-12
+.LB1:
+ mov r3, r2
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index b4865c1a42a04bb6a9b156d7369c065ca351efb4..2cf9507fbb5fe6505df66d2cd0c5abda2d53bdf9 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2718,6 +2718,8 @@ static const struct opcode16 thumb_opcodes[] =
%W print an offset for BF instruction
%Y print an offset for BFL instruction
%Z print an offset for BFCSEL instruction
+ %Q print an offset for Low Overhead Loop instructions
+ %P print an offset for Low Overhead Loop end instructions
%b print a conditional branch offset
%B print an unconditional branch offset
%s print the shift field of an SSAT instruction
@@ -2751,6 +2753,15 @@ static const struct opcode16 thumb_opcodes[] =
static const struct opcode32 thumb32_opcodes[] =
{
/* Armv8.1-M Mainline instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf02fc001, 0xfffff001, "le\t%P"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf00fc001, 0xfffff001, "le\tlr, %P"},
+
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
@@ -5945,6 +5956,32 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
}
break;
+ case 'Q':
+ {
+ unsigned int immh = (given & 0x000007feu) >> 1;
+ unsigned int imml = (given & 0x00000800u) >> 11;
+ bfd_vma imm32 = 0;
+
+ imm32 |= immh << 2;
+ imm32 |= imml << 1;
+
+ info->print_address_func (pc + 4 + imm32, info);
+ }
+ break;
+
+ case 'P':
+ {
+ unsigned int immh = (given & 0x000007feu) >> 1;
+ unsigned int imml = (given & 0x00000800u) >> 11;
+ bfd_vma imm32 = 0;
+
+ imm32 |= immh << 2;
+ imm32 |= imml << 1;
+
+ info->print_address_func (pc + 4 - imm32, info);
+ }
+ break;
+
case 'b':
{
unsigned int S = (given & 0x04000000u) >> 26;
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH, binutils, ARM, 13/16] Add support for CLRM
2019-04-04 13:24 [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Andre Vieira (lists)
` (11 preceding siblings ...)
2019-04-04 13:41 ` [PATCH, binutils, ARM, 11/16] New BFCSEL instruction " Andre Vieira (lists)
@ 2019-04-04 13:42 ` Andre Vieira (lists)
2019-04-04 13:43 ` [PATCH, opcodes, ARM, 14/16] Add mode availability to coprocessor table entries Andre Vieira (lists)
` (3 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-04 13:42 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 2908 bytes --]
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline architecture. Its purpose is to add support for the new CLRM
instruction.
=== Patch description ===
Given the similarity between LDM/STM and CLRM register lists, most of
the changes in this patch aim at sharing code between those two sets of
instruction. Sharing is achieved both in parsing and encoding of those
instructions.
In terms of parsing, parse_reg_list () is extended to take a type that
describe what type of instruction is being parsed. The reg_list_els used
for parse_vfp_reg_list () is reused for the type and that function is
added an assert for the new REGLIST_CLRM and REGLIST_RN enumerators.
parse_reg_list () is then taught to accept APSR and reject SP and PC
when parsing for a CLRM instruction. At last, caller of
parse_reg_list () is updated accordingly and logic is added for the new
OP_CLRMLST operand.
Encoding-wise, encode_thumb2_ldmstm () is reused to encode the variable
bits of CLRM and is thus renamed encode_thumb2_multi (). A new do_io
parameter is added to distinguish between LDM/STM and CLRM which guard
all the LDM/STM specific code of the function.
Finally objdump is told how to disassemble CLRM, again reusing the logic
to print the LDM/STM register list (format specifier 'm'). Tests are
also added in the form of negative tests to check parsing and
encoding/disassembling tests.
ChangeLog entries are as follows:
*** gas/ChangeLog ***
2019-04-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (enum reg_list_els): Define earlier and add
REGLIST_RN and REGLIST_CLRM enumerators.
(parse_reg_list): Add etype parameter to distinguish between regular
core register list and CLRM register list. Add logic to
recognize CLRM register list.
(parse_vfp_reg_list): Assert type is not for core register list.
(s_arm_unwind_save_core): Update call to parse_reg_list to new
prototype.
(enum operand_parse_code): Declare OP_CLRMLST enumerator.
(parse_operands): Update call to parse_reg_list to new prototype. Add
logic for OP_CLRMLST.
(encode_thumb2_ldmstm): Rename into ...
(encode_thumb2_multi): This. Add do_io parameter. Add logic to
encode CLRM and guard LDM/STM only code by do_io.
(do_t_ldmstm): Adapt to use encode_thumb2_multi.
(do_t_push_pop): Likewise.
(do_t_clrm): New function.
(insns): Define CLRM.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.d: New file.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Likewise.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Likewise.
* testsuite/gas/arm/archv8m_1m-cmse-main.d: Likewise.
* testsuite/gas/arm/archv8m_1m-cmse-main.s: Likewise.
*** opcodes/ChangeLog ***
2019-04-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
CLRM.
(print_insn_thumb32): Add logic to print %n CLRM register list.
[-- Attachment #2: 13.patch --]
[-- Type: text/x-patch, Size: 12174 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index ca143a9c7d1ffd0c73dafc972f2c50aed631665c..98b5cfd5845e9c5ecb16493a5e20662288676959 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -1688,14 +1688,27 @@ parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
return reg * 16 + atype.index;
}
+/* Types of registers in a list. */
+
+enum reg_list_els
+{
+ REGLIST_RN,
+ REGLIST_CLRM,
+ REGLIST_VFP_S,
+ REGLIST_VFP_D,
+ REGLIST_NEON_D
+};
+
/* Parse an ARM register list. Returns the bitmask, or FAIL. */
static long
-parse_reg_list (char ** strp)
+parse_reg_list (char ** strp, enum reg_list_els etype)
{
- char * str = * strp;
- long range = 0;
- int another_range;
+ char *str = *strp;
+ long range = 0;
+ int another_range;
+
+ gas_assert (etype == REGLIST_RN || etype == REGLIST_CLRM);
/* We come back here if we get ranges concatenated by '+' or '|'. */
do
@@ -1713,11 +1726,35 @@ parse_reg_list (char ** strp)
do
{
int reg;
+ const char apsr_str[] = "apsr";
+ int apsr_str_len = strlen (apsr_str);
- if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
+ reg = arm_reg_parse (&str, REGLIST_RN);
+ if (etype == REGLIST_CLRM)
{
- first_error (_(reg_expected_msgs[REG_TYPE_RN]));
- return FAIL;
+ if (reg == REG_SP || reg == REG_PC)
+ reg = FAIL;
+ else if (reg == FAIL
+ && !strncasecmp (str, apsr_str, apsr_str_len)
+ && !ISALPHA (*(str + apsr_str_len)))
+ {
+ reg = 15;
+ str += apsr_str_len;
+ }
+
+ if (reg == FAIL)
+ {
+ first_error (_("r0-r12, lr or APSR expected"));
+ return FAIL;
+ }
+ }
+ else /* etype == REGLIST_RN. */
+ {
+ if (reg == FAIL)
+ {
+ first_error (_(reg_expected_msgs[REGLIST_RN]));
+ return FAIL;
+ }
}
if (in_range)
@@ -1761,7 +1798,7 @@ parse_reg_list (char ** strp)
return FAIL;
}
}
- else
+ else if (etype == REGLIST_RN)
{
expressionS exp;
@@ -1816,15 +1853,6 @@ parse_reg_list (char ** strp)
return range;
}
-/* Types of registers in a list. */
-
-enum reg_list_els
-{
- REGLIST_VFP_S,
- REGLIST_VFP_D,
- REGLIST_NEON_D
-};
-
/* Parse a VFP register list. If the string is invalid return FAIL.
Otherwise return the number of registers, and set PBASE to the first
register. Parses registers of type ETYPE.
@@ -1873,6 +1901,9 @@ parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
case REGLIST_NEON_D:
regtype = REG_TYPE_NDQ;
break;
+
+ default:
+ gas_assert (0);
}
if (etype != REGLIST_VFP_S)
@@ -3988,7 +4019,7 @@ s_arm_unwind_save_core (void)
long range;
int n;
- range = parse_reg_list (&input_line_pointer);
+ range = parse_reg_list (&input_line_pointer, REGLIST_RN);
if (range == FAIL)
{
as_bad (_("expected register list"));
@@ -6548,6 +6579,7 @@ enum operand_parse_code
OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */
OP_REGLST, /* ARM register list */
+ OP_CLRMLST, /* CLRM register list */
OP_VRSLST, /* VFP single-precision register list */
OP_VRDLST, /* VFP double-precision register list */
OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
@@ -7173,7 +7205,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
/* Register lists. */
case OP_REGLST:
- val = parse_reg_list (&str);
+ val = parse_reg_list (&str, REGLIST_RN);
if (*str == '^')
{
inst.operands[i].writeback = 1;
@@ -7181,6 +7213,10 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
}
break;
+ case OP_CLRMLST:
+ val = parse_reg_list (&str, REGLIST_CLRM);
+ break;
+
case OP_VRSLST:
val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
break;
@@ -7304,6 +7340,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
case OP_COND:
case OP_oBARRIER_I15:
case OP_REGLST:
+ case OP_CLRMLST:
case OP_VRSLST:
case OP_VRDLST:
case OP_VRSDLST:
@@ -11489,16 +11526,19 @@ do_t_it (void)
/* Helper function used for both push/pop and ldm/stm. */
static void
-encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
+encode_thumb2_multi (bfd_boolean do_io, int base, unsigned mask,
+ bfd_boolean writeback)
{
- bfd_boolean load;
+ bfd_boolean load, store;
- load = (inst.instruction & (1 << 20)) != 0;
+ gas_assert (base != -1 || !do_io);
+ load = do_io && ((inst.instruction & (1 << 20)) != 0);
+ store = do_io && !load;
if (mask & (1 << 13))
inst.error = _("SP not allowed in register list");
- if ((mask & (1 << base)) != 0
+ if (do_io && (mask & (1 << base)) != 0
&& writeback)
inst.error = _("having the base register in the register list when "
"using write back is UNPREDICTABLE");
@@ -11513,13 +11553,13 @@ encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
set_it_insn_type_last ();
}
}
- else
+ else if (store)
{
if (mask & (1 << 15))
inst.error = _("PC not allowed in register list");
}
- if ((mask & (mask - 1)) == 0)
+ if (do_io && ((mask & (mask - 1)) == 0))
{
/* Single register transfers implemented as str/ldr. */
if (writeback)
@@ -11548,7 +11588,8 @@ encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
inst.instruction |= WRITE_BACK;
inst.instruction |= mask;
- inst.instruction |= base << 16;
+ if (do_io)
+ inst.instruction |= base << 16;
}
static void
@@ -11643,8 +11684,9 @@ do_t_ldmstm (void)
if (inst.instruction < 0xffff)
inst.instruction = THUMB_OP32 (inst.instruction);
- encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
- inst.operands[0].writeback);
+ encode_thumb2_multi (TRUE /* do_io */, inst.operands[0].reg,
+ inst.operands[1].imm,
+ inst.operands[0].writeback);
}
}
else
@@ -12751,8 +12793,20 @@ do_t_push_pop (void)
else if (unified_syntax)
{
inst.instruction = THUMB_OP32 (inst.instruction);
- encode_thumb2_ldmstm (13, mask, TRUE);
+ encode_thumb2_multi (TRUE /* do_io */, 13, mask, TRUE);
+ }
+ else
+ {
+ inst.error = _("invalid register list to push/pop instruction");
+ return;
}
+}
+
+static void
+do_t_clrm (void)
+{
+ if (unified_syntax)
+ encode_thumb2_multi (FALSE /* do_io */, -1, inst.operands[0].imm, FALSE);
else
{
inst.error = _("invalid register list to push/pop instruction");
@@ -21834,6 +21888,8 @@ static const struct asm_opcode insns[] =
toU("dls", _dls, 2, (LR, RRnpcsp), t_loloop),
toU("wls", _wls, 3, (LR, RRnpcsp, EXP), t_loloop),
toU("le", _le, 2, (oLR, EXP), t_loloop),
+
+ ToC("clrm", e89f0000, 1, (CLRMLST), t_clrm)
};
#undef ARM_VARIANT
#undef THUMB_VARIANT
diff --git a/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.d b/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..a5c755804dd9bd4cd50b4a5cd9d48d7bf417016f
--- /dev/null
+++ b/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.d
@@ -0,0 +1,4 @@
+#name: Invalid Armv8.1-M Mainline Security Extensions instructions
+#source: archv8m_1m-cmse-main-bad.s
+#as: -march=armv8.1-m.main
+#error_output: archv8m_1m-cmse-main-bad.l
diff --git a/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.l b/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..ed440bf2baa36e0f60cccff417d8148a17749f44
--- /dev/null
+++ b/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.l
@@ -0,0 +1,4 @@
+[^:]*: Assembler messages:
+[^:]*:6: Error: r0-r12, lr or APSR expected -- `clrm {}'
+[^:]*:7: Error: r0-r12, lr or APSR expected -- `clrm {sp}'
+[^:]*:8: Error: r0-r12, lr or APSR expected -- `clrm {pc}'
diff --git a/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.s b/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..c991a559093fd5da79f8eb54c02fde13208a8071
--- /dev/null
+++ b/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.s
@@ -0,0 +1,8 @@
+.thumb
+.syntax unified
+
+T:
+
+clrm {} @ Rejects empty list
+clrm {sp} @ Rejects SP in list
+clrm {pc} @ Reject PC in list
diff --git a/gas/testsuite/gas/arm/archv8m_1m-cmse-main.d b/gas/testsuite/gas/arm/archv8m_1m-cmse-main.d
new file mode 100644
index 0000000000000000000000000000000000000000..b082ff7e6451186763dd55cf96f9205d2f5ce4d8
--- /dev/null
+++ b/gas/testsuite/gas/arm/archv8m_1m-cmse-main.d
@@ -0,0 +1,14 @@
+#name: Armv8.1-M Mainline Security Extensions instructions
+#source: archv8m_1m-cmse-main.s
+#as: -march=armv8.1-m.main -mimplicit-it=always
+#objdump: -dr --prefix-addresses --show-raw-insn -marmv8.1-m.main
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+.* <[^>]*> e89f 0005 clrm {r0, r2}
+0+.* <[^>]*> e89f 8000 clrm {APSR}
+0+.* <[^>]*> e89f 8008 clrm {r3, APSR}
+0+.* <[^>]*> bf08 it eq
+0+.* <[^>]*> e89f 0010 clrmeq {r4}
+#...
diff --git a/gas/testsuite/gas/arm/archv8m_1m-cmse-main.s b/gas/testsuite/gas/arm/archv8m_1m-cmse-main.s
new file mode 100644
index 0000000000000000000000000000000000000000..084d83b88b63bb4f55fd9ab2388b80b91696f763
--- /dev/null
+++ b/gas/testsuite/gas/arm/archv8m_1m-cmse-main.s
@@ -0,0 +1,9 @@
+.thumb
+.syntax unified
+
+T:
+
+clrm {r0, r2} @ Accepts list without APSR
+clrm {APSR} @ Accepts APSR alone
+clrm {r3, APSR} @ Accepts core register and APSR together
+clrmeq {r4} @ Accepts conditional execution
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 2cf9507fbb5fe6505df66d2cd0c5abda2d53bdf9..d7a64671dc132bbb974dda91d5760180079a02f6 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2711,6 +2711,7 @@ static const struct opcode16 thumb_opcodes[] =
%a print the address of a plain load/store
%w print the width and signedness of a core load/store
%m print register mask for ldm/stm
+ %n print register mask for clrm
%E print the lsb and width fields of a bfc/bfi instruction
%F print the lsb and width fields of a sbfx/ubfx instruction
@@ -2752,7 +2753,8 @@ static const struct opcode16 thumb_opcodes[] =
makes heavy use of special-case bit patterns. */
static const struct opcode32 thumb32_opcodes[] =
{
- /* Armv8.1-M Mainline instructions. */
+ /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
+ instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
@@ -2773,6 +2775,8 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
/* ARMv8-M and ARMv8-M Security Extensions instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
@@ -5557,6 +5561,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
for (insn = thumb32_opcodes; insn->assembler; insn++)
if ((given & insn->mask) == insn->value)
{
+ bfd_boolean is_clrm = FALSE;
bfd_boolean is_unpredictable = FALSE;
signed long value_in_comment = 0;
const char *c = insn->assembler;
@@ -5852,6 +5857,9 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
}
break;
+ case 'n':
+ is_clrm = TRUE;
+ /* Fall through. */
case 'm':
{
int started = 0;
@@ -5864,7 +5872,12 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
if (started)
func (stream, ", ");
started = 1;
- func (stream, "%s", arm_regnames[reg]);
+ if (is_clrm && reg == 13)
+ func (stream, "(invalid: %s)", arm_regnames[reg]);
+ else if (is_clrm && reg == 15)
+ func (stream, "%s", "APSR");
+ else
+ func (stream, "%s", arm_regnames[reg]);
}
func (stream, "}");
}
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH, opcodes, ARM, 14/16] Add mode availability to coprocessor table entries
2019-04-04 13:24 [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Andre Vieira (lists)
` (12 preceding siblings ...)
2019-04-04 13:42 ` [PATCH, binutils, ARM, 13/16] Add support for CLRM Andre Vieira (lists)
@ 2019-04-04 13:43 ` Andre Vieira (lists)
2019-04-04 13:44 ` [PATCH, binutils, ARM, 16/16] Add support to VLDR and VSTR of system registers Andre Vieira (lists)
` (2 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-04 13:43 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 1403 bytes --]
The coprocessor_opcodes table is used both to share commonalities in
coprocessor-related instructions and to avoid duplication between Arm
and Thumb mode. However, some instructions do have differences between
Arm and Thumb. For instance, vldmia allows PC as base register in Arm
mode but not in Thumb mode.
In that very case the distinction becomes necessary because the encoding
with PC as base register is used in Thumb mode to denote a VSCCLRM. It
is thus necessary to distinguish what is Arm or Thumb only from what is
shared. This patch adds an extra field to the coprocessor_opcodes table
entries to indicate what mode is a given instruction available in. The
print_insn_coprocessor then uses that field to determine if an entry
that matched the mark and value checked should be allowed to match or
not given the current mode.
ChangeLog entry is as follows:
*** opcodes/ChangeLog ***
2019-04-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (enum isa): New enum.
(struct sopcode32): New structure.
(coprocessor_opcodes): change type of entries to struct sopcode32 and
set isa field of all current entries to ANY.
(print_insn_coprocessor): Change type of insn to struct sopcode32.
Only match an entry if its isa field allows the current mode.
Testing: Ran testsuite for arm-none-eabi targets without any regression.
Is this ok for master branch?
Best regards,
Thomas
[-- Attachment #2: 14.patch --]
[-- Type: text/x-patch, Size: 68034 bytes --]
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 7b457e318df660993179f5b429ac48fc69fc1813..5ab4df541bf03d384e1deb8b7ee4eb2e82600158 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -76,6 +76,23 @@ struct opcode32
const char * assembler; /* How to disassemble this insn. */
};
+enum isa {
+ ANY,
+ T32,
+ ARM
+};
+
+
+/* Shared (between Arm and Thumb mode) opcode. */
+struct sopcode32
+{
+ enum isa isa; /* Execution mode instruction availability. */
+ arm_feature_set arch; /* Architecture defining this insn. */
+ unsigned long value; /* If arch is 0 then value is a sentinel. */
+ unsigned long mask; /* Recognise insn if (op & mask) == value. */
+ const char * assembler; /* How to disassemble this insn. */
+};
+
struct opcode16
{
arm_feature_set arch; /* Architecture defining this insn. */
@@ -148,885 +165,885 @@ enum opcode_sentinel_enum
/* Common coprocessor opcodes shared between Arm and Thumb-2. */
-static const struct opcode32 coprocessor_opcodes[] =
+static const struct sopcode32 coprocessor_opcodes[] =
{
/* XScale instructions. */
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200010, 0x0fff0ff0,
"mia%c\tacc0, %0-3r, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e280010, 0x0fff0ff0,
"miaph%c\tacc0, %0-3r, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
/* Intel Wireless MMX technology instructions. */
- {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
- {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
+ {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800120, 0x0f800ff0,
"wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e8000a0, 0x0f800ff0,
"wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_CORE_LOW (0),
+ {ANY, ARM_FEATURE_CORE_LOW (0),
SENTINEL_IWMMXT_END, 0, "" },
/* Floating point coprocessor (FPA) instructions. */
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
/* ARMv8-M Mainline Security Extensions instructions. */
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
/* Register load/store. */
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
/* Data transfer between ARM and NEON registers. */
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
/* Half-precision conversion instructions. */
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
/* Floating point coprocessor (VFP) instructions. */
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
/* Cirrus coprocessor instructions. */
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000600, 0x0ff00f10,
"cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100600, 0x0ff00f10,
"cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200600, 0x0ff00f10,
"cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300600, 0x0ff00f10,
"cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
/* VFP Fused multiply add instructions. */
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
/* FP v5. */
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
/* Generic coprocessor instructions. */
- {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
+ {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
0x0c500000, 0x0ff00000,
"mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e000000, 0x0f000010,
"cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e10f010, 0x0f10f010,
"mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e100010, 0x0f100010,
"mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e000010, 0x0f100010,
"mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
/* V6 coprocessor instructions. */
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0xfc500000, 0xfff00000,
"mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0xfc400000, 0xfff00000,
"mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
/* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
/* Dot Product instructions in the space of coprocessor 13. */
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
/* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
/* V5 coprocessor instructions. */
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe000000, 0xff000010,
"cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe000010, 0xff100010,
"mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe100010, 0xff100010,
"mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
/* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
cp_num: bit <11:8> == 0b1001.
cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
/* ARMv8.3 javascript conversion instruction. */
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
- {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
+ {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
};
/* Neon opcode table: This does not encode the top byte -- that is
@@ -3430,7 +3447,7 @@ print_insn_coprocessor (bfd_vma pc,
long given,
bfd_boolean thumb)
{
- const struct opcode32 *insn;
+ const struct sopcode32 *insn;
void *stream = info->stream;
fprintf_ftype func = info->fprintf_func;
unsigned long mask;
@@ -3506,6 +3523,10 @@ print_insn_coprocessor (bfd_vma pc,
}
}
+ if ((insn->isa == T32 && !thumb)
+ || (insn->isa == ARM && thumb))
+ continue;
+
if ((given & mask) != value)
continue;
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH, binutils, ARM, 15/16] Add support for VSCCLRM
2019-04-04 13:24 [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Andre Vieira (lists)
` (14 preceding siblings ...)
2019-04-04 13:44 ` [PATCH, binutils, ARM, 16/16] Add support to VLDR and VSTR of system registers Andre Vieira (lists)
@ 2019-04-04 13:44 ` Andre Vieira (lists)
2019-04-11 10:04 ` [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Nick Clifton
16 siblings, 0 replies; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-04 13:44 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 3282 bytes --]
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline architecture. Its purpose is to add support for the new VSCCLRM
instruction.
=== Patch description ===
Like for CLRM, this patch aims to share as much logic with the similar
looking VLDM/VSTM. This is achieved by adding 2 new enumerator values in
enum reg_list_els for the single-precision and double-precision variants
of VSCCLRM and extending parse_vfp_reg_list () to deal with these types.
These behave like the existing REGLIST_VFP_S and REGLIST_VFP_D types
with extra logic to expect VPR as the last element in the register list.
The function is algo augmented with a new partial_match parameter to
indicate if any register other than VPR had already been parsed in the
register list so as to not try parsing the second variant if that's the
case and return the right error message.
The rest of the patch is the usual encoding function, new disassembler
table entries and format specifier and parsing, encoding and
disassembling tests.
It is worth mentioning that the new entry in the disassembler table was
added in the coprocessor-related table despite VSCCLRM always being
available even in FPU-less configurations. The main reason for this is
that VSCCLRM also match VLDMIA entry and must thus be tried first but
coprocessor entries are tried before T32 entries. It also makes sense
because it is in the same encoding space as coprocessor and VFP
instructions and is thus the natural place for someone to look for this
instruction.
Note: Both variants of VSCCLRM support D16-D31 registers but Armv8.1-M
Mainline overall does not. I have thus decided not to implement support
for these registers in order to keep the code simpler. It can always be
added later if needed.
ChangeLog entries are as follows:
*** gas/ChangeLog ***
2019-04-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (arm_typed_reg_parse): Fix typo in comment.
(enum reg_list_els): New REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
enumerators.
(parse_vfp_reg_list): Add new partial_match parameter. Set
*partial_match to TRUE if at least one element in the register list has
matched. Add support for REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
register lists which expect VPR as last element in the list.
(s_arm_unwind_save_vfp_armv6): Adapt call to parse_vfp_reg_list to new
prototype.
(s_arm_unwind_save_vfp): Likewise.
(enum operand_parse_code): New OP_VRSDVLST enumerator.
(parse_operands): Adapt call to parse_vfp_reg_list to new prototype.
Handle new OP_VRSDVLST case.
(do_t_vscclrm): New function.
(insns): New entry for VSCCLRM instruction.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add invalid VSCCLRM
instructions.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error expectations
for above instructions.
* testsuite/gas/arm/archv8m_1m-cmse-main.s: Add tests for VSCCLRM
instruction.
* testsuite/gas/arm/archv8m_1m-cmse-main.d: Add expected disassembly
for above instructions.
*** opcodes/ChangeLog ***
2019-04-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (coprocessor_opcodes): Document new %C format control code.
Add new entries for VSCCLRM instruction.
(print_insn_coprocessor): Handle new %C format control code.
[-- Attachment #2: 15.patch --]
[-- Type: text/x-patch, Size: 14249 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 98b5cfd5845e9c5ecb16493a5e20662288676959..f9e3756950d08dc5162bf97fd831315b4cef2873 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -1609,7 +1609,7 @@ parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
return reg->number;
}
-/* Like arm_reg_parse, but allow allow the following extra features:
+/* Like arm_reg_parse, but also allow the following extra features:
- If RTYPE is non-zero, return the (possibly restricted) type of the
register (e.g. Neon double or quad reg when either has been requested).
- If this is a Neon vector type with additional type information, fill
@@ -1695,7 +1695,9 @@ enum reg_list_els
REGLIST_RN,
REGLIST_CLRM,
REGLIST_VFP_S,
+ REGLIST_VFP_S_VPR,
REGLIST_VFP_D,
+ REGLIST_VFP_D_VPR,
REGLIST_NEON_D
};
@@ -1869,7 +1871,8 @@ parse_reg_list (char ** strp, enum reg_list_els etype)
bug. */
static int
-parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
+parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype,
+ bfd_boolean *partial_match)
{
char *str = *ccp;
int base_reg;
@@ -1880,6 +1883,9 @@ parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
int warned = 0;
unsigned long mask = 0;
int i;
+ bfd_boolean vpr_seen = FALSE;
+ bfd_boolean expect_vpr =
+ (etype == REGLIST_VFP_S_VPR) || (etype == REGLIST_VFP_D_VPR);
if (skip_past_char (&str, '{') == FAIL)
{
@@ -1890,11 +1896,13 @@ parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
switch (etype)
{
case REGLIST_VFP_S:
+ case REGLIST_VFP_S_VPR:
regtype = REG_TYPE_VFS;
max_regs = 32;
break;
case REGLIST_VFP_D:
+ case REGLIST_VFP_D_VPR:
regtype = REG_TYPE_VFD;
break;
@@ -1906,7 +1914,7 @@ parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
gas_assert (0);
}
- if (etype != REGLIST_VFP_S)
+ if (etype != REGLIST_VFP_S && etype != REGLIST_VFP_S_VPR)
{
/* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
@@ -1924,19 +1932,54 @@ parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
}
base_reg = max_regs;
+ *partial_match = FALSE;
do
{
int setmask = 1, addregs = 1;
+ const char vpr_str[] = "vpr";
+ int vpr_str_len = strlen (vpr_str);
new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
- if (new_base == FAIL)
+ if (expect_vpr)
+ {
+ if (new_base == FAIL
+ && !strncasecmp (str, vpr_str, vpr_str_len)
+ && !ISALPHA (*(str + vpr_str_len))
+ && !vpr_seen)
+ {
+ vpr_seen = TRUE;
+ str += vpr_str_len;
+ if (count == 0)
+ base_reg = 0; /* Canonicalize VPR only on d0 with 0 regs. */
+ }
+ else if (vpr_seen)
+ {
+ first_error (_("VPR expected last"));
+ return FAIL;
+ }
+ else if (new_base == FAIL)
+ {
+ if (regtype == REG_TYPE_VFS)
+ first_error (_("VFP single precision register or VPR "
+ "expected"));
+ else /* regtype == REG_TYPE_VFD. */
+ first_error (_("VFP/Neon double precision register or VPR "
+ "expected"));
+ return FAIL;
+ }
+ }
+ else if (new_base == FAIL)
{
first_error (_(reg_expected_msgs[regtype]));
return FAIL;
}
+ *partial_match = TRUE;
+ if (vpr_seen)
+ continue;
+
if (new_base >= max_regs)
{
first_error (_("register out of range in list"));
@@ -1959,7 +2002,7 @@ parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
return FAIL;
}
- if ((mask >> new_base) != 0 && ! warned)
+ if ((mask >> new_base) != 0 && ! warned && !vpr_seen)
{
as_tsktsk (_("register list not in ascending order"));
warned = 1;
@@ -2014,11 +2057,17 @@ parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
str++;
/* Sanity check -- should have raised a parse error above. */
- if (count == 0 || count > max_regs)
+ if ((!vpr_seen && count == 0) || count > max_regs)
abort ();
*pbase = base_reg;
+ if (expect_vpr && !vpr_seen)
+ {
+ first_error (_("VPR expected last"));
+ return FAIL;
+ }
+
/* Final test -- the registers must be consecutive. */
mask >>= base_reg;
for (i = 0; i < count; i++)
@@ -4146,8 +4195,10 @@ s_arm_unwind_save_vfp_armv6 (void)
valueT op;
int num_vfpv3_regs = 0;
int num_regs_below_16;
+ bfd_boolean partial_match;
- count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
+ count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D,
+ &partial_match);
if (count == FAIL)
{
as_bad (_("expected register list"));
@@ -4194,8 +4245,10 @@ s_arm_unwind_save_vfp (void)
int count;
unsigned int reg;
valueT op;
+ bfd_boolean partial_match;
- count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
+ count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D,
+ &partial_match);
if (count == FAIL)
{
as_bad (_("expected register list"));
@@ -6585,6 +6638,7 @@ enum operand_parse_code
OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
OP_NSTRLST, /* Neon element/structure list */
+ OP_VRSDVLST, /* VFP single or double-precision register list and VPR */
OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
@@ -6694,6 +6748,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
enum arm_reg_type rtype;
parse_operand_result result;
unsigned int op_parse_code;
+ bfd_boolean partial_match;
#define po_char_or_fail(chr) \
do \
@@ -7218,29 +7273,43 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
break;
case OP_VRSLST:
- val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
+ val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S,
+ &partial_match);
break;
case OP_VRDLST:
- val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
+ val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D,
+ &partial_match);
break;
case OP_VRSDLST:
/* Allow Q registers too. */
val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
- REGLIST_NEON_D);
+ REGLIST_NEON_D, &partial_match);
if (val == FAIL)
{
inst.error = NULL;
val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
- REGLIST_VFP_S);
+ REGLIST_VFP_S, &partial_match);
+ inst.operands[i].issingle = 1;
+ }
+ break;
+
+ case OP_VRSDVLST:
+ val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
+ REGLIST_VFP_D_VPR, &partial_match);
+ if (val == FAIL && !partial_match)
+ {
+ inst.error = NULL;
+ val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
+ REGLIST_VFP_S_VPR, &partial_match);
inst.operands[i].issingle = 1;
}
break;
case OP_NRDLST:
val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
- REGLIST_NEON_D);
+ REGLIST_NEON_D, &partial_match);
break;
case OP_NSTRLST:
@@ -7344,6 +7413,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
case OP_VRSLST:
case OP_VRDLST:
case OP_VRSDLST:
+ case OP_VRSDVLST:
case OP_NRDLST:
case OP_NSTRLST:
if (val == FAIL)
@@ -12814,6 +12884,24 @@ do_t_clrm (void)
}
}
+static void
+do_t_vscclrm (void)
+{
+ if (inst.operands[0].issingle)
+ {
+ inst.instruction |= (inst.operands[0].reg & 0x1) << 22;
+ inst.instruction |= (inst.operands[0].reg & 0x1e) << 11;
+ inst.instruction |= inst.operands[0].imm;
+ }
+ else
+ {
+ inst.instruction |= (inst.operands[0].reg & 0x10) << 18;
+ inst.instruction |= (inst.operands[0].reg & 0xf) << 12;
+ inst.instruction |= 1 << 8;
+ inst.instruction |= inst.operands[0].imm << 1;
+ }
+}
+
static void
do_t_rbit (void)
{
@@ -21889,7 +21977,8 @@ static const struct asm_opcode insns[] =
toU("wls", _wls, 3, (LR, RRnpcsp, EXP), t_loloop),
toU("le", _le, 2, (oLR, EXP), t_loloop),
- ToC("clrm", e89f0000, 1, (CLRMLST), t_clrm)
+ ToC("clrm", e89f0000, 1, (CLRMLST), t_clrm),
+ ToC("vscclrm", ec9f0a00, 1, (VRSDVLST), t_vscclrm)
};
#undef ARM_VARIANT
#undef THUMB_VARIANT
diff --git a/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.l b/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.l
index ed440bf2baa36e0f60cccff417d8148a17749f44..b64937d27f2af469daac5e3feb9167dccde0a986 100644
--- a/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.l
+++ b/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.l
@@ -2,3 +2,7 @@
[^:]*:6: Error: r0-r12, lr or APSR expected -- `clrm {}'
[^:]*:7: Error: r0-r12, lr or APSR expected -- `clrm {sp}'
[^:]*:8: Error: r0-r12, lr or APSR expected -- `clrm {pc}'
+[^:]*:10: Error: VFP single precision register or VPR expected -- `vscclrm {}'
+[^:]*:11: Error: VPR expected last -- `vscclrm {s0}'
+[^:]*:12: Error: VFP single precision register or VPR expected -- `vscclrm {s1,d1,VPR}'
+[^:]*:13: Error: VFP single precision register expected -- `vscclrm {s1-d1,VPR}'
diff --git a/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.s b/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.s
index c991a559093fd5da79f8eb54c02fde13208a8071..f4baefe73f84a0c93a9ab992b80a9f0b3644d051 100644
--- a/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.s
+++ b/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.s
@@ -6,3 +6,8 @@ T:
clrm {} @ Rejects empty list
clrm {sp} @ Rejects SP in list
clrm {pc} @ Reject PC in list
+
+vscclrm {} @ Rejects empty list
+vscclrm {s0} @ Rejects list without VPR
+vscclrm {s1, d1, VPR} @ Reject mix of single and double-precision VFP registers
+vscclrm {s1-d1, VPR} @ Likewise when using a range
diff --git a/gas/testsuite/gas/arm/archv8m_1m-cmse-main.d b/gas/testsuite/gas/arm/archv8m_1m-cmse-main.d
index b082ff7e6451186763dd55cf96f9205d2f5ce4d8..866adc9cb0db7a8c0f6061c3829ac07f3d5233f3 100644
--- a/gas/testsuite/gas/arm/archv8m_1m-cmse-main.d
+++ b/gas/testsuite/gas/arm/archv8m_1m-cmse-main.d
@@ -11,4 +11,13 @@ Disassembly of section .text:
0+.* <[^>]*> e89f 8008 clrm {r3, APSR}
0+.* <[^>]*> bf08 it eq
0+.* <[^>]*> e89f 0010 clrmeq {r4}
+0+.* <[^>]*> ec9f 0b00 vscclrm {VPR}
+0+.* <[^>]*> ec9f fa01 vscclrm {s30, VPR}
+0+.* <[^>]*> ec9f eb02 vscclrm {d14, VPR}
+0+.* <[^>]*> ecdf 0a04 vscclrm {s1-s4, VPR}
+0+.* <[^>]*> ec9f 1b08 vscclrm {d1-d4, VPR}
+0+.* <[^>]*> ec9f 0a20 vscclrm {s0-s31, VPR}
+0+.* <[^>]*> ec9f 0b20 vscclrm {d0-d15, VPR}
+0+.* <[^>]*> bf18 it ne
+0+.* <[^>]*> ecdf 1a01 vscclrmne {s3, VPR}
#...
diff --git a/gas/testsuite/gas/arm/archv8m_1m-cmse-main.s b/gas/testsuite/gas/arm/archv8m_1m-cmse-main.s
index 084d83b88b63bb4f55fd9ab2388b80b91696f763..f4df2dbb2f7666c4c762a9b62463d809ba91577e 100644
--- a/gas/testsuite/gas/arm/archv8m_1m-cmse-main.s
+++ b/gas/testsuite/gas/arm/archv8m_1m-cmse-main.s
@@ -7,3 +7,14 @@ clrm {r0, r2} @ Accepts list without APSR
clrm {APSR} @ Accepts APSR alone
clrm {r3, APSR} @ Accepts core register and APSR together
clrmeq {r4} @ Accepts conditional execution
+
+vscclrm {VPR} @ Accepts list with only VPR
+vscclrm {s30, VPR} @ Accept single-precision VFP register and VPR together
+vscclrm {d14, VPR} @ Likewise for double-precision VFP register
+vscclrm {s1-s4, VPR} @ Accept range of single-precision VFP registers
+ @ and VPR together
+vscclrm {d1-d4, VPR} @ Likewise for double-precision VFP registers
+vscclrm {s0-s31, VPR} @ Accept all single-precision VFP registers and VPR
+ @ together
+vscclrm {d0-d15, VPR} @ Likewise for double-precision VFP registers
+vscclrmne {s3, VPR} @ Accepts conditional execution
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index d41de41002519b459bb16dd0e00e1025848e5b37..cf11e616eaa50acdc546adfd9c92740770b27177 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -110,6 +110,7 @@ struct opcode16
UNPREDICTABLE if not AL in Thumb)
%A print address for ldc/stc/ldf/stf instruction
%B print vstm/vldm register list
+ %C print vscclrm register list
%I print cirrus signed shift immediate: bits 0..3|4..6
%F print the COUNT field of a LFM/SFM instruction.
%P print floating point precision in arithmetic insn
@@ -426,6 +427,12 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
+ /* Armv8.1-M Mainline instructions. */
+ {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
+ {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
+
/* ARMv8-M Mainline Security Extensions instructions. */
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
@@ -3643,6 +3650,31 @@ print_insn_coprocessor (bfd_vma pc,
}
break;
+ case 'C':
+ {
+ bfd_boolean single = ((given >> 8) & 1) == 0;
+ char reg_prefix = single ? 's' : 'd';
+ int Dreg = (given >> 22) & 0x1;
+ int Vdreg = (given >> 12) & 0xf;
+ int reg = single ? ((Vdreg << 1) | Dreg)
+ : ((Dreg << 4) | Vdreg);
+ int num = (given >> (single ? 0 : 1)) & 0x7f;
+ int maxreg = single ? 31 : 15;
+ int topreg = reg + num - 1;
+
+ if (!num)
+ func (stream, "{VPR}");
+ else if (num == 1)
+ func (stream, "{%c%d, VPR}", reg_prefix, reg);
+ else if (topreg > maxreg)
+ func (stream, "{%c%d-<overflow reg d%d, VPR}",
+ reg_prefix, reg, single ? topreg >> 1 : topreg);
+ else
+ func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
+ reg_prefix, topreg);
+ }
+ break;
+
case 'u':
if (cond != COND_UNCOND)
is_unpredictable = TRUE;
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH, binutils, ARM, 16/16] Add support to VLDR and VSTR of system registers
2019-04-04 13:24 [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Andre Vieira (lists)
` (13 preceding siblings ...)
2019-04-04 13:43 ` [PATCH, opcodes, ARM, 14/16] Add mode availability to coprocessor table entries Andre Vieira (lists)
@ 2019-04-04 13:44 ` Andre Vieira (lists)
2019-04-04 13:44 ` [PATCH, binutils, ARM, 15/16] Add support for VSCCLRM Andre Vieira (lists)
2019-04-11 10:04 ` [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Nick Clifton
16 siblings, 0 replies; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-04 13:44 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 3048 bytes --]
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline architecture. Its purpose is to add support for the new
VLDR (system register) and VSTR (system register) instructions.
=== Patch description ===
GNU as' Arm backend assumes each mnemonic has a single entry in the
instruction table but VLDR (system register) and VSTR (system register)
are different instructions than VLDR and VSTR. It is thus necessary to
add some form of demultiplexing in the parser. It starts by creating a
new operand type OP_VLDR which indicate that the operand is either the
existing OP_RVSD operand or a system register. The function
parse_operands () then tries these two cases in order, calling the new
parse_sys_vldr_vstr for the second case.
Since the encoding function is specified in the instruction table entry,
it also need to have some sort of demultiplexing. This is done in
do_vldr_vstr which either calls the existing do_neon_ldr_str () or calls
the new do_t_vldr_vstr_sysreg ().
A new internal relocation is needed as well since the offset has a
shorter range than in other Thumb coprocessor instructions. Disassembly
also requires special care since VSTR (system register) reuse the STC
encoding with the coprocessor number 15. Armv8.1-M Mainline ARM manual
states that coprocessor 8, 14 and 15 are reserved for floating-point and
MVE instructions a feature bit check is added if the coprocessor number
is one of this value and we are trying to match a coprocessor
instruction (eg. STC) to forbid the match.
ChangeLog entries are as follows:
*** bfd/ChangeLog ***
2019-04-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
* reloc.c (BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM): New internal
relocation.
* bfd-in2.h: Regenerate.
* libbfd.h: Likewise.
*** gas/ChangeLog ***
2019-04-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (parse_sys_vldr_vstr): New function.
(OP_VLDR): New enum operand_parse_code enumerator.
(parse_operands): Add logic for OP_VLDR.
(do_t_vldr_vstr_sysreg): New function.
(do_vldr_vstr): Likewise.
(insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode.
(md_apply_fix): Add bound check for VLDR and VSTR co-processor offset.
Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad
uses of VLDR and VSTR.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for
above bad uses.
* testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and
VSTR valid uses.
* testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the
above examples.
*** opcodes/ChangeLog ***
2019-04-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (coprocessor_opcodes): Document new %J and %K format
specifier. Add entries for VLDR and VSTR of system registers.
(print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
coprocessor instructions on Armv8.1-M Mainline targets. Add handling
of %J and %K format specifier.
[-- Attachment #2: 16.patch --]
[-- Type: text/x-patch, Size: 17161 bytes --]
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 540b9f71c181841ea782c63d87d0d5271c864966..13af0beade1ee1521be7db8307e5fa2e025594b2 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -3722,6 +3722,7 @@ pc-relative or some form of GOT-indirect relocation. */
BFD_RELOC_ARM_CP_OFF_IMM_S2,
BFD_RELOC_ARM_T32_CP_OFF_IMM,
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2,
+ BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM,
BFD_RELOC_ARM_ADR_IMM,
BFD_RELOC_ARM_LDR_IMM,
BFD_RELOC_ARM_LITERAL,
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index f64a8f3892ad3aff5c4570f0281875bce35846a6..b51df73179fd1d3185f904466fd995f113a22835 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -1634,6 +1634,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_ARM_CP_OFF_IMM_S2",
"BFD_RELOC_ARM_T32_CP_OFF_IMM",
"BFD_RELOC_ARM_T32_CP_OFF_IMM_S2",
+ "BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM",
"BFD_RELOC_ARM_ADR_IMM",
"BFD_RELOC_ARM_LDR_IMM",
"BFD_RELOC_ARM_LITERAL",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index e6ba9e265027a6c34a8ad183dd5825a9af9c1f82..9615279833228cff4cb7f4cd77e930b2ad7cf4ab 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -3292,6 +3292,8 @@ ENUMX
BFD_RELOC_ARM_T32_CP_OFF_IMM
ENUMX
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
+ENUMX
+ BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
ENUMX
BFD_RELOC_ARM_ADR_IMM
ENUMX
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index f3fe397d37460b47dc634214a3a3e4c167ff3bfe..8035fa1db4dcf88393c96f8d54a55766ca1ab580 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -6128,6 +6128,39 @@ check_suffix:
return FAIL;
}
+static int
+parse_sys_vldr_vstr (char **str)
+{
+ unsigned i;
+ int val = FAIL;
+ struct {
+ const char *name;
+ int regl;
+ int regh;
+ } sysregs[] = {
+ {"FPSCR", 0x1, 0x0},
+ {"FPSCR_nzcvqc", 0x2, 0x0},
+ {"VPR", 0x4, 0x1},
+ {"P0", 0x5, 0x1},
+ {"FPCXTNS", 0x6, 0x1},
+ {"FPCXTS", 0x7, 0x1}
+ };
+ char *op_end = strchr (*str, ',');
+ size_t op_strlen = op_end - *str;
+
+ for (i = 0; i < sizeof (sysregs) / sizeof (sysregs[0]); i++)
+ {
+ if (!strncmp (*str, sysregs[i].name, op_strlen))
+ {
+ val = sysregs[i].regl | (sysregs[i].regh << 3);
+ *str = op_end;
+ break;
+ }
+ }
+
+ return val;
+}
+
/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
value suitable for splatting into the AIF field of the instruction. */
@@ -6652,6 +6685,7 @@ enum operand_parse_code
OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
+ OP_VLDR, /* VLDR operand. */
OP_I0, /* immediate zero */
OP_I7, /* immediate value 0 .. 7 */
@@ -7225,6 +7259,13 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
val = parse_psr (&str, op_parse_code == OP_wPSR);
break;
+ case OP_VLDR:
+ po_reg_or_goto (REG_TYPE_VFSD, try_sysreg);
+ break;
+ try_sysreg:
+ val = parse_sys_vldr_vstr (&str);
+ break;
+
case OP_APSR_RR:
po_reg_or_goto (REG_TYPE_RN, try_apsr);
break;
@@ -7401,6 +7442,10 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
inst.error = BAD_PC;
break;
+ case OP_VLDR:
+ if (inst.operands[i].isreg)
+ break;
+ /* fall through. */
case OP_CPSF:
case OP_ENDI:
case OP_oROR:
@@ -17397,6 +17442,55 @@ do_neon_ldr_str (void)
}
}
+static void
+do_t_vldr_vstr_sysreg (void)
+{
+ int fp_vldr_bitno = 20, sysreg_vldr_bitno = 20;
+ bfd_boolean is_vldr = ((inst.instruction & (1 << fp_vldr_bitno)) != 0);
+
+ /* Use of PC is UNPREDICTABLE. */
+ if (inst.operands[1].reg == REG_PC)
+ inst.error = _("Use of PC here is UNPREDICTABLE");
+
+ if (inst.operands[1].immisreg)
+ inst.error = _("instruction does not accept register index");
+
+ if (!inst.operands[1].isreg)
+ inst.error = _("instruction does not accept PC-relative addressing");
+
+ if (abs (inst.operands[1].imm) >= (1 << 7))
+ inst.error = _("immediate value out of range");
+
+ inst.instruction = 0xec000f80;
+ if (is_vldr)
+ inst.instruction |= 1 << sysreg_vldr_bitno;
+ encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM);
+ inst.instruction |= (inst.operands[0].imm & 0x7) << 13;
+ inst.instruction |= (inst.operands[0].imm & 0x8) << 19;
+}
+
+static void
+do_vldr_vstr (void)
+{
+ bfd_boolean sysreg_op = !inst.operands[0].isreg;
+
+ /* VLDR/VSTR (System Register). */
+ if (sysreg_op)
+ {
+ if (!mark_feature_used (&arm_ext_v8_1m_main))
+ as_bad (_("Instruction not permitted on this architecture"));
+
+ do_t_vldr_vstr_sysreg ();
+ }
+ /* VLDR/VSTR. */
+ else
+ {
+ if (!mark_feature_used (&fpu_vfp_ext_v1xd))
+ as_bad (_("Instruction not permitted on this architecture"));
+ do_neon_ldr_str ();
+ }
+}
+
/* "interleave" version also handles non-interleaving register VLD1/VST1
instructions. */
@@ -21284,8 +21378,6 @@ static const struct asm_opcode insns[] =
NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
- NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
- NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
@@ -21297,6 +21389,15 @@ static const struct asm_opcode insns[] =
NCE(vmov, 0, 1, (VMOV), neon_mov),
NCE(vmovq, 0, 1, (VMOV), neon_mov),
+#undef THUMB_VARIANT
+/* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
+ by different feature bits. Since we are setting the Thumb guard, we can
+ require Thumb-1 which makes it a nop guard and set the right feature bit in
+ do_vldr_vstr (). */
+#define THUMB_VARIANT & arm_ext_v4t
+ NCE(vldr, d100b00, 2, (VLDR, ADDRGLDC), vldr_vstr),
+ NCE(vstr, d000b00, 2, (VLDR, ADDRGLDC), vldr_vstr),
+
#undef ARM_VARIANT
#define ARM_VARIANT & arm_ext_fp16
#undef THUMB_VARIANT
@@ -24548,6 +24649,7 @@ md_apply_fix (fixS * fixP,
case BFD_RELOC_ARM_CP_OFF_IMM:
case BFD_RELOC_ARM_T32_CP_OFF_IMM:
+ case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM:
if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM)
newval = md_chars_to_number (buf, INSN_SIZE);
else
@@ -24561,6 +24663,12 @@ md_apply_fix (fixS * fixP,
as_bad_where (fixP->fx_file, fixP->fx_line,
_("co-processor offset out of range"));
}
+ else if ((newval & 0xfe001f80) == 0xec000f80)
+ {
+ if (value < -511 || value > 512 || (value & 3))
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("co-processor offset out of range"));
+ }
else if (value < -1023 || value > 1023 || (value & 3))
as_bad_where (fixP->fx_file, fixP->fx_line,
_("co-processor offset out of range"));
@@ -24574,10 +24682,18 @@ md_apply_fix (fixS * fixP,
else
newval = get_thumb32_insn (buf);
if (value == 0)
- newval &= 0xffffff00;
+ {
+ if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM)
+ newval &= 0xffffff80;
+ else
+ newval &= 0xffffff00;
+ }
else
{
- newval &= 0xff7fff00;
+ if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM)
+ newval &= 0xff7fff80;
+ else
+ newval &= 0xff7fff00;
if ((newval & 0x0f200f00) == 0x0d000900)
{
/* This is a fp16 vstr/vldr.
diff --git a/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.l b/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.l
index b64937d27f2af469daac5e3feb9167dccde0a986..979982dd9f3bc2059ea059db37dd655c4140b8f5 100644
--- a/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.l
+++ b/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.l
@@ -6,3 +6,11 @@
[^:]*:11: Error: VPR expected last -- `vscclrm {s0}'
[^:]*:12: Error: VFP single precision register or VPR expected -- `vscclrm {s1,d1,VPR}'
[^:]*:13: Error: VFP single precision register expected -- `vscclrm {s1-d1,VPR}'
+[^:]*:15: Error: syntax error -- `vldr APSR,\[r2\]'
+[^:]*:20: Error: syntax error -- `vstr APSR,\[r2\]'
+[^:]*:16: Error: co-processor offset out of range
+[^:]*:17: Error: co-processor offset out of range
+[^:]*:18: Error: co-processor offset out of range
+[^:]*:21: Error: co-processor offset out of range
+[^:]*:22: Error: co-processor offset out of range
+[^:]*:23: Error: co-processor offset out of range
diff --git a/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.s b/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.s
index f4baefe73f84a0c93a9ab992b80a9f0b3644d051..894e8b2b8f03cef09bfe33dcf238af68fb07f95d 100644
--- a/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.s
+++ b/gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.s
@@ -11,3 +11,13 @@ vscclrm {} @ Rejects empty list
vscclrm {s0} @ Rejects list without VPR
vscclrm {s1, d1, VPR} @ Reject mix of single and double-precision VFP registers
vscclrm {s1-d1, VPR} @ Likewise when using a range
+
+vldr APSR, [r2] @ Rejects incorrect system register
+vldr FPSCR, [r2, #2] @ Rejects invalid immediate for offset variant
+vldr FPSCR, [r2, #2]! @ Likewise for pre-index variant
+vldr FPSCR, [r2], #2 @ Likewise for post-index variant
+
+vstr APSR, [r2] @ Rejects incorrect system register
+vstr FPSCR, [r2, #2] @ Rejects invalid immediate for offset variant
+vstr FPSCR, [r2, #2]! @ Likewise for pre-index variant
+vstr FPSCR, [r2], #2 @ Likewise for post-index variant
diff --git a/gas/testsuite/gas/arm/archv8m_1m-cmse-main.d b/gas/testsuite/gas/arm/archv8m_1m-cmse-main.d
index 866adc9cb0db7a8c0f6061c3829ac07f3d5233f3..1ed543a04e8602a0c6dfed28c0ec6ae455722af0 100644
--- a/gas/testsuite/gas/arm/archv8m_1m-cmse-main.d
+++ b/gas/testsuite/gas/arm/archv8m_1m-cmse-main.d
@@ -20,4 +20,38 @@ Disassembly of section .text:
0+.* <[^>]*> ec9f 0b20 vscclrm {d0-d15, VPR}
0+.* <[^>]*> bf18 it ne
0+.* <[^>]*> ecdf 1a01 vscclrmne {s3, VPR}
+0+.* <[^>]*> ed92 2f80 vldr FPSCR, \[r2\]
+0+.* <[^>]*> ed92 2f82 vldr FPSCR, \[r2, #8\]
+0+.* <[^>]*> ed92 2f82 vldr FPSCR, \[r2, #8\]
+0+.* <[^>]*> ed12 2f82 vldr FPSCR, \[r2, #-8\]
+0+.* <[^>]*> edb2 2f82 vldr FPSCR, \[r2, #8\]!
+0+.* <[^>]*> edb2 2f82 vldr FPSCR, \[r2, #8\]!
+0+.* <[^>]*> ed32 2f82 vldr FPSCR, \[r2, #-8\]!
+0+.* <[^>]*> ecb2 2f82 vldr FPSCR, \[r2\], #8
+0+.* <[^>]*> ecb2 2f82 vldr FPSCR, \[r2\], #8
+0+.* <[^>]*> ec32 2f82 vldr FPSCR, \[r2\], #-8
+0+.* <[^>]*> ed93 4f80 vldr FPSCR_nzcvqc, \[r3\]
+0+.* <[^>]*> edd3 8f80 vldr VPR, \[r3\]
+0+.* <[^>]*> edd3 af80 vldr P0, \[r3\]
+0+.* <[^>]*> edd3 cf80 vldr FPCXTNS, \[r3\]
+0+.* <[^>]*> edd3 ef80 vldr FPCXTS, \[r3\]
+0+.* <[^>]*> bfa8 it ge
+0+.* <[^>]*> edd3 ef80 vldrge FPCXTS, \[r3\]
+0+.* <[^>]*> ed82 2f80 vstr FPSCR, \[r2\]
+0+.* <[^>]*> ed82 2f82 vstr FPSCR, \[r2, #8\]
+0+.* <[^>]*> ed82 2f82 vstr FPSCR, \[r2, #8\]
+0+.* <[^>]*> ed02 2f82 vstr FPSCR, \[r2, #-8\]
+0+.* <[^>]*> eda2 2f82 vstr FPSCR, \[r2, #8\]!
+0+.* <[^>]*> eda2 2f82 vstr FPSCR, \[r2, #8\]!
+0+.* <[^>]*> ed22 2f82 vstr FPSCR, \[r2, #-8\]!
+0+.* <[^>]*> eca2 2f82 vstr FPSCR, \[r2\], #8
+0+.* <[^>]*> eca2 2f82 vstr FPSCR, \[r2\], #8
+0+.* <[^>]*> ec22 2f82 vstr FPSCR, \[r2\], #-8
+0+.* <[^>]*> ed83 4f80 vstr FPSCR_nzcvqc, \[r3\]
+0+.* <[^>]*> edc3 8f80 vstr VPR, \[r3\]
+0+.* <[^>]*> edc3 af80 vstr P0, \[r3\]
+0+.* <[^>]*> edc3 cf80 vstr FPCXTNS, \[r3\]
+0+.* <[^>]*> edc3 ef80 vstr FPCXTS, \[r3\]
+0+.* <[^>]*> bfa8 it ge
+0+.* <[^>]*> edc3 ef80 vstrge FPCXTS, \[r3\]
#...
diff --git a/gas/testsuite/gas/arm/archv8m_1m-cmse-main.s b/gas/testsuite/gas/arm/archv8m_1m-cmse-main.s
index f4df2dbb2f7666c4c762a9b62463d809ba91577e..9a20e1e4fe7ab1e497d83da13f288f1efcfc6a0c 100644
--- a/gas/testsuite/gas/arm/archv8m_1m-cmse-main.s
+++ b/gas/testsuite/gas/arm/archv8m_1m-cmse-main.s
@@ -18,3 +18,37 @@ vscclrm {s0-s31, VPR} @ Accept all single-precision VFP registers and VPR
@ together
vscclrm {d0-d15, VPR} @ Likewise for double-precision VFP registers
vscclrmne {s3, VPR} @ Accepts conditional execution
+
+vldr FPSCR, [r2] @ Accepts offset variant without immediate
+vldr FPSCR, [r2, #8] @ Likewise but with immediate without sign
+vldr FPSCR, [r2, #+8] @ Likewise but with positive sign
+vldr FPSCR, [r2, #-8] @ Likewise but with negative sign
+vldr FPSCR, [r2, #8]! @ Accepts pre-index variant with immediate without sign
+vldr FPSCR, [r2, #+8]! @ Likewise but with positive sign
+vldr FPSCR, [r2, #-8]! @ Likewise but with negative sign
+vldr FPSCR, [r2], #8 @ Accepts post-index variant with immediate without sign
+vldr FPSCR, [r2], #+8 @ Likewise but with positive sign
+vldr FPSCR, [r2], #-8 @ Likewise but with negative sign
+vldr FPSCR_nzcvqc, [r3] @ Accepts FPSCR_nzcvqc system register
+vldr VPR, [r3] @ Accepts VPR system register
+vldr P0, [r3] @ Accepts P0 system register
+vldr FPCXTNS, [r3] @ Accepts FPCXTNS system register
+vldr FPCXTS, [r3] @ Accepts FPCXTS system register
+vldrge FPCXTS, [r3] @ Accepts conditional execution
+
+vstr FPSCR, [r2] @ Accepts offset variant without immediate
+vstr FPSCR, [r2, #8] @ Likewise but with immediate without sign
+vstr FPSCR, [r2, #+8] @ Likewise but with positive sign
+vstr FPSCR, [r2, #-8] @ Likewise but with negative sign
+vstr FPSCR, [r2, #8]! @ Accepts pre-index variant with immediate without sign
+vstr FPSCR, [r2, #+8]! @ Likewise but with positive sign
+vstr FPSCR, [r2, #-8]! @ Likewise but with negative sign
+vstr FPSCR, [r2], #8 @ Accepts post-index variant with immediate without sign
+vstr FPSCR, [r2], #+8 @ Likewise but with positive sign
+vstr FPSCR, [r2], #-8 @ Likewise but with negative sign
+vstr FPSCR_nzcvqc, [r3] @ Accepts FPSCR_nzcvqc system register
+vstr VPR, [r3] @ Accepts VPR system register
+vstr P0, [r3] @ Accepts P0 system register
+vstr FPCXTNS, [r3] @ Accepts FPCXTNS system register
+vstr FPCXTS, [r3] @ Accepts FPCXTS system register
+vstrge FPCXTS, [r3] @ Accepts conditional execution
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index cf11e616eaa50acdc546adfd9c92740770b27177..6a02ad0b3d92903a03b5d2e6b49c0a1b643f5008 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -112,6 +112,8 @@ struct opcode16
%B print vstm/vldm register list
%C print vscclrm register list
%I print cirrus signed shift immediate: bits 0..3|4..6
+ %J print register for VLDR instruction
+ %K print address for VLDR instruction
%F print the COUNT field of a LFM/SFM instruction.
%P print floating point precision in arithmetic insn
%Q print floating point precision in ldf/stf insn
@@ -472,6 +474,10 @@ static const struct sopcode32 coprocessor_opcodes[] =
0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
+ {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
+ 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
+ {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
+ 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
@@ -3463,6 +3469,8 @@ print_insn_coprocessor (bfd_vma pc,
int cp_num;
struct arm_private_data *private_data = info->private_data;
arm_feature_set allowed_arches = ARM_ARCH_NONE;
+ arm_feature_set arm_ext_v8_1m_main =
+ ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
allowed_arches = private_data->features;
@@ -3558,23 +3566,34 @@ print_insn_coprocessor (bfd_vma pc,
/* Floating-point instructions. */
if (cp_num == 9 || cp_num == 10 || cp_num == 11)
continue;
+
+ /* Armv8.1-M Mainline FP & MVE instructions. */
+ if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
+ && !ARM_CPU_IS_ANY (allowed_arches)
+ && (cp_num == 8 || cp_num == 14 || cp_num == 15))
+ continue;
}
for (c = insn->assembler; *c; c++)
{
if (*c == '%')
{
- switch (*++c)
+ const char mod = *++c;
+ switch (mod)
{
case '%':
func (stream, "%%");
break;
case 'A':
+ case 'K':
{
int rn = (given >> 16) & 0xf;
bfd_vma offset = given & 0xff;
+ if (mod == 'K')
+ offset = given & 0x7f;
+
func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
if (PRE_BIT_SET || WRITEBACK_BIT_SET)
@@ -3706,6 +3725,37 @@ print_insn_coprocessor (bfd_vma pc,
break;
+ case 'J':
+ {
+ int regno = ((given >> 19) & 0x8) | ((given >> 13) & 0x7);
+
+ switch (regno)
+ {
+ case 0x1:
+ func (stream, "FPSCR");
+ break;
+ case 0x2:
+ func (stream, "FPSCR_nzcvqc");
+ break;
+ case 0xc:
+ func (stream, "VPR");
+ break;
+ case 0xd:
+ func (stream, "P0");
+ break;
+ case 0xe:
+ func (stream, "FPCXTNS");
+ break;
+ case 0xf:
+ func (stream, "FPCXTS");
+ break;
+ default:
+ func (stream, "<invalid reg %d>", regno);
+ break;
+ }
+ }
+ break;
+
case 'F':
switch (given & 0x00408000)
{
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline
2019-04-04 13:24 [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Andre Vieira (lists)
` (15 preceding siblings ...)
2019-04-04 13:44 ` [PATCH, binutils, ARM, 15/16] Add support for VSCCLRM Andre Vieira (lists)
@ 2019-04-11 10:04 ` Nick Clifton
2019-04-12 10:39 ` Andre Vieira (lists)
16 siblings, 1 reply; 32+ messages in thread
From: Nick Clifton @ 2019-04-11 10:04 UTC (permalink / raw)
To: Andre Vieira (lists), binutils
Hi Andre,
> This is a patch series to implement support for Armv8.1-M Mainline. The specifications for the Armv8.1-M Mainline can be found in https://developer.arm.com/docs/ddi0553/latest
The patch series looks fine to me, apart from two small problems:
1) It introduces some assembler testsuite failures for non-ELF based
ARM toolchains:
Checking Binutils in: arm-wince-pe ...
GAS REGRESSION: Valid Armv8.1-M Mainline BF instruction
GAS REGRESSION: Valid Armv8.1-M Mainline BFCSEL instruction
GAS REGRESSION: Valid Armv8.1-M Mainline BFL instruction
GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
GAS REGRESSION: Valid Armv8.1-M Mainline BF instruction
GAS REGRESSION: Valid Armv8.1-M Mainline BFCSEL instruction
GAS REGRESSION: Valid Armv8.1-M Mainline BFL instruction
GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
GAS REGRESSION: Valid Armv8.1-M Mainline BF instruction
GAS REGRESSION: Valid Armv8.1-M Mainline BFCSEL instruction
GAS REGRESSION: Valid Armv8.1-M Mainline BFL instruction
GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
GAS REGRESSION: Valid Armv8.1-M Mainline BF instruction
GAS REGRESSION: Valid Armv8.1-M Mainline BFCSEL instruction
GAS REGRESSION: Valid Armv8.1-M Mainline BFL instruction
GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
2) It introduces some assembler and linker testsuite failures for
big-endian ARM toolchains:
Checking Binutils in: armeb-eabi ...
GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
LD REGRESSION: Armv8.1-M Mainline BF
LD REGRESSION: Armv8.1-M Mainline BFL
LD REGRESSION: Armv8.1-M Mainline BFCSEL
LD REGRESSION: Armv8.1-M Mainline BF
LD REGRESSION: Armv8.1-M Mainline BFL
LD REGRESSION: Armv8.1-M Mainline BFCSEL
LD REGRESSION: Armv8.1-M Mainline BF
LD REGRESSION: Armv8.1-M Mainline BFL
LD REGRESSION: Armv8.1-M Mainline BFCSEL
LD REGRESSION: Armv8.1-M Mainline BF
LD REGRESSION: Armv8.1-M Mainline BFL
LD REGRESSION: Armv8.1-M Mainline BFCSEL
Would you mind taking a look at these please ?
Cheers
Nick
PS. This was from testing with the entire patch series applied.
I have not narrowed down the specific patches that introduce the
new failures, but I assume that it will be simple for you to do
this yourself.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH, binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M Mainline
2019-04-04 13:41 ` [PATCH, binutils, ARM, 11/16] New BFCSEL instruction " Andre Vieira (lists)
@ 2019-04-12 10:39 ` Andre Vieira (lists)
0 siblings, 0 replies; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-12 10:39 UTC (permalink / raw)
To: binutils; +Cc: nickc
[-- Attachment #1: Type: text/plain, Size: 2999 bytes --]
Hi,
Fixed some testisms highlighted by Nick.
This OK?
*** bfd/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation.
* bfd-in2.h: Regenerated.
* libbfd.h: Likewise.
*** gas/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (T16_32_TAB): New entriy for bfcsel.
(do_t_v8_1_branch): New switch case for bfcsel.
(toU): Define.
(insns): New instruction for bfcsel.
(md_pcrel_from_section): New switch case
for BFD_RELOC_THUMB_PCREL_BFCSEL.
(md_appdy_fix): Likewise
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/armv8_1-m-bfcsel.d: New.
* testsuite/gas/arm/armv8_1-m-bfcsel.s: New.
*** ld/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bfcsel.s: New.
* testsuite/ld-arm/bfcsel.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instruction bfcsel.
(print_insn_thumb32): Edit the switch case for %Z.
On 04/04/2019 14:41, Andre Vieira (lists) wrote:
> Hi
>
> This patch is part of a series of patches to add support for Armv8.1-M
> Mainline instructions to binutils.
>
> This patch adds the BFCSEL instruction. It also adds a local relocation
> with a new bfd_reloc_code_real enum.
> Testing: Added new test for the valid instruction operands. Testsuite
> shows no regression when run for arm-none-eabi targets.
>
> Thanks
> Sudi
>
>
> ChangeLog entries are as follows :
>
> *** bfd/ChangeLog ***
>
> 2019-04-04 Sudakshina Das <sudi.das@arm.com>
>
> Â Â Â Â * reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation.
> Â Â Â Â * bfd-in2.h: Regenerated.
> Â Â Â Â * libbfd.h: Likewise.
>
> *** gas/ChangeLog ***
>
> 2019-04-04 Sudakshina Das <sudi.das@arm.com>
>
> Â Â Â Â * config/tc-arm.c (T16_32_TAB): New entriy for bfcsel.
> Â Â Â Â (do_t_v8_1_branch): New switch case for bfcsel.
> Â Â Â Â (toU): Define.
> Â Â Â Â (insns): New instruction for bfcsel.
> Â Â Â Â (md_pcrel_from_section): New switch case
> Â Â Â Â for BFD_RELOC_THUMB_PCREL_BFCSEL.
> Â Â Â Â (md_appdy_fix): Likewise
> Â Â Â Â (tc_gen_reloc): Likewise.
> Â Â Â Â * testsuite/gas/arm/armv8_1-m-bfcsel.d: New.
> Â Â Â Â * testsuite/gas/arm/armv8_1-m-bfcsel.s: New.
>
> *** ld/ChangeLog ***
>
> 2019-04-04 Sudakshina Das <sudi.das@arm.com>
>
> Â Â Â Â * testsuite/ld-arm/bfcsel.s: New.
> Â Â Â Â * testsuite/ld-arm/bfcsel.d: New.
> Â Â Â Â * testsuite/ld-arm/arm-elf.exp: Add above test.
>
> *** opcodes/ChangeLog ***
>
> 2019-04-04 Sudakshina Das <sudi.das@arm.com>
>
> Â Â Â Â * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
> Â Â Â Â (print_insn_thumb32): Edit the switch case for %Z.
[-- Attachment #2: 11.patch --]
[-- Type: text/x-patch, Size: 10450 bytes --]
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 95d66b586d608ea397121f9124f24b0f2e9a9307..4a3fa75867c814f082ba3ab3079cf60c30ad2b62 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -3567,6 +3567,9 @@ field in the instruction. */
/* ARM 5-bit pc-relative branch for Branch Future instructions. */
BFD_RELOC_THUMB_PCREL_BRANCH5,
+/* ARM 6-bit pc-relative branch for BFCSEL instruction. */
+ BFD_RELOC_THUMB_PCREL_BFCSEL,
+
/* ARM 17-bit pc-relative branch for Branch Future instructions. */
BFD_RELOC_ARM_THUMB_BF17,
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index b3d71d976a437454593dde7afb7c0d8e368c56ca..32080db8c3f6141ae9aa9674c8776694db29905a 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -1530,6 +1530,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_ARM_PCREL_CALL",
"BFD_RELOC_ARM_PCREL_JUMP",
"BFD_RELOC_THUMB_PCREL_BRANCH5",
+ "BFD_RELOC_THUMB_PCREL_BFCSEL",
"BFD_RELOC_ARM_THUMB_BF17",
"BFD_RELOC_ARM_THUMB_BF13",
"BFD_RELOC_ARM_THUMB_BF19",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index c41b2fe75d10e9441cd38861b2f6f02f546f6a64..c0e413cd19dbfaf5100143c8879d84cb63ba4a17 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -3019,6 +3019,11 @@ ENUM
ENUMDOC
ARM 5-bit pc-relative branch for Branch Future instructions.
+ENUM
+ BFD_RELOC_THUMB_PCREL_BFCSEL
+ENUMDOC
+ ARM 6-bit pc-relative branch for BFCSEL instruction.
+
ENUM
BFD_RELOC_ARM_THUMB_BF17
ENUMDOC
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 5d7f2c0a6d4d7834038b92d6c4256cee7e69ed4c..5e59078890752b0580ae443c7b330e32baecccf6 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -10506,6 +10506,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
X(_b, e000, f000b000), \
X(_bcond, d000, f0008000), \
X(_bf, 0000, f040e001), \
+ X(_bfcsel,0000, f000e001), \
X(_bfx, 0000, f060e001), \
X(_bfl, 0000, f000c001), \
X(_bflx, 0000, f070e001), \
@@ -13384,6 +13385,46 @@ do_t_branch_future (void)
}
break;
+ case T_MNEM_bfcsel:
+ /* Operand 1. */
+ if (inst.operands[1].hasreloc == 0)
+ {
+ int val = inst.operands[1].imm;
+ int immA = (val & 0x00001000) >> 12;
+ int immB = (val & 0x00000ffc) >> 2;
+ int immC = (val & 0x00000002) >> 1;
+ inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
+ }
+ else
+ {
+ inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF13;
+ inst.relocs[1].pc_rel = 1;
+ }
+
+ /* Operand 2. */
+ if (inst.operands[2].hasreloc == 0)
+ {
+ constraint ((inst.operands[0].hasreloc != 0), BAD_ARGS);
+ int val2 = inst.operands[2].imm;
+ int val0 = inst.operands[0].imm & 0x1f;
+ int diff = val2 - val0;
+ if (diff == 4)
+ inst.instruction |= 1 << 17; /* T bit. */
+ else if (diff != 2)
+ as_bad (_("out of range label-relative fixup value"));
+ }
+ else
+ {
+ constraint ((inst.operands[0].hasreloc == 0), BAD_ARGS);
+ inst.relocs[2].type = BFD_RELOC_THUMB_PCREL_BFCSEL;
+ inst.relocs[2].pc_rel = 1;
+ }
+
+ /* Operand 3. */
+ constraint (inst.cond != COND_ALWAYS, BAD_COND);
+ inst.instruction |= (inst.operands[3].imm & 0xf) << 18;
+ break;
+
case T_MNEM_bfx:
case T_MNEM_bflx:
inst.instruction |= inst.operands[1].reg << 16;
@@ -19616,6 +19657,11 @@ static struct asm_barrier_opt barrier_opt_names[] =
{ mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
do_##te }
+/* T_MNEM_xyz enumerator variants of ToU. */
+#define toU(mnem, top, nops, ops, te) \
+ { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
+ NULL, do_##te }
+
/* Legacy mnemonics that always have conditional infix after the third
character. */
#define CL(mnem, op, nops, ops, ae) \
@@ -21706,6 +21752,7 @@ static const struct asm_opcode insns[] =
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_v8_1m_main
toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
+ toU("bfcsel", _bfcsel, 4, (EXPs, EXPs, EXPs, COND), t_branch_future),
toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future),
toC("bfl", _bfl, 2, (EXPs, EXPs), t_branch_future),
toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future),
@@ -21741,6 +21788,7 @@ static const struct asm_opcode insns[] =
#undef ToC
#undef toC
#undef ToU
+#undef toU
\f
/* MD interface: bits in the object file. */
@@ -22944,6 +22992,7 @@ md_pcrel_from_section (fixS * fixP, segT seg)
case BFD_RELOC_THUMB_PCREL_BRANCH12:
case BFD_RELOC_THUMB_PCREL_BRANCH20:
case BFD_RELOC_THUMB_PCREL_BRANCH25:
+ case BFD_RELOC_THUMB_PCREL_BFCSEL:
case BFD_RELOC_ARM_THUMB_BF17:
case BFD_RELOC_ARM_THUMB_BF19:
case BFD_RELOC_ARM_THUMB_BF13:
@@ -24844,6 +24893,39 @@ md_apply_fix (fixS * fixP,
}
break;
+ case BFD_RELOC_THUMB_PCREL_BFCSEL:
+ if (fixP->fx_addsy
+ && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
+ && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && ARM_IS_FUNC (fixP->fx_addsy)
+ && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
+ {
+ fixP->fx_done = 0;
+ }
+ if ((value & ~0x7f) && ((value & ~0x3f) != ~0x3f))
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("branch out of range"));
+
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ newval = md_chars_to_number (buf, THUMB_SIZE);
+
+ addressT boff = ((newval & 0x0780) >> 7) << 1;
+ addressT diff = value - boff;
+
+ if (diff == 4)
+ {
+ newval |= 1 << 1; /* T bit. */
+ }
+ else if (diff != 2)
+ {
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("out of range label-relative fixup value"));
+ }
+ md_number_to_chars (buf, newval, THUMB_SIZE);
+ }
+ break;
+
case BFD_RELOC_ARM_THUMB_BF17:
if (fixP->fx_addsy
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
@@ -25158,6 +25240,7 @@ tc_gen_reloc (asection *section, fixS *fixp)
return NULL;
case BFD_RELOC_THUMB_PCREL_BRANCH5:
+ case BFD_RELOC_THUMB_PCREL_BFCSEL:
as_bad_where (fixp->fx_file, fixp->fx_line,
_("%s used for a symbol not defined in the same file"),
bfd_get_reloc_code_name (fixp->fx_r_type));
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d b/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d
new file mode 100644
index 0000000000000000000000000000000000000000..a498f06cd3e68370b737976ac3453855852f5b58
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d
@@ -0,0 +1,12 @@
+#name: Valid Armv8.1-M Mainline BFCSEL instruction
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f080 e803 bfcsel 2, 0000000a <foo\+0xa>, 4, eq
+0[0-9a-f]+ <[^>]+> 4609 mov r1, r1
+0[0-9a-f]+ <[^>]+> d000 beq.n 0000000a <foo\+0xa>
+0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
+0[0-9a-f]+ <[^>]+> 4614 mov r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfcsel.s b/gas/testsuite/gas/arm/armv8_1-m-bfcsel.s
new file mode 100644
index 0000000000000000000000000000000000000000..07903ba5f0d282e865e383b32982ca178e1daa2b
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfcsel.s
@@ -0,0 +1,12 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+ bfcsel .LB1, .LBranch, .LB2, eq
+ mov r1, r1
+.LB1:
+ beq .LBranch
+.LB2:
+ mov r3, r2
+.LBranch:
+ mov r4, r2
diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp
index 528565e97bee829c193ad54ab21e2f9a7071a718..5471895e63a68c0ee5e9c9644564e7b9235a4184 100644
--- a/ld/testsuite/ld-arm/arm-elf.exp
+++ b/ld/testsuite/ld-arm/arm-elf.exp
@@ -673,6 +673,9 @@ set armeabitests_nonacl {
{"Armv8.1-M Mainline BFL" "-r -Ttext 0x1000 --section-start .foo=0x1001000" "" "-march=armv8.1-m.main" {bfl.s}
{{objdump -dr bfl.d}}
"bfl"}
+ {"Armv8.1-M Mainline BFCSEL" "-r -Ttext 0x1000 --section-start .foo=0x1001000" "" "-march=armv8.1-m.main" {bfcsel.s}
+ {{objdump -dr bfcsel.d}}
+ "bfcsel"}
{"R_ARM_THM_JUMP24 Relocation veneers: Short 1"
"--no-fix-arm1176 --section-start destsect=0x00009000 --section-start .text=0x8000" ""
diff --git a/ld/testsuite/ld-arm/bfcsel.d b/ld/testsuite/ld-arm/bfcsel.d
new file mode 100644
index 0000000000000000000000000000000000000000..914ea93cec431126613bf6326f1446482fba95e0
--- /dev/null
+++ b/ld/testsuite/ld-arm/bfcsel.d
@@ -0,0 +1,18 @@
+
+.*: file format elf32-.*arm
+
+
+Disassembly of section .text:
+
+00001000 <_start>:
+ 1000: f101 e7ff bfcsel 4, 1001000 <bar>, 6, eq
+ 1000: R_ARM_THM_BF12 bar
+ 1004: 4623 mov r3, r4
+ 1006: 4611 mov r1, r2
+ 1008: d0ff beq.n 100a <_start\+0xa>
+ 100a: 4613 mov r3, r2
+
+Disassembly of section .foo:
+
+01001000 <bar>:
+ 1001000: 4770 bx lr
diff --git a/ld/testsuite/ld-arm/bfcsel.s b/ld/testsuite/ld-arm/bfcsel.s
new file mode 100644
index 0000000000000000000000000000000000000000..675e2ea1ae28b64663cd02411550670112dd91a2
--- /dev/null
+++ b/ld/testsuite/ld-arm/bfcsel.s
@@ -0,0 +1,25 @@
+ .global _start
+ .syntax unified
+
+@ We will place the section .text at 0x1000.
+
+ .text
+ .thumb_func
+
+_start:
+ bfcsel .LB1, bar, .LB2, eq
+ mov r3, r4
+ mov r1, r2
+.LB1:
+ beq .LB2
+.LB2:
+ mov r3, r2
+
+@ We will place the section .foo at 0x1001000.
+
+ .section .foo, "xa"
+ .thumb_func
+
+bar:
+ bx lr
+
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index f53afc584cfdd271fde85d86ecab219a87c77bd3..b4865c1a42a04bb6a9b156d7369c065ca351efb4 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2759,6 +2759,8 @@ static const struct opcode32 thumb32_opcodes[] =
0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
/* ARMv8-M and ARMv8-M Security Extensions instructions. */
@@ -5934,6 +5936,12 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
info->print_address_func (pc + 4 + offset, info);
+
+ unsigned int T = (given & 0x00020000u) >> 17;
+ unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
+ unsigned int boffset = (T == 1) ? 4 : 2;
+ func (stream, ", ");
+ func (stream, "%x", endoffset + boffset);
}
break;
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline
2019-04-11 10:04 ` [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Nick Clifton
@ 2019-04-12 10:39 ` Andre Vieira (lists)
2019-04-12 13:51 ` Nick Clifton
0 siblings, 1 reply; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-12 10:39 UTC (permalink / raw)
To: Nick Clifton, binutils
Hi Nick,
Thanks for that! Most of them were testisms. Though there was an actual
issue with big-endian and the LE instruction. I replied to each
relevant patch with an updated version.
Cheers,
Andre
On 11/04/2019 11:04, Nick Clifton wrote:
> Hi Andre,
>
>> This is a patch series to implement support for Armv8.1-M Mainline. The specifications for the Armv8.1-M Mainline can be found in https://developer.arm.com/docs/ddi0553/latest
>
> The patch series looks fine to me, apart from two small problems:
>
> 1) It introduces some assembler testsuite failures for non-ELF based
> ARM toolchains:
>
> Checking Binutils in: arm-wince-pe ...
> GAS REGRESSION: Valid Armv8.1-M Mainline BF instruction
> GAS REGRESSION: Valid Armv8.1-M Mainline BFCSEL instruction
> GAS REGRESSION: Valid Armv8.1-M Mainline BFL instruction
> GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
> GAS REGRESSION: Valid Armv8.1-M Mainline BF instruction
> GAS REGRESSION: Valid Armv8.1-M Mainline BFCSEL instruction
> GAS REGRESSION: Valid Armv8.1-M Mainline BFL instruction
> GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
> GAS REGRESSION: Valid Armv8.1-M Mainline BF instruction
> GAS REGRESSION: Valid Armv8.1-M Mainline BFCSEL instruction
> GAS REGRESSION: Valid Armv8.1-M Mainline BFL instruction
> GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
> GAS REGRESSION: Valid Armv8.1-M Mainline BF instruction
> GAS REGRESSION: Valid Armv8.1-M Mainline BFCSEL instruction
> GAS REGRESSION: Valid Armv8.1-M Mainline BFL instruction
> GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
>
> 2) It introduces some assembler and linker testsuite failures for
> big-endian ARM toolchains:
>
> Checking Binutils in: armeb-eabi ...
> GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
> GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
> GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
> GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
> LD REGRESSION: Armv8.1-M Mainline BF
> LD REGRESSION: Armv8.1-M Mainline BFL
> LD REGRESSION: Armv8.1-M Mainline BFCSEL
> LD REGRESSION: Armv8.1-M Mainline BF
> LD REGRESSION: Armv8.1-M Mainline BFL
> LD REGRESSION: Armv8.1-M Mainline BFCSEL
> LD REGRESSION: Armv8.1-M Mainline BF
> LD REGRESSION: Armv8.1-M Mainline BFL
> LD REGRESSION: Armv8.1-M Mainline BFCSEL
> LD REGRESSION: Armv8.1-M Mainline BF
> LD REGRESSION: Armv8.1-M Mainline BFL
> LD REGRESSION: Armv8.1-M Mainline BFCSEL
>
> Would you mind taking a look at these please ?
>
> Cheers
> Nick
>
> PS. This was from testing with the entire patch series applied.
> I have not narrowed down the specific patches that introduce the
> new failures, but I assume that it will be simple for you to do
> this yourself.
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH, binutils, ARM, 9/16] New BFL instruction for Armv8.1-M Mainline
2019-04-04 13:39 ` [PATCH, binutils, ARM, 9/16] New BFL instruction for Armv8.1-M Mainline Andre Vieira (lists)
@ 2019-04-12 10:40 ` Andre Vieira (lists)
0 siblings, 0 replies; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-12 10:40 UTC (permalink / raw)
To: binutils; +Cc: nickc
[-- Attachment #1: Type: text/plain, Size: 2385 bytes --]
Hi,
Fixed some testisms highlighted by Nick.
This OK?
*** gas/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (T16_32_TAB): New entrie for bfl.
(do_t_v8_1_branch): New switch case for bfl.
(insns): New instruction for bfl.
* testsuite/gas/arm/armv8_1-m-bfl.d: New.
* testsuite/gas/arm/armv8_1-m-bfl.s: New.
* testsuite/gas/arm/armv8_1-m-bfl-bad.s: New.
* testsuite/gas/arm/armv8_1-m-bfl-bad.d: New.
* testsuite/gas/arm/armv8_1-m-bfl-bad.l: New.
* testsuite/gas/arm/armv8_1-m-bfl-rel.d: New.
* testsuite/gas/arm/armv8_1-m-bfl-rel.s: New.
*** ld/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bfl.s: New.
* testsuite/ld-arm/bfl.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instruction bfl.
On 04/04/2019 14:39, Andre Vieira (lists) wrote:
> Hi
>
> This patch is part of a series of patches to add support for Armv8.1-M
> Mainline instructions to binutils.
>
> This patch adds the BFL instruction.
>
> Testing: Added new test for the valid and invalid instruction operands.
> Testsuite shows no regression when run for arm-none-eabi targets.
>
> Thanks
> Sudi
>
>
> ChangeLog entries are as follows :
>
> *** gas/ChangeLog ***
>
> 2019-04-04 Sudakshina Das <sudi.das@arm.com>
>
> Â Â Â Â * config/tc-arm.c (T16_32_TAB): New entrie for bfl.
> Â Â Â Â (do_t_v8_1_branch): New switch case for bfl.
> Â Â Â Â (insns): New instruction for bfl.
> Â Â Â Â * testsuite/gas/arm/armv8_1-m-bfl.d: New.
> Â Â Â Â * testsuite/gas/arm/armv8_1-m-bfl.s: New.
> Â Â Â Â * testsuite/gas/arm/armv8_1-m-bfl-bad.s: New.
> Â Â Â Â * testsuite/gas/arm/armv8_1-m-bfl-bad.d: New.
> Â Â Â Â * testsuite/gas/arm/armv8_1-m-bfl-bad.l: New.
>
> *** ld/ChangeLog ***
>
> 2019-04-04 Sudakshina Das <sudi.das@arm.com>
>
> Â Â Â Â * testsuite/ld-arm/bfl.s: New.
> Â Â Â Â * testsuite/ld-arm/bfl.d: New.
> Â Â Â Â * testsuite/ld-arm/arm-elf.exp: Add above test.
>
> *** opcodes/ChangeLog ***
>
> 2019-04-04 Sudakshina Das <sudi.das@arm.com>
>
> Â Â Â Â * arm-dis.c (thumb32_opcodes): New instruction bfl.
[-- Attachment #2: 9.patch --]
[-- Type: text/x-patch, Size: 7781 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 177d90f1c6fdc9ad99a395b479b16e5b9f8ae0b6..5643e3f6bcafe95816c666ad3ed9844ad458c54e 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -10507,6 +10507,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
X(_bcond, d000, f0008000), \
X(_bf, 0000, f040e001), \
X(_bfx, 0000, f060e001), \
+ X(_bfl, 0000, f000c001), \
X(_bflx, 0000, f070e001), \
X(_bic, 4380, ea200000), \
X(_bics, 4380, ea300000), \
@@ -13364,6 +13365,25 @@ do_t_branch_future (void)
}
break;
+ case T_MNEM_bfl:
+ if (inst.operands[1].hasreloc == 0)
+ {
+ int val = inst.operands[1].imm;
+ if (v8_1_branch_value_check (inst.operands[1].imm, 19, TRUE) == FAIL)
+ as_bad (BAD_BRANCH_OFF);
+
+ int immA = (val & 0x0007f000) >> 12;
+ int immB = (val & 0x00000ffc) >> 2;
+ int immC = (val & 0x00000002) >> 1;
+ inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
+ }
+ else
+ {
+ inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF19;
+ inst.relocs[1].pc_rel = 1;
+ }
+ break;
+
case T_MNEM_bfx:
case T_MNEM_bflx:
inst.instruction |= inst.operands[1].reg << 16;
@@ -21687,6 +21707,7 @@ static const struct asm_opcode insns[] =
#define THUMB_VARIANT & arm_ext_v8_1m_main
toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future),
+ toC("bfl", _bfl, 2, (EXPs, EXPs), t_branch_future),
toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future),
};
#undef ARM_VARIANT
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl-bad.d b/gas/testsuite/gas/arm/armv8_1-m-bfl-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..6a8f6f3cfd74d2f068048c39eab29eb70d165350
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl-bad.d
@@ -0,0 +1,4 @@
+#name: Invalid Armv8.1-M Mainline BFL instructions
+#source: armv8_1-m-bfl-bad.s
+#as: -march=armv8.1-m.main
+#error_output: armv8_1-m-bfl-bad.l
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl-bad.l b/gas/testsuite/gas/arm/armv8_1-m-bfl-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..3f7ed80a6d07a4a2c05e8968e95c26d66eae2fab
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl-bad.l
@@ -0,0 +1,9 @@
+.*: Assembler messages:
+.*:6: Error: branch out of range or not a multiple of 2
+.*:7: Error: branch out of range or not a multiple of 2
+.*:8: Error: branch out of range or not a multiple of 2
+.*:9: Error: branch out of range or not a multiple of 2
+.*:11: Error: branch out of range or not a multiple of 2
+.*:12: Error: branch out of range or not a multiple of 2
+.*:13: Error: branch out of range or not a multiple of 2
+.*:14: Error: branch out of range or not a multiple of 2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl-bad.s b/gas/testsuite/gas/arm/armv8_1-m-bfl-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..2af310820c39231978b50a8b5728b0f1f40e9efe
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl-bad.s
@@ -0,0 +1,14 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+ # OP0 : Unsigned, 5-bit, even
+ bfl 0, 36
+ bfl -2, 36
+ bfl 3, 36
+ bfl 32, 36
+ # OP1 : signed, 19-bit, even
+ bf 2, -5
+ bf 2, 5
+ bf 2, 262144
+ bf 2, -262146
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d b/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d
new file mode 100644
index 0000000000000000000000000000000000000000..13c6bf1caa5cb68844bd4b4d33acef9223edfa03
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d
@@ -0,0 +1,10 @@
+#name: Valid Armv8.1-M Mainline BFL instruction with relocation
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-pe *-wince-*
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f0ff c7ff bfl 2, 00000000 <.target>
+ 0: R_ARM_THM_BF18 .target
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.s b/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.s
new file mode 100644
index 0000000000000000000000000000000000000000..01c68828a792f4a06c8aad947e6da26dd5455cf6
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.s
@@ -0,0 +1,5 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+ bfl 2, .target
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl.d b/gas/testsuite/gas/arm/armv8_1-m-bfl.d
new file mode 100644
index 0000000000000000000000000000000000000000..e15636b359f8db2829e46706f9cd0ea3e1d45500
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl.d
@@ -0,0 +1,13 @@
+#name: Valid Armv8.1-M Mainline BFL instruction
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f080 c803 bfl 2, 0000000a <foo\+0xa>
+0[0-9a-f]+ <[^>]+> 4608 mov r0, r1
+0[0-9a-f]+ <[^>]+> f100 c801 bfl 4, 0000000c <foo\+0xc>
+0[0-9a-f]+ <[^>]+> 460a mov r2, r1
+0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
+0[0-9a-f]+ <[^>]+> 4614 mov r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl.s b/gas/testsuite/gas/arm/armv8_1-m-bfl.s
new file mode 100644
index 0000000000000000000000000000000000000000..4605bee468618b76c52f3d90737a060b1b5614a2
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl.s
@@ -0,0 +1,12 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+ bfl 2, 6
+ mov r0, r1
+ bfl .LBranch, .LB2
+ mov r2, r1
+.LB2:
+ mov r3, r2
+.LBranch:
+ mov r4, r2
diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp
index ef3a49c23742f4c43c78e73aa692928ba3d56123..528565e97bee829c193ad54ab21e2f9a7071a718 100644
--- a/ld/testsuite/ld-arm/arm-elf.exp
+++ b/ld/testsuite/ld-arm/arm-elf.exp
@@ -670,6 +670,9 @@ set armeabitests_nonacl {
{"Armv8.1-M Mainline BF" "-r -Ttext 0x1000 --section-start .foo=0x1001000" "" "-march=armv8.1-m.main" {bf.s}
{{objdump -dr bf.d}}
"bf"}
+ {"Armv8.1-M Mainline BFL" "-r -Ttext 0x1000 --section-start .foo=0x1001000" "" "-march=armv8.1-m.main" {bfl.s}
+ {{objdump -dr bfl.d}}
+ "bfl"}
{"R_ARM_THM_JUMP24 Relocation veneers: Short 1"
"--no-fix-arm1176 --section-start destsect=0x00009000 --section-start .text=0x8000" ""
diff --git a/ld/testsuite/ld-arm/bfl.d b/ld/testsuite/ld-arm/bfl.d
new file mode 100644
index 0000000000000000000000000000000000000000..dcf3202eaad16c5659bc65f4890fbd3b6796f206
--- /dev/null
+++ b/ld/testsuite/ld-arm/bfl.d
@@ -0,0 +1,14 @@
+
+.*: file format elf32-.*arm
+
+
+Disassembly of section .text:
+
+00001000 <_start>:
+ 1000: f0ff c7ff bfl 2, 1001000 <bar>
+ 1000: R_ARM_THM_BF18 bar
+
+Disassembly of section .foo:
+
+01001000 <bar>:
+ 1001000: 4770 bx lr
diff --git a/ld/testsuite/ld-arm/bfl.s b/ld/testsuite/ld-arm/bfl.s
new file mode 100644
index 0000000000000000000000000000000000000000..e9fb0a70f6c6c6ee802b0bd91dfcd608c94a0d30
--- /dev/null
+++ b/ld/testsuite/ld-arm/bfl.s
@@ -0,0 +1,19 @@
+ .global _start
+ .syntax unified
+
+@ We will place the section .text at 0x1000.
+
+ .text
+ .thumb_func
+
+_start:
+ bfl 2, bar
+
+@ We will place the section .foo at 0x1001000.
+
+ .section .foo, "xa"
+ .thumb_func
+
+bar:
+ bx lr
+
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index a70ed814fb1177132df1d5121cc68b2fef876b0c..12e28c3df6d79df7e1ae3a69e61b8c07b0e7c4e3 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2754,6 +2754,8 @@ static const struct opcode32 thumb32_opcodes[] =
0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH, binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Mainline
2019-04-04 13:41 ` [PATCH, binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Mainline Andre Vieira (lists)
@ 2019-04-12 10:40 ` Andre Vieira (lists)
0 siblings, 0 replies; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-12 10:40 UTC (permalink / raw)
To: binutils; +Cc: nickc
[-- Attachment #1: Type: text/plain, Size: 3898 bytes --]
Hi,
The former patch had an issue with the LE branch value sign flip. It
wasn't doing it for big-endian because of the wrong use of 'md_
chars_to_number'. Swapping it for 'get_thumb32_insn' fixes the issue.
Also fixed a testism.
Is this OK?
Cheers,
Andre
*** bfd/ChnageLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
*** gas/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR
for the LR operand and optional LR operand.
(parse_operands): Add switch cases for OP_LR and OP_oLR for
both type checking and value checking.
(encode_thumb32_addr_mode): New entries for DLS, WLS and LE.
(v8_1_loop_reloc): New helper function for handling labels
for the low overhead loop instructions.
(do_t_loloop): New function to encode DLS, WLS and LE.
(insns): New entries for WLS, DLS and LE.
(md_pcrel_from_section): New switch case
for BFD_RELOC_ARM_THUMB_LOOP12.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/armv8_1-m-tloop.s: New.
* testsuite/gas/arm/armv8_1-m-tloop.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.s: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.l: New.
*** opcodes/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %P
and %Q patterns.
On 04/04/2019 14:41, Andre Vieira (lists) wrote:
> Hi
>
> This patch is part of a series of patches to add support for Armv8.1-M
> Mainline instructions to binutils.
> This patch adds support to the Scalar low overhead loop instructions:
> LE
> WLS
> DLS
>
> We also add a new assembler resolvable relocation bfd_reloc_code_real
> enum for the 12-bit branch offset used in these instructions.
> Testing: Builds successfully and no regressions. Added new tests for the
> valid and invalid instructions operands. Testsuite shows no regression
> when run for arm-none-eabi targets.
>
> Thanks
> Sudi
>
>
> ChangeLog entries are as follows :
>
> *** bfd/ChnageLog ***
>
> 2019-04-04 Sudakshina Das <sudi.das@arm.com>
>
> Â Â Â Â * reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New.
> Â Â Â Â * bfd-in2.h: Regenerated.
> Â Â Â Â * libbfd.h: Regenerated.
>
> *** gas/ChangeLog ***
>
> 2019-04-04 Sudakshina Das <sudi.das@arm.com>
>
> Â Â Â Â * config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR
> Â Â Â Â for the LR operand and optional LR operand.
> Â Â Â Â (parse_operands): Add switch cases for OP_LR and OP_oLR for
> Â Â Â Â both type checking and value checking.
> Â Â Â Â (encode_thumb32_addr_mode): New entries for DLS, WLS and LE.
> Â Â Â Â (v8_1_loop_reloc): New helper function for handling labels
> Â Â Â Â for the low overhead loop instructions.
> Â Â Â Â (do_t_loloop): New function to encode DLS, WLS and LE.
> Â Â Â Â (insns): New entries for WLS, DLS and LE.
> Â Â Â Â (md_pcrel_from_section): New switch case
> Â Â Â Â for BFD_RELOC_ARM_THUMB_LOOP12.
> Â Â Â Â (md_appdy_fix): Likewise.
> Â Â Â Â (tc_gen_reloc): Likewise.
> Â Â Â Â * testsuite/gas/arm/armv8_1-m-tloop.s: New.
> Â Â Â Â * testsuite/gas/arm/armv8_1-m-tloop.d: New.
> Â Â Â Â * testsuite/gas/arm/armv8_1-m-tloop-bad.s: New.
> Â Â Â Â * testsuite/gas/arm/armv8_1-m-tloop-bad.d: New.
> Â Â Â Â * testsuite/gas/arm/armv8_1-m-tloop-bad.l: New.
>
> *** opcodes/ChangeLog ***
>
> 2019-04-04 Sudakshina Das <sudi.das@arm.com>
>
> Â Â Â Â * arm-dis.c (print_insn_thumb32): Updated to accept new %P
> Â Â Â Â and %Q patterns.
[-- Attachment #2: 12.patch --]
[-- Type: text/x-patch, Size: 13162 bytes --]
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 4a3fa75867c814f082ba3ab3079cf60c30ad2b62..540b9f71c181841ea782c63d87d0d5271c864966 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -3579,6 +3579,9 @@ field in the instruction. */
/* ARM 19-bit pc-relative branch for Branch Future Link instruction. */
BFD_RELOC_ARM_THUMB_BF19,
+/* ARM 12-bit pc-relative branch for Low Overhead Loop instructions. */
+ BFD_RELOC_ARM_THUMB_LOOP12,
+
/* Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
The lowest bit must be zero and is not stored in the instruction.
Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index 32080db8c3f6141ae9aa9674c8776694db29905a..f64a8f3892ad3aff5c4570f0281875bce35846a6 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -1534,6 +1534,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_ARM_THUMB_BF17",
"BFD_RELOC_ARM_THUMB_BF13",
"BFD_RELOC_ARM_THUMB_BF19",
+ "BFD_RELOC_ARM_THUMB_LOOP12",
"BFD_RELOC_THUMB_PCREL_BRANCH7",
"BFD_RELOC_THUMB_PCREL_BRANCH9",
"BFD_RELOC_THUMB_PCREL_BRANCH12",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index c0e413cd19dbfaf5100143c8879d84cb63ba4a17..e6ba9e265027a6c34a8ad183dd5825a9af9c1f82 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -3039,6 +3039,11 @@ ENUM
ENUMDOC
ARM 19-bit pc-relative branch for Branch Future Link instruction.
+ENUM
+ BFD_RELOC_ARM_THUMB_LOOP12
+ENUMDOC
+ ARM 12-bit pc-relative branch for Low Overhead Loop instructions.
+
ENUM
BFD_RELOC_THUMB_PCREL_BRANCH7
ENUMX
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 5e59078890752b0580ae443c7b330e32baecccf6..828dfc1eddce9857a1c038b2ff927d71eccda6e9 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -6543,6 +6543,10 @@ enum operand_parse_code
OP_RIWG, /* iWMMXt wCG register */
OP_RXA, /* XScale accumulator register */
+ /* New operands for Armv8.1-M Mainline. */
+ OP_LR, /* ARM LR register */
+ OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */
+
OP_REGLST, /* ARM register list */
OP_VRSLST, /* VFP single-precision register list */
OP_VRDLST, /* VFP double-precision register list */
@@ -6622,6 +6626,7 @@ enum operand_parse_code
OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
OP_oRR, /* ARM register */
+ OP_oLR, /* ARM LR register */
OP_oRRnpc, /* ARM register, not the PC */
OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
OP_oRRw, /* ARM register, not r15, optional trailing ! */
@@ -6790,6 +6795,8 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
case OP_RRnpc:
case OP_RRnpcsp:
case OP_oRR:
+ case OP_LR:
+ case OP_oLR:
case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
@@ -7307,6 +7314,12 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
inst.operands[i].imm = val;
break;
+ case OP_LR:
+ case OP_oLR:
+ if (inst.operands[i].reg != REG_LR)
+ inst.error = _("operand must be LR register");
+ break;
+
default:
break;
}
@@ -10518,6 +10531,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
X(_cpsid, b670, f3af8600), \
X(_cpy, 4600, ea4f0000), \
X(_dec_sp,80dd, f1ad0d00), \
+ X(_dls, 0000, f040e001), \
X(_eor, 4040, ea800000), \
X(_eors, 4040, ea900000), \
X(_inc_sp,00dd, f10d0d00), \
@@ -10530,6 +10544,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
X(_ldr_pc,4800, f85f0000), \
X(_ldr_pc2,4800, f85f0000), \
X(_ldr_sp,9800, f85d0000), \
+ X(_le, 0000, f00fc001), \
X(_lsl, 0000, fa00f000), \
X(_lsls, 0000, fa10f000), \
X(_lsr, 0800, fa20f000), \
@@ -10571,6 +10586,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
X(_yield, bf10, f3af8001), \
X(_wfe, bf20, f3af8002), \
X(_wfi, bf30, f3af8003), \
+ X(_wls, 0000, f040c001), \
X(_sev, bf40, f3af8004), \
X(_sevl, bf50, f3af8005), \
X(_udf, de00, f7f0a000)
@@ -13434,6 +13450,64 @@ do_t_branch_future (void)
}
}
+/* Helper function for do_t_loloop to handle relocations. */
+static void
+v8_1_loop_reloc (int is_le)
+{
+ if (inst.relocs[0].exp.X_op == O_constant)
+ {
+ int value = inst.relocs[0].exp.X_add_number;
+ value = (is_le) ? -value : value;
+
+ if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
+ as_bad (BAD_BRANCH_OFF);
+
+ int imml, immh;
+
+ immh = (value & 0x00000ffc) >> 2;
+ imml = (value & 0x00000002) >> 1;
+
+ inst.instruction |= (imml << 11) | (immh << 1);
+ }
+ else
+ {
+ inst.relocs[0].type = BFD_RELOC_ARM_THUMB_LOOP12;
+ inst.relocs[0].pc_rel = 1;
+ }
+}
+
+/* To handle the Scalar Low Overhead Loop instructions
+ in Armv8.1-M Mainline. */
+static void
+do_t_loloop (void)
+{
+ unsigned long insn = inst.instruction;
+
+ set_it_insn_type (OUTSIDE_IT_INSN);
+ inst.instruction = THUMB_OP32 (inst.instruction);
+
+ switch (insn)
+ {
+ case T_MNEM_le:
+ /* le <label>. */
+ if (!inst.operands[0].present)
+ inst.instruction |= 1 << 21;
+
+ v8_1_loop_reloc (TRUE);
+ break;
+
+ case T_MNEM_wls:
+ v8_1_loop_reloc (FALSE);
+ /* Fall through. */
+ case T_MNEM_dls:
+ constraint (inst.operands[1].isreg != 1, BAD_ARGS);
+ inst.instruction |= (inst.operands[1].reg << 16);
+ break;
+
+ default: abort();
+ }
+}
+
/* Neon instruction encoder helpers. */
/* Encodings for the different types for various Neon opcodes. */
@@ -21756,6 +21830,10 @@ static const struct asm_opcode insns[] =
toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future),
toC("bfl", _bfl, 2, (EXPs, EXPs), t_branch_future),
toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future),
+
+ toU("dls", _dls, 2, (LR, RRnpcsp), t_loloop),
+ toU("wls", _wls, 3, (LR, RRnpcsp, EXP), t_loloop),
+ toU("le", _le, 2, (oLR, EXP), t_loloop),
};
#undef ARM_VARIANT
#undef THUMB_VARIANT
@@ -22996,6 +23074,7 @@ md_pcrel_from_section (fixS * fixP, segT seg)
case BFD_RELOC_ARM_THUMB_BF17:
case BFD_RELOC_ARM_THUMB_BF19:
case BFD_RELOC_ARM_THUMB_BF13:
+ case BFD_RELOC_ARM_THUMB_LOOP12:
return base + 4;
case BFD_RELOC_THUMB_PCREL_BRANCH23:
@@ -25025,6 +25104,39 @@ md_apply_fix (fixS * fixP,
}
break;
+ case BFD_RELOC_ARM_THUMB_LOOP12:
+ if (fixP->fx_addsy
+ && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
+ && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && ARM_IS_FUNC (fixP->fx_addsy)
+ && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
+ {
+ /* Force a relocation for a branch 12 bits wide. */
+ fixP->fx_done = 0;
+ }
+
+ bfd_vma insn = get_thumb32_insn (buf);
+ /* le lr, <label> or le <label> */
+ if (((insn & 0xffffffff) == 0xf00fc001)
+ || ((insn & 0xffffffff) == 0xf02fc001))
+ value = -value;
+
+ if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ BAD_BRANCH_OFF);
+ if (fixP->fx_done || !seg->use_rela_p)
+ {
+ addressT imml, immh;
+
+ immh = (value & 0x00000ffc) >> 2;
+ imml = (value & 0x00000002) >> 1;
+
+ newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
+ newval |= (imml << 11) | (immh << 1);
+ md_number_to_chars (buf + THUMB_SIZE, newval, THUMB_SIZE);
+ }
+ break;
+
case BFD_RELOC_ARM_V4BX:
/* This will need to go in the object file. */
fixP->fx_done = 0;
@@ -25241,6 +25353,7 @@ tc_gen_reloc (asection *section, fixS *fixp)
case BFD_RELOC_THUMB_PCREL_BRANCH5:
case BFD_RELOC_THUMB_PCREL_BFCSEL:
+ case BFD_RELOC_ARM_THUMB_LOOP12:
as_bad_where (fixp->fx_file, fixp->fx_line,
_("%s used for a symbol not defined in the same file"),
bfd_get_reloc_code_name (fixp->fx_r_type));
diff --git a/gas/testsuite/gas/arm/armv8_1-m-loloop-bad.d b/gas/testsuite/gas/arm/armv8_1-m-loloop-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..d1f2a8dfae4fdcb7ca031f8d198d3e5091697391
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-loloop-bad.d
@@ -0,0 +1,4 @@
+#name: Invalid Armv8.1-M Mainline Low Overhead Loop instructions
+#source: armv8_1-m-loloop-bad.s
+#as: -march=armv8.1-m.main
+#error_output: armv8_1-m-loloop-bad.l
diff --git a/gas/testsuite/gas/arm/armv8_1-m-loloop-bad.l b/gas/testsuite/gas/arm/armv8_1-m-loloop-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..691917ebdcefb33aadf8e25314a2aaa4dbc13f86
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-loloop-bad.l
@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*:5: Error: operand must be LR register -- `wls r1,r2,.LB1'
+.*:6: Error: operand must be LR register -- `dls r2,r2'
+.*:7: Error: r15 not allowed here -- `dls lr,pc'
+.*:8: Error: branch out of range or not a multiple of 2
+.*:9: Error: branch out of range or not a multiple of 2
+.*:10: Error: branch out of range or not a multiple of 2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-loloop-bad.s b/gas/testsuite/gas/arm/armv8_1-m-loloop-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..b4f19625db1406e503c2d80ef19162c2d0c1f27e
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-loloop-bad.s
@@ -0,0 +1,12 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+ wls r1, r2, .LB1
+ dls r2, r2
+ dls lr, pc
+ le lr, #4096
+ le #-4098
+ le #-4095
+.LB1:
+ mov r3, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-loloop.d b/gas/testsuite/gas/arm/armv8_1-m-loloop.d
new file mode 100644
index 0000000000000000000000000000000000000000..1e02b82651f7127c5c98d3518a0a653445db4c9a
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-loloop.d
@@ -0,0 +1,17 @@
+#name: Valid Armv8.1-M Mainline Low Overhead loop instructions
+#source: armv8_1-m-loloop.s
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f042 c00d wls lr, r2, 0000001c <foo\+0x1c>
+0[0-9a-f]+ <[^>]+> f042 e001 dls lr, r2
+0[0-9a-f]+ <[^>]+> f04e e001 dls lr, lr
+0[0-9a-f]+ <[^>]+> f00f c009 le lr, 00000000 <foo>
+0[0-9a-f]+ <[^>]+> f02f c00b le 00000000 <foo>
+0[0-9a-f]+ <[^>]+> f00f c24b le lr, fffffb84 <foo\+0xfffffb84>
+0[0-9a-f]+ <[^>]+> f02f c007 le 00000010 <foo\+0x10>
+0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
+#...
diff --git a/gas/testsuite/gas/arm/armv8_1-m-loloop.s b/gas/testsuite/gas/arm/armv8_1-m-loloop.s
new file mode 100644
index 0000000000000000000000000000000000000000..8fb87e40aa5d17955903ff473e55c0f37eac50bb
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-loloop.s
@@ -0,0 +1,14 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+.Lstart:
+ wls lr, r2, .LB1
+ dls lr, r2
+ dls lr, lr
+ le lr, .Lstart
+ le .Lstart
+ le lr, #-1172
+ le #-12
+.LB1:
+ mov r3, r2
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index b4865c1a42a04bb6a9b156d7369c065ca351efb4..2cf9507fbb5fe6505df66d2cd0c5abda2d53bdf9 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2718,6 +2718,8 @@ static const struct opcode16 thumb_opcodes[] =
%W print an offset for BF instruction
%Y print an offset for BFL instruction
%Z print an offset for BFCSEL instruction
+ %Q print an offset for Low Overhead Loop instructions
+ %P print an offset for Low Overhead Loop end instructions
%b print a conditional branch offset
%B print an unconditional branch offset
%s print the shift field of an SSAT instruction
@@ -2751,6 +2753,15 @@ static const struct opcode16 thumb_opcodes[] =
static const struct opcode32 thumb32_opcodes[] =
{
/* Armv8.1-M Mainline instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf02fc001, 0xfffff001, "le\t%P"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf00fc001, 0xfffff001, "le\tlr, %P"},
+
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
@@ -5945,6 +5956,32 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
}
break;
+ case 'Q':
+ {
+ unsigned int immh = (given & 0x000007feu) >> 1;
+ unsigned int imml = (given & 0x00000800u) >> 11;
+ bfd_vma imm32 = 0;
+
+ imm32 |= immh << 2;
+ imm32 |= imml << 1;
+
+ info->print_address_func (pc + 4 + imm32, info);
+ }
+ break;
+
+ case 'P':
+ {
+ unsigned int immh = (given & 0x000007feu) >> 1;
+ unsigned int imml = (given & 0x00000800u) >> 11;
+ bfd_vma imm32 = 0;
+
+ imm32 |= immh << 2;
+ imm32 |= imml << 1;
+
+ info->print_address_func (pc + 4 - imm32, info);
+ }
+ break;
+
case 'b':
{
unsigned int S = (given & 0x04000000u) >> 26;
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH, binutils, ARM, 6/16] New BF instruction for Armv8.1-M Mainline
2019-04-04 13:37 ` [PATCH, binutils, ARM, 6/16] New BF instruction for Armv8.1-M Mainline Andre Vieira (lists)
@ 2019-04-12 10:41 ` Andre Vieira (lists)
0 siblings, 0 replies; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-04-12 10:41 UTC (permalink / raw)
To: binutils; +Cc: nickc
[-- Attachment #1: Type: text/plain, Size: 2343 bytes --]
Hi,
Fixed some testisms highlighted by Nick.
This OK?
*** gas/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (T16_32_TAB): New entries for bf.
(do_t_branch_future): New.
(insns): New instruction for bf.
* testsuite/gas/arm/armv8_1-m-bf.d: New.
* testsuite/gas/arm/armv8_1-m-bf.s: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.s: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.l: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.d: New.
* testsuite/gas/arm/armv8_1-m-bf-rel.d: New.
* testsuite/gas/arm/armv8_1-m-bf-rel.s: New.
*** ld/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bf.s: New.
* testsuite/ld-arm/bf.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instructions for bf.
On 04/04/2019 14:37, Andre Vieira (lists) wrote:
> Hi
>
> This patch is part of a series of patches to add support for Armv8.1-M
> Mainline instructions to binutils.
>
> This patch adds the BF instruction.
>
> Testing: Added new tests for the valid instructions operands. Testsuite
> shows no regression when run for arm-none-eabi targets.
>
> Thanks
> Sudi
>
>
> ChangeLog entries are as follows :
>
> *** gas/ChangeLog ***
>
> 2019-04-04 Sudakshina Das <sudi.das@arm.com>
>
> Â Â Â Â * config/tc-arm.c (T16_32_TAB): New entries for bf.
> Â Â Â Â (do_t_branch_future): New.
> Â Â Â Â (insns): New instruction for bf.
> Â Â Â Â * testsuite/gas/arm/armv8_1-m-bf.d: New.
> Â Â Â Â * testsuite/gas/arm/armv8_1-m-bf.s: New.
> Â Â Â Â * testsuite/gas/arm/armv8_1-m-bf-bad.s: New
> Â Â Â Â * testsuite/gas/arm/armv8_1-m-bf-bad.l: New
> Â Â Â Â * testsuite/gas/arm/armv8_1-m-bf-bad.d: New
>
> *** ld/ChangeLog ***
>
> 2019-04-04 Sudakshina Das <sudi.das@arm.com>
>
> Â Â Â Â * testsuite/ld-arm/bf.s: New.
> Â Â Â Â * testsuite/ld-arm/bf.d: New.
> Â Â Â Â * testsuite/ld-arm/arm-elf.exp: Add above test.
>
> *** opcodes/ChangeLog ***
>
> 2019-04-04 Sudakshina Das <sudi.das@arm.com>
>
> Â Â Â Â * arm-dis.c (thumb32_opcodes): New instructions for bf.
[-- Attachment #2: 6.patch --]
[-- Type: text/x-patch, Size: 9277 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index d3a21d63575c194051606bb723a224d3c10334e9..caba2736c16c9dbd61ca1a7637cc171682058d13 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -10505,6 +10505,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
X(_asrs, 1000, fa50f000), \
X(_b, e000, f000b000), \
X(_bcond, d000, f0008000), \
+ X(_bf, 0000, f040e001), \
X(_bic, 4380, ea200000), \
X(_bics, 4380, ea300000), \
X(_cmn, 42c0, eb100f00), \
@@ -13320,6 +13321,51 @@ v8_1_branch_value_check (int val, int nbits, int is_signed)
return SUCCESS;
}
+/* For branches in Armv8.1-M Mainline. */
+static void
+do_t_branch_future (void)
+{
+ unsigned long insn = inst.instruction;
+
+ inst.instruction = THUMB_OP32 (inst.instruction);
+ if (inst.operands[0].hasreloc == 0)
+ {
+ if (v8_1_branch_value_check (inst.operands[0].imm, 5, FALSE) == FAIL)
+ as_bad (BAD_BRANCH_OFF);
+
+ inst.instruction |= ((inst.operands[0].imm & 0x1f) >> 1) << 23;
+ }
+ else
+ {
+ inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH5;
+ inst.relocs[0].pc_rel = 1;
+ }
+
+ switch (insn)
+ {
+ case T_MNEM_bf:
+ if (inst.operands[1].hasreloc == 0)
+ {
+ int val = inst.operands[1].imm;
+ if (v8_1_branch_value_check (inst.operands[1].imm, 17, TRUE) == FAIL)
+ as_bad (BAD_BRANCH_OFF);
+
+ int immA = (val & 0x0001f000) >> 12;
+ int immB = (val & 0x00000ffc) >> 2;
+ int immC = (val & 0x00000002) >> 1;
+ inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
+ }
+ else
+ {
+ inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF17;
+ inst.relocs[1].pc_rel = 1;
+ }
+ break;
+
+ default: abort ();
+ }
+}
+
/* Neon instruction encoder helpers. */
/* Encodings for the different types for various Neon opcodes. */
@@ -19538,6 +19584,11 @@ static struct asm_barrier_opt barrier_opt_names[] =
{ mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
NULL, do_##te }
+/* T_MNEM_xyz enumerator variants of ToC. */
+#define toC(mnem, top, nops, ops, te) \
+ { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
+ do_##te }
+
/* Legacy mnemonics that always have conditional infix after the third
character. */
#define CL(mnem, op, nops, ops, ae) \
@@ -21623,6 +21674,11 @@ static const struct asm_opcode insns[] =
#define THUMB_VARIANT & arm_ext_v8m_main
ToC("vlldm", ec300a00, 1, (RRnpc), rn),
ToC("vlstm", ec200a00, 1, (RRnpc), rn),
+
+ /* Armv8.1-M Mainline instructions. */
+#undef THUMB_VARIANT
+#define THUMB_VARIANT & arm_ext_v8_1m_main
+ toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
};
#undef ARM_VARIANT
#undef THUMB_VARIANT
@@ -21633,8 +21689,10 @@ static const struct asm_opcode insns[] =
#undef cCE
#undef cCL
#undef C3E
+#undef C3
#undef CE
#undef CM
+#undef CL
#undef UE
#undef UF
#undef UT
@@ -21650,6 +21708,9 @@ static const struct asm_opcode insns[] =
#undef OPS5
#undef OPS6
#undef do_0
+#undef ToC
+#undef toC
+#undef ToU
\f
/* MD interface: bits in the object file. */
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-bad.d b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..d61aad79e9a6faa26a733245b3769b867f5e126d
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.d
@@ -0,0 +1,4 @@
+#name: Invalid Armv8.1-M Mainline BF instructions
+#source: armv8_1-m-bf-bad.s
+#as: -march=armv8.1-m.main
+#error_output: armv8_1-m-bf-bad.l
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-bad.l b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..3f7ed80a6d07a4a2c05e8968e95c26d66eae2fab
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.l
@@ -0,0 +1,9 @@
+.*: Assembler messages:
+.*:6: Error: branch out of range or not a multiple of 2
+.*:7: Error: branch out of range or not a multiple of 2
+.*:8: Error: branch out of range or not a multiple of 2
+.*:9: Error: branch out of range or not a multiple of 2
+.*:11: Error: branch out of range or not a multiple of 2
+.*:12: Error: branch out of range or not a multiple of 2
+.*:13: Error: branch out of range or not a multiple of 2
+.*:14: Error: branch out of range or not a multiple of 2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-bad.s b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..43ef4b1bf92fa42956f2fdabd29eeec7bcf168fb
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.s
@@ -0,0 +1,14 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+ # OP0 : Unsigned, 5-bit, even
+ bf 0, 36
+ bf -2, 36
+ bf 3, 36
+ bf 32, 36
+ # OP1 : signed, 17-bit, even
+ bf 2, -5
+ bf 2, 5
+ bf 2, 65536
+ bf 2, -65538
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d b/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d
new file mode 100644
index 0000000000000000000000000000000000000000..e429c136f2ea7818de2a7479a21f0cc6bc0702e1
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d
@@ -0,0 +1,10 @@
+#name: Valid Armv8.1-M Mainline BF instruction with relocation
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-pe *-wince-*
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f0df e7ff bf 2, 00000000 <.target>
+ 0: R_ARM_THM_BF16 .target
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-rel.s b/gas/testsuite/gas/arm/armv8_1-m-bf-rel.s
new file mode 100644
index 0000000000000000000000000000000000000000..c11c9c177a4483589e4477f2e151ae8b742b019a
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-rel.s
@@ -0,0 +1,5 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+ bf 2, .target
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf.d b/gas/testsuite/gas/arm/armv8_1-m-bf.d
new file mode 100644
index 0000000000000000000000000000000000000000..dd30b2a2ff1d35cd58299813614ec5a79cbcdadf
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf.d
@@ -0,0 +1,13 @@
+#name: Valid Armv8.1-M Mainline BF instruction
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f0c0 e803 bf 2, 0000000a <foo\+0xa>
+0[0-9a-f]+ <[^>]+> 4609 mov r1, r1
+0[0-9a-f]+ <[^>]+> f140 e801 bf 4, 0000000c <foo\+0xc>
+0[0-9a-f]+ <[^>]+> 460a mov r2, r1
+0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
+0[0-9a-f]+ <[^>]+> 4614 mov r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf.s b/gas/testsuite/gas/arm/armv8_1-m-bf.s
new file mode 100644
index 0000000000000000000000000000000000000000..8c6dac748dc1fef96e54bc38c9abe4e13b7ef2ab
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf.s
@@ -0,0 +1,12 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+ bf 2, 6
+ mov r1, r1
+ bf .LBranch, .LB2
+ mov r2, r1
+.LB2:
+ mov r3, r2
+.LBranch:
+ mov r4, r2
diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp
index 450a76b7082be883d0bbc818420edd2d6a762e6e..ef3a49c23742f4c43c78e73aa692928ba3d56123 100644
--- a/ld/testsuite/ld-arm/arm-elf.exp
+++ b/ld/testsuite/ld-arm/arm-elf.exp
@@ -667,6 +667,10 @@ set armeabitests_nonacl {
{{objdump -d armv4-bx.d}}
"armv4-bx"}
+ {"Armv8.1-M Mainline BF" "-r -Ttext 0x1000 --section-start .foo=0x1001000" "" "-march=armv8.1-m.main" {bf.s}
+ {{objdump -dr bf.d}}
+ "bf"}
+
{"R_ARM_THM_JUMP24 Relocation veneers: Short 1"
"--no-fix-arm1176 --section-start destsect=0x00009000 --section-start .text=0x8000" ""
"-march=armv7-a -mthumb"
diff --git a/ld/testsuite/ld-arm/bf.d b/ld/testsuite/ld-arm/bf.d
new file mode 100644
index 0000000000000000000000000000000000000000..658120abb693ba7b86c669a5b8a6fb3e3e335e37
--- /dev/null
+++ b/ld/testsuite/ld-arm/bf.d
@@ -0,0 +1,14 @@
+
+.*: file format elf32-.*arm
+
+
+Disassembly of section .text:
+
+00001000 <_start>:
+ 1000: f0df e7ff bf 2, 1001000 <bar>
+ 1000: R_ARM_THM_BF16 bar
+
+Disassembly of section .foo:
+
+01001000 <bar>:
+ 1001000: 4770 bx lr
diff --git a/ld/testsuite/ld-arm/bf.s b/ld/testsuite/ld-arm/bf.s
new file mode 100644
index 0000000000000000000000000000000000000000..164a90d04b4e995add2c54beee31e63fbdc5c12d
--- /dev/null
+++ b/ld/testsuite/ld-arm/bf.s
@@ -0,0 +1,19 @@
+ .global _start
+ .syntax unified
+
+@ We will place the section .text at 0x1000.
+
+ .text
+ .thumb_func
+
+_start:
+ bf 2, bar
+
+@ We will place the section .foo at 0x1001000.
+
+ .section .foo, "xa"
+ .thumb_func
+
+bar:
+ bx lr
+
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 71443d3ea41966309d4516754eb8f2e38e3e6df0..966a4d4d92fa660b1754c4c703648ec008efcfb0 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2747,6 +2747,11 @@ static const struct opcode16 thumb_opcodes[] =
makes heavy use of special-case bit patterns. */
static const struct opcode32 thumb32_opcodes[] =
{
+ /* Armv8.1-M Mainline instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
+
+
/* ARMv8-M and ARMv8-M Security Extensions instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline
2019-04-12 10:39 ` Andre Vieira (lists)
@ 2019-04-12 13:51 ` Nick Clifton
2019-04-15 9:41 ` Andre Simoes Dias Vieira
0 siblings, 1 reply; 32+ messages in thread
From: Nick Clifton @ 2019-04-12 13:51 UTC (permalink / raw)
To: Andre Vieira (lists), binutils
Hi Andre,
> Thanks for that! Most of them were testisms. Though there was an actual issue with big-endian and the LE instruction. I replied to each relevant patch with an updated version.
Great - in which case the patch series is approved. Do you need to me ACK each
of them individually, or is this approval enough ?
Cheers
Nick
^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline
2019-04-12 13:51 ` Nick Clifton
@ 2019-04-15 9:41 ` Andre Simoes Dias Vieira
2019-04-16 1:58 ` Alan Modra
0 siblings, 1 reply; 32+ messages in thread
From: Andre Simoes Dias Vieira @ 2019-04-15 9:41 UTC (permalink / raw)
To: nickc, binutils; +Cc: nd
Hi Nick,
No need, Ill start upstreaming them. Thank you for the review.
Cheers,
Andre
-----Original Message-----
From: Nick Clifton <nickc@redhat.com>
Sent: 12 April 2019 14:51
To: Andre Simoes Dias Vieira <Andre.SimoesDiasVieira@arm.com>; binutils@sourceware.org
Subject: Re: [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline
Hi Andre,
> Thanks for that! Most of them were testisms. Though there was an actual issue with big-endian and the LE instruction. I replied to each relevant patch with an updated version.
Great - in which case the patch series is approved. Do you need to me ACK each of them individually, or is this approval enough ?
Cheers
Nick
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline
2019-04-15 9:41 ` Andre Simoes Dias Vieira
@ 2019-04-16 1:58 ` Alan Modra
2019-04-16 11:52 ` Andre Simoes Dias Vieira
0 siblings, 1 reply; 32+ messages in thread
From: Alan Modra @ 2019-04-16 1:58 UTC (permalink / raw)
To: Andre Simoes Dias Vieira; +Cc: nickc, binutils, nd
These failures remain.
arm-pe +FAIL: Valid Armv8.1-M Mainline BF instruction
arm-pe +FAIL: Valid Armv8.1-M Mainline BFCSEL instruction
arm-pe +FAIL: Valid Armv8.1-M Mainline BFL instruction
arm-pe +FAIL: Valid Armv8.1-M Mainline Low Overhead loop instructions
arm-vxworks +FAIL: Valid Armv8.1-M Mainline BF instruction with relocation
arm-vxworks +FAIL: Valid Armv8.1-M Mainline BFL instruction with relocation
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline
2019-04-16 1:58 ` Alan Modra
@ 2019-04-16 11:52 ` Andre Simoes Dias Vieira
2019-04-16 12:36 ` Alan Modra
0 siblings, 1 reply; 32+ messages in thread
From: Andre Simoes Dias Vieira @ 2019-04-16 11:52 UTC (permalink / raw)
To: Alan Modra; +Cc: nickc, binutils, nd
Hi Alan,
Thanks for the heads up. I am on holidays so I don't have much time to look at this right now. But after a quick look I think the arm-pe fails are due to objdump printing the branch targets in a different format. I'll double-check later, but it should be a case of accepting both answers.
The VxWorks failures seem to be related to the relocations. I did a quick search but couldn't determine whether VxWorks uses Elf binary format. Do you reckon VxWorks should support this elf relocation? If so I'll need to look at it a bit further, otherwise I'll skip the relocation tests for VxWorks.
Cheers,
Andre
-----Original Message-----
From: Alan Modra <amodra@gmail.com>
Sent: 16 April 2019 02:58
To: Andre Simoes Dias Vieira <Andre.SimoesDiasVieira@arm.com>
Cc: nickc@redhat.com; binutils@sourceware.org; nd <nd@arm.com>
Subject: Re: [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline
These failures remain.
arm-pe +FAIL: Valid Armv8.1-M Mainline BF instruction arm-pe +FAIL: Valid Armv8.1-M Mainline BFCSEL instruction arm-pe +FAIL: Valid Armv8.1-M Mainline BFL instruction arm-pe +FAIL: Valid Armv8.1-M Mainline Low Overhead loop instructions arm-vxworks +FAIL: Valid Armv8.1-M Mainline BF instruction with relocation arm-vxworks +FAIL: Valid Armv8.1-M Mainline BFL instruction with relocation
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline
2019-04-16 11:52 ` Andre Simoes Dias Vieira
@ 2019-04-16 12:36 ` Alan Modra
2019-05-01 9:32 ` Andre Vieira (lists)
0 siblings, 1 reply; 32+ messages in thread
From: Alan Modra @ 2019-04-16 12:36 UTC (permalink / raw)
To: Andre Simoes Dias Vieira; +Cc: nickc, binutils, nd
On Tue, Apr 16, 2019 at 11:52:19AM +0000, Andre Simoes Dias Vieira wrote:
> Hi Alan,
>
> Thanks for the heads up. I am on holidays so I don't have much time to look at this right now. But after a quick look I think the arm-pe fails are due to objdump printing the branch targets in a different format. I'll double-check later, but it should be a case of accepting both answers.
>
> The VxWorks failures seem to be related to the relocations. I did a quick search but couldn't determine whether VxWorks uses Elf binary format. Do you reckon VxWorks should support this elf relocation? If so I'll need to look at it a bit further, otherwise I'll skip the relocation tests for VxWorks.
VxWorks uses ELF. The difference is that unlike other ARM targets,
arm-vxworks uses rela style relocations. Very likely your new reloc
processing is broken for rela. ie. You shouldn't just sweep this
under the rug. ;-)
> Cheers,
> Andre
>
> -----Original Message-----
> From: Alan Modra <amodra@gmail.com>
> Sent: 16 April 2019 02:58
> To: Andre Simoes Dias Vieira <Andre.SimoesDiasVieira@arm.com>
> Cc: nickc@redhat.com; binutils@sourceware.org; nd <nd@arm.com>
> Subject: Re: [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline
>
> These failures remain.
> arm-pe +FAIL: Valid Armv8.1-M Mainline BF instruction arm-pe +FAIL: Valid Armv8.1-M Mainline BFCSEL instruction arm-pe +FAIL: Valid Armv8.1-M Mainline BFL instruction arm-pe +FAIL: Valid Armv8.1-M Mainline Low Overhead loop instructions arm-vxworks +FAIL: Valid Armv8.1-M Mainline BF instruction with relocation arm-vxworks +FAIL: Valid Armv8.1-M Mainline BFL instruction with relocation
>
> --
> Alan Modra
> Australia Development Lab, IBM
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline
2019-04-16 12:36 ` Alan Modra
@ 2019-05-01 9:32 ` Andre Vieira (lists)
2019-05-02 1:21 ` Alan Modra
0 siblings, 1 reply; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-05-01 9:32 UTC (permalink / raw)
To: Alan Modra; +Cc: nickc, binutils, sudi.das
[-- Attachment #1: Type: text/plain, Size: 4003 bytes --]
Hello,
After some investigation I found there were more things wrong with the
way we handled the branch future relocations. I fixed these and added a
linker test for ELF targets (and a duplicate entry for vxworks as we
seem to skip other elf linker tests for it).
As for the vxworks failures Alan spotted, I believe this is due to the
relocations being treated differently, as you pointed out one uses REL
and the other RELA. This leads to different relocation encodings. So for
instance when a REL target encodes a relocation for 'target' it seems to
do so with:
A = 0
S = target
whereas for RELA it uses:
A = 4
S = target-4
These do get handled correctly by the linker as shown in the test added
for vxworks and other elf targets. I also checked other similar
relocations, such as the R_ARM_THM_JUMP24, and these behave the same way.
As a side effect, this patch also removes the unnecessary
'get_value_helper' function thus also fixing PR/target 24460 @Sudi
please do not commit your earlier fix.
Tested on arm-none-eabi, arm-vxworks, arm-wince-pe, and arm-pe.
Is this OK for trunk?
bfd/ChangeLog:
2019-04-30 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR/target 24460
* elf32-arm.c (get_value_helper): Remove.
(elf32_arm_final_link_relocate): Fix branch future relocations.
gas/ChangeLog:
2019-04-30 Andre Vieira <andre.simoesdiasvieira@arm.com>
* testsuite/gas/arm/armv8_1-m-bf.d: Allow different branch target
naming conventions.
* testsuite/gas/arm/armv8_1-m-bfl.d: Likewise.
* testsuite/gas/arm/armv8_1-m-bfcsel.d: Likewise.
* testsuite/gas/arm/armv8_1-m-loloop.d: Likewise.
* testsuite/gas/arm/armv8_1-m-bf-rel.d: Skip for vxworks.
* testsuite/gas/arm/armv8_1-m-bf-rela.d: New test.
* testsuite/gas/arm/armv8_1-m-bfl-rel.d: Skip for vxworks.
* testsuite/gas/arm/armv8_1-m-bfl-rela.d: New test.
ld/ChangeLog:
2019-04-30 Andre Vieira <andre.simoesdiasvieira@arm.com>
* testsuite/ld-arm/arm-elf.exp: Add tests
* testsuite/ld-arm/bfs-0.s: New test.
* testsuite/ld-arm/bfs-1.s: New test.
* testsuite/ld-arm/branch-futures.d: New test.
On 16/04/2019 13:36, Alan Modra wrote:
> On Tue, Apr 16, 2019 at 11:52:19AM +0000, Andre Simoes Dias Vieira wrote:
>> Hi Alan,
>>
>> Thanks for the heads up. I am on holidays so I don't have much time to look at this right now. But after a quick look I think the arm-pe fails are due to objdump printing the branch targets in a different format. I'll double-check later, but it should be a case of accepting both answers.
>>
>> The VxWorks failures seem to be related to the relocations. I did a quick search but couldn't determine whether VxWorks uses Elf binary format. Do you reckon VxWorks should support this elf relocation? If so I'll need to look at it a bit further, otherwise I'll skip the relocation tests for VxWorks.
>
> VxWorks uses ELF. The difference is that unlike other ARM targets,
> arm-vxworks uses rela style relocations. Very likely your new reloc
> processing is broken for rela. ie. You shouldn't just sweep this
> under the rug. ;-)
>
>> Cheers,
>> Andre
>>
>> -----Original Message-----
>> From: Alan Modra <amodra@gmail.com>
>> Sent: 16 April 2019 02:58
>> To: Andre Simoes Dias Vieira <Andre.SimoesDiasVieira@arm.com>
>> Cc: nickc@redhat.com; binutils@sourceware.org; nd <nd@arm.com>
>> Subject: Re: [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline
>>
>> These failures remain.
>> arm-pe +FAIL: Valid Armv8.1-M Mainline BF instruction arm-pe +FAIL: Valid Armv8.1-M Mainline BFCSEL instruction arm-pe +FAIL: Valid Armv8.1-M Mainline BFL instruction arm-pe +FAIL: Valid Armv8.1-M Mainline Low Overhead loop instructions arm-vxworks +FAIL: Valid Armv8.1-M Mainline BF instruction with relocation arm-vxworks +FAIL: Valid Armv8.1-M Mainline BFL instruction with relocation
>>
>> --
>> Alan Modra
>> Australia Development Lab, IBM
>
[-- Attachment #2: fix.patch --]
[-- Type: text/x-patch, Size: 11894 bytes --]
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 337961d26e16c6458f41d54b2e8dbe6891a5017c..a4fd7de7aa2354dd25ebca8a5c222716a5468197 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -10293,59 +10293,6 @@ identify_add_or_sub (bfd_vma insn)
return 0;
}
-/* Helper function to compute the Addend for Armv8.1-M Mainline relocations. */
-static bfd_vma
-get_value_helper (bfd_vma plt_offset,
- asection *splt,
- asection *input_section,
- asection *sym_sec,
- struct elf_link_hash_entry * h,
- struct bfd_link_info *info,
- bfd *input_bfd,
- Elf_Internal_Rela *rel,
- const char *sym_name,
- unsigned char st_type,
- struct elf32_arm_link_hash_table *globals,
- bfd_boolean *unresolved_reloc_p)
-{
- bfd_vma value = 0;
- enum arm_st_branch_type branch_type;
- enum elf32_arm_stub_type stub_type = arm_stub_none;
- struct elf32_arm_stub_hash_entry *stub_entry;
- struct elf32_arm_link_hash_entry *hash
- = (struct elf32_arm_link_hash_entry *)h;
-
-
- if (plt_offset != (bfd_vma) -1)
- {
- value = (splt->output_section->vma
- + splt->output_offset
- + plt_offset);
- value -= PLT_THUMB_STUB_SIZE;
- *unresolved_reloc_p = FALSE;
- }
-
- stub_type = arm_type_of_stub (info, input_section, rel,
- st_type, &branch_type,
- hash, value, sym_sec,
- input_bfd, sym_name);
-
- if (stub_type != arm_stub_none)
- {
- stub_entry = elf32_arm_get_stub_entry (input_section,
- sym_sec, h,
- rel, globals,
- stub_type);
- if (stub_entry != NULL)
- {
- value = (stub_entry->stub_offset
- + stub_entry->stub_sec->output_offset
- + stub_entry->stub_sec->output_section->vma);
- }
- }
- return value;
-}
-
/* Perform a relocation as part of a final link. */
static bfd_reloc_status_type
@@ -12968,14 +12915,10 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
addend |= (immC << 1);
addend |= 1;
/* Sign extend. */
- addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
+ signed_addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
}
- value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
- info, input_bfd, rel, sym_name, st_type,
- globals, unresolved_reloc_p);
-
- relocation = value + addend;
+ relocation = value + signed_addend;
relocation -= (input_section->output_section->vma
+ input_section->output_offset
+ rel->r_offset);
@@ -13014,13 +12957,10 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
addend |= 1;
/* Sign extend. */
addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
+ signed_addend = addend;
}
- value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
- info, input_bfd, rel, sym_name, st_type,
- globals, unresolved_reloc_p);
-
- relocation = value + addend;
+ relocation = value + signed_addend;
relocation -= (input_section->output_section->vma
+ input_section->output_offset
+ rel->r_offset);
@@ -13059,13 +12999,10 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
addend |= 1;
/* Sign extend. */
addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
+ signed_addend = addend;
}
- value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
- info, input_bfd, rel, sym_name, st_type,
- globals, unresolved_reloc_p);
-
- relocation = value + addend;
+ relocation = value + signed_addend;
relocation -= (input_section->output_section->vma
+ input_section->output_offset
+ rel->r_offset);
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d b/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d
index e429c136f2ea7818de2a7479a21f0cc6bc0702e1..bdb265c5a3aa8cc4f4d0112562249b559d468784 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d
@@ -1,7 +1,7 @@
-#name: Valid Armv8.1-M Mainline BF instruction with relocation
+#name: Valid Armv8.1-M Mainline BF instruction with REL
#as: -march=armv8.1-m.main
#objdump: -dr --prefix-addresses --show-raw-insn
-#skip: *-*-pe *-wince-*
+#skip: *-*-pe *-wince-* *-vxworks
.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-rela.d b/gas/testsuite/gas/arm/armv8_1-m-bf-rela.d
new file mode 100644
index 0000000000000000000000000000000000000000..d363d098523ae5ef54870f595b7aa8dd1bc7a226
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-rela.d
@@ -0,0 +1,12 @@
+#name: Valid Armv8.1-M Mainline BF instruction with RELA
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+#source:armv8_1-m-bf-rel.s
+#noskip: *-vxworks
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f0c0 e001 bf 2, 00000004 <.target\+0x4>
+ 0: R_ARM_THM_BF16 .target-0x4
+
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf.d b/gas/testsuite/gas/arm/armv8_1-m-bf.d
index dd30b2a2ff1d35cd58299813614ec5a79cbcdadf..99de065903bca1ffc407b043a0c9cd554c44a25e 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-bf.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf.d
@@ -5,9 +5,9 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> f0c0 e803 bf 2, 0000000a <foo\+0xa>
+0[0-9a-f]+ <[^>]+> f0c0 e803 bf 2, 0000000a <.*>
0[0-9a-f]+ <[^>]+> 4609 mov r1, r1
-0[0-9a-f]+ <[^>]+> f140 e801 bf 4, 0000000c <foo\+0xc>
+0[0-9a-f]+ <[^>]+> f140 e801 bf 4, 0000000c <.*>
0[0-9a-f]+ <[^>]+> 460a mov r2, r1
0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
0[0-9a-f]+ <[^>]+> 4614 mov r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d b/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d
index a498f06cd3e68370b737976ac3453855852f5b58..b66e9295f59e164533c2dd928fff5173ec6778be 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d
@@ -5,8 +5,8 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> f080 e803 bfcsel 2, 0000000a <foo\+0xa>, 4, eq
+0[0-9a-f]+ <[^>]+> f080 e803 bfcsel 2, 0000000a <.*>, 4, eq
0[0-9a-f]+ <[^>]+> 4609 mov r1, r1
-0[0-9a-f]+ <[^>]+> d000 beq.n 0000000a <foo\+0xa>
+0[0-9a-f]+ <[^>]+> d000 beq.n 0000000a <.*>
0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
0[0-9a-f]+ <[^>]+> 4614 mov r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d b/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d
index 13c6bf1caa5cb68844bd4b4d33acef9223edfa03..951074cff0962e5ee13ebf8219a0ab515df60f5f 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d
@@ -1,7 +1,7 @@
-#name: Valid Armv8.1-M Mainline BFL instruction with relocation
+#name: Valid Armv8.1-M Mainline BFL instruction with REL
#as: -march=armv8.1-m.main
#objdump: -dr --prefix-addresses --show-raw-insn
-#skip: *-*-pe *-wince-*
+#skip: *-*-pe *-wince-* *-vxworks
.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl-rela.d b/gas/testsuite/gas/arm/armv8_1-m-bfl-rela.d
new file mode 100644
index 0000000000000000000000000000000000000000..291d10b4af82d376a260d06ee6c434d6fe1b4f6a
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl-rela.d
@@ -0,0 +1,12 @@
+#name: Valid Armv8.1-M Mainline BFL instruction with RELA
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+#source: armv8_1-m-bfl-rel.s
+#noskip: *-vxworks
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f080 c001 bfl 2, 00000004 <.target\+0x4>
+ 0: R_ARM_THM_BF18 .target-0x4
+
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl.d b/gas/testsuite/gas/arm/armv8_1-m-bfl.d
index e15636b359f8db2829e46706f9cd0ea3e1d45500..b28d0b111e362c130b5c17b57749f1170c845e50 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-bfl.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl.d
@@ -5,9 +5,9 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> f080 c803 bfl 2, 0000000a <foo\+0xa>
+0[0-9a-f]+ <[^>]+> f080 c803 bfl 2, 0000000a <.*>
0[0-9a-f]+ <[^>]+> 4608 mov r0, r1
-0[0-9a-f]+ <[^>]+> f100 c801 bfl 4, 0000000c <foo\+0xc>
+0[0-9a-f]+ <[^>]+> f100 c801 bfl 4, 0000000c <.*>
0[0-9a-f]+ <[^>]+> 460a mov r2, r1
0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
0[0-9a-f]+ <[^>]+> 4614 mov r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-loloop.d b/gas/testsuite/gas/arm/armv8_1-m-loloop.d
index 1e02b82651f7127c5c98d3518a0a653445db4c9a..20506c692005d40e3ed328a0f27251e8663e27ed 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-loloop.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-loloop.d
@@ -6,12 +6,12 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> f042 c00d wls lr, r2, 0000001c <foo\+0x1c>
+0[0-9a-f]+ <[^>]+> f042 c00d wls lr, r2, 0000001c <.*>
0[0-9a-f]+ <[^>]+> f042 e001 dls lr, r2
0[0-9a-f]+ <[^>]+> f04e e001 dls lr, lr
-0[0-9a-f]+ <[^>]+> f00f c009 le lr, 00000000 <foo>
-0[0-9a-f]+ <[^>]+> f02f c00b le 00000000 <foo>
-0[0-9a-f]+ <[^>]+> f00f c24b le lr, fffffb84 <foo\+0xfffffb84>
-0[0-9a-f]+ <[^>]+> f02f c007 le 00000010 <foo\+0x10>
+0[0-9a-f]+ <[^>]+> f00f c009 le lr, 00000000 <.*>
+0[0-9a-f]+ <[^>]+> f02f c00b le 00000000 <.*>
+0[0-9a-f]+ <[^>]+> f00f c24b le lr, fffffb84 <.*>
+0[0-9a-f]+ <[^>]+> f02f c007 le 00000010 <.*>
0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
#...
diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp
index 5471895e63a68c0ee5e9c9644564e7b9235a4184..7d3217f87a26303f776d2390cdab9a426ef3d3e9 100644
--- a/ld/testsuite/ld-arm/arm-elf.exp
+++ b/ld/testsuite/ld-arm/arm-elf.exp
@@ -42,6 +42,11 @@ if {[istarget "arm-*-vxworks"]} {
"" {vxworks2.s}
{{readelf --segments vxworks2-static.sd}}
"vxworks2"}
+ {"Branch future relocations for armv8.1-m.main target"
+ "-static -T arm.ld"
+ "" "" {bfs-0.s bfs-1.s}
+ {{objdump -dw branch-futures.d}}
+ "branch-futures"}
}
run_ld_link_tests $armvxworkstests
run_dump_test "vxworks1-static"
@@ -260,6 +265,10 @@ set armelftests_common_3 {
{"ADDS thumb1 relocations for armv7-m target" "-static -T arm.ld" "" "" {thumb1-adds-armv7-m.s}
{{objdump -dw thumb1-adds.d}}
"thumb1-adds"}
+ {"Branch future relocations for armv8.1-m.main target" "-static -T arm.ld"
+ "" "" {bfs-0.s bfs-1.s}
+ {{objdump -dw branch-futures.d}}
+ "branch-futures"}
}
run_ld_link_tests $armelftests_common_1
diff --git a/ld/testsuite/ld-arm/bfs-0.s b/ld/testsuite/ld-arm/bfs-0.s
new file mode 100644
index 0000000000000000000000000000000000000000..844417a56c6f35e56716ef929d3a81f09b7615b2
--- /dev/null
+++ b/ld/testsuite/ld-arm/bfs-0.s
@@ -0,0 +1,12 @@
+.arch armv8.1-m.main
+.text
+.syntax unified
+.thumb
+future:
+ bf branch, target
+ bfcsel branch, target, else, eq
+ bfl branch, target
+ add r0, r0, r1
+branch:
+ b target
+else:
diff --git a/ld/testsuite/ld-arm/bfs-1.s b/ld/testsuite/ld-arm/bfs-1.s
new file mode 100644
index 0000000000000000000000000000000000000000..2b72819598edf1509d12cf8b01e5d2028bddda38
--- /dev/null
+++ b/ld/testsuite/ld-arm/bfs-1.s
@@ -0,0 +1,9 @@
+.arch armv8.1-m.main
+.text
+.syntax unified
+.thumb
+.global _start
+.global target
+_start:
+target:
+ add r0, r0, r1
diff --git a/ld/testsuite/ld-arm/branch-futures.d b/ld/testsuite/ld-arm/branch-futures.d
new file mode 100644
index 0000000000000000000000000000000000000000..427ecce62a4d2f22b3b64fe03435802845c567cf
--- /dev/null
+++ b/ld/testsuite/ld-arm/branch-futures.d
@@ -0,0 +1,17 @@
+
+.*: file format elf32-.*
+
+
+Disassembly of section .text:
+
+0[0-9a-f]+ <future>:
+ [0-9a-f]+: f2c0 e807 bf a, 8012 <_start>
+ [0-9a-f]+: f182 e805 bfcsel 6, 8012 <_start>, a, eq
+ [0-9a-f]+: f080 c803 bfl 2, 8012 <_start>
+ [0-9a-f]+: 4408 add r0, r1
+
+0[0-9a-f]+ <branch>:
+ [0-9a-f]+: f000 b800 b.w 8012 <_start>
+
+0[0-9a-f]+ <_start>:
+ [0-9a-f]+: 4408 add r0, r1
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline
2019-05-01 9:32 ` Andre Vieira (lists)
@ 2019-05-02 1:21 ` Alan Modra
2019-05-15 15:34 ` Andre Vieira (lists)
0 siblings, 1 reply; 32+ messages in thread
From: Alan Modra @ 2019-05-02 1:21 UTC (permalink / raw)
To: Andre Vieira (lists); +Cc: nickc, binutils, sudi.das
On Wed, May 01, 2019 at 10:32:17AM +0100, Andre Vieira (lists) wrote:
> As for the vxworks failures Alan spotted, I believe this is due to the
> relocations being treated differently, as you pointed out one uses REL and
> the other RELA. This leads to different relocation encodings. So for
> instance when a REL target encodes a relocation for 'target' it seems to do
> so with:
> A = 0
> S = target
>
> whereas for RELA it uses:
> A = 4
> S = target-4
No, this is confused. The "A" you are showing here is the value
displayed by objdump after decoding. This is completely irrelevant.
In actual fact the value of "A", the addend as per the ABI, is -4 for
both REL and RELA. "S" is the symbol, ie. "target" (there is no such
thing as S = target-4).
For your first testcase, armv8_1-m-bf-rel.d, you expect
f0df e7ff bf 2, 00000000 <.target>
0: R_ARM_THM_BF16 .target
If you squint at that instruction long enough, you'll see that the
instruction (split) field is indeed -4, and since addends are taken
from the instruction for REL relocations, "A" is -4.
armv8_1-m-bf-rela.d expects
f0c0 e001 bf 2, 00000004 <.target\+0x4>
0: R_ARM_THM_BF16 .target-0x4
Here the instruction field is left as 0 (the value of the field
doesn't matter), and "A" of -4 is taken from the RELA relocation
addend.
I believe the reason for the -4 addend is that ARM processors
calculate branch targets relative to the insn PC plus 4 for 4-byte
insns. So I don't have any problem with the patch itself, but wanted
to clear up any confusion in your patch explanation. Approval of the
patch will be handled by one of the ARM maintainers.
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline
2019-05-02 1:21 ` Alan Modra
@ 2019-05-15 15:34 ` Andre Vieira (lists)
2019-05-20 10:31 ` Nick Clifton
0 siblings, 1 reply; 32+ messages in thread
From: Andre Vieira (lists) @ 2019-05-15 15:34 UTC (permalink / raw)
To: Alan Modra; +Cc: nickc, binutils, sudi.das
Ping, this one still needs an OK.
Cheers,
Andre
On 02/05/2019 02:21, Alan Modra wrote:
> On Wed, May 01, 2019 at 10:32:17AM +0100, Andre Vieira (lists) wrote:
>> As for the vxworks failures Alan spotted, I believe this is due to the
>> relocations being treated differently, as you pointed out one uses REL and
>> the other RELA. This leads to different relocation encodings. So for
>> instance when a REL target encodes a relocation for 'target' it seems to do
>> so with:
>> A = 0
>> S = target
>>
>> whereas for RELA it uses:
>> A = 4
>> S = target-4
>
> No, this is confused. The "A" you are showing here is the value
> displayed by objdump after decoding. This is completely irrelevant.
> In actual fact the value of "A", the addend as per the ABI, is -4 for
> both REL and RELA. "S" is the symbol, ie. "target" (there is no such
> thing as S = target-4).
>
> For your first testcase, armv8_1-m-bf-rel.d, you expect
> f0df e7ff bf 2, 00000000 <.target>
> 0: R_ARM_THM_BF16 .target
> If you squint at that instruction long enough, you'll see that the
> instruction (split) field is indeed -4, and since addends are taken
> from the instruction for REL relocations, "A" is -4.
>
> armv8_1-m-bf-rela.d expects
> f0c0 e001 bf 2, 00000004 <.target\+0x4>
> 0: R_ARM_THM_BF16 .target-0x4
> Here the instruction field is left as 0 (the value of the field
> doesn't matter), and "A" of -4 is taken from the RELA relocation
> addend.
>
> I believe the reason for the -4 addend is that ARM processors
> calculate branch targets relative to the insn PC plus 4 for 4-byte
> insns. So I don't have any problem with the patch itself, but wanted
> to clear up any confusion in your patch explanation. Approval of the
> patch will be handled by one of the ARM maintainers.
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline
2019-05-15 15:34 ` Andre Vieira (lists)
@ 2019-05-20 10:31 ` Nick Clifton
0 siblings, 0 replies; 32+ messages in thread
From: Nick Clifton @ 2019-05-20 10:31 UTC (permalink / raw)
To: Andre Vieira (lists), Alan Modra; +Cc: binutils, sudi.das
Hi Andre,
> Ping, this one still needs an OK.
oopsie...
Patch series approved - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2019-05-20 10:31 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-04 13:24 [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Andre Vieira (lists)
2019-04-04 13:28 ` [PATCH, binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI Andre Vieira (lists)
2019-04-04 13:28 ` [PATCH, GAS, ARM, 2/16] Add CLI extension support for Armv8.1-M Mainline Andre Vieira (lists)
2019-04-04 13:34 ` [PATCH, binutils, ARM, 4/16] BF insns infrastructure with array of relocs in struct arm_it Andre Vieira (lists)
2019-04-04 13:34 ` [PATCH, binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real for fallback branch Andre Vieira (lists)
2019-04-04 13:36 ` [PATCH, binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM_BF16 Andre Vieira (lists)
2019-04-04 13:37 ` [PATCH, binutils, ARM, 6/16] New BF instruction for Armv8.1-M Mainline Andre Vieira (lists)
2019-04-12 10:41 ` Andre Vieira (lists)
2019-04-04 13:38 ` [PATCH, binutils, ARM, 7/16] New BFX and BFLX " Andre Vieira (lists)
2019-04-04 13:38 ` [PATCH, binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18 Andre Vieira (lists)
2019-04-04 13:39 ` [PATCH, binutils, ARM, 9/16] New BFL instruction for Armv8.1-M Mainline Andre Vieira (lists)
2019-04-12 10:40 ` Andre Vieira (lists)
2019-04-04 13:40 ` [PATCH, binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_BF12 Andre Vieira (lists)
2019-04-04 13:41 ` [PATCH, binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Mainline Andre Vieira (lists)
2019-04-12 10:40 ` Andre Vieira (lists)
2019-04-04 13:41 ` [PATCH, binutils, ARM, 11/16] New BFCSEL instruction " Andre Vieira (lists)
2019-04-12 10:39 ` Andre Vieira (lists)
2019-04-04 13:42 ` [PATCH, binutils, ARM, 13/16] Add support for CLRM Andre Vieira (lists)
2019-04-04 13:43 ` [PATCH, opcodes, ARM, 14/16] Add mode availability to coprocessor table entries Andre Vieira (lists)
2019-04-04 13:44 ` [PATCH, binutils, ARM, 16/16] Add support to VLDR and VSTR of system registers Andre Vieira (lists)
2019-04-04 13:44 ` [PATCH, binutils, ARM, 15/16] Add support for VSCCLRM Andre Vieira (lists)
2019-04-11 10:04 ` [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Nick Clifton
2019-04-12 10:39 ` Andre Vieira (lists)
2019-04-12 13:51 ` Nick Clifton
2019-04-15 9:41 ` Andre Simoes Dias Vieira
2019-04-16 1:58 ` Alan Modra
2019-04-16 11:52 ` Andre Simoes Dias Vieira
2019-04-16 12:36 ` Alan Modra
2019-05-01 9:32 ` Andre Vieira (lists)
2019-05-02 1:21 ` Alan Modra
2019-05-15 15:34 ` Andre Vieira (lists)
2019-05-20 10:31 ` Nick Clifton
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