* [PATCH V2 7/9] ld: add support for eBPF
2019-05-22 15:26 [PATCH V2 0/9] eBPF support for GNU binutils Jose E. Marchesi
` (4 preceding siblings ...)
2019-05-22 15:24 ` [PATCH V2 6/9] gas: " Jose E. Marchesi
@ 2019-05-22 15:24 ` Jose E. Marchesi
2019-05-22 15:24 ` [PATCH V2 4/9] cpu: add eBPF cpu description Jose E. Marchesi
` (4 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Jose E. Marchesi @ 2019-05-22 15:24 UTC (permalink / raw)
To: binutils
This patch adds support to the linker for the Linux eBPF architecture.
A minimal testsuite is included.
ld/ChangeLog:
2019-05-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* Makefile.am (ALL_64_EMULATION_SOURCES): Add eelf64bpf.c.
* Makefile.in (prefix): Regenerate.
* configure.tgt (targ_extra_ofiles): Add case for bpf-*-* targets.
* emulparams/elf64bpf.sh: New file.
* testsuite/lib/ld-lib.exp (check_gc_sections_available): Add
bpf-*-* to the list of targets not supporting gc-sections.
* testsuite/ld-bpf/bar.s: New file.
* testsuite/ld-bpf/jump-1.d: Likewise.
* testsuite/ld-bpf/foo.s: Likewise.
* testsuite/ld-bpf/call-1.d: Likewise.
* testsuite/ld-bpf/bpf.exp: Likewise.
* testsuite/ld-bpf/baz.s: Likewise.
---
ld/ChangeLog | 15 +++++++++++++++
ld/Makefile.am | 2 ++
ld/Makefile.in | 4 ++++
ld/configure | 28 ++++++++++++++++++++--------
ld/configure.tgt | 1 +
ld/emulparams/elf64bpf.sh | 10 ++++++++++
ld/testsuite/ld-bpf/bar.s | 5 +++++
ld/testsuite/ld-bpf/baz.s | 5 +++++
ld/testsuite/ld-bpf/bpf.exp | 29 +++++++++++++++++++++++++++++
ld/testsuite/ld-bpf/call-1.d | 23 +++++++++++++++++++++++
ld/testsuite/ld-bpf/foo.s | 5 +++++
ld/testsuite/ld-bpf/jump-1.d | 23 +++++++++++++++++++++++
ld/testsuite/lib/ld-lib.exp | 1 +
13 files changed, 143 insertions(+), 8 deletions(-)
create mode 100644 ld/emulparams/elf64bpf.sh
create mode 100644 ld/testsuite/ld-bpf/bar.s
create mode 100644 ld/testsuite/ld-bpf/baz.s
create mode 100644 ld/testsuite/ld-bpf/bpf.exp
create mode 100644 ld/testsuite/ld-bpf/call-1.d
create mode 100644 ld/testsuite/ld-bpf/foo.s
create mode 100644 ld/testsuite/ld-bpf/jump-1.d
diff --git a/ld/Makefile.am b/ld/Makefile.am
index 4a0bb15227..0509c2e50f 100644
--- a/ld/Makefile.am
+++ b/ld/Makefile.am
@@ -423,6 +423,7 @@ ALL_64_EMULATION_SOURCES = \
eelf32ltsmipn32_fbsd.c \
eelf32mipswindiss.c \
eelf64_aix.c \
+ eelf64bpf.c \
eelf64_ia64.c \
eelf64_ia64_fbsd.c \
eelf64_ia64_vms.c \
@@ -907,6 +908,7 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ltsmipn32_fbsd.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32mipswindiss.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_aix.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64bpf.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64_fbsd.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64_vms.Pc@am__quote@
diff --git a/ld/Makefile.in b/ld/Makefile.in
index fbccfbc9d7..9bc14f76c8 100644
--- a/ld/Makefile.in
+++ b/ld/Makefile.in
@@ -521,6 +521,7 @@ pdfdir = @pdfdir@
prefix = @prefix@
program_transform_name = @program_transform_name@
psdir = @psdir@
+runstatedir = @runstatedir@
sbindir = @sbindir@
sharedstatedir = @sharedstatedir@
srcdir = @srcdir@
@@ -909,6 +910,7 @@ ALL_64_EMULATION_SOURCES = \
eelf32ltsmipn32_fbsd.c \
eelf32mipswindiss.c \
eelf64_aix.c \
+ eelf64bpf.c \
eelf64_ia64.c \
eelf64_ia64_fbsd.c \
eelf64_ia64_vms.c \
@@ -1359,6 +1361,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha_fbsd.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha_nbsd.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64bmip.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64bpf.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64btsmip.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64btsmip_fbsd.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64hppa.Po@am__quote@
@@ -2507,6 +2510,7 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ltsmipn32_fbsd.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32mipswindiss.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_aix.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64bpf.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64_fbsd.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64_vms.Pc@am__quote@
diff --git a/ld/configure b/ld/configure
index 3b50f5db8e..9952489f8c 100755
--- a/ld/configure
+++ b/ld/configure
@@ -786,6 +786,7 @@ infodir
docdir
oldincludedir
includedir
+runstatedir
localstatedir
sharedstatedir
sysconfdir
@@ -888,6 +889,7 @@ datadir='${datarootdir}'
sysconfdir='${prefix}/etc'
sharedstatedir='${prefix}/com'
localstatedir='${prefix}/var'
+runstatedir='${localstatedir}/run'
includedir='${prefix}/include'
oldincludedir='/usr/include'
docdir='${datarootdir}/doc/${PACKAGE_TARNAME}'
@@ -1140,6 +1142,15 @@ do
| -silent | --silent | --silen | --sile | --sil)
silent=yes ;;
+ -runstatedir | --runstatedir | --runstatedi | --runstated \
+ | --runstate | --runstat | --runsta | --runst | --runs \
+ | --run | --ru | --r)
+ ac_prev=runstatedir ;;
+ -runstatedir=* | --runstatedir=* | --runstatedi=* | --runstated=* \
+ | --runstate=* | --runstat=* | --runsta=* | --runst=* | --runs=* \
+ | --run=* | --ru=* | --r=*)
+ runstatedir=$ac_optarg ;;
+
-sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
ac_prev=sbindir ;;
-sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
@@ -1277,7 +1288,7 @@ fi
for ac_var in exec_prefix prefix bindir sbindir libexecdir datarootdir \
datadir sysconfdir sharedstatedir localstatedir includedir \
oldincludedir docdir infodir htmldir dvidir pdfdir psdir \
- libdir localedir mandir
+ libdir localedir mandir runstatedir
do
eval ac_val=\$$ac_var
# Remove trailing slashes.
@@ -1430,6 +1441,7 @@ Fine tuning of the installation directories:
--sysconfdir=DIR read-only single-machine data [PREFIX/etc]
--sharedstatedir=DIR modifiable architecture-independent data [PREFIX/com]
--localstatedir=DIR modifiable single-machine data [PREFIX/var]
+ --runstatedir=DIR modifiable per-process data [LOCALSTATEDIR/run]
--libdir=DIR object code libraries [EPREFIX/lib]
--includedir=DIR C header files [PREFIX/include]
--oldincludedir=DIR C header files for non-gcc [/usr/include]
@@ -12027,7 +12039,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 12030 "configure"
+#line 12042 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -12133,7 +12145,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 12136 "configure"
+#line 12148 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -15536,7 +15548,7 @@ else
We can't simply define LARGE_OFF_T to be 9223372036854775807,
since some C++ compilers masquerading as C compilers
incorrectly reject 9223372036854775807. */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
&& LARGE_OFF_T % 2147483647 == 1)
? 1 : -1];
@@ -15582,7 +15594,7 @@ else
We can't simply define LARGE_OFF_T to be 9223372036854775807,
since some C++ compilers masquerading as C compilers
incorrectly reject 9223372036854775807. */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
&& LARGE_OFF_T % 2147483647 == 1)
? 1 : -1];
@@ -15606,7 +15618,7 @@ rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
We can't simply define LARGE_OFF_T to be 9223372036854775807,
since some C++ compilers masquerading as C compilers
incorrectly reject 9223372036854775807. */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
&& LARGE_OFF_T % 2147483647 == 1)
? 1 : -1];
@@ -15651,7 +15663,7 @@ else
We can't simply define LARGE_OFF_T to be 9223372036854775807,
since some C++ compilers masquerading as C compilers
incorrectly reject 9223372036854775807. */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
&& LARGE_OFF_T % 2147483647 == 1)
? 1 : -1];
@@ -15675,7 +15687,7 @@ rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
We can't simply define LARGE_OFF_T to be 9223372036854775807,
since some C++ compilers masquerading as C compilers
incorrectly reject 9223372036854775807. */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
&& LARGE_OFF_T % 2147483647 == 1)
? 1 : -1];
diff --git a/ld/configure.tgt b/ld/configure.tgt
index e92d4484b4..c81bc8a7d8 100644
--- a/ld/configure.tgt
+++ b/ld/configure.tgt
@@ -182,6 +182,7 @@ bfin-*-linux-uclibc*) targ_emul=elf32bfinfd;
targ_extra_emuls="elf32bfin"
targ_extra_libpath=$targ_extra_emuls
;;
+bpf-*-*) targ_emul=elf64bpf ;;
cr16-*-elf*) targ_emul=elf32cr16 ;;
cr16c-*-elf*) targ_emul=elf32cr16c
;;
diff --git a/ld/emulparams/elf64bpf.sh b/ld/emulparams/elf64bpf.sh
new file mode 100644
index 0000000000..39b23f0451
--- /dev/null
+++ b/ld/emulparams/elf64bpf.sh
@@ -0,0 +1,10 @@
+TEMPLATE_NAME=elf32
+SCRIPT_NAME=elf
+BIG_OUTPUT_FORMAT="elf64-bpfbe"
+LITTLE_OUTPUT_FORMAT="elf64-bpfle"
+OUTPUT_FORMAT="$LITTLE_OUTPUT_FORMAT"
+ARCH=bpf
+MACHINE=
+TARGET_PAGE_SIZE=0x1000
+# XXX this is arbitrary, for now
+TEXT_START_ADDR=0x00400000
diff --git a/ld/testsuite/ld-bpf/bar.s b/ld/testsuite/ld-bpf/bar.s
new file mode 100644
index 0000000000..b577d87d74
--- /dev/null
+++ b/ld/testsuite/ld-bpf/bar.s
@@ -0,0 +1,5 @@
+ .global bar
+bar:
+ mov %r1,%r2
+ mov %r3,%r1
+ exit
diff --git a/ld/testsuite/ld-bpf/baz.s b/ld/testsuite/ld-bpf/baz.s
new file mode 100644
index 0000000000..2e159a8829
--- /dev/null
+++ b/ld/testsuite/ld-bpf/baz.s
@@ -0,0 +1,5 @@
+ mov %r1,1
+ mov %r2,2
+ mov %r3,3
+ ja bar
+ exit
diff --git a/ld/testsuite/ld-bpf/bpf.exp b/ld/testsuite/ld-bpf/bpf.exp
new file mode 100644
index 0000000000..02b2e03021
--- /dev/null
+++ b/ld/testsuite/ld-bpf/bpf.exp
@@ -0,0 +1,29 @@
+# Copyright (C) 2019 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+if { ![istarget bpf*-*-*] } {
+ return
+}
+
+set bpf_test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+foreach bpf_test $bpf_test_list {
+ verbose [file rootname $bpf_test]
+ run_dump_test [file rootname $bpf_test]
+}
diff --git a/ld/testsuite/ld-bpf/call-1.d b/ld/testsuite/ld-bpf/call-1.d
new file mode 100644
index 0000000000..f408cd4db9
--- /dev/null
+++ b/ld/testsuite/ld-bpf/call-1.d
@@ -0,0 +1,23 @@
+#as: --EL
+#source: foo.s
+#source: bar.s
+#objdump: -dr
+#ld: -EL
+#warning: .*cannot find entry symbol _start.*
+#name: CALL with disp32 reloc
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+ *[0-9a-f]+: b7 01 00 00 01 00 00 00 mov %r1,1
+ *[0-9a-f]+: b7 02 00 00 02 00 00 00 mov %r2,2
+ *[0-9a-f]+: b7 03 00 00 03 00 00 00 mov %r3,3
+ *[0-9a-f]+: 85 10 00 00 01 00 00 00 call 1
+ *[0-9a-f]+: 95 00 00 00 00 00 00 00 exit
+
+[0-9a-f]+ <bar>:
+ *[0-9a-f]+: bf 21 00 00 00 00 00 00 mov %r1,%r2
+ *[0-9a-f]+: bf 13 00 00 00 00 00 00 mov %r3,%r1
+ *[0-9a-f]+: 95 00 00 00 00 00 00 00 exit
diff --git a/ld/testsuite/ld-bpf/foo.s b/ld/testsuite/ld-bpf/foo.s
new file mode 100644
index 0000000000..0958bbf67c
--- /dev/null
+++ b/ld/testsuite/ld-bpf/foo.s
@@ -0,0 +1,5 @@
+ mov %r1,1
+ mov %r2,2
+ mov %r3,3
+ call bar
+ exit
diff --git a/ld/testsuite/ld-bpf/jump-1.d b/ld/testsuite/ld-bpf/jump-1.d
new file mode 100644
index 0000000000..b57bcf1f40
--- /dev/null
+++ b/ld/testsuite/ld-bpf/jump-1.d
@@ -0,0 +1,23 @@
+#as: --EL
+#source: baz.s
+#source: bar.s
+#objdump: -dr
+#ld: -EL
+#warning: .*cannot find entry symbol _start.*
+#name: jump with disp16 reloc
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+ *[0-9a-f]+: b7 01 00 00 01 00 00 00 mov %r1,1
+ *[0-9a-f]+: b7 02 00 00 02 00 00 00 mov %r2,2
+ *[0-9a-f]+: b7 03 00 00 03 00 00 00 mov %r3,3
+ *[0-9a-f]+: 05 00 01 00 00 00 00 00 ja 1
+ *[0-9a-f]+: 95 00 00 00 00 00 00 00 exit
+
+[0-9a-f]+ <bar>:
+ *[0-9a-f]+: bf 21 00 00 00 00 00 00 mov %r1,%r2
+ *[0-9a-f]+: bf 13 00 00 00 00 00 00 mov %r3,%r1
+ *[0-9a-f]+: 95 00 00 00 00 00 00 00 exit
diff --git a/ld/testsuite/lib/ld-lib.exp b/ld/testsuite/lib/ld-lib.exp
index 0ff51c9526..5ebb7fa35f 100644
--- a/ld/testsuite/lib/ld-lib.exp
+++ b/ld/testsuite/lib/ld-lib.exp
@@ -1045,6 +1045,7 @@ proc check_gc_sections_available { } {
# Some targets don't support gc-sections despite whatever's
# advertised by ld's options.
if { [istarget alpha-*-*]
+ || [istarget bpf-*-*]
|| [istarget d30v-*-*]
|| [istarget dlx-*-*]
|| [istarget hppa*64-*-*]
--
2.11.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH V2 5/9] opcodes: add support for eBPF
2019-05-22 15:26 [PATCH V2 0/9] eBPF support for GNU binutils Jose E. Marchesi
2019-05-22 15:24 ` [PATCH V2 9/9] binutils: add myself as the maintainer for BPF Jose E. Marchesi
@ 2019-05-22 15:24 ` Jose E. Marchesi
2019-05-22 15:24 ` [PATCH V2 2/9] include: add elf/bpf.h Jose E. Marchesi
` (8 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Jose E. Marchesi @ 2019-05-22 15:24 UTC (permalink / raw)
To: binutils
This patch adds support for the Linux kernel eBPF architecture to the
opcodes. The port is based on CGEN.
opcodes/ChangeLog:
2019-05-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
* configure: Regenerated.
* Makefile.am: Add rules for the files generated from cpu/bpf.cpu
and cpu/bpf.opc.
(HFILES): Add bpf-desc.h and bpf-opc.h.
(TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
bpf-ibld.c and bpf-opc.c.
(BPF_DEPS): Define.
* Makefile.in: Regenerated.
* disassemble.c (ARCH_bpf): Define.
(disassembler): Add case for bfd_arch_bpf.
(disassemble_init_for_target): Likewise.
(enum epbf_isa_attr): Define.
* disassemble.h: extern print_insn_bpf.
* bpf-asm.c: Generated.
* bpf-opc.h: Likewise.
* bpf-opc.c: Likewise.
* bpf-ibld.c: Likewise.
* bpf-dis.c: Likewise.
* bpf-desc.h: Likewise.
* bpf-desc.c: Likewise.
---
opcodes/ChangeLog | 24 +
opcodes/Makefile.am | 17 +
opcodes/Makefile.in | 23 +
opcodes/bpf-asm.c | 590 ++++++++++++++++++
opcodes/bpf-desc.c | 1638 +++++++++++++++++++++++++++++++++++++++++++++++++
opcodes/bpf-desc.h | 266 ++++++++
opcodes/bpf-dis.c | 624 +++++++++++++++++++
opcodes/bpf-ibld.c | 956 +++++++++++++++++++++++++++++
opcodes/bpf-opc.c | 1495 ++++++++++++++++++++++++++++++++++++++++++++
opcodes/bpf-opc.h | 151 +++++
opcodes/configure | 19 +-
opcodes/configure.ac | 1 +
opcodes/disassemble.c | 35 ++
opcodes/disassemble.h | 1 +
14 files changed, 5837 insertions(+), 3 deletions(-)
create mode 100644 opcodes/bpf-asm.c
create mode 100644 opcodes/bpf-desc.c
create mode 100644 opcodes/bpf-desc.h
create mode 100644 opcodes/bpf-dis.c
create mode 100644 opcodes/bpf-ibld.c
create mode 100644 opcodes/bpf-opc.c
create mode 100644 opcodes/bpf-opc.h
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index 458a2b56c5..20a8a8d2c0 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -59,6 +59,7 @@ BUILD_LIB_DEPS = @BUILD_LIB_DEPS@
# Header files.
HFILES = \
aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \
+ bpf-desc.h bpf-opc.h \
epiphany-desc.h epiphany-opc.h \
fr30-desc.h fr30-opc.h \
frv-desc.h frv-opc.h \
@@ -117,6 +118,11 @@ TARGET_LIBOPCODES_CFILES = \
d30v-dis.c \
d30v-opc.c \
dlx-dis.c \
+ bpf-asm.c \
+ bpf-desc.c \
+ bpf-dis.c \
+ bpf-ibld.c \
+ bpf-opc.c \
epiphany-asm.c \
epiphany-desc.c \
epiphany-dis.c \
@@ -370,6 +376,7 @@ CGENDEPS = \
CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xc16x xstormy16
if CGEN_MAINT
+BPF_DEPS = stamp-bpf
EPIPHANY_DEPS = stamp-epiphany
FR30_DEPS = stamp-fr30
FRV_DEPS = stamp-frv
@@ -384,6 +391,7 @@ OR1K_DEPS = stamp-or1k
XC16X_DEPS = stamp-xc16x
XSTORMY16_DEPS = stamp-xstormy16
else
+BPF_DEPS =
EPIPHANY_DEPS =
FR30_DEPS =
FRV_DEPS =
@@ -416,6 +424,15 @@ run-cgen-all:
# For now, require developers to configure with --enable-cgen-maint.
+$(srcdir)/bpf-desc.h $(srcdir)/bpf-desc.c $(srcdir)/bpf-opc.h \
+ $(srcdir)/bpf-opc.c $(srcdir)/bpf-ibld.c \
+ $(srcdir)/bpf-asm.c $(srcdir)/bpf-dis.c: $(BPF_DEPS)
+ @true
+
+stamp-bpf: $(CGENDEPS) $(CPUDIR)/bpf.cpu $(CPUDIR)/bpf.opc
+ $(MAKE) run-cgen arch=bpf prefix=bpf \
+ archfile=$(CPUDIR)/bpf.cpu opcfile=$(CPUDIR)/bpf.opc
+
$(srcdir)/epiphany-desc.h $(srcdir)/epiphany-desc.c $(srcdir)/epiphany-opc.h \
$(srcdir)/epiphany-opc.c $(srcdir)/epiphany-ibld.c \
$(srcdir)/epiphany-opinst.c $(srcdir)/epiphany-asm.c \
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index 3277ba954a..ee8b31153f 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -408,6 +408,7 @@ pdfdir = @pdfdir@
prefix = @prefix@
program_transform_name = @program_transform_name@
psdir = @psdir@
+runstatedir = @runstatedir@
sbindir = @sbindir@
sharedstatedir = @sharedstatedir@
srcdir = @srcdir@
@@ -448,6 +449,7 @@ BFD_H = ../bfd/bfd.h
# Header files.
HFILES = \
aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \
+ bpf-desc.h bpf-opc.h \
epiphany-desc.h epiphany-opc.h \
fr30-desc.h fr30-opc.h \
frv-desc.h frv-opc.h \
@@ -507,6 +509,11 @@ TARGET_LIBOPCODES_CFILES = \
d30v-dis.c \
d30v-opc.c \
dlx-dis.c \
+ bpf-asm.c \
+ bpf-desc.c \
+ bpf-dis.c \
+ bpf-ibld.c \
+ bpf-opc.c \
epiphany-asm.c \
epiphany-desc.c \
epiphany-dis.c \
@@ -725,6 +732,8 @@ CGENDEPS = \
cgen-asm.in cgen-dis.in cgen-ibld.in
CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xc16x xstormy16
+@CGEN_MAINT_FALSE@BPF_DEPS =
+@CGEN_MAINT_TRUE@BPF_DEPS = stamp-bpf
@CGEN_MAINT_FALSE@EPIPHANY_DEPS =
@CGEN_MAINT_TRUE@EPIPHANY_DEPS = stamp-epiphany
@CGEN_MAINT_FALSE@FR30_DEPS =
@@ -897,6 +906,11 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arm-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/avr-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bfin-dis.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-asm.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-desc.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-dis.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-ibld.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cgen-asm.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cgen-bitset.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cgen-dis.Plo@am__quote@
@@ -1398,6 +1412,15 @@ run-cgen-all:
# For now, require developers to configure with --enable-cgen-maint.
+$(srcdir)/bpf-desc.h $(srcdir)/bpf-desc.c $(srcdir)/bpf-opc.h \
+ $(srcdir)/bpf-opc.c $(srcdir)/bpf-ibld.c \
+ $(srcdir)/bpf-asm.c $(srcdir)/bpf-dis.c: $(BPF_DEPS)
+ @true
+
+stamp-bpf: $(CGENDEPS) $(CPUDIR)/bpf.cpu $(CPUDIR)/bpf.opc
+ $(MAKE) run-cgen arch=bpf prefix=bpf \
+ archfile=$(CPUDIR)/bpf.cpu opcfile=$(CPUDIR)/bpf.opc
+
$(srcdir)/epiphany-desc.h $(srcdir)/epiphany-desc.c $(srcdir)/epiphany-opc.h \
$(srcdir)/epiphany-opc.c $(srcdir)/epiphany-ibld.c \
$(srcdir)/epiphany-opinst.c $(srcdir)/epiphany-asm.c \
diff --git a/opcodes/bpf-asm.c b/opcodes/bpf-asm.c
new file mode 100644
index 0000000000..4332edcc5e
--- /dev/null
+++ b/opcodes/bpf-asm.c
@@ -0,0 +1,590 @@
+/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
+/* Assembler interface for targets using CGEN. -*- C -*-
+ CGEN: Cpu tools GENerator
+
+ THIS FILE IS MACHINE GENERATED WITH CGEN.
+ - the resultant file is machine generated, cgen-asm.in isn't
+
+ Copyright (C) 1996-2019 Free Software Foundation, Inc.
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+ Keep that in mind. */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "bpf-desc.h"
+#include "bpf-opc.h"
+#include "opintl.h"
+#include "xregex.h"
+#include "libiberty.h"
+#include "safe-ctype.h"
+
+#undef min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+static const char * parse_insn_normal
+ (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
+\f
+/* -- assembler routines inserted here. */
+
+/* -- asm.c */
+
+/* Parse a signed 64-bit immediate. */
+
+static const char *
+parse_imm64 (CGEN_CPU_DESC cd,
+ const char **strp,
+ int opindex,
+ int64_t *valuep)
+{
+ bfd_vma value;
+ enum cgen_parse_operand_result result;
+ const char *errmsg;
+
+ errmsg = (* cd->parse_operand_fn)
+ (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE,
+ &result, &value);
+ if (!errmsg)
+ *valuep = value;
+
+ return errmsg;
+}
+
+/* Endianness size operands are integer immediates whose values can be
+ 16, 32 or 64. */
+
+static const char *
+parse_endsize (CGEN_CPU_DESC cd,
+ const char **strp,
+ int opindex,
+ unsigned long *valuep)
+{
+ const char *errmsg;
+
+ errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+ if (errmsg)
+ return errmsg;
+
+ switch (*valuep)
+ {
+ case 16:
+ case 32:
+ case 64:
+ break;
+ default:
+ return _("expected 16, 32 or 64 in");
+ }
+
+ return NULL;
+}
+
+/* Special check to ensure that the right instruction variant is used
+ for the given endianness induced by the ISA selected in the CPU.
+ See bpf.cpu for a discussion on how eBPF is really two instruction
+ sets. */
+
+int
+bpf_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
+{
+ CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA);
+
+ return cgen_bitset_intersect_p (&isas, cd->isas);
+}
+
+\f
+/* -- dis.c */
+
+const char * bpf_cgen_parse_operand
+ (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
+
+/* Main entry point for operand parsing.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `parse_insn_normal', but keeping it
+ separate makes clear the interface between `parse_insn_normal' and each of
+ the handlers. */
+
+const char *
+bpf_cgen_parse_operand (CGEN_CPU_DESC cd,
+ int opindex,
+ const char ** strp,
+ CGEN_FIELDS * fields)
+{
+ const char * errmsg = NULL;
+ /* Used by scalar operands that still need to be parsed. */
+ long junk ATTRIBUTE_UNUSED;
+
+ switch (opindex)
+ {
+ case BPF_OPERAND_DISP16 :
+ errmsg = cgen_parse_signed_integer (cd, strp, BPF_OPERAND_DISP16, (long *) (& fields->f_offset16));
+ break;
+ case BPF_OPERAND_DISP32 :
+ errmsg = cgen_parse_signed_integer (cd, strp, BPF_OPERAND_DISP32, (long *) (& fields->f_imm32));
+ break;
+ case BPF_OPERAND_DSTBE :
+ errmsg = cgen_parse_keyword (cd, strp, & bpf_cgen_opval_h_gpr, & fields->f_dstbe);
+ break;
+ case BPF_OPERAND_DSTLE :
+ errmsg = cgen_parse_keyword (cd, strp, & bpf_cgen_opval_h_gpr, & fields->f_dstle);
+ break;
+ case BPF_OPERAND_ENDSIZE :
+ errmsg = parse_endsize (cd, strp, BPF_OPERAND_ENDSIZE, (unsigned long *) (& fields->f_imm32));
+ break;
+ case BPF_OPERAND_IMM32 :
+ errmsg = cgen_parse_signed_integer (cd, strp, BPF_OPERAND_IMM32, (long *) (& fields->f_imm32));
+ break;
+ case BPF_OPERAND_IMM64 :
+ errmsg = parse_imm64 (cd, strp, BPF_OPERAND_IMM64, (int64_t *) (& fields->f_imm64));
+ break;
+ case BPF_OPERAND_OFFSET16 :
+ errmsg = cgen_parse_signed_integer (cd, strp, BPF_OPERAND_OFFSET16, (long *) (& fields->f_offset16));
+ break;
+ case BPF_OPERAND_SRCBE :
+ errmsg = cgen_parse_keyword (cd, strp, & bpf_cgen_opval_h_gpr, & fields->f_srcbe);
+ break;
+ case BPF_OPERAND_SRCLE :
+ errmsg = cgen_parse_keyword (cd, strp, & bpf_cgen_opval_h_gpr, & fields->f_srcle);
+ break;
+
+ default :
+ /* xgettext:c-format */
+ opcodes_error_handler
+ (_("internal error: unrecognized field %d while parsing"),
+ opindex);
+ abort ();
+ }
+
+ return errmsg;
+}
+
+cgen_parse_fn * const bpf_cgen_parse_handlers[] =
+{
+ parse_insn_normal,
+};
+
+void
+bpf_cgen_init_asm (CGEN_CPU_DESC cd)
+{
+ bpf_cgen_init_opcode_table (cd);
+ bpf_cgen_init_ibld_table (cd);
+ cd->parse_handlers = & bpf_cgen_parse_handlers[0];
+ cd->parse_operand = bpf_cgen_parse_operand;
+#ifdef CGEN_ASM_INIT_HOOK
+CGEN_ASM_INIT_HOOK
+#endif
+}
+
+\f
+
+/* Regex construction routine.
+
+ This translates an opcode syntax string into a regex string,
+ by replacing any non-character syntax element (such as an
+ opcode) with the pattern '.*'
+
+ It then compiles the regex and stores it in the opcode, for
+ later use by bpf_cgen_assemble_insn
+
+ Returns NULL for success, an error message for failure. */
+
+char *
+bpf_cgen_build_insn_regex (CGEN_INSN *insn)
+{
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+ const char *mnem = CGEN_INSN_MNEMONIC (insn);
+ char rxbuf[CGEN_MAX_RX_ELEMENTS];
+ char *rx = rxbuf;
+ const CGEN_SYNTAX_CHAR_TYPE *syn;
+ int reg_err;
+
+ syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc));
+
+ /* Mnemonics come first in the syntax string. */
+ if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
+ return _("missing mnemonic in syntax string");
+ ++syn;
+
+ /* Generate a case sensitive regular expression that emulates case
+ insensitive matching in the "C" locale. We cannot generate a case
+ insensitive regular expression because in Turkish locales, 'i' and 'I'
+ are not equal modulo case conversion. */
+
+ /* Copy the literal mnemonic out of the insn. */
+ for (; *mnem; mnem++)
+ {
+ char c = *mnem;
+
+ if (ISALPHA (c))
+ {
+ *rx++ = '[';
+ *rx++ = TOLOWER (c);
+ *rx++ = TOUPPER (c);
+ *rx++ = ']';
+ }
+ else
+ *rx++ = c;
+ }
+
+ /* Copy any remaining literals from the syntax string into the rx. */
+ for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+ {
+ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ char c = CGEN_SYNTAX_CHAR (* syn);
+
+ switch (c)
+ {
+ /* Escape any regex metacharacters in the syntax. */
+ case '.': case '[': case '\\':
+ case '*': case '^': case '$':
+
+#ifdef CGEN_ESCAPE_EXTENDED_REGEX
+ case '?': case '{': case '}':
+ case '(': case ')': case '*':
+ case '|': case '+': case ']':
+#endif
+ *rx++ = '\\';
+ *rx++ = c;
+ break;
+
+ default:
+ if (ISALPHA (c))
+ {
+ *rx++ = '[';
+ *rx++ = TOLOWER (c);
+ *rx++ = TOUPPER (c);
+ *rx++ = ']';
+ }
+ else
+ *rx++ = c;
+ break;
+ }
+ }
+ else
+ {
+ /* Replace non-syntax fields with globs. */
+ *rx++ = '.';
+ *rx++ = '*';
+ }
+ }
+
+ /* Trailing whitespace ok. */
+ * rx++ = '[';
+ * rx++ = ' ';
+ * rx++ = '\t';
+ * rx++ = ']';
+ * rx++ = '*';
+
+ /* But anchor it after that. */
+ * rx++ = '$';
+ * rx = '\0';
+
+ CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+ reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+ if (reg_err == 0)
+ return NULL;
+ else
+ {
+ static char msg[80];
+
+ regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80);
+ regfree ((regex_t *) CGEN_INSN_RX (insn));
+ free (CGEN_INSN_RX (insn));
+ (CGEN_INSN_RX (insn)) = NULL;
+ return msg;
+ }
+}
+
+\f
+/* Default insn parser.
+
+ The syntax string is scanned and operands are parsed and stored in FIELDS.
+ Relocs are queued as we go via other callbacks.
+
+ ??? Note that this is currently an all-or-nothing parser. If we fail to
+ parse the instruction, we return 0 and the caller will start over from
+ the beginning. Backtracking will be necessary in parsing subexpressions,
+ but that can be handled there. Not handling backtracking here may get
+ expensive in the case of the m68k. Deal with later.
+
+ Returns NULL for success, an error message for failure. */
+
+static const char *
+parse_insn_normal (CGEN_CPU_DESC cd,
+ const CGEN_INSN *insn,
+ const char **strp,
+ CGEN_FIELDS *fields)
+{
+ /* ??? Runtime added insns not handled yet. */
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ const char *str = *strp;
+ const char *errmsg;
+ const char *p;
+ const CGEN_SYNTAX_CHAR_TYPE * syn;
+#ifdef CGEN_MNEMONIC_OPERANDS
+ /* FIXME: wip */
+ int past_opcode_p;
+#endif
+
+ /* For now we assume the mnemonic is first (there are no leading operands).
+ We can parse it without needing to set up operand parsing.
+ GAS's input scrubber will ensure mnemonics are lowercase, but we may
+ not be called from GAS. */
+ p = CGEN_INSN_MNEMONIC (insn);
+ while (*p && TOLOWER (*p) == TOLOWER (*str))
+ ++p, ++str;
+
+ if (* p)
+ return _("unrecognized instruction");
+
+#ifndef CGEN_MNEMONIC_OPERANDS
+ if (* str && ! ISSPACE (* str))
+ return _("unrecognized instruction");
+#endif
+
+ CGEN_INIT_PARSE (cd);
+ cgen_init_parse_operand (cd);
+#ifdef CGEN_MNEMONIC_OPERANDS
+ past_opcode_p = 0;
+#endif
+
+ /* We don't check for (*str != '\0') here because we want to parse
+ any trailing fake arguments in the syntax string. */
+ syn = CGEN_SYNTAX_STRING (syntax);
+
+ /* Mnemonics come first for now, ensure valid string. */
+ if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
+ abort ();
+
+ ++syn;
+
+ while (* syn != 0)
+ {
+ /* Non operand chars must match exactly. */
+ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ /* FIXME: While we allow for non-GAS callers above, we assume the
+ first char after the mnemonic part is a space. */
+ /* FIXME: We also take inappropriate advantage of the fact that
+ GAS's input scrubber will remove extraneous blanks. */
+ if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn)))
+ {
+#ifdef CGEN_MNEMONIC_OPERANDS
+ if (CGEN_SYNTAX_CHAR(* syn) == ' ')
+ past_opcode_p = 1;
+#endif
+ ++ syn;
+ ++ str;
+ }
+ else if (*str)
+ {
+ /* Syntax char didn't match. Can't be this insn. */
+ static char msg [80];
+
+ /* xgettext:c-format */
+ sprintf (msg, _("syntax error (expected char `%c', found `%c')"),
+ CGEN_SYNTAX_CHAR(*syn), *str);
+ return msg;
+ }
+ else
+ {
+ /* Ran out of input. */
+ static char msg [80];
+
+ /* xgettext:c-format */
+ sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"),
+ CGEN_SYNTAX_CHAR(*syn));
+ return msg;
+ }
+ continue;
+ }
+
+#ifdef CGEN_MNEMONIC_OPERANDS
+ (void) past_opcode_p;
+#endif
+ /* We have an operand of some sort. */
+ errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields);
+ if (errmsg)
+ return errmsg;
+
+ /* Done with this operand, continue with next one. */
+ ++ syn;
+ }
+
+ /* If we're at the end of the syntax string, we're done. */
+ if (* syn == 0)
+ {
+ /* FIXME: For the moment we assume a valid `str' can only contain
+ blanks now. IE: We needn't try again with a longer version of
+ the insn and it is assumed that longer versions of insns appear
+ before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */
+ while (ISSPACE (* str))
+ ++ str;
+
+ if (* str != '\0')
+ return _("junk at end of line"); /* FIXME: would like to include `str' */
+
+ return NULL;
+ }
+
+ /* We couldn't parse it. */
+ return _("unrecognized instruction");
+}
+\f
+/* Main entry point.
+ This routine is called for each instruction to be assembled.
+ STR points to the insn to be assembled.
+ We assume all necessary tables have been initialized.
+ The assembled instruction, less any fixups, is stored in BUF.
+ Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
+ still needs to be converted to target byte order, otherwise BUF is an array
+ of bytes in target byte order.
+ The result is a pointer to the insn's entry in the opcode table,
+ or NULL if an error occured (an error message will have already been
+ printed).
+
+ Note that when processing (non-alias) macro-insns,
+ this function recurses.
+
+ ??? It's possible to make this cpu-independent.
+ One would have to deal with a few minor things.
+ At this point in time doing so would be more of a curiosity than useful
+ [for example this file isn't _that_ big], but keeping the possibility in
+ mind helps keep the design clean. */
+
+const CGEN_INSN *
+bpf_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ const char *str,
+ CGEN_FIELDS *fields,
+ CGEN_INSN_BYTES_PTR buf,
+ char **errmsg)
+{
+ const char *start;
+ CGEN_INSN_LIST *ilist;
+ const char *parse_errmsg = NULL;
+ const char *insert_errmsg = NULL;
+ int recognized_mnemonic = 0;
+
+ /* Skip leading white space. */
+ while (ISSPACE (* str))
+ ++ str;
+
+ /* The instructions are stored in hashed lists.
+ Get the first in the list. */
+ ilist = CGEN_ASM_LOOKUP_INSN (cd, str);
+
+ /* Keep looking until we find a match. */
+ start = str;
+ for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
+ {
+ const CGEN_INSN *insn = ilist->insn;
+ recognized_mnemonic = 1;
+
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not usually needed as unsupported opcodes
+ shouldn't be in the hash lists. */
+ /* Is this insn supported by the selected cpu? */
+ if (! bpf_cgen_insn_supported (cd, insn))
+ continue;
+#endif
+ /* If the RELAXED attribute is set, this is an insn that shouldn't be
+ chosen immediately. Instead, it is used during assembler/linker
+ relaxation if possible. */
+ if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
+ continue;
+
+ str = start;
+
+ /* Skip this insn if str doesn't look right lexically. */
+ if (CGEN_INSN_RX (insn) != NULL &&
+ regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
+ continue;
+
+ /* Allow parse/insert handlers to obtain length of insn. */
+ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+ parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
+ if (parse_errmsg != NULL)
+ continue;
+
+ /* ??? 0 is passed for `pc'. */
+ insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
+ (bfd_vma) 0);
+ if (insert_errmsg != NULL)
+ continue;
+
+ /* It is up to the caller to actually output the insn and any
+ queued relocs. */
+ return insn;
+ }
+
+ {
+ static char errbuf[150];
+ const char *tmp_errmsg;
+#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS
+#define be_verbose 1
+#else
+#define be_verbose 0
+#endif
+
+ if (be_verbose)
+ {
+ /* If requesting verbose error messages, use insert_errmsg.
+ Failing that, use parse_errmsg. */
+ tmp_errmsg = (insert_errmsg ? insert_errmsg :
+ parse_errmsg ? parse_errmsg :
+ recognized_mnemonic ?
+ _("unrecognized form of instruction") :
+ _("unrecognized instruction"));
+
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+ else
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+ }
+ else
+ {
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+ else
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s'"), start);
+ }
+
+ *errmsg = errbuf;
+ return NULL;
+ }
+}
diff --git a/opcodes/bpf-desc.c b/opcodes/bpf-desc.c
new file mode 100644
index 0000000000..4c94723baf
--- /dev/null
+++ b/opcodes/bpf-desc.c
@@ -0,0 +1,1638 @@
+/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
+/* CPU data for bpf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996-2019 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#include "sysdep.h"
+#include <stdio.h>
+#include <stdarg.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "bpf-desc.h"
+#include "bpf-opc.h"
+#include "opintl.h"
+#include "libiberty.h"
+#include "xregex.h"
+
+/* Attributes. */
+
+static const CGEN_ATTR_ENTRY bool_attr[] =
+{
+ { "#f", 0 },
+ { "#t", 1 },
+ { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
+{
+ { "base", MACH_BASE },
+ { "bpf", MACH_BPF },
+ { "max", MACH_MAX },
+ { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
+{
+ { "ebpfle", ISA_EBPFLE },
+ { "ebpfbe", ISA_EBPFBE },
+ { "max", ISA_MAX },
+ { 0, 0 }
+};
+
+const CGEN_ATTR_TABLE bpf_cgen_ifield_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "ISA", & ISA_attr[0], & ISA_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "RESERVED", &bool_attr[0], &bool_attr[0] },
+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { "SIGNED", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE bpf_cgen_hardware_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "ISA", & ISA_attr[0], & ISA_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "PC", &bool_attr[0], &bool_attr[0] },
+ { "PROFILE", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE bpf_cgen_operand_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "ISA", & ISA_attr[0], & ISA_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { "SIGNED", &bool_attr[0], &bool_attr[0] },
+ { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
+ { "RELAX", &bool_attr[0], &bool_attr[0] },
+ { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE bpf_cgen_insn_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "ISA", & ISA_attr[0], & ISA_attr[0] },
+ { "ALIAS", &bool_attr[0], &bool_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
+ { "COND-CTI", &bool_attr[0], &bool_attr[0] },
+ { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
+ { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
+ { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
+ { "RELAXED", &bool_attr[0], &bool_attr[0] },
+ { "NO-DIS", &bool_attr[0], &bool_attr[0] },
+ { "PBB", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+/* Instruction set variants. */
+
+static const CGEN_ISA bpf_cgen_isa_table[] = {
+ { "ebpfle", 64, 8, 64, 128 },
+ { "ebpfbe", 64, 8, 64, 128 },
+ { 0, 0, 0, 0, 0 }
+};
+
+/* Machine variants. */
+
+static const CGEN_MACH bpf_cgen_mach_table[] = {
+ { "bpf", "bpf", MACH_BPF, 0 },
+ { 0, 0, 0, 0 }
+};
+
+static CGEN_KEYWORD_ENTRY bpf_cgen_opval_h_gpr_entries[] =
+{
+ { "%a", 0, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r1", 1, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r2", 2, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r3", 3, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r4", 4, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r5", 5, {0, {{{0, 0}}}}, 0, 0 },
+ { "%ctx", 6, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r7", 7, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r8", 8, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r9", 9, {0, {{{0, 0}}}}, 0, 0 },
+ { "%fp", 10, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r6", 6, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r10", 10, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD bpf_cgen_opval_h_gpr =
+{
+ & bpf_cgen_opval_h_gpr_entries[0],
+ 14,
+ 0, 0, 0, 0, ""
+};
+
+
+/* The hardware table. */
+
+#define A(a) (1 << CGEN_HW_##a)
+
+const CGEN_HW_ENTRY bpf_cgen_hw_table[] =
+{
+ { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & bpf_cgen_opval_h_gpr, { 0, { { { (1<<MACH_BPF), 0 } }, { { 1, "\xc0" } } } } },
+ { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
+ { "h-sint64", HW_H_SINT64, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
+};
+
+#undef A
+
+
+/* The instruction field table. */
+
+#define A(a) (1 << CGEN_IFLD_##a)
+
+const CGEN_IFLD bpf_cgen_ifld_table[] =
+{
+ { BPF_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_OP_CODE, "f-op-code", 0, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_OP_SRC, "f-op-src", 0, 8, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_OP_CLASS, "f-op-class", 0, 8, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_OP_MODE, "f-op-mode", 0, 8, 7, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_OP_SIZE, "f-op-size", 0, 8, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_DSTLE, "f-dstle", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
+ { BPF_F_SRCLE, "f-srcle", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
+ { BPF_F_DSTBE, "f-dstbe", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
+ { BPF_F_SRCBE, "f-srcbe", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
+ { BPF_F_REGS, "f-regs", 8, 8, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_OFFSET16, "f-offset16", 16, 16, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_IMM32, "f-imm32", 32, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_IMM64_A, "f-imm64-a", 32, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_IMM64_B, "f-imm64-b", 64, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_IMM64_C, "f-imm64-c", 96, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_IMM64, "f-imm64", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
+};
+
+#undef A
+
+
+
+/* multi ifield declarations */
+
+const CGEN_MAYBE_MULTI_IFLD BPF_F_IMM64_MULTI_IFIELD [];
+
+
+/* multi ifield definitions */
+
+const CGEN_MAYBE_MULTI_IFLD BPF_F_IMM64_MULTI_IFIELD [] =
+{
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_A] } },
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_B] } },
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_C] } },
+ { 0, { (const PTR) 0 } }
+};
+
+/* The operand table. */
+
+#define A(a) (1 << CGEN_OPERAND_##a)
+#define OPERAND(op) BPF_OPERAND_##op
+
+const CGEN_OPERAND bpf_cgen_operand_table[] =
+{
+/* pc: program counter */
+ { "pc", BPF_OPERAND_PC, HW_H_PC, 0, 0,
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_NIL] } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+/* dstle: destination register */
+ { "dstle", BPF_OPERAND_DSTLE, HW_H_GPR, 3, 4,
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_DSTLE] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
+/* srcle: source register */
+ { "srcle", BPF_OPERAND_SRCLE, HW_H_GPR, 7, 4,
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_SRCLE] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
+/* dstbe: destination register */
+ { "dstbe", BPF_OPERAND_DSTBE, HW_H_GPR, 7, 4,
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_DSTBE] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
+/* srcbe: source register */
+ { "srcbe", BPF_OPERAND_SRCBE, HW_H_GPR, 3, 4,
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_SRCBE] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
+/* disp16: 16-bit PC-relative address */
+ { "disp16", BPF_OPERAND_DISP16, HW_H_SINT, 15, 16,
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_OFFSET16] } },
+ { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+/* disp32: 32-bit PC-relative address */
+ { "disp32", BPF_OPERAND_DISP32, HW_H_SINT, 31, 32,
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
+ { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+/* imm32: 32-bit immediate */
+ { "imm32", BPF_OPERAND_IMM32, HW_H_SINT, 31, 32,
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+/* offset16: 16-bit offset */
+ { "offset16", BPF_OPERAND_OFFSET16, HW_H_SINT, 15, 16,
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_OFFSET16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+/* imm64: 64-bit immediate */
+ { "imm64", BPF_OPERAND_IMM64, HW_H_SINT64, 31, 96,
+ { 3, { (const PTR) &BPF_F_IMM64_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+/* endsize: endianness size immediate: 16, 32 or 64 */
+ { "endsize", BPF_OPERAND_ENDSIZE, HW_H_UINT, 31, 32,
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+/* sentinel */
+ { 0, 0, 0, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
+};
+
+#undef A
+
+
+/* The instruction table. */
+
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+#define A(a) (1 << CGEN_INSN_##a)
+
+static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] =
+{
+ /* Special null first entry.
+ A `num' value of zero is thus invalid.
+ Also, the special `invalid' insn resides here. */
+ { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
+/* add $dstle,$imm32 */
+ {
+ BPF_INSN_ADDILE, "addile", "add", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* add $dstle,$srcle */
+ {
+ BPF_INSN_ADDRLE, "addrle", "add", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* add32 $dstle,$imm32 */
+ {
+ BPF_INSN_ADD32ILE, "add32ile", "add32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* add32 $dstle,$srcle */
+ {
+ BPF_INSN_ADD32RLE, "add32rle", "add32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* sub $dstle,$imm32 */
+ {
+ BPF_INSN_SUBILE, "subile", "sub", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* sub $dstle,$srcle */
+ {
+ BPF_INSN_SUBRLE, "subrle", "sub", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* sub32 $dstle,$imm32 */
+ {
+ BPF_INSN_SUB32ILE, "sub32ile", "sub32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* sub32 $dstle,$srcle */
+ {
+ BPF_INSN_SUB32RLE, "sub32rle", "sub32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mul $dstle,$imm32 */
+ {
+ BPF_INSN_MULILE, "mulile", "mul", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mul $dstle,$srcle */
+ {
+ BPF_INSN_MULRLE, "mulrle", "mul", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mul32 $dstle,$imm32 */
+ {
+ BPF_INSN_MUL32ILE, "mul32ile", "mul32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mul32 $dstle,$srcle */
+ {
+ BPF_INSN_MUL32RLE, "mul32rle", "mul32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* div $dstle,$imm32 */
+ {
+ BPF_INSN_DIVILE, "divile", "div", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* div $dstle,$srcle */
+ {
+ BPF_INSN_DIVRLE, "divrle", "div", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* div32 $dstle,$imm32 */
+ {
+ BPF_INSN_DIV32ILE, "div32ile", "div32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* div32 $dstle,$srcle */
+ {
+ BPF_INSN_DIV32RLE, "div32rle", "div32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* or $dstle,$imm32 */
+ {
+ BPF_INSN_ORILE, "orile", "or", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* or $dstle,$srcle */
+ {
+ BPF_INSN_ORRLE, "orrle", "or", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* or32 $dstle,$imm32 */
+ {
+ BPF_INSN_OR32ILE, "or32ile", "or32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* or32 $dstle,$srcle */
+ {
+ BPF_INSN_OR32RLE, "or32rle", "or32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* and $dstle,$imm32 */
+ {
+ BPF_INSN_ANDILE, "andile", "and", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* and $dstle,$srcle */
+ {
+ BPF_INSN_ANDRLE, "andrle", "and", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* and32 $dstle,$imm32 */
+ {
+ BPF_INSN_AND32ILE, "and32ile", "and32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* and32 $dstle,$srcle */
+ {
+ BPF_INSN_AND32RLE, "and32rle", "and32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* lsh $dstle,$imm32 */
+ {
+ BPF_INSN_LSHILE, "lshile", "lsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* lsh $dstle,$srcle */
+ {
+ BPF_INSN_LSHRLE, "lshrle", "lsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* lsh32 $dstle,$imm32 */
+ {
+ BPF_INSN_LSH32ILE, "lsh32ile", "lsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* lsh32 $dstle,$srcle */
+ {
+ BPF_INSN_LSH32RLE, "lsh32rle", "lsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* rsh $dstle,$imm32 */
+ {
+ BPF_INSN_RSHILE, "rshile", "rsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* rsh $dstle,$srcle */
+ {
+ BPF_INSN_RSHRLE, "rshrle", "rsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* rsh32 $dstle,$imm32 */
+ {
+ BPF_INSN_RSH32ILE, "rsh32ile", "rsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* rsh32 $dstle,$srcle */
+ {
+ BPF_INSN_RSH32RLE, "rsh32rle", "rsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mod $dstle,$imm32 */
+ {
+ BPF_INSN_MODILE, "modile", "mod", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mod $dstle,$srcle */
+ {
+ BPF_INSN_MODRLE, "modrle", "mod", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mod32 $dstle,$imm32 */
+ {
+ BPF_INSN_MOD32ILE, "mod32ile", "mod32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mod32 $dstle,$srcle */
+ {
+ BPF_INSN_MOD32RLE, "mod32rle", "mod32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* xor $dstle,$imm32 */
+ {
+ BPF_INSN_XORILE, "xorile", "xor", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* xor $dstle,$srcle */
+ {
+ BPF_INSN_XORRLE, "xorrle", "xor", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* xor32 $dstle,$imm32 */
+ {
+ BPF_INSN_XOR32ILE, "xor32ile", "xor32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* xor32 $dstle,$srcle */
+ {
+ BPF_INSN_XOR32RLE, "xor32rle", "xor32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mov $dstle,$imm32 */
+ {
+ BPF_INSN_MOVILE, "movile", "mov", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mov $dstle,$srcle */
+ {
+ BPF_INSN_MOVRLE, "movrle", "mov", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mov32 $dstle,$imm32 */
+ {
+ BPF_INSN_MOV32ILE, "mov32ile", "mov32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mov32 $dstle,$srcle */
+ {
+ BPF_INSN_MOV32RLE, "mov32rle", "mov32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* arsh $dstle,$imm32 */
+ {
+ BPF_INSN_ARSHILE, "arshile", "arsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* arsh $dstle,$srcle */
+ {
+ BPF_INSN_ARSHRLE, "arshrle", "arsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* arsh32 $dstle,$imm32 */
+ {
+ BPF_INSN_ARSH32ILE, "arsh32ile", "arsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* arsh32 $dstle,$srcle */
+ {
+ BPF_INSN_ARSH32RLE, "arsh32rle", "arsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* neg $dstle */
+ {
+ BPF_INSN_NEGLE, "negle", "neg", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* neg32 $dstle */
+ {
+ BPF_INSN_NEG32LE, "neg32le", "neg32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* add $dstbe,$imm32 */
+ {
+ BPF_INSN_ADDIBE, "addibe", "add", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* add $dstbe,$srcbe */
+ {
+ BPF_INSN_ADDRBE, "addrbe", "add", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* add32 $dstbe,$imm32 */
+ {
+ BPF_INSN_ADD32IBE, "add32ibe", "add32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* add32 $dstbe,$srcbe */
+ {
+ BPF_INSN_ADD32RBE, "add32rbe", "add32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* sub $dstbe,$imm32 */
+ {
+ BPF_INSN_SUBIBE, "subibe", "sub", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* sub $dstbe,$srcbe */
+ {
+ BPF_INSN_SUBRBE, "subrbe", "sub", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* sub32 $dstbe,$imm32 */
+ {
+ BPF_INSN_SUB32IBE, "sub32ibe", "sub32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* sub32 $dstbe,$srcbe */
+ {
+ BPF_INSN_SUB32RBE, "sub32rbe", "sub32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mul $dstbe,$imm32 */
+ {
+ BPF_INSN_MULIBE, "mulibe", "mul", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mul $dstbe,$srcbe */
+ {
+ BPF_INSN_MULRBE, "mulrbe", "mul", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mul32 $dstbe,$imm32 */
+ {
+ BPF_INSN_MUL32IBE, "mul32ibe", "mul32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mul32 $dstbe,$srcbe */
+ {
+ BPF_INSN_MUL32RBE, "mul32rbe", "mul32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* div $dstbe,$imm32 */
+ {
+ BPF_INSN_DIVIBE, "divibe", "div", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* div $dstbe,$srcbe */
+ {
+ BPF_INSN_DIVRBE, "divrbe", "div", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* div32 $dstbe,$imm32 */
+ {
+ BPF_INSN_DIV32IBE, "div32ibe", "div32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* div32 $dstbe,$srcbe */
+ {
+ BPF_INSN_DIV32RBE, "div32rbe", "div32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* or $dstbe,$imm32 */
+ {
+ BPF_INSN_ORIBE, "oribe", "or", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* or $dstbe,$srcbe */
+ {
+ BPF_INSN_ORRBE, "orrbe", "or", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* or32 $dstbe,$imm32 */
+ {
+ BPF_INSN_OR32IBE, "or32ibe", "or32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* or32 $dstbe,$srcbe */
+ {
+ BPF_INSN_OR32RBE, "or32rbe", "or32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* and $dstbe,$imm32 */
+ {
+ BPF_INSN_ANDIBE, "andibe", "and", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* and $dstbe,$srcbe */
+ {
+ BPF_INSN_ANDRBE, "andrbe", "and", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* and32 $dstbe,$imm32 */
+ {
+ BPF_INSN_AND32IBE, "and32ibe", "and32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* and32 $dstbe,$srcbe */
+ {
+ BPF_INSN_AND32RBE, "and32rbe", "and32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* lsh $dstbe,$imm32 */
+ {
+ BPF_INSN_LSHIBE, "lshibe", "lsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* lsh $dstbe,$srcbe */
+ {
+ BPF_INSN_LSHRBE, "lshrbe", "lsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* lsh32 $dstbe,$imm32 */
+ {
+ BPF_INSN_LSH32IBE, "lsh32ibe", "lsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* lsh32 $dstbe,$srcbe */
+ {
+ BPF_INSN_LSH32RBE, "lsh32rbe", "lsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* rsh $dstbe,$imm32 */
+ {
+ BPF_INSN_RSHIBE, "rshibe", "rsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* rsh $dstbe,$srcbe */
+ {
+ BPF_INSN_RSHRBE, "rshrbe", "rsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* rsh32 $dstbe,$imm32 */
+ {
+ BPF_INSN_RSH32IBE, "rsh32ibe", "rsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* rsh32 $dstbe,$srcbe */
+ {
+ BPF_INSN_RSH32RBE, "rsh32rbe", "rsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mod $dstbe,$imm32 */
+ {
+ BPF_INSN_MODIBE, "modibe", "mod", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mod $dstbe,$srcbe */
+ {
+ BPF_INSN_MODRBE, "modrbe", "mod", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mod32 $dstbe,$imm32 */
+ {
+ BPF_INSN_MOD32IBE, "mod32ibe", "mod32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mod32 $dstbe,$srcbe */
+ {
+ BPF_INSN_MOD32RBE, "mod32rbe", "mod32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* xor $dstbe,$imm32 */
+ {
+ BPF_INSN_XORIBE, "xoribe", "xor", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* xor $dstbe,$srcbe */
+ {
+ BPF_INSN_XORRBE, "xorrbe", "xor", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* xor32 $dstbe,$imm32 */
+ {
+ BPF_INSN_XOR32IBE, "xor32ibe", "xor32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* xor32 $dstbe,$srcbe */
+ {
+ BPF_INSN_XOR32RBE, "xor32rbe", "xor32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mov $dstbe,$imm32 */
+ {
+ BPF_INSN_MOVIBE, "movibe", "mov", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mov $dstbe,$srcbe */
+ {
+ BPF_INSN_MOVRBE, "movrbe", "mov", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mov32 $dstbe,$imm32 */
+ {
+ BPF_INSN_MOV32IBE, "mov32ibe", "mov32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mov32 $dstbe,$srcbe */
+ {
+ BPF_INSN_MOV32RBE, "mov32rbe", "mov32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* arsh $dstbe,$imm32 */
+ {
+ BPF_INSN_ARSHIBE, "arshibe", "arsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* arsh $dstbe,$srcbe */
+ {
+ BPF_INSN_ARSHRBE, "arshrbe", "arsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* arsh32 $dstbe,$imm32 */
+ {
+ BPF_INSN_ARSH32IBE, "arsh32ibe", "arsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* arsh32 $dstbe,$srcbe */
+ {
+ BPF_INSN_ARSH32RBE, "arsh32rbe", "arsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* neg $dstbe */
+ {
+ BPF_INSN_NEGBE, "negbe", "neg", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* neg32 $dstbe */
+ {
+ BPF_INSN_NEG32BE, "neg32be", "neg32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* endle $dstle,$endsize */
+ {
+ BPF_INSN_ENDLELE, "endlele", "endle", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* endbe $dstle,$endsize */
+ {
+ BPF_INSN_ENDBELE, "endbele", "endbe", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* endle $dstbe,$endsize */
+ {
+ BPF_INSN_ENDLEBE, "endlebe", "endle", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* endbe $dstbe,$endsize */
+ {
+ BPF_INSN_ENDBEBE, "endbebe", "endbe", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* lddw $dstle,$imm64 */
+ {
+ BPF_INSN_LDDWLE, "lddwle", "lddw", 128,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* lddw $dstbe,$imm64 */
+ {
+ BPF_INSN_LDDWBE, "lddwbe", "lddw", 128,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldabsw $dstle,$srcle,$imm32 */
+ {
+ BPF_INSN_LDABSWLE, "ldabswle", "ldabsw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldabsh $dstle,$srcle,$imm32 */
+ {
+ BPF_INSN_LDABSHLE, "ldabshle", "ldabsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldabsb $dstle,$srcle,$imm32 */
+ {
+ BPF_INSN_LDABSBLE, "ldabsble", "ldabsb", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldabsdw $dstle,$srcle,$imm32 */
+ {
+ BPF_INSN_LDABSDWLE, "ldabsdwle", "ldabsdw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldindw $dstle,$srcle,$imm32 */
+ {
+ BPF_INSN_LDINDWLE, "ldindwle", "ldindw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldindh $dstle,$srcle,$imm32 */
+ {
+ BPF_INSN_LDINDHLE, "ldindhle", "ldindh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldindb $dstle,$srcle,$imm32 */
+ {
+ BPF_INSN_LDINDBLE, "ldindble", "ldindb", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldinddw $dstle,$srcle,$imm32 */
+ {
+ BPF_INSN_LDINDDWLE, "ldinddwle", "ldinddw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldabsw $dstbe,$srcbe,$imm32 */
+ {
+ BPF_INSN_LDABSWBE, "ldabswbe", "ldabsw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldabsh $dstbe,$srcbe,$imm32 */
+ {
+ BPF_INSN_LDABSHBE, "ldabshbe", "ldabsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldabsb $dstbe,$srcbe,$imm32 */
+ {
+ BPF_INSN_LDABSBBE, "ldabsbbe", "ldabsb", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldabsdw $dstbe,$srcbe,$imm32 */
+ {
+ BPF_INSN_LDABSDWBE, "ldabsdwbe", "ldabsdw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldindw $dstbe,$srcbe,$imm32 */
+ {
+ BPF_INSN_LDINDWBE, "ldindwbe", "ldindw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldindh $dstbe,$srcbe,$imm32 */
+ {
+ BPF_INSN_LDINDHBE, "ldindhbe", "ldindh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldindb $dstbe,$srcbe,$imm32 */
+ {
+ BPF_INSN_LDINDBBE, "ldindbbe", "ldindb", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldinddw $dstbe,$srcbe,$imm32 */
+ {
+ BPF_INSN_LDINDDWBE, "ldinddwbe", "ldinddw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldxw $dstle,[$srcle+$offset16] */
+ {
+ BPF_INSN_LDXWLE, "ldxwle", "ldxw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldxh $dstle,[$srcle+$offset16] */
+ {
+ BPF_INSN_LDXHLE, "ldxhle", "ldxh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldxb $dstle,[$srcle+$offset16] */
+ {
+ BPF_INSN_LDXBLE, "ldxble", "ldxb", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldxdw $dstle,[$srcle+$offset16] */
+ {
+ BPF_INSN_LDXDWLE, "ldxdwle", "ldxdw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* stxw [$dstle+$offset16],$srcle */
+ {
+ BPF_INSN_STXWLE, "stxwle", "stxw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* stxh [$dstle+$offset16],$srcle */
+ {
+ BPF_INSN_STXHLE, "stxhle", "stxh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* stxb [$dstle+$offset16],$srcle */
+ {
+ BPF_INSN_STXBLE, "stxble", "stxb", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* stxdw [$dstle+$offset16],$srcle */
+ {
+ BPF_INSN_STXDWLE, "stxdwle", "stxdw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldxw $dstbe,[$srcbe+$offset16] */
+ {
+ BPF_INSN_LDXWBE, "ldxwbe", "ldxw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldxh $dstbe,[$srcbe+$offset16] */
+ {
+ BPF_INSN_LDXHBE, "ldxhbe", "ldxh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldxb $dstbe,[$srcbe+$offset16] */
+ {
+ BPF_INSN_LDXBBE, "ldxbbe", "ldxb", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldxdw $dstbe,[$srcbe+$offset16] */
+ {
+ BPF_INSN_LDXDWBE, "ldxdwbe", "ldxdw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* stxw [$dstbe+$offset16],$srcbe */
+ {
+ BPF_INSN_STXWBE, "stxwbe", "stxw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* stxh [$dstbe+$offset16],$srcbe */
+ {
+ BPF_INSN_STXHBE, "stxhbe", "stxh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* stxb [$dstbe+$offset16],$srcbe */
+ {
+ BPF_INSN_STXBBE, "stxbbe", "stxb", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* stxdw [$dstbe+$offset16],$srcbe */
+ {
+ BPF_INSN_STXDWBE, "stxdwbe", "stxdw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* stb [$dstle+$offset16],$imm32 */
+ {
+ BPF_INSN_STBLE, "stble", "stb", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* sth [$dstle+$offset16],$imm32 */
+ {
+ BPF_INSN_STHLE, "sthle", "sth", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* stw [$dstle+$offset16],$imm32 */
+ {
+ BPF_INSN_STWLE, "stwle", "stw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* stdw [$dstle+$offset16],$imm32 */
+ {
+ BPF_INSN_STDWLE, "stdwle", "stdw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* stb [$dstbe+$offset16],$imm32 */
+ {
+ BPF_INSN_STBBE, "stbbe", "stb", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* sth [$dstbe+$offset16],$imm32 */
+ {
+ BPF_INSN_STHBE, "sthbe", "sth", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* stw [$dstbe+$offset16],$imm32 */
+ {
+ BPF_INSN_STWBE, "stwbe", "stw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* stdw [$dstbe+$offset16],$imm32 */
+ {
+ BPF_INSN_STDWBE, "stdwbe", "stdw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jeq $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JEQILE, "jeqile", "jeq", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jeq $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JEQRLE, "jeqrle", "jeq", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jgt $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JGTILE, "jgtile", "jgt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jgt $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JGTRLE, "jgtrle", "jgt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jge $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JGEILE, "jgeile", "jge", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jge $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JGERLE, "jgerle", "jge", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jlt $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JLTILE, "jltile", "jlt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jlt $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JLTRLE, "jltrle", "jlt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jle $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JLEILE, "jleile", "jle", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jle $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JLERLE, "jlerle", "jle", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jset $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JSETILE, "jsetile", "jset", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jset $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JSETRLE, "jsetrle", "jset", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jne $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JNEILE, "jneile", "jne", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jne $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JNERLE, "jnerle", "jne", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jsgt $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JSGTILE, "jsgtile", "jsgt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jsgt $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JSGTRLE, "jsgtrle", "jsgt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jsge $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JSGEILE, "jsgeile", "jsge", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jsge $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JSGERLE, "jsgerle", "jsge", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jslt $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JSLTILE, "jsltile", "jslt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jslt $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JSLTRLE, "jsltrle", "jslt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jsle $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JSLEILE, "jsleile", "jsle", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jsle $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JSLERLE, "jslerle", "jsle", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jeq $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JEQIBE, "jeqibe", "jeq", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jeq $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JEQRBE, "jeqrbe", "jeq", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jgt $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JGTIBE, "jgtibe", "jgt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jgt $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JGTRBE, "jgtrbe", "jgt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jge $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JGEIBE, "jgeibe", "jge", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jge $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JGERBE, "jgerbe", "jge", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jlt $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JLTIBE, "jltibe", "jlt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jlt $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JLTRBE, "jltrbe", "jlt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jle $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JLEIBE, "jleibe", "jle", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jle $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JLERBE, "jlerbe", "jle", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jset $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JSETIBE, "jsetibe", "jset", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jset $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JSETRBE, "jsetrbe", "jset", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jne $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JNEIBE, "jneibe", "jne", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jne $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JNERBE, "jnerbe", "jne", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jsgt $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JSGTIBE, "jsgtibe", "jsgt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jsgt $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JSGTRBE, "jsgtrbe", "jsgt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jsge $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JSGEIBE, "jsgeibe", "jsge", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jsge $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JSGERBE, "jsgerbe", "jsge", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jslt $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JSLTIBE, "jsltibe", "jslt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jslt $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JSLTRBE, "jsltrbe", "jslt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jsle $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JSLEIBE, "jsleibe", "jsle", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jsle $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JSLERBE, "jslerbe", "jsle", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ja $disp16 */
+ {
+ BPF_INSN_JA, "ja", "ja", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
+ },
+/* call $disp32 */
+ {
+ BPF_INSN_CALL, "call", "call", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
+ },
+/* exit */
+ {
+ BPF_INSN_EXIT, "exit", "exit", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
+ },
+/* xadddw [$dstle+$offset16],$srcle */
+ {
+ BPF_INSN_XADDDWLE, "xadddwle", "xadddw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* xaddw [$dstle+$offset16],$srcle */
+ {
+ BPF_INSN_XADDWLE, "xaddwle", "xaddw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* xadddw [$dstbe+$offset16],$srcbe */
+ {
+ BPF_INSN_XADDDWBE, "xadddwbe", "xadddw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* xaddw [$dstbe+$offset16],$srcbe */
+ {
+ BPF_INSN_XADDWBE, "xaddwbe", "xaddw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+};
+
+#undef OP
+#undef A
+
+/* Initialize anything needed to be done once, before any cpu_open call. */
+
+static void
+init_tables (void)
+{
+}
+
+#ifndef opcodes_error_handler
+#define opcodes_error_handler(...) \
+ fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
+#endif
+
+static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
+static void build_hw_table (CGEN_CPU_TABLE *);
+static void build_ifield_table (CGEN_CPU_TABLE *);
+static void build_operand_table (CGEN_CPU_TABLE *);
+static void build_insn_table (CGEN_CPU_TABLE *);
+static void bpf_cgen_rebuild_tables (CGEN_CPU_TABLE *);
+
+/* Subroutine of bpf_cgen_cpu_open to look up a mach via its bfd name. */
+
+static const CGEN_MACH *
+lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
+{
+ while (table->name)
+ {
+ if (strcmp (name, table->bfd_name) == 0)
+ return table;
+ ++table;
+ }
+ return NULL;
+}
+
+/* Subroutine of bpf_cgen_cpu_open to build the hardware table. */
+
+static void
+build_hw_table (CGEN_CPU_TABLE *cd)
+{
+ int i;
+ int machs = cd->machs;
+ const CGEN_HW_ENTRY *init = & bpf_cgen_hw_table[0];
+ /* MAX_HW is only an upper bound on the number of selected entries.
+ However each entry is indexed by it's enum so there can be holes in
+ the table. */
+ const CGEN_HW_ENTRY **selected =
+ (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
+
+ cd->hw_table.init_entries = init;
+ cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
+ memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
+ /* ??? For now we just use machs to determine which ones we want. */
+ for (i = 0; init[i].name != NULL; ++i)
+ if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
+ & machs)
+ selected[init[i].type] = &init[i];
+ cd->hw_table.entries = selected;
+ cd->hw_table.num_entries = MAX_HW;
+}
+
+/* Subroutine of bpf_cgen_cpu_open to build the hardware table. */
+
+static void
+build_ifield_table (CGEN_CPU_TABLE *cd)
+{
+ cd->ifld_table = & bpf_cgen_ifld_table[0];
+}
+
+/* Subroutine of bpf_cgen_cpu_open to build the hardware table. */
+
+static void
+build_operand_table (CGEN_CPU_TABLE *cd)
+{
+ int i;
+ int machs = cd->machs;
+ const CGEN_OPERAND *init = & bpf_cgen_operand_table[0];
+ /* MAX_OPERANDS is only an upper bound on the number of selected entries.
+ However each entry is indexed by it's enum so there can be holes in
+ the table. */
+ const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
+
+ cd->operand_table.init_entries = init;
+ cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
+ memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+ /* ??? For now we just use mach to determine which ones we want. */
+ for (i = 0; init[i].name != NULL; ++i)
+ if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
+ & machs)
+ selected[init[i].type] = &init[i];
+ cd->operand_table.entries = selected;
+ cd->operand_table.num_entries = MAX_OPERANDS;
+}
+
+/* Subroutine of bpf_cgen_cpu_open to build the hardware table.
+ ??? This could leave out insns not supported by the specified mach/isa,
+ but that would cause errors like "foo only supported by bar" to become
+ "unknown insn", so for now we include all insns and require the app to
+ do the checking later.
+ ??? On the other hand, parsing of such insns may require their hardware or
+ operand elements to be in the table [which they mightn't be]. */
+
+static void
+build_insn_table (CGEN_CPU_TABLE *cd)
+{
+ int i;
+ const CGEN_IBASE *ib = & bpf_cgen_insn_table[0];
+ CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+
+ memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
+ for (i = 0; i < MAX_INSNS; ++i)
+ insns[i].base = &ib[i];
+ cd->insn_table.init_entries = insns;
+ cd->insn_table.entry_size = sizeof (CGEN_IBASE);
+ cd->insn_table.num_init_entries = MAX_INSNS;
+}
+
+/* Subroutine of bpf_cgen_cpu_open to rebuild the tables. */
+
+static void
+bpf_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
+{
+ int i;
+ CGEN_BITSET *isas = cd->isas;
+ unsigned int machs = cd->machs;
+
+ cd->int_insn_p = CGEN_INT_INSN_P;
+
+ /* Data derived from the isa spec. */
+#define UNSET (CGEN_SIZE_UNKNOWN + 1)
+ cd->default_insn_bitsize = UNSET;
+ cd->base_insn_bitsize = UNSET;
+ cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
+ cd->max_insn_bitsize = 0;
+ for (i = 0; i < MAX_ISAS; ++i)
+ if (cgen_bitset_contains (isas, i))
+ {
+ const CGEN_ISA *isa = & bpf_cgen_isa_table[i];
+
+ /* Default insn sizes of all selected isas must be
+ equal or we set the result to 0, meaning "unknown". */
+ if (cd->default_insn_bitsize == UNSET)
+ cd->default_insn_bitsize = isa->default_insn_bitsize;
+ else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
+ ; /* This is ok. */
+ else
+ cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+ /* Base insn sizes of all selected isas must be equal
+ or we set the result to 0, meaning "unknown". */
+ if (cd->base_insn_bitsize == UNSET)
+ cd->base_insn_bitsize = isa->base_insn_bitsize;
+ else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
+ ; /* This is ok. */
+ else
+ cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+ /* Set min,max insn sizes. */
+ if (isa->min_insn_bitsize < cd->min_insn_bitsize)
+ cd->min_insn_bitsize = isa->min_insn_bitsize;
+ if (isa->max_insn_bitsize > cd->max_insn_bitsize)
+ cd->max_insn_bitsize = isa->max_insn_bitsize;
+ }
+
+ /* Data derived from the mach spec. */
+ for (i = 0; i < MAX_MACHS; ++i)
+ if (((1 << i) & machs) != 0)
+ {
+ const CGEN_MACH *mach = & bpf_cgen_mach_table[i];
+
+ if (mach->insn_chunk_bitsize != 0)
+ {
+ if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
+ {
+ opcodes_error_handler
+ (/* xgettext:c-format */
+ _("internal error: bpf_cgen_rebuild_tables: "
+ "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
+ cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
+ abort ();
+ }
+
+ cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
+ }
+ }
+
+ /* Determine which hw elements are used by MACH. */
+ build_hw_table (cd);
+
+ /* Build the ifield table. */
+ build_ifield_table (cd);
+
+ /* Determine which operands are used by MACH/ISA. */
+ build_operand_table (cd);
+
+ /* Build the instruction table. */
+ build_insn_table (cd);
+}
+
+/* Initialize a cpu table and return a descriptor.
+ It's much like opening a file, and must be the first function called.
+ The arguments are a set of (type/value) pairs, terminated with
+ CGEN_CPU_OPEN_END.
+
+ Currently supported values:
+ CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
+ CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
+ CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
+ CGEN_CPU_OPEN_ENDIAN: specify endian choice
+ CGEN_CPU_OPEN_END: terminates arguments
+
+ ??? Simultaneous multiple isas might not make sense, but it's not (yet)
+ precluded. */
+
+CGEN_CPU_DESC
+bpf_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+{
+ CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
+ static int init_p;
+ CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
+ unsigned int machs = 0; /* 0 = "unspecified" */
+ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
+ va_list ap;
+
+ if (! init_p)
+ {
+ init_tables ();
+ init_p = 1;
+ }
+
+ memset (cd, 0, sizeof (*cd));
+
+ va_start (ap, arg_type);
+ while (arg_type != CGEN_CPU_OPEN_END)
+ {
+ switch (arg_type)
+ {
+ case CGEN_CPU_OPEN_ISAS :
+ isas = va_arg (ap, CGEN_BITSET *);
+ break;
+ case CGEN_CPU_OPEN_MACHS :
+ machs = va_arg (ap, unsigned int);
+ break;
+ case CGEN_CPU_OPEN_BFDMACH :
+ {
+ const char *name = va_arg (ap, const char *);
+ const CGEN_MACH *mach =
+ lookup_mach_via_bfd_name (bpf_cgen_mach_table, name);
+
+ if (mach != NULL)
+ machs |= 1 << mach->num;
+ break;
+ }
+ case CGEN_CPU_OPEN_ENDIAN :
+ endian = va_arg (ap, enum cgen_endian);
+ break;
+ default :
+ opcodes_error_handler
+ (/* xgettext:c-format */
+ _("internal error: bpf_cgen_cpu_open: "
+ "unsupported argument `%d'"),
+ arg_type);
+ abort (); /* ??? return NULL? */
+ }
+ arg_type = va_arg (ap, enum cgen_cpu_open_arg);
+ }
+ va_end (ap);
+
+ /* Mach unspecified means "all". */
+ if (machs == 0)
+ machs = (1 << MAX_MACHS) - 1;
+ /* Base mach is always selected. */
+ machs |= 1;
+ if (endian == CGEN_ENDIAN_UNKNOWN)
+ {
+ /* ??? If target has only one, could have a default. */
+ opcodes_error_handler
+ (/* xgettext:c-format */
+ _("internal error: bpf_cgen_cpu_open: no endianness specified"));
+ abort ();
+ }
+
+ cd->isas = cgen_bitset_copy (isas);
+ cd->machs = machs;
+ cd->endian = endian;
+ /* FIXME: for the sparc case we can determine insn-endianness statically.
+ The worry here is where both data and insn endian can be independently
+ chosen, in which case this function will need another argument.
+ Actually, will want to allow for more arguments in the future anyway. */
+ cd->insn_endian = endian;
+
+ /* Table (re)builder. */
+ cd->rebuild_tables = bpf_cgen_rebuild_tables;
+ bpf_cgen_rebuild_tables (cd);
+
+ /* Default to not allowing signed overflow. */
+ cd->signed_overflow_ok_p = 0;
+
+ return (CGEN_CPU_DESC) cd;
+}
+
+/* Cover fn to bpf_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
+ MACH_NAME is the bfd name of the mach. */
+
+CGEN_CPU_DESC
+bpf_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
+{
+ return bpf_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
+ CGEN_CPU_OPEN_ENDIAN, endian,
+ CGEN_CPU_OPEN_END);
+}
+
+/* Close a cpu table.
+ ??? This can live in a machine independent file, but there's currently
+ no place to put this file (there's no libcgen). libopcodes is the wrong
+ place as some simulator ports use this but they don't use libopcodes. */
+
+void
+bpf_cgen_cpu_close (CGEN_CPU_DESC cd)
+{
+ unsigned int i;
+ const CGEN_INSN *insns;
+
+ if (cd->macro_insn_table.init_entries)
+ {
+ insns = cd->macro_insn_table.init_entries;
+ for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
+ if (CGEN_INSN_RX ((insns)))
+ regfree (CGEN_INSN_RX (insns));
+ }
+
+ if (cd->insn_table.init_entries)
+ {
+ insns = cd->insn_table.init_entries;
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ if (CGEN_INSN_RX (insns))
+ regfree (CGEN_INSN_RX (insns));
+ }
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+
+ if (cd->insn_table.init_entries)
+ free ((CGEN_INSN *) cd->insn_table.init_entries);
+
+ if (cd->hw_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+
+ if (cd->operand_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+
+ free (cd);
+}
+
diff --git a/opcodes/bpf-desc.h b/opcodes/bpf-desc.h
new file mode 100644
index 0000000000..5293517953
--- /dev/null
+++ b/opcodes/bpf-desc.h
@@ -0,0 +1,266 @@
+/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
+/* CPU data header for bpf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996-2019 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef BPF_CPU_H
+#define BPF_CPU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CGEN_ARCH bpf
+
+/* Given symbol S, return bpf_cgen_<S>. */
+#define CGEN_SYM(s) bpf##_cgen_##s
+
+
+/* Selected cpu families. */
+#define HAVE_CPU_BPFBF
+
+#define CGEN_INSN_LSB0_P 1
+
+/* Minimum size of any insn (in bytes). */
+#define CGEN_MIN_INSN_SIZE 8
+
+/* Maximum size of any insn (in bytes). */
+#define CGEN_MAX_INSN_SIZE 16
+
+#define CGEN_INT_INSN_P 0
+
+/* Maximum number of syntax elements in an instruction. */
+#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 16
+
+/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
+ e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
+ we can't hash on everything up to the space. */
+#define CGEN_MNEMONIC_OPERANDS
+
+/* Maximum number of fields in an instruction. */
+#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7
+
+/* Enums. */
+
+/* Enum declaration for eBPF instruction codes. */
+typedef enum insn_op_code_alu {
+ OP_CODE_ADD = 0, OP_CODE_SUB = 1, OP_CODE_MUL = 2, OP_CODE_DIV = 3
+ , OP_CODE_OR = 4, OP_CODE_AND = 5, OP_CODE_LSH = 6, OP_CODE_RSH = 7
+ , OP_CODE_NEG = 8, OP_CODE_MOD = 9, OP_CODE_XOR = 10, OP_CODE_MOV = 11
+ , OP_CODE_ARSH = 12, OP_CODE_END = 13, OP_CODE_JA = 0, OP_CODE_JEQ = 1
+ , OP_CODE_JGT = 2, OP_CODE_JGE = 3, OP_CODE_JSET = 4, OP_CODE_JNE = 5
+ , OP_CODE_JSGT = 6, OP_CODE_JSGE = 7, OP_CODE_CALL = 8, OP_CODE_EXIT = 9
+ , OP_CODE_JLT = 10, OP_CODE_JLE = 11, OP_CODE_JSLT = 12, OP_CODE_JSLE = 13
+} INSN_OP_CODE_ALU;
+
+/* Enum declaration for eBPF instruction source. */
+typedef enum insn_op_src {
+ OP_SRC_K, OP_SRC_X
+} INSN_OP_SRC;
+
+/* Enum declaration for eBPF instruction class. */
+typedef enum insn_op_class {
+ OP_CLASS_LD = 0, OP_CLASS_LDX = 1, OP_CLASS_ST = 2, OP_CLASS_STX = 3
+ , OP_CLASS_ALU = 4, OP_CLASS_JMP = 5, OP_CLASS_ALU64 = 7
+} INSN_OP_CLASS;
+
+/* Enum declaration for eBPF load/store instruction modes. */
+typedef enum insn_op_mode {
+ OP_MODE_IMM = 0, OP_MODE_ABS = 1, OP_MODE_IND = 2, OP_MODE_MEM = 3
+ , OP_MODE_XADD = 6
+} INSN_OP_MODE;
+
+/* Enum declaration for eBPF load/store instruction sizes. */
+typedef enum insn_op_size {
+ OP_SIZE_W, OP_SIZE_H, OP_SIZE_B, OP_SIZE_DW
+} INSN_OP_SIZE;
+
+/* Attributes. */
+
+/* Enum declaration for machine type selection. */
+typedef enum mach_attr {
+ MACH_BASE, MACH_BPF, MACH_MAX
+} MACH_ATTR;
+
+/* Enum declaration for instruction set selection. */
+typedef enum isa_attr {
+ ISA_EBPFLE, ISA_EBPFBE, ISA_MAX
+} ISA_ATTR;
+
+/* Number of architecture variants. */
+#define MAX_ISAS ((int) ISA_MAX)
+#define MAX_MACHS ((int) MACH_MAX)
+
+/* Ifield support. */
+
+/* Ifield attribute indices. */
+
+/* Enum declaration for cgen_ifld attrs. */
+typedef enum cgen_ifld_attr {
+ CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
+ , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
+ , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS
+} CGEN_IFLD_ATTR;
+
+/* Number of non-boolean elements in cgen_ifld_attr. */
+#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
+
+/* cgen_ifld attribute accessor macros. */
+#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset)
+#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0)
+
+/* Enum declaration for bpf ifield types. */
+typedef enum ifield_type {
+ BPF_F_NIL, BPF_F_ANYOF, BPF_F_OP_CODE, BPF_F_OP_SRC
+ , BPF_F_OP_CLASS, BPF_F_OP_MODE, BPF_F_OP_SIZE, BPF_F_DSTLE
+ , BPF_F_SRCLE, BPF_F_DSTBE, BPF_F_SRCBE, BPF_F_REGS
+ , BPF_F_OFFSET16, BPF_F_IMM32, BPF_F_IMM64_A, BPF_F_IMM64_B
+ , BPF_F_IMM64_C, BPF_F_IMM64, BPF_F_MAX
+} IFIELD_TYPE;
+
+#define MAX_IFLD ((int) BPF_F_MAX)
+
+/* Hardware attribute indices. */
+
+/* Enum declaration for cgen_hw attrs. */
+typedef enum cgen_hw_attr {
+ CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
+ , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_ISA
+ , CGEN_HW_END_NBOOLS
+} CGEN_HW_ATTR;
+
+/* Number of non-boolean elements in cgen_hw_attr. */
+#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
+
+/* cgen_hw attribute accessor macros. */
+#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset)
+#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0)
+#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0)
+
+/* Enum declaration for bpf hardware types. */
+typedef enum cgen_hw_type {
+ HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
+ , HW_H_IADDR, HW_H_GPR, HW_H_PC, HW_H_SINT64
+ , HW_MAX
+} CGEN_HW_TYPE;
+
+#define MAX_HW ((int) HW_MAX)
+
+/* Operand attribute indices. */
+
+/* Enum declaration for cgen_operand attrs. */
+typedef enum cgen_operand_attr {
+ CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
+ , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
+ , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA
+ , CGEN_OPERAND_END_NBOOLS
+} CGEN_OPERAND_ATTR;
+
+/* Number of non-boolean elements in cgen_operand_attr. */
+#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
+
+/* cgen_operand attribute accessor macros. */
+#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset)
+#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
+
+/* Enum declaration for bpf operand types. */
+typedef enum cgen_operand_type {
+ BPF_OPERAND_PC, BPF_OPERAND_DSTLE, BPF_OPERAND_SRCLE, BPF_OPERAND_DSTBE
+ , BPF_OPERAND_SRCBE, BPF_OPERAND_DISP16, BPF_OPERAND_DISP32, BPF_OPERAND_IMM32
+ , BPF_OPERAND_OFFSET16, BPF_OPERAND_IMM64, BPF_OPERAND_ENDSIZE, BPF_OPERAND_MAX
+} CGEN_OPERAND_TYPE;
+
+/* Number of operands types. */
+#define MAX_OPERANDS 11
+
+/* Maximum number of operands referenced by any insn. */
+#define MAX_OPERAND_INSTANCES 8
+
+/* Insn attribute indices. */
+
+/* Enum declaration for cgen_insn attrs. */
+typedef enum cgen_insn_attr {
+ CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
+ , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
+ , CGEN_INSN_MACH, CGEN_INSN_ISA, CGEN_INSN_END_NBOOLS
+} CGEN_INSN_ATTR;
+
+/* Number of non-boolean elements in cgen_insn_attr. */
+#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
+
+/* cgen_insn attribute accessor macros. */
+#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset)
+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0)
+#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0)
+
+/* cgen.h uses things we just defined. */
+#include "opcode/cgen.h"
+
+extern const struct cgen_ifld bpf_cgen_ifld_table[];
+
+/* Attributes. */
+extern const CGEN_ATTR_TABLE bpf_cgen_hardware_attr_table[];
+extern const CGEN_ATTR_TABLE bpf_cgen_ifield_attr_table[];
+extern const CGEN_ATTR_TABLE bpf_cgen_operand_attr_table[];
+extern const CGEN_ATTR_TABLE bpf_cgen_insn_attr_table[];
+
+/* Hardware decls. */
+
+extern CGEN_KEYWORD bpf_cgen_opval_h_gpr;
+
+extern const CGEN_HW_ENTRY bpf_cgen_hw_table[];
+
+
+
+ #ifdef __cplusplus
+ }
+ #endif
+
+#endif /* BPF_CPU_H */
diff --git a/opcodes/bpf-dis.c b/opcodes/bpf-dis.c
new file mode 100644
index 0000000000..c48bce85e6
--- /dev/null
+++ b/opcodes/bpf-dis.c
@@ -0,0 +1,624 @@
+/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
+/* Disassembler interface for targets using CGEN. -*- C -*-
+ CGEN: Cpu tools GENerator
+
+ THIS FILE IS MACHINE GENERATED WITH CGEN.
+ - the resultant file is machine generated, cgen-dis.in isn't
+
+ Copyright (C) 1996-2019 Free Software Foundation, Inc.
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+ Keep that in mind. */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "disassemble.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "libiberty.h"
+#include "bpf-desc.h"
+#include "bpf-opc.h"
+#include "opintl.h"
+
+/* Default text to print if an instruction isn't recognized. */
+#define UNKNOWN_INSN_MSG _("*unknown*")
+
+static void print_normal
+ (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
+static void print_address
+ (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
+static void print_keyword
+ (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
+static void print_insn_normal
+ (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
+static int print_insn
+ (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned);
+static int default_print_insn
+ (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
+static int read_insn
+ (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
+ unsigned long *);
+\f
+/* -- disassembler routines inserted here. */
+
+/* -- dis.c */
+
+/* We need to customize the disassembler a bit:
+ - Use 8 bytes per line by default.
+*/
+
+#define CGEN_PRINT_INSN bpf_print_insn
+
+static int
+bpf_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
+{
+ bfd_byte buf[CGEN_MAX_INSN_SIZE];
+ int buflen;
+ int status;
+
+ info->bytes_per_chunk = 1;
+ info->bytes_per_line = 8;
+
+ /* Attempt to read the base part of the insn. */
+ buflen = cd->base_insn_bitsize / 8;
+ status = (*info->read_memory_func) (pc, buf, buflen, info);
+
+ /* Try again with the minimum part, if min < base. */
+ if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
+ {
+ buflen = cd->min_insn_bitsize / 8;
+ status = (*info->read_memory_func) (pc, buf, buflen, info);
+ }
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
+ }
+
+ return print_insn (cd, pc, info, buf, buflen);
+}
+
+/* Signed immediates should be printed in hexadecimal. */
+
+static void
+print_immediate (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void *dis_info,
+ int64_t value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+ if (value <= 9)
+ (*info->fprintf_func) (info->stream, "%" PRId64, value);
+ else
+ (*info->fprintf_func) (info->stream, "%#" PRIx64, value);
+
+ /* This is to avoid -Wunused-function for print_normal. */
+ if (0)
+ print_normal (cd, dis_info, value, attrs, pc, length);
+}
+
+/* Endianness bit sizes should be printed in decimal. */
+
+static void
+print_endsize (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void *dis_info,
+ unsigned long value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+ (*info->fprintf_func) (info->stream, "%lu", value);
+}
+
+\f
+/* -- */
+
+void bpf_cgen_print_operand
+ (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
+
+/* Main entry point for printing operands.
+ XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
+ of dis-asm.h on cgen.h.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `print_insn_normal', but keeping it
+ separate makes clear the interface between `print_insn_normal' and each of
+ the handlers. */
+
+void
+bpf_cgen_print_operand (CGEN_CPU_DESC cd,
+ int opindex,
+ void * xinfo,
+ CGEN_FIELDS *fields,
+ void const *attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc,
+ int length)
+{
+ disassemble_info *info = (disassemble_info *) xinfo;
+
+ switch (opindex)
+ {
+ case BPF_OPERAND_DISP16 :
+ print_normal (cd, info, fields->f_offset16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+ case BPF_OPERAND_DISP32 :
+ print_normal (cd, info, fields->f_imm32, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+ case BPF_OPERAND_DSTBE :
+ print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_dstbe, 0);
+ break;
+ case BPF_OPERAND_DSTLE :
+ print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_dstle, 0);
+ break;
+ case BPF_OPERAND_ENDSIZE :
+ print_endsize (cd, info, fields->f_imm32, 0, pc, length);
+ break;
+ case BPF_OPERAND_IMM32 :
+ print_immediate (cd, info, fields->f_imm32, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
+ case BPF_OPERAND_IMM64 :
+ print_immediate (cd, info, fields->f_imm64, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
+ case BPF_OPERAND_OFFSET16 :
+ print_immediate (cd, info, fields->f_offset16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
+ case BPF_OPERAND_SRCBE :
+ print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_srcbe, 0);
+ break;
+ case BPF_OPERAND_SRCLE :
+ print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_srcle, 0);
+ break;
+
+ default :
+ /* xgettext:c-format */
+ opcodes_error_handler
+ (_("internal error: unrecognized field %d while printing insn"),
+ opindex);
+ abort ();
+ }
+}
+
+cgen_print_fn * const bpf_cgen_print_handlers[] =
+{
+ print_insn_normal,
+};
+
+
+void
+bpf_cgen_init_dis (CGEN_CPU_DESC cd)
+{
+ bpf_cgen_init_opcode_table (cd);
+ bpf_cgen_init_ibld_table (cd);
+ cd->print_handlers = & bpf_cgen_print_handlers[0];
+ cd->print_operand = bpf_cgen_print_operand;
+}
+
+\f
+/* Default print handler. */
+
+static void
+print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void *dis_info,
+ long value,
+ unsigned int attrs,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+ /* Print the operand as directed by the attributes. */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+ ; /* nothing to do */
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
+ (*info->fprintf_func) (info->stream, "%ld", value);
+ else
+ (*info->fprintf_func) (info->stream, "0x%lx", value);
+}
+
+/* Default address handler. */
+
+static void
+print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void *dis_info,
+ bfd_vma value,
+ unsigned int attrs,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+ /* Print the operand as directed by the attributes. */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+ ; /* Nothing to do. */
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
+ (*info->print_address_func) (value, info);
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
+ (*info->print_address_func) (value, info);
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
+ (*info->fprintf_func) (info->stream, "%ld", (long) value);
+ else
+ (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
+}
+
+/* Keyword print handler. */
+
+static void
+print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void *dis_info,
+ CGEN_KEYWORD *keyword_table,
+ long value,
+ unsigned int attrs ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+ const CGEN_KEYWORD_ENTRY *ke;
+
+ ke = cgen_keyword_lookup_value (keyword_table, value);
+ if (ke != NULL)
+ (*info->fprintf_func) (info->stream, "%s", ke->name);
+ else
+ (*info->fprintf_func) (info->stream, "???");
+}
+\f
+/* Default insn printer.
+
+ DIS_INFO is defined as `void *' so the disassembler needn't know anything
+ about disassemble_info. */
+
+static void
+print_insn_normal (CGEN_CPU_DESC cd,
+ void *dis_info,
+ const CGEN_INSN *insn,
+ CGEN_FIELDS *fields,
+ bfd_vma pc,
+ int length)
+{
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ disassemble_info *info = (disassemble_info *) dis_info;
+ const CGEN_SYNTAX_CHAR_TYPE *syn;
+
+ CGEN_INIT_PRINT (cd);
+
+ for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
+ {
+ if (CGEN_SYNTAX_MNEMONIC_P (*syn))
+ {
+ (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
+ continue;
+ }
+ if (CGEN_SYNTAX_CHAR_P (*syn))
+ {
+ (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
+ continue;
+ }
+
+ /* We have an operand. */
+ bpf_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
+ fields, CGEN_INSN_ATTRS (insn), pc, length);
+ }
+}
+\f
+/* Subroutine of print_insn. Reads an insn into the given buffers and updates
+ the extract info.
+ Returns 0 if all is well, non-zero otherwise. */
+
+static int
+read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ bfd_vma pc,
+ disassemble_info *info,
+ bfd_byte *buf,
+ int buflen,
+ CGEN_EXTRACT_INFO *ex_info,
+ unsigned long *insn_value)
+{
+ int status = (*info->read_memory_func) (pc, buf, buflen, info);
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
+ }
+
+ ex_info->dis_info = info;
+ ex_info->valid = (1 << buflen) - 1;
+ ex_info->insn_bytes = buf;
+
+ *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
+ return 0;
+}
+
+/* Utility to print an insn.
+ BUF is the base part of the insn, target byte order, BUFLEN bytes long.
+ The result is the size of the insn in bytes or zero for an unknown insn
+ or -1 if an error occurs fetching data (memory_error_func will have
+ been called). */
+
+static int
+print_insn (CGEN_CPU_DESC cd,
+ bfd_vma pc,
+ disassemble_info *info,
+ bfd_byte *buf,
+ unsigned int buflen)
+{
+ CGEN_INSN_INT insn_value;
+ const CGEN_INSN_LIST *insn_list;
+ CGEN_EXTRACT_INFO ex_info;
+ int basesize;
+
+ /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
+ basesize = cd->base_insn_bitsize < buflen * 8 ?
+ cd->base_insn_bitsize : buflen * 8;
+ insn_value = cgen_get_insn_value (cd, buf, basesize);
+
+
+ /* Fill in ex_info fields like read_insn would. Don't actually call
+ read_insn, since the incoming buffer is already read (and possibly
+ modified a la m32r). */
+ ex_info.valid = (1 << buflen) - 1;
+ ex_info.dis_info = info;
+ ex_info.insn_bytes = buf;
+
+ /* The instructions are stored in hash lists.
+ Pick the first one and keep trying until we find the right one. */
+
+ insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
+ while (insn_list != NULL)
+ {
+ const CGEN_INSN *insn = insn_list->insn;
+ CGEN_FIELDS fields;
+ int length;
+ unsigned long insn_value_cropped;
+
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
+ /* Supported by this cpu? */
+ if (! bpf_cgen_insn_supported (cd, insn))
+ {
+ insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+ continue;
+ }
+#endif
+
+ /* Basic bit mask must be correct. */
+ /* ??? May wish to allow target to defer this check until the extract
+ handler. */
+
+ /* Base size may exceed this instruction's size. Extract the
+ relevant part from the buffer. */
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ info->endian == BFD_ENDIAN_BIG);
+ else
+ insn_value_cropped = insn_value;
+
+ if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
+ == CGEN_INSN_BASE_VALUE (insn))
+ {
+ /* Printing is handled in two passes. The first pass parses the
+ machine insn and extracts the fields. The second pass prints
+ them. */
+
+ /* Make sure the entire insn is loaded into insn_value, if it
+ can fit. */
+ if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ {
+ unsigned long full_insn_value;
+ int rc = read_insn (cd, pc, info, buf,
+ CGEN_INSN_BITSIZE (insn) / 8,
+ & ex_info, & full_insn_value);
+ if (rc != 0)
+ return rc;
+ length = CGEN_EXTRACT_FN (cd, insn)
+ (cd, insn, &ex_info, full_insn_value, &fields, pc);
+ }
+ else
+ length = CGEN_EXTRACT_FN (cd, insn)
+ (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
+
+ /* Length < 0 -> error. */
+ if (length < 0)
+ return length;
+ if (length > 0)
+ {
+ CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
+ /* Length is in bits, result is in bytes. */
+ return length / 8;
+ }
+ }
+
+ insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+ }
+
+ return 0;
+}
+
+/* Default value for CGEN_PRINT_INSN.
+ The result is the size of the insn in bytes or zero for an unknown insn
+ or -1 if an error occured fetching bytes. */
+
+#ifndef CGEN_PRINT_INSN
+#define CGEN_PRINT_INSN default_print_insn
+#endif
+
+static int
+default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
+{
+ bfd_byte buf[CGEN_MAX_INSN_SIZE];
+ int buflen;
+ int status;
+
+ /* Attempt to read the base part of the insn. */
+ buflen = cd->base_insn_bitsize / 8;
+ status = (*info->read_memory_func) (pc, buf, buflen, info);
+
+ /* Try again with the minimum part, if min < base. */
+ if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
+ {
+ buflen = cd->min_insn_bitsize / 8;
+ status = (*info->read_memory_func) (pc, buf, buflen, info);
+ }
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
+ }
+
+ return print_insn (cd, pc, info, buf, buflen);
+}
+
+/* Main entry point.
+ Print one instruction from PC on INFO->STREAM.
+ Return the size of the instruction (in bytes). */
+
+typedef struct cpu_desc_list
+{
+ struct cpu_desc_list *next;
+ CGEN_BITSET *isa;
+ int mach;
+ int endian;
+ CGEN_CPU_DESC cd;
+} cpu_desc_list;
+
+int
+print_insn_bpf (bfd_vma pc, disassemble_info *info)
+{
+ static cpu_desc_list *cd_list = 0;
+ cpu_desc_list *cl = 0;
+ static CGEN_CPU_DESC cd = 0;
+ static CGEN_BITSET *prev_isa;
+ static int prev_mach;
+ static int prev_endian;
+ int length;
+ CGEN_BITSET *isa;
+ int mach;
+ int endian = (info->endian == BFD_ENDIAN_BIG
+ ? CGEN_ENDIAN_BIG
+ : CGEN_ENDIAN_LITTLE);
+ enum bfd_architecture arch;
+
+ /* ??? gdb will set mach but leave the architecture as "unknown" */
+#ifndef CGEN_BFD_ARCH
+#define CGEN_BFD_ARCH bfd_arch_bpf
+#endif
+ arch = info->arch;
+ if (arch == bfd_arch_unknown)
+ arch = CGEN_BFD_ARCH;
+
+ /* There's no standard way to compute the machine or isa number
+ so we leave it to the target. */
+#ifdef CGEN_COMPUTE_MACH
+ mach = CGEN_COMPUTE_MACH (info);
+#else
+ mach = info->mach;
+#endif
+
+#ifdef CGEN_COMPUTE_ISA
+ {
+ static CGEN_BITSET *permanent_isa;
+
+ if (!permanent_isa)
+ permanent_isa = cgen_bitset_create (MAX_ISAS);
+ isa = permanent_isa;
+ cgen_bitset_clear (isa);
+ cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
+ }
+#else
+ isa = info->insn_sets;
+#endif
+
+ /* If we've switched cpu's, try to find a handle we've used before */
+ if (cd
+ && (cgen_bitset_compare (isa, prev_isa) != 0
+ || mach != prev_mach
+ || endian != prev_endian))
+ {
+ cd = 0;
+ for (cl = cd_list; cl; cl = cl->next)
+ {
+ if (cgen_bitset_compare (cl->isa, isa) == 0 &&
+ cl->mach == mach &&
+ cl->endian == endian)
+ {
+ cd = cl->cd;
+ prev_isa = cd->isas;
+ break;
+ }
+ }
+ }
+
+ /* If we haven't initialized yet, initialize the opcode table. */
+ if (! cd)
+ {
+ const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
+ const char *mach_name;
+
+ if (!arch_type)
+ abort ();
+ mach_name = arch_type->printable_name;
+
+ prev_isa = cgen_bitset_copy (isa);
+ prev_mach = mach;
+ prev_endian = endian;
+ cd = bpf_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
+ CGEN_CPU_OPEN_BFDMACH, mach_name,
+ CGEN_CPU_OPEN_ENDIAN, prev_endian,
+ CGEN_CPU_OPEN_END);
+ if (!cd)
+ abort ();
+
+ /* Save this away for future reference. */
+ cl = xmalloc (sizeof (struct cpu_desc_list));
+ cl->cd = cd;
+ cl->isa = prev_isa;
+ cl->mach = mach;
+ cl->endian = endian;
+ cl->next = cd_list;
+ cd_list = cl;
+
+ bpf_cgen_init_dis (cd);
+ }
+
+ /* We try to have as much common code as possible.
+ But at this point some targets need to take over. */
+ /* ??? Some targets may need a hook elsewhere. Try to avoid this,
+ but if not possible try to move this hook elsewhere rather than
+ have two hooks. */
+ length = CGEN_PRINT_INSN (cd, pc, info);
+ if (length > 0)
+ return length;
+ if (length < 0)
+ return -1;
+
+ (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
+ return cd->default_insn_bitsize / 8;
+}
diff --git a/opcodes/bpf-ibld.c b/opcodes/bpf-ibld.c
new file mode 100644
index 0000000000..b14c28b43b
--- /dev/null
+++ b/opcodes/bpf-ibld.c
@@ -0,0 +1,956 @@
+/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
+/* Instruction building/extraction support for bpf. -*- C -*-
+
+ THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
+ - the resultant file is machine generated, cgen-ibld.in isn't
+
+ Copyright (C) 1996-2019 Free Software Foundation, Inc.
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+ Keep that in mind. */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "dis-asm.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "bpf-desc.h"
+#include "bpf-opc.h"
+#include "cgen/basic-modes.h"
+#include "opintl.h"
+#include "safe-ctype.h"
+
+#undef min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+/* Used by the ifield rtx function. */
+#define FLD(f) (fields->f)
+
+static const char * insert_normal
+ (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
+ unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
+static const char * insert_insn_normal
+ (CGEN_CPU_DESC, const CGEN_INSN *,
+ CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
+static int extract_normal
+ (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+ unsigned int, unsigned int, unsigned int, unsigned int,
+ unsigned int, unsigned int, bfd_vma, long *);
+static int extract_insn_normal
+ (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
+ CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
+#if CGEN_INT_INSN_P
+static void put_insn_int_value
+ (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
+#endif
+#if ! CGEN_INT_INSN_P
+static CGEN_INLINE void insert_1
+ (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
+static CGEN_INLINE int fill_cache
+ (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma);
+static CGEN_INLINE long extract_1
+ (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
+#endif
+\f
+/* Operand insertion. */
+
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of insert_normal. */
+
+static CGEN_INLINE void
+insert_1 (CGEN_CPU_DESC cd,
+ unsigned long value,
+ int start,
+ int length,
+ int word_length,
+ unsigned char *bufp)
+{
+ unsigned long x,mask;
+ int shift;
+
+ x = cgen_get_insn_value (cd, bufp, word_length);
+
+ /* Written this way to avoid undefined behaviour. */
+ mask = (((1L << (length - 1)) - 1) << 1) | 1;
+ if (CGEN_INSN_LSB0_P)
+ shift = (start + 1) - length;
+ else
+ shift = (word_length - (start + length));
+ x = (x & ~(mask << shift)) | ((value & mask) << shift);
+
+ cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
+/* Default insertion routine.
+
+ ATTRS is a mask of the boolean attributes.
+ WORD_OFFSET is the offset in bits from the start of the insn of the value.
+ WORD_LENGTH is the length of the word in bits in which the value resides.
+ START is the starting bit number in the word, architecture origin.
+ LENGTH is the length of VALUE in bits.
+ TOTAL_LENGTH is the total length of the insn in bits.
+
+ The result is an error message or NULL if success. */
+
+/* ??? This duplicates functionality with bfd's howto table and
+ bfd_install_relocation. */
+/* ??? This doesn't handle bfd_vma's. Create another function when
+ necessary. */
+
+static const char *
+insert_normal (CGEN_CPU_DESC cd,
+ long value,
+ unsigned int attrs,
+ unsigned int word_offset,
+ unsigned int start,
+ unsigned int length,
+ unsigned int word_length,
+ unsigned int total_length,
+ CGEN_INSN_BYTES_PTR buffer)
+{
+ static char errbuf[100];
+ /* Written this way to avoid undefined behaviour. */
+ unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+ /* If LENGTH is zero, this operand doesn't contribute to the value. */
+ if (length == 0)
+ return NULL;
+
+ if (word_length > 8 * sizeof (CGEN_INSN_INT))
+ abort ();
+
+ /* For architectures with insns smaller than the base-insn-bitsize,
+ word_length may be too big. */
+ if (cd->min_insn_bitsize < cd->base_insn_bitsize)
+ {
+ if (word_offset == 0
+ && word_length > total_length)
+ word_length = total_length;
+ }
+
+ /* Ensure VALUE will fit. */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
+ {
+ long minval = - (1L << (length - 1));
+ unsigned long maxval = mask;
+
+ if ((value > 0 && (unsigned long) value > maxval)
+ || value < minval)
+ {
+ /* xgettext:c-format */
+ sprintf (errbuf,
+ _("operand out of range (%ld not between %ld and %lu)"),
+ value, minval, maxval);
+ return errbuf;
+ }
+ }
+ else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
+ {
+ unsigned long maxval = mask;
+ unsigned long val = (unsigned long) value;
+
+ /* For hosts with a word size > 32 check to see if value has been sign
+ extended beyond 32 bits. If so then ignore these higher sign bits
+ as the user is attempting to store a 32-bit signed value into an
+ unsigned 32-bit field which is allowed. */
+ if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
+ val &= 0xFFFFFFFF;
+
+ if (val > maxval)
+ {
+ /* xgettext:c-format */
+ sprintf (errbuf,
+ _("operand out of range (0x%lx not between 0 and 0x%lx)"),
+ val, maxval);
+ return errbuf;
+ }
+ }
+ else
+ {
+ if (! cgen_signed_overflow_ok_p (cd))
+ {
+ long minval = - (1L << (length - 1));
+ long maxval = (1L << (length - 1)) - 1;
+
+ if (value < minval || value > maxval)
+ {
+ sprintf
+ /* xgettext:c-format */
+ (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
+ value, minval, maxval);
+ return errbuf;
+ }
+ }
+ }
+
+#if CGEN_INT_INSN_P
+
+ {
+ int shift_within_word, shift_to_word, shift;
+
+ /* How to shift the value to BIT0 of the word. */
+ shift_to_word = total_length - (word_offset + word_length);
+
+ /* How to shift the value to the field within the word. */
+ if (CGEN_INSN_LSB0_P)
+ shift_within_word = start + 1 - length;
+ else
+ shift_within_word = word_length - start - length;
+
+ /* The total SHIFT, then mask in the value. */
+ shift = shift_to_word + shift_within_word;
+ *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
+ }
+
+#else /* ! CGEN_INT_INSN_P */
+
+ {
+ unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
+
+ insert_1 (cd, value, start, length, word_length, bufp);
+ }
+
+#endif /* ! CGEN_INT_INSN_P */
+
+ return NULL;
+}
+
+/* Default insn builder (insert handler).
+ The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
+ that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
+ recorded in host byte order, otherwise BUFFER is an array of bytes
+ and the value is recorded in target byte order).
+ The result is an error message or NULL if success. */
+
+static const char *
+insert_insn_normal (CGEN_CPU_DESC cd,
+ const CGEN_INSN * insn,
+ CGEN_FIELDS * fields,
+ CGEN_INSN_BYTES_PTR buffer,
+ bfd_vma pc)
+{
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ unsigned long value;
+ const CGEN_SYNTAX_CHAR_TYPE * syn;
+
+ CGEN_INIT_INSERT (cd);
+ value = CGEN_INSN_BASE_VALUE (insn);
+
+ /* If we're recording insns as numbers (rather than a string of bytes),
+ target byte order handling is deferred until later. */
+
+#if CGEN_INT_INSN_P
+
+ put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
+ CGEN_FIELDS_BITSIZE (fields), value);
+
+#else
+
+ cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
+ (unsigned) CGEN_FIELDS_BITSIZE (fields)),
+ value);
+
+#endif /* ! CGEN_INT_INSN_P */
+
+ /* ??? It would be better to scan the format's fields.
+ Still need to be able to insert a value based on the operand though;
+ e.g. storing a branch displacement that got resolved later.
+ Needs more thought first. */
+
+ for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
+ {
+ const char *errmsg;
+
+ if (CGEN_SYNTAX_CHAR_P (* syn))
+ continue;
+
+ errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
+ fields, buffer, pc);
+ if (errmsg)
+ return errmsg;
+ }
+
+ return NULL;
+}
+
+#if CGEN_INT_INSN_P
+/* Cover function to store an insn value into an integral insn. Must go here
+ because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
+
+static void
+put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ CGEN_INSN_BYTES_PTR buf,
+ int length,
+ int insn_length,
+ CGEN_INSN_INT value)
+{
+ /* For architectures with insns smaller than the base-insn-bitsize,
+ length may be too big. */
+ if (length > insn_length)
+ *buf = value;
+ else
+ {
+ int shift = insn_length - length;
+ /* Written this way to avoid undefined behaviour. */
+ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+ *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
+ }
+}
+#endif
+\f
+/* Operand extraction. */
+
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of extract_normal.
+ Ensure sufficient bytes are cached in EX_INFO.
+ OFFSET is the offset in bytes from the start of the insn of the value.
+ BYTES is the length of the needed value.
+ Returns 1 for success, 0 for failure. */
+
+static CGEN_INLINE int
+fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ CGEN_EXTRACT_INFO *ex_info,
+ int offset,
+ int bytes,
+ bfd_vma pc)
+{
+ /* It's doubtful that the middle part has already been fetched so
+ we don't optimize that case. kiss. */
+ unsigned int mask;
+ disassemble_info *info = (disassemble_info *) ex_info->dis_info;
+
+ /* First do a quick check. */
+ mask = (1 << bytes) - 1;
+ if (((ex_info->valid >> offset) & mask) == mask)
+ return 1;
+
+ /* Search for the first byte we need to read. */
+ for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
+ if (! (mask & ex_info->valid))
+ break;
+
+ if (bytes)
+ {
+ int status;
+
+ pc += offset;
+ status = (*info->read_memory_func)
+ (pc, ex_info->insn_bytes + offset, bytes, info);
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return 0;
+ }
+
+ ex_info->valid |= ((1 << bytes) - 1) << offset;
+ }
+
+ return 1;
+}
+
+/* Subroutine of extract_normal. */
+
+static CGEN_INLINE long
+extract_1 (CGEN_CPU_DESC cd,
+ CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
+ int start,
+ int length,
+ int word_length,
+ unsigned char *bufp,
+ bfd_vma pc ATTRIBUTE_UNUSED)
+{
+ unsigned long x;
+ int shift;
+
+ x = cgen_get_insn_value (cd, bufp, word_length);
+
+ if (CGEN_INSN_LSB0_P)
+ shift = (start + 1) - length;
+ else
+ shift = (word_length - (start + length));
+ return x >> shift;
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
+/* Default extraction routine.
+
+ INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
+ or sometimes less for cases like the m32r where the base insn size is 32
+ but some insns are 16 bits.
+ ATTRS is a mask of the boolean attributes. We only need `SIGNED',
+ but for generality we take a bitmask of all of them.
+ WORD_OFFSET is the offset in bits from the start of the insn of the value.
+ WORD_LENGTH is the length of the word in bits in which the value resides.
+ START is the starting bit number in the word, architecture origin.
+ LENGTH is the length of VALUE in bits.
+ TOTAL_LENGTH is the total length of the insn in bits.
+
+ Returns 1 for success, 0 for failure. */
+
+/* ??? The return code isn't properly used. wip. */
+
+/* ??? This doesn't handle bfd_vma's. Create another function when
+ necessary. */
+
+static int
+extract_normal (CGEN_CPU_DESC cd,
+#if ! CGEN_INT_INSN_P
+ CGEN_EXTRACT_INFO *ex_info,
+#else
+ CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
+#endif
+ CGEN_INSN_INT insn_value,
+ unsigned int attrs,
+ unsigned int word_offset,
+ unsigned int start,
+ unsigned int length,
+ unsigned int word_length,
+ unsigned int total_length,
+#if ! CGEN_INT_INSN_P
+ bfd_vma pc,
+#else
+ bfd_vma pc ATTRIBUTE_UNUSED,
+#endif
+ long *valuep)
+{
+ long value, mask;
+
+ /* If LENGTH is zero, this operand doesn't contribute to the value
+ so give it a standard value of zero. */
+ if (length == 0)
+ {
+ *valuep = 0;
+ return 1;
+ }
+
+ if (word_length > 8 * sizeof (CGEN_INSN_INT))
+ abort ();
+
+ /* For architectures with insns smaller than the insn-base-bitsize,
+ word_length may be too big. */
+ if (cd->min_insn_bitsize < cd->base_insn_bitsize)
+ {
+ if (word_offset + word_length > total_length)
+ word_length = total_length - word_offset;
+ }
+
+ /* Does the value reside in INSN_VALUE, and at the right alignment? */
+
+ if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
+ {
+ if (CGEN_INSN_LSB0_P)
+ value = insn_value >> ((word_offset + start + 1) - length);
+ else
+ value = insn_value >> (total_length - ( word_offset + start + length));
+ }
+
+#if ! CGEN_INT_INSN_P
+
+ else
+ {
+ unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
+
+ if (word_length > 8 * sizeof (CGEN_INSN_INT))
+ abort ();
+
+ if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
+ return 0;
+
+ value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
+ }
+
+#endif /* ! CGEN_INT_INSN_P */
+
+ /* Written this way to avoid undefined behaviour. */
+ mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+ value &= mask;
+ /* sign extend? */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
+ && (value & (1L << (length - 1))))
+ value |= ~mask;
+
+ *valuep = value;
+
+ return 1;
+}
+
+/* Default insn extractor.
+
+ INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
+ The extracted fields are stored in FIELDS.
+ EX_INFO is used to handle reading variable length insns.
+ Return the length of the insn in bits, or 0 if no match,
+ or -1 if an error occurs fetching data (memory_error_func will have
+ been called). */
+
+static int
+extract_insn_normal (CGEN_CPU_DESC cd,
+ const CGEN_INSN *insn,
+ CGEN_EXTRACT_INFO *ex_info,
+ CGEN_INSN_INT insn_value,
+ CGEN_FIELDS *fields,
+ bfd_vma pc)
+{
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ const CGEN_SYNTAX_CHAR_TYPE *syn;
+
+ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+ CGEN_INIT_EXTRACT (cd);
+
+ for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
+ {
+ int length;
+
+ if (CGEN_SYNTAX_CHAR_P (*syn))
+ continue;
+
+ length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
+ ex_info, insn_value, fields, pc);
+ if (length <= 0)
+ return length;
+ }
+
+ /* We recognized and successfully extracted this insn. */
+ return CGEN_INSN_BITSIZE (insn);
+}
+\f
+/* Machine generated code added here. */
+
+const char * bpf_cgen_insert_operand
+ (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
+
+/* Main entry point for operand insertion.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `parse_insn_normal', but keeping it
+ separate makes clear the interface between `parse_insn_normal' and each of
+ the handlers. It's also needed by GAS to insert operands that couldn't be
+ resolved during parsing. */
+
+const char *
+bpf_cgen_insert_operand (CGEN_CPU_DESC cd,
+ int opindex,
+ CGEN_FIELDS * fields,
+ CGEN_INSN_BYTES_PTR buffer,
+ bfd_vma pc ATTRIBUTE_UNUSED)
+{
+ const char * errmsg = NULL;
+ unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
+
+ switch (opindex)
+ {
+ case BPF_OPERAND_DISP16 :
+ errmsg = insert_normal (cd, fields->f_offset16, 0|(1<<CGEN_IFLD_SIGNED), 16, 15, 16, 16, total_length, buffer);
+ break;
+ case BPF_OPERAND_DISP32 :
+ errmsg = insert_normal (cd, fields->f_imm32, 0|(1<<CGEN_IFLD_SIGNED), 32, 31, 32, 32, total_length, buffer);
+ break;
+ case BPF_OPERAND_DSTBE :
+ errmsg = insert_normal (cd, fields->f_dstbe, 0, 8, 7, 4, 8, total_length, buffer);
+ break;
+ case BPF_OPERAND_DSTLE :
+ errmsg = insert_normal (cd, fields->f_dstle, 0, 8, 3, 4, 8, total_length, buffer);
+ break;
+ case BPF_OPERAND_ENDSIZE :
+ errmsg = insert_normal (cd, fields->f_imm32, 0|(1<<CGEN_IFLD_SIGNED), 32, 31, 32, 32, total_length, buffer);
+ break;
+ case BPF_OPERAND_IMM32 :
+ errmsg = insert_normal (cd, fields->f_imm32, 0|(1<<CGEN_IFLD_SIGNED), 32, 31, 32, 32, total_length, buffer);
+ break;
+ case BPF_OPERAND_IMM64 :
+ {
+{
+ FLD (f_imm64_b) = 0;
+ FLD (f_imm64_c) = ((UDI) (FLD (f_imm64)) >> (32));
+ FLD (f_imm64_a) = ((FLD (f_imm64)) & (MAKEDI (0, 0xffffffff)));
+}
+ errmsg = insert_normal (cd, fields->f_imm64_a, 0, 32, 31, 32, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_imm64_b, 0, 64, 31, 32, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_imm64_c, 0, 96, 31, 32, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
+ case BPF_OPERAND_OFFSET16 :
+ errmsg = insert_normal (cd, fields->f_offset16, 0|(1<<CGEN_IFLD_SIGNED), 16, 15, 16, 16, total_length, buffer);
+ break;
+ case BPF_OPERAND_SRCBE :
+ errmsg = insert_normal (cd, fields->f_srcbe, 0, 8, 3, 4, 8, total_length, buffer);
+ break;
+ case BPF_OPERAND_SRCLE :
+ errmsg = insert_normal (cd, fields->f_srcle, 0, 8, 7, 4, 8, total_length, buffer);
+ break;
+
+ default :
+ /* xgettext:c-format */
+ opcodes_error_handler
+ (_("internal error: unrecognized field %d while building insn"),
+ opindex);
+ abort ();
+ }
+
+ return errmsg;
+}
+
+int bpf_cgen_extract_operand
+ (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
+
+/* Main entry point for operand extraction.
+ The result is <= 0 for error, >0 for success.
+ ??? Actual values aren't well defined right now.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `print_insn_normal', but keeping it
+ separate makes clear the interface between `print_insn_normal' and each of
+ the handlers. */
+
+int
+bpf_cgen_extract_operand (CGEN_CPU_DESC cd,
+ int opindex,
+ CGEN_EXTRACT_INFO *ex_info,
+ CGEN_INSN_INT insn_value,
+ CGEN_FIELDS * fields,
+ bfd_vma pc)
+{
+ /* Assume success (for those operands that are nops). */
+ int length = 1;
+ unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
+
+ switch (opindex)
+ {
+ case BPF_OPERAND_DISP16 :
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 16, 15, 16, 16, total_length, pc, & fields->f_offset16);
+ break;
+ case BPF_OPERAND_DISP32 :
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 32, 31, 32, 32, total_length, pc, & fields->f_imm32);
+ break;
+ case BPF_OPERAND_DSTBE :
+ length = extract_normal (cd, ex_info, insn_value, 0, 8, 7, 4, 8, total_length, pc, & fields->f_dstbe);
+ break;
+ case BPF_OPERAND_DSTLE :
+ length = extract_normal (cd, ex_info, insn_value, 0, 8, 3, 4, 8, total_length, pc, & fields->f_dstle);
+ break;
+ case BPF_OPERAND_ENDSIZE :
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 32, 31, 32, 32, total_length, pc, & fields->f_imm32);
+ break;
+ case BPF_OPERAND_IMM32 :
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 32, 31, 32, 32, total_length, pc, & fields->f_imm32);
+ break;
+ case BPF_OPERAND_IMM64 :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 32, 31, 32, 32, total_length, pc, & fields->f_imm64_a);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 64, 31, 32, 32, total_length, pc, & fields->f_imm64_b);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 96, 31, 32, 32, total_length, pc, & fields->f_imm64_c);
+ if (length <= 0) break;
+{
+ FLD (f_imm64) = ((((((DI) (UINT) (FLD (f_imm64_c)))) << (32))) | (((DI) (UINT) (FLD (f_imm64_a)))));
+}
+ }
+ break;
+ case BPF_OPERAND_OFFSET16 :
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 16, 15, 16, 16, total_length, pc, & fields->f_offset16);
+ break;
+ case BPF_OPERAND_SRCBE :
+ length = extract_normal (cd, ex_info, insn_value, 0, 8, 3, 4, 8, total_length, pc, & fields->f_srcbe);
+ break;
+ case BPF_OPERAND_SRCLE :
+ length = extract_normal (cd, ex_info, insn_value, 0, 8, 7, 4, 8, total_length, pc, & fields->f_srcle);
+ break;
+
+ default :
+ /* xgettext:c-format */
+ opcodes_error_handler
+ (_("internal error: unrecognized field %d while decoding insn"),
+ opindex);
+ abort ();
+ }
+
+ return length;
+}
+
+cgen_insert_fn * const bpf_cgen_insert_handlers[] =
+{
+ insert_insn_normal,
+};
+
+cgen_extract_fn * const bpf_cgen_extract_handlers[] =
+{
+ extract_insn_normal,
+};
+
+int bpf_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+bfd_vma bpf_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+
+/* Getting values from cgen_fields is handled by a collection of functions.
+ They are distinguished by the type of the VALUE argument they return.
+ TODO: floating point, inlining support, remove cases where result type
+ not appropriate. */
+
+int
+bpf_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ int opindex,
+ const CGEN_FIELDS * fields)
+{
+ int value;
+
+ switch (opindex)
+ {
+ case BPF_OPERAND_DISP16 :
+ value = fields->f_offset16;
+ break;
+ case BPF_OPERAND_DISP32 :
+ value = fields->f_imm32;
+ break;
+ case BPF_OPERAND_DSTBE :
+ value = fields->f_dstbe;
+ break;
+ case BPF_OPERAND_DSTLE :
+ value = fields->f_dstle;
+ break;
+ case BPF_OPERAND_ENDSIZE :
+ value = fields->f_imm32;
+ break;
+ case BPF_OPERAND_IMM32 :
+ value = fields->f_imm32;
+ break;
+ case BPF_OPERAND_IMM64 :
+ value = fields->f_imm64;
+ break;
+ case BPF_OPERAND_OFFSET16 :
+ value = fields->f_offset16;
+ break;
+ case BPF_OPERAND_SRCBE :
+ value = fields->f_srcbe;
+ break;
+ case BPF_OPERAND_SRCLE :
+ value = fields->f_srcle;
+ break;
+
+ default :
+ /* xgettext:c-format */
+ opcodes_error_handler
+ (_("internal error: unrecognized field %d while getting int operand"),
+ opindex);
+ abort ();
+ }
+
+ return value;
+}
+
+bfd_vma
+bpf_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ int opindex,
+ const CGEN_FIELDS * fields)
+{
+ bfd_vma value;
+
+ switch (opindex)
+ {
+ case BPF_OPERAND_DISP16 :
+ value = fields->f_offset16;
+ break;
+ case BPF_OPERAND_DISP32 :
+ value = fields->f_imm32;
+ break;
+ case BPF_OPERAND_DSTBE :
+ value = fields->f_dstbe;
+ break;
+ case BPF_OPERAND_DSTLE :
+ value = fields->f_dstle;
+ break;
+ case BPF_OPERAND_ENDSIZE :
+ value = fields->f_imm32;
+ break;
+ case BPF_OPERAND_IMM32 :
+ value = fields->f_imm32;
+ break;
+ case BPF_OPERAND_IMM64 :
+ value = fields->f_imm64;
+ break;
+ case BPF_OPERAND_OFFSET16 :
+ value = fields->f_offset16;
+ break;
+ case BPF_OPERAND_SRCBE :
+ value = fields->f_srcbe;
+ break;
+ case BPF_OPERAND_SRCLE :
+ value = fields->f_srcle;
+ break;
+
+ default :
+ /* xgettext:c-format */
+ opcodes_error_handler
+ (_("internal error: unrecognized field %d while getting vma operand"),
+ opindex);
+ abort ();
+ }
+
+ return value;
+}
+
+void bpf_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
+void bpf_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
+
+/* Stuffing values in cgen_fields is handled by a collection of functions.
+ They are distinguished by the type of the VALUE argument they accept.
+ TODO: floating point, inlining support, remove cases where argument type
+ not appropriate. */
+
+void
+bpf_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ int opindex,
+ CGEN_FIELDS * fields,
+ int value)
+{
+ switch (opindex)
+ {
+ case BPF_OPERAND_DISP16 :
+ fields->f_offset16 = value;
+ break;
+ case BPF_OPERAND_DISP32 :
+ fields->f_imm32 = value;
+ break;
+ case BPF_OPERAND_DSTBE :
+ fields->f_dstbe = value;
+ break;
+ case BPF_OPERAND_DSTLE :
+ fields->f_dstle = value;
+ break;
+ case BPF_OPERAND_ENDSIZE :
+ fields->f_imm32 = value;
+ break;
+ case BPF_OPERAND_IMM32 :
+ fields->f_imm32 = value;
+ break;
+ case BPF_OPERAND_IMM64 :
+ fields->f_imm64 = value;
+ break;
+ case BPF_OPERAND_OFFSET16 :
+ fields->f_offset16 = value;
+ break;
+ case BPF_OPERAND_SRCBE :
+ fields->f_srcbe = value;
+ break;
+ case BPF_OPERAND_SRCLE :
+ fields->f_srcle = value;
+ break;
+
+ default :
+ /* xgettext:c-format */
+ opcodes_error_handler
+ (_("internal error: unrecognized field %d while setting int operand"),
+ opindex);
+ abort ();
+ }
+}
+
+void
+bpf_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ int opindex,
+ CGEN_FIELDS * fields,
+ bfd_vma value)
+{
+ switch (opindex)
+ {
+ case BPF_OPERAND_DISP16 :
+ fields->f_offset16 = value;
+ break;
+ case BPF_OPERAND_DISP32 :
+ fields->f_imm32 = value;
+ break;
+ case BPF_OPERAND_DSTBE :
+ fields->f_dstbe = value;
+ break;
+ case BPF_OPERAND_DSTLE :
+ fields->f_dstle = value;
+ break;
+ case BPF_OPERAND_ENDSIZE :
+ fields->f_imm32 = value;
+ break;
+ case BPF_OPERAND_IMM32 :
+ fields->f_imm32 = value;
+ break;
+ case BPF_OPERAND_IMM64 :
+ fields->f_imm64 = value;
+ break;
+ case BPF_OPERAND_OFFSET16 :
+ fields->f_offset16 = value;
+ break;
+ case BPF_OPERAND_SRCBE :
+ fields->f_srcbe = value;
+ break;
+ case BPF_OPERAND_SRCLE :
+ fields->f_srcle = value;
+ break;
+
+ default :
+ /* xgettext:c-format */
+ opcodes_error_handler
+ (_("internal error: unrecognized field %d while setting vma operand"),
+ opindex);
+ abort ();
+ }
+}
+
+/* Function to call before using the instruction builder tables. */
+
+void
+bpf_cgen_init_ibld_table (CGEN_CPU_DESC cd)
+{
+ cd->insert_handlers = & bpf_cgen_insert_handlers[0];
+ cd->extract_handlers = & bpf_cgen_extract_handlers[0];
+
+ cd->insert_operand = bpf_cgen_insert_operand;
+ cd->extract_operand = bpf_cgen_extract_operand;
+
+ cd->get_int_operand = bpf_cgen_get_int_operand;
+ cd->set_int_operand = bpf_cgen_set_int_operand;
+ cd->get_vma_operand = bpf_cgen_get_vma_operand;
+ cd->set_vma_operand = bpf_cgen_set_vma_operand;
+}
diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c
new file mode 100644
index 0000000000..bb00ba8b58
--- /dev/null
+++ b/opcodes/bpf-opc.c
@@ -0,0 +1,1495 @@
+/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
+/* Instruction opcode table for bpf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996-2019 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#include "sysdep.h"
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "bpf-desc.h"
+#include "bpf-opc.h"
+#include "libiberty.h"
+
+/* -- opc.c */
+\f
+/* -- asm.c */
+/* The hash functions are recorded here to help keep assembler code out of
+ the disassembler and vice versa. */
+
+static int asm_hash_insn_p (const CGEN_INSN *);
+static unsigned int asm_hash_insn (const char *);
+static int dis_hash_insn_p (const CGEN_INSN *);
+static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
+
+/* Instruction formats. */
+
+#define F(f) & bpf_cgen_ifld_table[BPF_##f]
+static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
+ 0, 0, 0x0, { { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addile ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addrle ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_negle ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addibe ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addrbe ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_negbe ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_endlele ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_endlebe ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lddwle ATTRIBUTE_UNUSED = {
+ 8, 128, 0xff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lddwbe ATTRIBUTE_UNUSED = {
+ 8, 128, 0xff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldabswle ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldabswbe ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldxwle ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldxwbe ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_stble ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_stbbe ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jeqile ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jeqrle ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jeqibe ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jeqrbe ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ja ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_call ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_exit ATTRIBUTE_UNUSED = {
+ 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+#undef F
+
+#define A(a) (1 << CGEN_INSN_##a)
+#define OPERAND(op) BPF_OPERAND_##op
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The instruction table. */
+
+static const CGEN_OPCODE bpf_cgen_insn_opcode_table[MAX_INSNS] =
+{
+ /* Special null first entry.
+ A `num' value of zero is thus invalid.
+ Also, the special `invalid' insn resides here. */
+ { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
+/* add $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0x7 }
+ },
+/* add $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0xf }
+ },
+/* add32 $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0x4 }
+ },
+/* add32 $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0xc }
+ },
+/* sub $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0x17 }
+ },
+/* sub $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0x1f }
+ },
+/* sub32 $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0x14 }
+ },
+/* sub32 $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0x1c }
+ },
+/* mul $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0x27 }
+ },
+/* mul $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0x2f }
+ },
+/* mul32 $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0x24 }
+ },
+/* mul32 $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0x2c }
+ },
+/* div $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0x37 }
+ },
+/* div $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0x3f }
+ },
+/* div32 $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0x34 }
+ },
+/* div32 $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0x3c }
+ },
+/* or $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0x47 }
+ },
+/* or $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0x4f }
+ },
+/* or32 $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0x44 }
+ },
+/* or32 $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0x4c }
+ },
+/* and $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0x57 }
+ },
+/* and $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0x5f }
+ },
+/* and32 $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0x54 }
+ },
+/* and32 $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0x5c }
+ },
+/* lsh $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0x67 }
+ },
+/* lsh $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0x6f }
+ },
+/* lsh32 $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0x64 }
+ },
+/* lsh32 $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0x6c }
+ },
+/* rsh $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0x77 }
+ },
+/* rsh $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0x7f }
+ },
+/* rsh32 $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0x74 }
+ },
+/* rsh32 $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0x7c }
+ },
+/* mod $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0x97 }
+ },
+/* mod $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0x9f }
+ },
+/* mod32 $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0x94 }
+ },
+/* mod32 $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0x9c }
+ },
+/* xor $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0xa7 }
+ },
+/* xor $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0xaf }
+ },
+/* xor32 $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0xa4 }
+ },
+/* xor32 $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0xac }
+ },
+/* mov $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0xb7 }
+ },
+/* mov $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0xbf }
+ },
+/* mov32 $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0xb4 }
+ },
+/* mov32 $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0xbc }
+ },
+/* arsh $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0xc7 }
+ },
+/* arsh $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0xcf }
+ },
+/* arsh32 $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0xc4 }
+ },
+/* arsh32 $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0xcc }
+ },
+/* neg $dstle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), 0 } },
+ & ifmt_negle, { 0x8f }
+ },
+/* neg32 $dstle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), 0 } },
+ & ifmt_negle, { 0x8c }
+ },
+/* add $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0x7 }
+ },
+/* add $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0xf }
+ },
+/* add32 $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0x4 }
+ },
+/* add32 $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0xc }
+ },
+/* sub $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0x17 }
+ },
+/* sub $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0x1f }
+ },
+/* sub32 $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0x14 }
+ },
+/* sub32 $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0x1c }
+ },
+/* mul $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0x27 }
+ },
+/* mul $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0x2f }
+ },
+/* mul32 $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0x24 }
+ },
+/* mul32 $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0x2c }
+ },
+/* div $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0x37 }
+ },
+/* div $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0x3f }
+ },
+/* div32 $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0x34 }
+ },
+/* div32 $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0x3c }
+ },
+/* or $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0x47 }
+ },
+/* or $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0x4f }
+ },
+/* or32 $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0x44 }
+ },
+/* or32 $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0x4c }
+ },
+/* and $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0x57 }
+ },
+/* and $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0x5f }
+ },
+/* and32 $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0x54 }
+ },
+/* and32 $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0x5c }
+ },
+/* lsh $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0x67 }
+ },
+/* lsh $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0x6f }
+ },
+/* lsh32 $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0x64 }
+ },
+/* lsh32 $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0x6c }
+ },
+/* rsh $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0x77 }
+ },
+/* rsh $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0x7f }
+ },
+/* rsh32 $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0x74 }
+ },
+/* rsh32 $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0x7c }
+ },
+/* mod $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0x97 }
+ },
+/* mod $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0x9f }
+ },
+/* mod32 $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0x94 }
+ },
+/* mod32 $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0x9c }
+ },
+/* xor $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0xa7 }
+ },
+/* xor $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0xaf }
+ },
+/* xor32 $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0xa4 }
+ },
+/* xor32 $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0xac }
+ },
+/* mov $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0xb7 }
+ },
+/* mov $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0xbf }
+ },
+/* mov32 $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0xb4 }
+ },
+/* mov32 $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0xbc }
+ },
+/* arsh $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0xc7 }
+ },
+/* arsh $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0xcf }
+ },
+/* arsh32 $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0xc4 }
+ },
+/* arsh32 $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0xcc }
+ },
+/* neg $dstbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), 0 } },
+ & ifmt_negbe, { 0x8f }
+ },
+/* neg32 $dstbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), 0 } },
+ & ifmt_negbe, { 0x8c }
+ },
+/* endle $dstle,$endsize */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (ENDSIZE), 0 } },
+ & ifmt_endlele, { 0xd4 }
+ },
+/* endbe $dstle,$endsize */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (ENDSIZE), 0 } },
+ & ifmt_endlele, { 0xdc }
+ },
+/* endle $dstbe,$endsize */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (ENDSIZE), 0 } },
+ & ifmt_endlebe, { 0xd4 }
+ },
+/* endbe $dstbe,$endsize */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (ENDSIZE), 0 } },
+ & ifmt_endlebe, { 0xdc }
+ },
+/* lddw $dstle,$imm64 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM64), 0 } },
+ & ifmt_lddwle, { 0x18 }
+ },
+/* lddw $dstbe,$imm64 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM64), 0 } },
+ & ifmt_lddwbe, { 0x18 }
+ },
+/* ldabsw $dstle,$srcle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (IMM32), 0 } },
+ & ifmt_ldabswle, { 0x20 }
+ },
+/* ldabsh $dstle,$srcle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (IMM32), 0 } },
+ & ifmt_ldabswle, { 0x28 }
+ },
+/* ldabsb $dstle,$srcle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (IMM32), 0 } },
+ & ifmt_ldabswle, { 0x30 }
+ },
+/* ldabsdw $dstle,$srcle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (IMM32), 0 } },
+ & ifmt_ldabswle, { 0x38 }
+ },
+/* ldindw $dstle,$srcle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (IMM32), 0 } },
+ & ifmt_ldabswle, { 0x40 }
+ },
+/* ldindh $dstle,$srcle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (IMM32), 0 } },
+ & ifmt_ldabswle, { 0x48 }
+ },
+/* ldindb $dstle,$srcle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (IMM32), 0 } },
+ & ifmt_ldabswle, { 0x50 }
+ },
+/* ldinddw $dstle,$srcle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (IMM32), 0 } },
+ & ifmt_ldabswle, { 0x58 }
+ },
+/* ldabsw $dstbe,$srcbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (IMM32), 0 } },
+ & ifmt_ldabswbe, { 0x20 }
+ },
+/* ldabsh $dstbe,$srcbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (IMM32), 0 } },
+ & ifmt_ldabswbe, { 0x28 }
+ },
+/* ldabsb $dstbe,$srcbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (IMM32), 0 } },
+ & ifmt_ldabswbe, { 0x30 }
+ },
+/* ldabsdw $dstbe,$srcbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (IMM32), 0 } },
+ & ifmt_ldabswbe, { 0x38 }
+ },
+/* ldindw $dstbe,$srcbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (IMM32), 0 } },
+ & ifmt_ldabswbe, { 0x40 }
+ },
+/* ldindh $dstbe,$srcbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (IMM32), 0 } },
+ & ifmt_ldabswbe, { 0x48 }
+ },
+/* ldindb $dstbe,$srcbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (IMM32), 0 } },
+ & ifmt_ldabswbe, { 0x50 }
+ },
+/* ldinddw $dstbe,$srcbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (IMM32), 0 } },
+ & ifmt_ldabswbe, { 0x58 }
+ },
+/* ldxw $dstle,[$srcle+$offset16] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', '[', OP (SRCLE), '+', OP (OFFSET16), ']', 0 } },
+ & ifmt_ldxwle, { 0x61 }
+ },
+/* ldxh $dstle,[$srcle+$offset16] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', '[', OP (SRCLE), '+', OP (OFFSET16), ']', 0 } },
+ & ifmt_ldxwle, { 0x69 }
+ },
+/* ldxb $dstle,[$srcle+$offset16] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', '[', OP (SRCLE), '+', OP (OFFSET16), ']', 0 } },
+ & ifmt_ldxwle, { 0x71 }
+ },
+/* ldxdw $dstle,[$srcle+$offset16] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', '[', OP (SRCLE), '+', OP (OFFSET16), ']', 0 } },
+ & ifmt_ldxwle, { 0x79 }
+ },
+/* stxw [$dstle+$offset16],$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },
+ & ifmt_ldxwle, { 0x63 }
+ },
+/* stxh [$dstle+$offset16],$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },
+ & ifmt_ldxwle, { 0x6b }
+ },
+/* stxb [$dstle+$offset16],$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },
+ & ifmt_ldxwle, { 0x73 }
+ },
+/* stxdw [$dstle+$offset16],$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },
+ & ifmt_ldxwle, { 0x7b }
+ },
+/* ldxw $dstbe,[$srcbe+$offset16] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', '[', OP (SRCBE), '+', OP (OFFSET16), ']', 0 } },
+ & ifmt_ldxwbe, { 0x61 }
+ },
+/* ldxh $dstbe,[$srcbe+$offset16] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', '[', OP (SRCBE), '+', OP (OFFSET16), ']', 0 } },
+ & ifmt_ldxwbe, { 0x69 }
+ },
+/* ldxb $dstbe,[$srcbe+$offset16] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', '[', OP (SRCBE), '+', OP (OFFSET16), ']', 0 } },
+ & ifmt_ldxwbe, { 0x71 }
+ },
+/* ldxdw $dstbe,[$srcbe+$offset16] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', '[', OP (SRCBE), '+', OP (OFFSET16), ']', 0 } },
+ & ifmt_ldxwbe, { 0x79 }
+ },
+/* stxw [$dstbe+$offset16],$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },
+ & ifmt_ldxwbe, { 0x63 }
+ },
+/* stxh [$dstbe+$offset16],$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },
+ & ifmt_ldxwbe, { 0x6b }
+ },
+/* stxb [$dstbe+$offset16],$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },
+ & ifmt_ldxwbe, { 0x73 }
+ },
+/* stxdw [$dstbe+$offset16],$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },
+ & ifmt_ldxwbe, { 0x7b }
+ },
+/* stb [$dstle+$offset16],$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
+ & ifmt_stble, { 0x72 }
+ },
+/* sth [$dstle+$offset16],$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
+ & ifmt_stble, { 0x6a }
+ },
+/* stw [$dstle+$offset16],$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
+ & ifmt_stble, { 0x62 }
+ },
+/* stdw [$dstle+$offset16],$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
+ & ifmt_stble, { 0x7a }
+ },
+/* stb [$dstbe+$offset16],$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
+ & ifmt_stbbe, { 0x72 }
+ },
+/* sth [$dstbe+$offset16],$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
+ & ifmt_stbbe, { 0x6a }
+ },
+/* stw [$dstbe+$offset16],$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
+ & ifmt_stbbe, { 0x62 }
+ },
+/* stdw [$dstbe+$offset16],$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
+ & ifmt_stbbe, { 0x7a }
+ },
+/* jeq $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0x15 }
+ },
+/* jeq $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0x1d }
+ },
+/* jgt $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0x25 }
+ },
+/* jgt $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0x2d }
+ },
+/* jge $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0x35 }
+ },
+/* jge $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0x3d }
+ },
+/* jlt $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0xa5 }
+ },
+/* jlt $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0xad }
+ },
+/* jle $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0xb5 }
+ },
+/* jle $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0xbd }
+ },
+/* jset $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0x45 }
+ },
+/* jset $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0x4d }
+ },
+/* jne $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0x55 }
+ },
+/* jne $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0x5d }
+ },
+/* jsgt $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0x65 }
+ },
+/* jsgt $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0x6d }
+ },
+/* jsge $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0x75 }
+ },
+/* jsge $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0x7d }
+ },
+/* jslt $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0xc5 }
+ },
+/* jslt $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0xcd }
+ },
+/* jsle $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0xd5 }
+ },
+/* jsle $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0xdd }
+ },
+/* jeq $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0x15 }
+ },
+/* jeq $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0x1d }
+ },
+/* jgt $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0x25 }
+ },
+/* jgt $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0x2d }
+ },
+/* jge $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0x35 }
+ },
+/* jge $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0x3d }
+ },
+/* jlt $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0xa5 }
+ },
+/* jlt $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0xad }
+ },
+/* jle $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0xb5 }
+ },
+/* jle $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0xbd }
+ },
+/* jset $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0x45 }
+ },
+/* jset $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0x4d }
+ },
+/* jne $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0x55 }
+ },
+/* jne $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0x5d }
+ },
+/* jsgt $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0x65 }
+ },
+/* jsgt $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0x6d }
+ },
+/* jsge $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0x75 }
+ },
+/* jsge $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0x7d }
+ },
+/* jslt $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0xc5 }
+ },
+/* jslt $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0xcd }
+ },
+/* jsle $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0xd5 }
+ },
+/* jsle $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0xdd }
+ },
+/* ja $disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DISP16), 0 } },
+ & ifmt_ja, { 0x5 }
+ },
+/* call $disp32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DISP32), 0 } },
+ & ifmt_call, { 0x85 }
+ },
+/* exit */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_exit, { 0x95 }
+ },
+/* xadddw [$dstle+$offset16],$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },
+ & ifmt_ldxwle, { 0xdb }
+ },
+/* xaddw [$dstle+$offset16],$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },
+ & ifmt_ldxwle, { 0xc3 }
+ },
+/* xadddw [$dstbe+$offset16],$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },
+ & ifmt_ldxwbe, { 0xdb }
+ },
+/* xaddw [$dstbe+$offset16],$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },
+ & ifmt_ldxwbe, { 0xc3 }
+ },
+};
+
+#undef A
+#undef OPERAND
+#undef MNEM
+#undef OP
+
+/* Formats for ALIAS macro-insns. */
+
+#define F(f) & bpf_cgen_ifld_table[BPF_##f]
+#undef F
+
+/* Each non-simple macro entry points to an array of expansion possibilities. */
+
+#define A(a) (1 << CGEN_INSN_##a)
+#define OPERAND(op) BPF_OPERAND_##op
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The macro instruction table. */
+
+static const CGEN_IBASE bpf_cgen_macro_insn_table[] =
+{
+};
+
+/* The macro instruction opcode table. */
+
+static const CGEN_OPCODE bpf_cgen_macro_insn_opcode_table[] =
+{
+};
+
+#undef A
+#undef OPERAND
+#undef MNEM
+#undef OP
+
+#ifndef CGEN_ASM_HASH_P
+#define CGEN_ASM_HASH_P(insn) 1
+#endif
+
+#ifndef CGEN_DIS_HASH_P
+#define CGEN_DIS_HASH_P(insn) 1
+#endif
+
+/* Return non-zero if INSN is to be added to the hash table.
+ Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
+
+static int
+asm_hash_insn_p (const CGEN_INSN *insn ATTRIBUTE_UNUSED)
+{
+ return CGEN_ASM_HASH_P (insn);
+}
+
+static int
+dis_hash_insn_p (const CGEN_INSN *insn)
+{
+ /* If building the hash table and the NO-DIS attribute is present,
+ ignore. */
+ if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
+ return 0;
+ return CGEN_DIS_HASH_P (insn);
+}
+
+#ifndef CGEN_ASM_HASH
+#define CGEN_ASM_HASH_SIZE 127
+#ifdef CGEN_MNEMONIC_OPERANDS
+#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
+#else
+#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
+#endif
+#endif
+
+/* It doesn't make much sense to provide a default here,
+ but while this is under development we do.
+ BUFFER is a pointer to the bytes of the insn, target order.
+ VALUE is the first base_insn_bitsize bits as an int in host order. */
+
+#ifndef CGEN_DIS_HASH
+#define CGEN_DIS_HASH_SIZE 256
+#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
+#endif
+
+/* The result is the hash value of the insn.
+ Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
+
+static unsigned int
+asm_hash_insn (const char *mnem)
+{
+ return CGEN_ASM_HASH (mnem);
+}
+
+/* BUF is a pointer to the bytes of the insn, target order.
+ VALUE is the first base_insn_bitsize bits as an int in host order. */
+
+static unsigned int
+dis_hash_insn (const char *buf ATTRIBUTE_UNUSED,
+ CGEN_INSN_INT value ATTRIBUTE_UNUSED)
+{
+ return CGEN_DIS_HASH (buf, value);
+}
+
+/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
+
+static void
+set_fields_bitsize (CGEN_FIELDS *fields, int size)
+{
+ CGEN_FIELDS_BITSIZE (fields) = size;
+}
+
+/* Function to call before using the operand instance table.
+ This plugs the opcode entries and macro instructions into the cpu table. */
+
+void
+bpf_cgen_init_opcode_table (CGEN_CPU_DESC cd)
+{
+ int i;
+ int num_macros = (sizeof (bpf_cgen_macro_insn_table) /
+ sizeof (bpf_cgen_macro_insn_table[0]));
+ const CGEN_IBASE *ib = & bpf_cgen_macro_insn_table[0];
+ const CGEN_OPCODE *oc = & bpf_cgen_macro_insn_opcode_table[0];
+ CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
+
+ /* This test has been added to avoid a warning generated
+ if memset is called with a third argument of value zero. */
+ if (num_macros >= 1)
+ memset (insns, 0, num_macros * sizeof (CGEN_INSN));
+ for (i = 0; i < num_macros; ++i)
+ {
+ insns[i].base = &ib[i];
+ insns[i].opcode = &oc[i];
+ bpf_cgen_build_insn_regex (& insns[i]);
+ }
+ cd->macro_insn_table.init_entries = insns;
+ cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
+ cd->macro_insn_table.num_init_entries = num_macros;
+
+ oc = & bpf_cgen_insn_opcode_table[0];
+ insns = (CGEN_INSN *) cd->insn_table.init_entries;
+ for (i = 0; i < MAX_INSNS; ++i)
+ {
+ insns[i].opcode = &oc[i];
+ bpf_cgen_build_insn_regex (& insns[i]);
+ }
+
+ cd->sizeof_fields = sizeof (CGEN_FIELDS);
+ cd->set_fields_bitsize = set_fields_bitsize;
+
+ cd->asm_hash_p = asm_hash_insn_p;
+ cd->asm_hash = asm_hash_insn;
+ cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
+
+ cd->dis_hash_p = dis_hash_insn_p;
+ cd->dis_hash = dis_hash_insn;
+ cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
+}
diff --git a/opcodes/bpf-opc.h b/opcodes/bpf-opc.h
new file mode 100644
index 0000000000..b989d7f031
--- /dev/null
+++ b/opcodes/bpf-opc.h
@@ -0,0 +1,151 @@
+/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
+/* Instruction opcode header for bpf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996-2019 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef BPF_OPC_H
+#define BPF_OPC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* -- opc.h */
+
+#undef CGEN_DIS_HASH_SIZE
+#define CGEN_DIS_HASH_SIZE 1
+
+#undef CGEN_DIS_HASH
+#define CGEN_DIS_HASH(buffer, value) 0
+
+/* Allows reason codes to be output when assembler errors occur. */
+#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+
+#define CGEN_VALIDATE_INSN_SUPPORTED
+extern int bpf_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
+
+\f
+/* -- opc.c */
+/* Enum declaration for bpf instruction types. */
+typedef enum cgen_insn_type {
+ BPF_INSN_INVALID, BPF_INSN_ADDILE, BPF_INSN_ADDRLE, BPF_INSN_ADD32ILE
+ , BPF_INSN_ADD32RLE, BPF_INSN_SUBILE, BPF_INSN_SUBRLE, BPF_INSN_SUB32ILE
+ , BPF_INSN_SUB32RLE, BPF_INSN_MULILE, BPF_INSN_MULRLE, BPF_INSN_MUL32ILE
+ , BPF_INSN_MUL32RLE, BPF_INSN_DIVILE, BPF_INSN_DIVRLE, BPF_INSN_DIV32ILE
+ , BPF_INSN_DIV32RLE, BPF_INSN_ORILE, BPF_INSN_ORRLE, BPF_INSN_OR32ILE
+ , BPF_INSN_OR32RLE, BPF_INSN_ANDILE, BPF_INSN_ANDRLE, BPF_INSN_AND32ILE
+ , BPF_INSN_AND32RLE, BPF_INSN_LSHILE, BPF_INSN_LSHRLE, BPF_INSN_LSH32ILE
+ , BPF_INSN_LSH32RLE, BPF_INSN_RSHILE, BPF_INSN_RSHRLE, BPF_INSN_RSH32ILE
+ , BPF_INSN_RSH32RLE, BPF_INSN_MODILE, BPF_INSN_MODRLE, BPF_INSN_MOD32ILE
+ , BPF_INSN_MOD32RLE, BPF_INSN_XORILE, BPF_INSN_XORRLE, BPF_INSN_XOR32ILE
+ , BPF_INSN_XOR32RLE, BPF_INSN_MOVILE, BPF_INSN_MOVRLE, BPF_INSN_MOV32ILE
+ , BPF_INSN_MOV32RLE, BPF_INSN_ARSHILE, BPF_INSN_ARSHRLE, BPF_INSN_ARSH32ILE
+ , BPF_INSN_ARSH32RLE, BPF_INSN_NEGLE, BPF_INSN_NEG32LE, BPF_INSN_ADDIBE
+ , BPF_INSN_ADDRBE, BPF_INSN_ADD32IBE, BPF_INSN_ADD32RBE, BPF_INSN_SUBIBE
+ , BPF_INSN_SUBRBE, BPF_INSN_SUB32IBE, BPF_INSN_SUB32RBE, BPF_INSN_MULIBE
+ , BPF_INSN_MULRBE, BPF_INSN_MUL32IBE, BPF_INSN_MUL32RBE, BPF_INSN_DIVIBE
+ , BPF_INSN_DIVRBE, BPF_INSN_DIV32IBE, BPF_INSN_DIV32RBE, BPF_INSN_ORIBE
+ , BPF_INSN_ORRBE, BPF_INSN_OR32IBE, BPF_INSN_OR32RBE, BPF_INSN_ANDIBE
+ , BPF_INSN_ANDRBE, BPF_INSN_AND32IBE, BPF_INSN_AND32RBE, BPF_INSN_LSHIBE
+ , BPF_INSN_LSHRBE, BPF_INSN_LSH32IBE, BPF_INSN_LSH32RBE, BPF_INSN_RSHIBE
+ , BPF_INSN_RSHRBE, BPF_INSN_RSH32IBE, BPF_INSN_RSH32RBE, BPF_INSN_MODIBE
+ , BPF_INSN_MODRBE, BPF_INSN_MOD32IBE, BPF_INSN_MOD32RBE, BPF_INSN_XORIBE
+ , BPF_INSN_XORRBE, BPF_INSN_XOR32IBE, BPF_INSN_XOR32RBE, BPF_INSN_MOVIBE
+ , BPF_INSN_MOVRBE, BPF_INSN_MOV32IBE, BPF_INSN_MOV32RBE, BPF_INSN_ARSHIBE
+ , BPF_INSN_ARSHRBE, BPF_INSN_ARSH32IBE, BPF_INSN_ARSH32RBE, BPF_INSN_NEGBE
+ , BPF_INSN_NEG32BE, BPF_INSN_ENDLELE, BPF_INSN_ENDBELE, BPF_INSN_ENDLEBE
+ , BPF_INSN_ENDBEBE, BPF_INSN_LDDWLE, BPF_INSN_LDDWBE, BPF_INSN_LDABSWLE
+ , BPF_INSN_LDABSHLE, BPF_INSN_LDABSBLE, BPF_INSN_LDABSDWLE, BPF_INSN_LDINDWLE
+ , BPF_INSN_LDINDHLE, BPF_INSN_LDINDBLE, BPF_INSN_LDINDDWLE, BPF_INSN_LDABSWBE
+ , BPF_INSN_LDABSHBE, BPF_INSN_LDABSBBE, BPF_INSN_LDABSDWBE, BPF_INSN_LDINDWBE
+ , BPF_INSN_LDINDHBE, BPF_INSN_LDINDBBE, BPF_INSN_LDINDDWBE, BPF_INSN_LDXWLE
+ , BPF_INSN_LDXHLE, BPF_INSN_LDXBLE, BPF_INSN_LDXDWLE, BPF_INSN_STXWLE
+ , BPF_INSN_STXHLE, BPF_INSN_STXBLE, BPF_INSN_STXDWLE, BPF_INSN_LDXWBE
+ , BPF_INSN_LDXHBE, BPF_INSN_LDXBBE, BPF_INSN_LDXDWBE, BPF_INSN_STXWBE
+ , BPF_INSN_STXHBE, BPF_INSN_STXBBE, BPF_INSN_STXDWBE, BPF_INSN_STBLE
+ , BPF_INSN_STHLE, BPF_INSN_STWLE, BPF_INSN_STDWLE, BPF_INSN_STBBE
+ , BPF_INSN_STHBE, BPF_INSN_STWBE, BPF_INSN_STDWBE, BPF_INSN_JEQILE
+ , BPF_INSN_JEQRLE, BPF_INSN_JGTILE, BPF_INSN_JGTRLE, BPF_INSN_JGEILE
+ , BPF_INSN_JGERLE, BPF_INSN_JLTILE, BPF_INSN_JLTRLE, BPF_INSN_JLEILE
+ , BPF_INSN_JLERLE, BPF_INSN_JSETILE, BPF_INSN_JSETRLE, BPF_INSN_JNEILE
+ , BPF_INSN_JNERLE, BPF_INSN_JSGTILE, BPF_INSN_JSGTRLE, BPF_INSN_JSGEILE
+ , BPF_INSN_JSGERLE, BPF_INSN_JSLTILE, BPF_INSN_JSLTRLE, BPF_INSN_JSLEILE
+ , BPF_INSN_JSLERLE, BPF_INSN_JEQIBE, BPF_INSN_JEQRBE, BPF_INSN_JGTIBE
+ , BPF_INSN_JGTRBE, BPF_INSN_JGEIBE, BPF_INSN_JGERBE, BPF_INSN_JLTIBE
+ , BPF_INSN_JLTRBE, BPF_INSN_JLEIBE, BPF_INSN_JLERBE, BPF_INSN_JSETIBE
+ , BPF_INSN_JSETRBE, BPF_INSN_JNEIBE, BPF_INSN_JNERBE, BPF_INSN_JSGTIBE
+ , BPF_INSN_JSGTRBE, BPF_INSN_JSGEIBE, BPF_INSN_JSGERBE, BPF_INSN_JSLTIBE
+ , BPF_INSN_JSLTRBE, BPF_INSN_JSLEIBE, BPF_INSN_JSLERBE, BPF_INSN_JA
+ , BPF_INSN_CALL, BPF_INSN_EXIT, BPF_INSN_XADDDWLE, BPF_INSN_XADDWLE
+ , BPF_INSN_XADDDWBE, BPF_INSN_XADDWBE
+} CGEN_INSN_TYPE;
+
+/* Index of `invalid' insn place holder. */
+#define CGEN_INSN_INVALID BPF_INSN_INVALID
+
+/* Total number of insns in table. */
+#define MAX_INSNS ((int) BPF_INSN_XADDWBE + 1)
+
+/* This struct records data prior to insertion or after extraction. */
+struct cgen_fields
+{
+ int length;
+ long f_nil;
+ long f_anyof;
+ long f_op_code;
+ long f_op_src;
+ long f_op_class;
+ long f_op_mode;
+ long f_op_size;
+ long f_dstle;
+ long f_srcle;
+ long f_dstbe;
+ long f_srcbe;
+ long f_regs;
+ long f_offset16;
+ long f_imm32;
+ long f_imm64_a;
+ long f_imm64_b;
+ long f_imm64_c;
+ int64_t f_imm64;
+};
+
+#define CGEN_INIT_PARSE(od) \
+{\
+}
+#define CGEN_INIT_INSERT(od) \
+{\
+}
+#define CGEN_INIT_EXTRACT(od) \
+{\
+}
+#define CGEN_INIT_PRINT(od) \
+{\
+}
+
+
+ #ifdef __cplusplus
+ }
+ #endif
+
+#endif /* BPF_OPC_H */
diff --git a/opcodes/configure b/opcodes/configure
index 8eb5dde2d7..3b99d9786b 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -769,6 +769,7 @@ infodir
docdir
oldincludedir
includedir
+runstatedir
localstatedir
sharedstatedir
sysconfdir
@@ -854,6 +855,7 @@ datadir='${datarootdir}'
sysconfdir='${prefix}/etc'
sharedstatedir='${prefix}/com'
localstatedir='${prefix}/var'
+runstatedir='${localstatedir}/run'
includedir='${prefix}/include'
oldincludedir='/usr/include'
docdir='${datarootdir}/doc/${PACKAGE_TARNAME}'
@@ -1106,6 +1108,15 @@ do
| -silent | --silent | --silen | --sile | --sil)
silent=yes ;;
+ -runstatedir | --runstatedir | --runstatedi | --runstated \
+ | --runstate | --runstat | --runsta | --runst | --runs \
+ | --run | --ru | --r)
+ ac_prev=runstatedir ;;
+ -runstatedir=* | --runstatedir=* | --runstatedi=* | --runstated=* \
+ | --runstate=* | --runstat=* | --runsta=* | --runst=* | --runs=* \
+ | --run=* | --ru=* | --r=*)
+ runstatedir=$ac_optarg ;;
+
-sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
ac_prev=sbindir ;;
-sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
@@ -1243,7 +1254,7 @@ fi
for ac_var in exec_prefix prefix bindir sbindir libexecdir datarootdir \
datadir sysconfdir sharedstatedir localstatedir includedir \
oldincludedir docdir infodir htmldir dvidir pdfdir psdir \
- libdir localedir mandir
+ libdir localedir mandir runstatedir
do
eval ac_val=\$$ac_var
# Remove trailing slashes.
@@ -1396,6 +1407,7 @@ Fine tuning of the installation directories:
--sysconfdir=DIR read-only single-machine data [PREFIX/etc]
--sharedstatedir=DIR modifiable architecture-independent data [PREFIX/com]
--localstatedir=DIR modifiable single-machine data [PREFIX/var]
+ --runstatedir=DIR modifiable per-process data [LOCALSTATEDIR/run]
--libdir=DIR object code libraries [EPREFIX/lib]
--includedir=DIR C header files [PREFIX/include]
--oldincludedir=DIR C header files for non-gcc [/usr/include]
@@ -11439,7 +11451,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 11442 "configure"
+#line 11454 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -11545,7 +11557,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 11548 "configure"
+#line 11560 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -12949,6 +12961,7 @@ if test x${all_targets} = xfalse ; then
bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;;
bfd_z80_arch) ta="$ta z80-dis.lo" ;;
bfd_z8k_arch) ta="$ta z8k-dis.lo" ;;
+ bfd_bpf_arch) ta="$ta bpf-asm.lo bpf-desc.lo bpf-dis.lo bpf-ibld.lo bpf-opc.lo" using_cgen=yes ;;
"") ;;
*) as_fn_error $? "*** unknown target architecture $arch" "$LINENO" 5 ;;
diff --git a/opcodes/configure.ac b/opcodes/configure.ac
index 4eb19005e8..500c701a62 100644
--- a/opcodes/configure.ac
+++ b/opcodes/configure.ac
@@ -340,6 +340,7 @@ if test x${all_targets} = xfalse ; then
bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;;
bfd_z80_arch) ta="$ta z80-dis.lo" ;;
bfd_z8k_arch) ta="$ta z8k-dis.lo" ;;
+ bfd_bpf_arch) ta="$ta bpf-asm.lo bpf-desc.lo bpf-dis.lo bpf-ibld.lo bpf-opc.lo" using_cgen=yes ;;
"") ;;
*) AC_MSG_ERROR(*** unknown target architecture $arch) ;;
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index 1ef8b8f625..aef2fd8644 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -37,6 +37,7 @@
#define ARCH_d10v
#define ARCH_d30v
#define ARCH_dlx
+#define ARCH_bpf
#define ARCH_epiphany
#define ARCH_fr30
#define ARCH_frv
@@ -106,6 +107,23 @@
#include "m32c-desc.h"
#endif
+#ifdef ARCH_bpf
+/* XXX this should be including bpf-desc.h instead of this hackery,
+ but at the moment it is not possible to include several CGEN
+ generated *-desc.h files simultaneously. To be fixed in
+ CGEN... */
+
+# ifdef ARCH_m32c
+enum epbf_isa_attr
+{
+ ISA_EBPFLE, ISA_EBPFBE, ISA_EBPFMAX
+};
+# else
+# include "bpf-desc.h"
+# define ISA_EBPFMAX ISA_MAX
+# endif
+#endif /* ARCH_bpf */
+
disassembler_ftype
disassembler (enum bfd_architecture a,
bfd_boolean big ATTRIBUTE_UNUSED,
@@ -224,6 +242,11 @@ disassembler (enum bfd_architecture a,
disassemble = print_insn_ip2k;
break;
#endif
+#ifdef ARCH_bpf
+ case bfd_arch_bpf:
+ disassemble = print_insn_bpf;
+ break;
+#endif
#ifdef ARCH_epiphany
case bfd_arch_epiphany:
disassemble = print_insn_epiphany;
@@ -641,6 +664,18 @@ disassemble_init_for_target (struct disassemble_info * info)
}
break;
#endif
+#ifdef ARCH_bpf
+ case bfd_arch_bpf:
+ if (!info->insn_sets)
+ {
+ info->insn_sets = cgen_bitset_create (ISA_EBPFMAX);
+ if (info->endian == BFD_ENDIAN_BIG)
+ cgen_bitset_set (info->insn_sets, ISA_EBPFBE);
+ else
+ cgen_bitset_set (info->insn_sets, ISA_EBPFLE);
+ }
+ break;
+#endif
#ifdef ARCH_pru
case bfd_arch_pru:
info->disassembler_needs_relocs = TRUE;
diff --git a/opcodes/disassemble.h b/opcodes/disassemble.h
index 7b4ea92cca..ceb2814fe6 100644
--- a/opcodes/disassemble.h
+++ b/opcodes/disassemble.h
@@ -36,6 +36,7 @@ extern int print_insn_csky (bfd_vma, disassemble_info *);
extern int print_insn_d10v (bfd_vma, disassemble_info *);
extern int print_insn_d30v (bfd_vma, disassemble_info *);
extern int print_insn_dlx (bfd_vma, disassemble_info *);
+extern int print_insn_bpf (bfd_vma, disassemble_info *);
extern int print_insn_epiphany (bfd_vma, disassemble_info *);
extern int print_insn_fr30 (bfd_vma, disassemble_info *);
extern int print_insn_frv (bfd_vma, disassemble_info *);
--
2.11.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH V2 4/9] cpu: add eBPF cpu description
2019-05-22 15:26 [PATCH V2 0/9] eBPF support for GNU binutils Jose E. Marchesi
` (5 preceding siblings ...)
2019-05-22 15:24 ` [PATCH V2 7/9] ld: " Jose E. Marchesi
@ 2019-05-22 15:24 ` Jose E. Marchesi
2019-05-22 15:26 ` [PATCH V2 1/9] config: recognize eBPF triplets Jose E. Marchesi
` (3 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Jose E. Marchesi @ 2019-05-22 15:24 UTC (permalink / raw)
To: binutils
This patch adds a CPU description for the Linux kernel eBPF virtual
machine, plus supporting code for disassembler and assembler.
cpu/ChangeLog:
2019-05-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf.cpu: New file.
* bpf.opc: Likewise.
---
cpu/ChangeLog | 5 +
cpu/bpf.cpu | 647 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
cpu/bpf.opc | 191 +++++++++++++++++
3 files changed, 843 insertions(+)
create mode 100644 cpu/bpf.cpu
create mode 100644 cpu/bpf.opc
diff --git a/cpu/bpf.cpu b/cpu/bpf.cpu
new file mode 100644
index 0000000000..85bac2152f
--- /dev/null
+++ b/cpu/bpf.cpu
@@ -0,0 +1,647 @@
+;; Linux BPF CPU description -*- Scheme -*-
+;; Copyright (C) 2019 Free Software Foundation, Inc.
+;;
+;; Contributed by Oracle Inc.
+;;
+;; This file is part of the GNU Binutils and of GDB.
+;;
+;; This program is free software; you can redistribute it and/or
+;; modify it under the terms of the GNU General Public License as
+;; published by the Free Software Foundation; either version 3 of the
+;; License, or (at your option) any later version.
+;;
+;; This program is distributed in the hope that it will be useful, but
+;; WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+;; General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with this program; if not, write to the Free Software
+;; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+;; 02110-1301, USA.
+
+;; This file contains a CGEN CPU description for the Linux kernel eBPF
+;; instruction set. eBPF is documented in the linux kernel source
+;; tree. See linux/Documentation/networking/filter.txt, and also the
+;; sources in the networking subsystem, notably
+;; linux/net/core/filter.c.
+
+(include "simplify.inc")
+
+(define-arch
+ (name bpf)
+ (comment "Linux kernel BPF")
+ (insn-lsb0? #t)
+ (machs bpf)
+ (isas ebpfle ebpfbe))
+
+;;;; The ISAs
+
+;; Logically, eBPF comforms a single instruction set featuring two
+;; kind of instructions: 64-bit instructions and 128-bit instructions.
+;;
+;; The 64-bit instructions have the form:
+;;
+;; code:8 regs:8 offset:16 imm:32
+;;
+;; Whereas the 128-bit instructions (at the moment there is only one
+;; of such instructions, lddw) have the form:
+;;
+;; code:8 regs:8 offset:16 imm:32 imm:32 unused:32
+;;
+;; In both formats `regs' is itself composed by two fields:
+;;
+;; dst:4 src:4
+;;
+;; The ISA is supposed to be orthogonal to endianness: the endianness
+;; of the instruction fields follow the endianness of the host running
+;; the eBPF program, and that's all. However, this is not entirely
+;; true. The definition of an eBPF code in the Linux kernel is:
+;;
+;; struct bpf_insn {
+;; __u8 code; /* opcode */
+;; __u8 dst_reg:4; /* dest register */
+;; __u8 src_reg:4; /* source register */
+;; __s16 off; /* signed offset */
+;; __s32 imm; /* signed immediate constant */
+;; };
+;;
+;; Since the ordering of fields in C bitmaps is defined by the
+;; implementation, the impact of endianness in the encoding of eBPF
+;; instructions is effectively defined by GCC. In particular, GCC
+;; places dst_reg before src_reg in little-endian code, and the other
+;; way around in big-endian code.
+;;
+;; So, in reality, eBPF comprises two instruction sets: one for
+;; little-endian with instructions like:
+;;
+;; code:8 src:4 dst:4 offset:16 imm:32 [unused:32 imm:32]
+;;
+;; and another for big-endian with instructions like:
+;;
+;; code:8 dst:4 src:4 offset:16 imm:32 [unused:32 imm:32]
+;;
+;; where `offset' and the immediate fields are encoded in
+;; little-endian and big-endian byte-order, respectively.
+
+(define-pmacro (define-bpf-isa x-endian)
+ (define-isa
+ (name (.sym ebpf x-endian))
+ (comment "The eBPF instruction set")
+ ;; Default length to record in ifields. This is used in
+ ;; calculations involving bit numbers.
+ (default-insn-word-bitsize 64)
+ ;; Length of an unknown instruction. Used by disassembly and by the
+ ;; simulator's invalid insn handler.
+ (default-insn-bitsize 64)
+ ;; Number of bits of insn that can be initially fetched. XXX this
+ ;; should be 64 (the size of the smallest insn) but until CGEN
+ ;; gets fixed to place constant fields in their own words, we have
+ ;; to use this workaround to avoid the opcode byte to be placed at
+ ;; the wrong side of the instruction when assembling in
+ ;; big-endian.
+ (base-insn-bitsize 8)))
+
+(define-bpf-isa le)
+(define-bpf-isa be)
+
+(define-pmacro all-isas () (ISA ebpfle,ebpfbe))
+
+;;;; Hardware Hierarchy
+
+;;
+;; bpf architecture
+;; |
+;; bpfbf cpu-family
+;; |
+;; bpf machine
+;; |
+;; bpf-def model
+
+(define-cpu
+ (name bpfbf)
+ (comment "Linux kernel eBPF virtual CPU")
+ (word-bitsize 32))
+
+(define-mach
+ (name bpf)
+ (comment "Linux eBPF")
+ (cpu bpfbf)
+ (isas ebpfle ebpfbe))
+
+(define-model
+ (name bpf-def)
+ (comment "Linux eBPF default model")
+ (mach bpf)
+ (unit u-exec "execution unit" ()
+ 1 ; issue
+ 1 ; done
+ () ; state
+ () ; inputs
+ () ; outputs
+ () ; profile action (default)
+ ))
+
+;;;; Hardware Elements
+
+;; eBPF programs can access 10 general-purpose registers which are
+;; 64-bit.
+
+(define-hardware
+ (name h-gpr)
+ (comment "General Purpose Registers")
+ (attrs all-isas (MACH bpf))
+ (type register DI (16))
+ (indices keyword "%"
+ ;; XXX the frame pointer fp is read-only, so it should
+ ;; go in a different hardware.
+ (;; ABI names. Take priority when disassembling.
+ (a 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (ctx 6)
+ (r7 7) (r8 8) (r9 9) (fp 10)
+ ;; Additional names recognized when assembling.
+ (r0 0) (r6 6) (r10 10))))
+
+;; The program counter. CGEN requires it, even if it is not visible
+;; to eBPF programs.
+
+(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
+
+;; A 64-bit h-sint to be used by the imm64 operand below. XXX this
+;; shouldn't be needed, as h-sint is supposed to be able to hold
+;; 64-bit values. However, in practice CGEN limits h-sint to 32 bits
+;; in 32-bit hosts. To be fixed in CGEN.
+
+(dnh h-sint64 "signed 64-bit integer" (all-isas) (immediate DI)
+ () () ())
+
+;;;; The Instruction Sets
+
+;;; Fields and Opcodes
+
+;; Convenience macro to shorten the definition of the fields below.
+(define-pmacro (dwf x-name x-comment x-attrs
+ x-word-offset x-word-length x-start x-length
+ x-mode)
+ "Define a field including its containing word."
+ (define-ifield
+ (name x-name)
+ (comment x-comment)
+ (.splice attrs (.unsplice x-attrs))
+ (word-offset x-word-offset)
+ (word-length x-word-length)
+ (start x-start)
+ (length x-length)
+ (mode x-mode)))
+
+;; For arithmetic and jump instructions the 8-bit code field is
+;; subdivided in:
+;;
+;; op-code:4 op-src:1 op-class:3
+
+(dwf f-op-code "eBPF opcode code" (all-isas) 0 8 7 4 UINT)
+(dwf f-op-src "eBPF opcode source" (all-isas) 0 8 3 1 UINT)
+(dwf f-op-class "eBPF opcode instruction class" (all-isas) 0 8 2 3 UINT)
+
+(define-normal-insn-enum insn-op-code-alu "eBPF instruction codes"
+ (all-isas) OP_CODE_ f-op-code
+ (;; Codes for OP_CLASS_ALU and OP_CLASS_ALU64
+ (ADD #x0) (SUB #x1) (MUL #x2) (DIV #x3) (OR #x4) (AND #x5)
+ (LSH #x6) (RSH #x7) (NEG #x8) (MOD #x9) (XOR #xa) (MOV #xb)
+ (ARSH #xc) (END #xd)
+ ;; Codes for OP_CLASS_JMP
+ (JA #x0) (JEQ #x1) (JGT #x2) (JGE #x3) (JSET #x4)
+ (JNE #x5) (JSGT #x6) (JSGE #x7) (CALL #x8) (EXIT #x9)
+ (JLT #xa) (JLE #xb) (JSLT #xc) (JSLE #xd)))
+
+(define-normal-insn-enum insn-op-src "eBPF instruction source"
+ (all-isas) OP_SRC_ f-op-src
+ ;; X => use `src' as source operand.
+ ;; K => use `imm32' as source operand.
+ ((K #b0) (X #b1)))
+
+(define-normal-insn-enum insn-op-class "eBPF instruction class"
+ (all-isas) OP_CLASS_ f-op-class
+ ((LD #b000) (LDX #b001) (ST #b010) (STX #b011)
+ (ALU #b100) (JMP #b101) (ALU64 #b111)))
+
+;; For load/store instructions, the 8-bit code field is subdivided in:
+;;
+;; op-mode:3 op-size:2 op-class:3
+
+(dwf f-op-mode "eBPF opcode mode" (all-isas) 0 8 7 3 UINT)
+(dwf f-op-size "eBPF opcode size" (all-isas) 0 8 4 2 UINT)
+
+(define-normal-insn-enum insn-op-mode "eBPF load/store instruction modes"
+ (all-isas) OP_MODE_ f-op-mode
+ ((IMM #b000) (ABS #b001) (IND #b010) (MEM #b011)
+ ;; #b100 and #b101 are used in classic BPF only, reserved in eBPF.
+ (XADD #b110)))
+
+(define-normal-insn-enum insn-op-size "eBPF load/store instruction sizes"
+ (all-isas) OP_SIZE_ f-op-size
+ ((W #b00) ;; Word: 4 byte
+ (H #b01) ;; Half-word: 2 byte
+ (B #b10) ;; Byte: 1 byte
+ (DW #b11))) ;; Double-word: 8 byte
+
+;; The fields for the source and destination registers are a bit
+;; tricky. Due to the bizarre nibble swap between little-endian and
+;; big-endian ISAs we need to keep different variants of the fields.
+;;
+;; Note that f-regs is used in the format spec of instructions that do
+;; NOT use registers, where endianness is irrelevant i.e. f-regs is a
+;; constant 0 opcode.
+
+(dwf f-dstle "eBPF dst register field" ((ISA ebpfle)) 8 8 3 4 UINT)
+(dwf f-srcle "eBPF source register field" ((ISA ebpfle)) 8 8 7 4 UINT)
+
+(dwf f-dstbe "eBPF dst register field" ((ISA ebpfbe)) 8 8 7 4 UINT)
+(dwf f-srcbe "eBPF source register field" ((ISA ebpfbe)) 8 8 3 4 UINT)
+
+(dwf f-regs "eBPF registers field" (all-isas) 8 8 7 8 UINT)
+
+;; Finally, the fields for the immediates.
+;;
+;; The 16-bit offsets and 32-bit immediates do not present any special
+;; difficulty: we put them in their own instruction word so the
+;; byte-endianness will be properly applied.
+
+(dwf f-offset16 "eBPF offset field" (all-isas) 16 16 15 16 INT)
+(dwf f-imm32 "eBPF 32-bit immediate field" (all-isas) 32 32 31 32 INT)
+
+;; For the disjoint 64-bit signed immediate, however, we need to use a
+;; multi-ifield.
+
+(dwf f-imm64-a "eBPF 64-bit immediate a" (all-isas) 32 32 31 32 UINT)
+(dwf f-imm64-b "eBPF 64-bit immediate b" (all-isas) 64 32 31 32 UINT)
+(dwf f-imm64-c "eBPF 64-bit immediate c" (all-isas) 96 32 31 32 UINT)
+
+(define-multi-ifield
+ (name f-imm64)
+ (comment "eBPF 64-bit immediate field")
+ (attrs all-isas)
+ (mode DI)
+ (subfields f-imm64-a f-imm64-b f-imm64-c)
+ (insert (sequence ()
+ (set (ifield f-imm64-b) (const 0))
+ (set (ifield f-imm64-c) (srl (ifield f-imm64) (const 32)))
+ (set (ifield f-imm64-a) (and (ifield f-imm64) (const #xffffffff)))))
+ (extract (sequence ()
+ (set (ifield f-imm64)
+ (or (sll DI (zext DI (ifield f-imm64-c)) (const 32))
+ (zext DI (ifield f-imm64-a)))))))
+
+;;; Operands
+
+;; A couple of source and destination register operands are defined
+;; for each ISA: ebpfle and ebpfbe.
+
+(dno dstle "destination register" ((ISA ebpfle)) h-gpr f-dstle)
+(dno srcle "source register" ((ISA ebpfle)) h-gpr f-srcle)
+
+(dno dstbe "destination register" ((ISA ebpfbe)) h-gpr f-dstbe)
+(dno srcbe "source register" ((ISA ebpfbe)) h-gpr f-srcbe)
+
+;; Jump instructions have a 16-bit PC-relative address.
+;; CALL instructions have a 32-bit PC-relative address.
+
+(dno disp16 "16-bit PC-relative address" (all-isas PCREL-ADDR) h-sint
+ f-offset16)
+(dno disp32 "32-bit PC-relative address" (all-isas PCREL-ADDR) h-sint
+ f-imm32)
+
+;; Immediate operands in eBPF are signed, and we want the disassembler
+;; to print negative values in a sane way. Therefore we use the macro
+;; below to register a printer, which is itself defined as a C
+;; function in bpf.opc.
+
+;; define-normal-signed-immediate-operand
+(define-pmacro (dnsio x-name x-comment x-attrs x-type x-index)
+ (define-operand
+ (name x-name)
+ (comment x-comment)
+ (.splice attrs (.unsplice x-attrs))
+ (type x-type)
+ (index x-index)
+ (handlers (print "immediate"))))
+
+(dnsio imm32 "32-bit immediate" (all-isas) h-sint f-imm32)
+(dnsio offset16 "16-bit offset" (all-isas) h-sint f-offset16)
+
+;; The 64-bit immediate cannot use the default
+;; cgen_parse_signed_integer, because it assumes operands are at much
+;; 32-bit wide. Use our own.
+
+(define-operand
+ (name imm64)
+ (comment "64-bit immediate")
+ (attrs all-isas)
+ (type h-sint64)
+ (index f-imm64)
+ (handlers (parse "imm64") (print "immediate")))
+
+;; The endle/endbe instructions take an operand to specify the word
+;; width in endianness conversions. We use both a parser and printer,
+;; which are defined as C functions in bpf.opc.
+
+(define-operand
+ (name endsize)
+ (comment "endianness size immediate: 16, 32 or 64")
+ (attrs all-isas)
+ (type h-uint)
+ (index f-imm32)
+ (handlers (parse "endsize") (print "endsize")))
+
+;;; ALU instructions
+
+;; For each opcode in insn-op-code-alu representing and integer
+;; arithmetic instruction (ADD, SUB, etc) we define a bunch of
+;; instruction variants:
+;;
+;; ADD[32]{i,r}le for the little-endian ISA
+;; ADD[32]{i,r}be for the big-endian ISA
+;;
+;; The `i' variants perform `src OP dst -> dst' operations.
+;; The `r' variants perform `dst OP imm32 -> dst' operations.
+;;
+;; The variants with 32 in their name are of ALU class. Otherwise
+;; they are ALU64 class.
+
+(define-pmacro (define-alu-insn-un x-basename x-suffix x-op-class x-op-code x-endian)
+ (dni (.sym x-basename x-suffix x-endian)
+ (.str x-basename x-suffix)
+ ((ISA (.sym ebpf x-endian)))
+ (.str x-basename x-suffix " $dst" x-endian)
+ (+ (f-imm32 0) (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
+ x-op-class OP_SRC_X x-op-code) () ()))
+
+(define-pmacro (define-alu-insn-bin x-basename x-suffix x-op-class x-op-code x-endian)
+ (begin
+ (dni (.sym x-basename x-suffix "i" x-endian)
+ (.str x-basename x-suffix " immediate")
+ ((ISA (.sym ebpf x-endian)))
+ (.str x-basename x-suffix " $dst" x-endian ",$imm32")
+ (+ imm32 (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
+ x-op-class OP_SRC_K x-op-code) () ())
+ (dni (.sym x-basename x-suffix "r" x-endian)
+ (.str x-basename x-suffix " register")
+ ((ISA (.sym ebpf x-endian)))
+ (.str x-basename x-suffix " $dst" x-endian ",$src" x-endian)
+ (+ (f-imm32 0) (f-offset16 0) (.sym src x-endian) (.sym dst x-endian)
+ x-op-class OP_SRC_X x-op-code) () ())))
+
+(define-pmacro (daiu x-basename x-op-code x-endian)
+ (begin
+ (define-alu-insn-un x-basename "" OP_CLASS_ALU64 x-op-code x-endian)
+ (define-alu-insn-un x-basename "32" OP_CLASS_ALU x-op-code x-endian)))
+
+(define-pmacro (daib x-basename x-op-code x-endian)
+ (begin
+ (define-alu-insn-bin x-basename "" OP_CLASS_ALU64 x-op-code x-endian)
+ (define-alu-insn-bin x-basename "32" OP_CLASS_ALU x-op-code x-endian)))
+
+(define-pmacro (define-alu-instructions x-endian)
+ (begin
+ (daib add OP_CODE_ADD x-endian)
+ (daib sub OP_CODE_SUB x-endian)
+ (daib mul OP_CODE_MUL x-endian)
+ (daib div OP_CODE_DIV x-endian)
+ (daib or OP_CODE_OR x-endian)
+ (daib and OP_CODE_AND x-endian)
+ (daib lsh OP_CODE_LSH x-endian)
+ (daib rsh OP_CODE_RSH x-endian)
+ (daib mod OP_CODE_MOD x-endian)
+ (daib xor OP_CODE_XOR x-endian)
+ (daib mov OP_CODE_MOV x-endian)
+ (daib arsh OP_CODE_ARSH x-endian)
+ (daiu neg OP_CODE_NEG x-endian)))
+
+(define-alu-instructions le)
+(define-alu-instructions be)
+
+;;; Endianness conversion instructions
+
+;; The endianness conversion instructions come in several variants:
+;;
+;; END{le,be}le for the little-endian ISA
+;; END{le,be}be for the big-endian ISA
+;;
+;; Please do not be confused by the repeated `be' and `le' here. Each
+;; ISA has both endle and endbe instructions. It is the disposition
+;; of the source and destination register fields that change between
+;; ISAs, not the semantics of the instructions themselves (see section
+;; "The ISAs" above in this very file.)
+
+(define-pmacro (define-endian-insn x-suffix x-op-src x-endian)
+ (dni (.sym "end" x-suffix x-endian)
+ (.str "end" x-suffix " register")
+ ((ISA (.sym ebpf x-endian)))
+ (.str "end" x-suffix " $dst" x-endian ",$endsize")
+ (+ (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian) endsize
+ OP_CLASS_ALU x-op-src OP_CODE_END) () ()))
+
+(define-endian-insn "le" OP_SRC_K le)
+(define-endian-insn "be" OP_SRC_X le)
+(define-endian-insn "le" OP_SRC_K be)
+(define-endian-insn "be" OP_SRC_X be)
+
+;;; Load/Store instructions
+
+;; The lddw instruction takes a 64-bit immediate as an operand. Since
+;; this instruction also takes a `dst' operand, we need to define a
+;; variant for each ISA:
+;;
+;; LDDWle for the little-endian ISA
+;; LDDWbe for the big-endian ISA
+
+(define-pmacro (define-lddw x-endian)
+ (dni (.sym lddw x-endian)
+ (.str "lddw" x-endian)
+ ((ISA (.sym ebpf x-endian)))
+ (.str "lddw $dst" x-endian ",$imm64")
+ (+ imm64 (f-offset16 0) ((.sym f-src x-endian) 0)
+ (.sym dst x-endian)
+ OP_CLASS_LD OP_SIZE_DW OP_MODE_IMM) () ()))
+
+(define-lddw le)
+(define-lddw be)
+
+;; The absolute/indirect load instructions are non-generic loads
+;; designed to be used in socket filters. They come in several
+;; variants:
+;;
+;; LD{abs,ind}{w,h,b,dw}le for the little-endian ISA
+;; LD{abs,ind}[w,h,b,dw}be for the big-endian ISA
+
+(define-pmacro (dlsi x-basename x-suffix x-class x-size x-mode x-endian)
+ (dni (.sym x-basename x-suffix x-endian)
+ (.str x-basename x-suffix)
+ ((ISA (.sym ebpf x-endian)))
+ (.str x-basename x-suffix " $dst" x-endian ",$src" x-endian ",$imm32")
+ (+ imm32 (f-offset16 0) (.sym src x-endian) (.sym dst x-endian)
+ (.sym OP_CLASS_ x-class) (.sym OP_SIZE_ x-size)
+ (.sym OP_MODE_ x-mode)) () ()))
+
+(define-pmacro (define-ldabsind x-endian)
+ (begin
+ (dlsi "ldabs" "w" LD W ABS x-endian)
+ (dlsi "ldabs" "h" LD H ABS x-endian)
+ (dlsi "ldabs" "b" LD B ABS x-endian)
+ (dlsi "ldabs" "dw" LD DW ABS x-endian)
+
+ (dlsi "ldind" "w" LD W IND x-endian)
+ (dlsi "ldind" "h" LD H IND x-endian)
+ (dlsi "ldind" "b" LD B IND x-endian)
+ (dlsi "ldind" "dw" LD DW IND x-endian)))
+
+(define-ldabsind le)
+(define-ldabsind be)
+
+;; Generic load and store instructions are provided for several word
+;; sizes. They come in several variants:
+;;
+;; LDX{b,h,w,dw}le, STX{b,h,w,dw}le for the little-endian ISA
+;;
+;; LDX{b,h,w,dw}be, STX{b,h,w,dw}be for the big-endian ISA
+;;
+;; Loads operate on [$SRC+-OFFSET] -> $DST
+;; Stores operate on $SRC -> [$DST+-OFFSET]
+
+(define-pmacro (dxli x-basename x-suffix x-size x-endian)
+ (dni (.sym x-basename x-suffix x-endian)
+ (.str x-basename x-suffix)
+ ((ISA (.sym ebpf x-endian)))
+ (.str x-basename x-suffix " $dst" x-endian ",[$src" x-endian "+$offset16]")
+ (+ (f-imm32 0) offset16 (.sym src x-endian) (.sym dst x-endian)
+ OP_CLASS_LDX (.sym OP_SIZE_ x-size) OP_MODE_MEM)
+ () ()))
+
+(define-pmacro (dxsi x-basename x-suffix x-size x-endian)
+ (dni (.sym x-basename x-suffix x-endian)
+ (.str x-basename x-suffix)
+ ((ISA (.sym ebpf x-endian)))
+ (.str x-basename x-suffix " [$dst" x-endian "+$offset16],$src" x-endian)
+ (+ (f-imm32 0) offset16 (.sym src x-endian) (.sym dst x-endian)
+ OP_CLASS_STX (.sym OP_SIZE_ x-size) OP_MODE_MEM)
+ () ()))
+
+(define-pmacro (define-ldstx-insns x-endian)
+ (begin
+ (dxli "ldx" "w" W x-endian)
+ (dxli "ldx" "h" H x-endian)
+ (dxli "ldx" "b" B x-endian)
+ (dxli "ldx" "dw" DW x-endian)
+
+ (dxsi "stx" "w" W x-endian)
+ (dxsi "stx" "h" H x-endian)
+ (dxsi "stx" "b" B x-endian)
+ (dxsi "stx" "dw" DW x-endian)))
+
+(define-ldstx-insns le)
+(define-ldstx-insns be)
+
+;; Generic store instructions of the form IMM32 -> [$DST+OFFSET] are
+;; provided in several variants:
+;;
+;; ST{b,h,w,dw}le for the little-endian ISA
+;; ST{b,h,w,dw}be for the big-endian ISA
+
+(define-pmacro (dsti x-suffix x-size x-endian)
+ (dni (.sym "st" x-suffix x-endian)
+ (.str "st" x-suffix)
+ ((ISA (.sym ebpf x-endian)))
+ (.str "st" x-suffix " [$dst" x-endian "+$offset16],$imm32")
+ (+ imm32 offset16 ((.sym f-src x-endian) 0) (.sym dst x-endian)
+ OP_CLASS_ST (.sym OP_SIZE_ x-size) OP_MODE_MEM) () ()))
+
+(define-pmacro (define-st-insns x-endian)
+ (begin
+ (dsti "b" B x-endian)
+ (dsti "h" H x-endian)
+ (dsti "w" W x-endian)
+ (dsti "dw" DW x-endian)))
+
+(define-st-insns le)
+(define-st-insns be)
+
+;;; Jump instructions
+
+;; Compare-and-jump instructions, on the other hand, make use of
+;; registers. Therefore, we need to define several variants in both
+;; ISAs:
+;;
+;; J{eq,gt,ge,lt,le,set,ne,sgt,sge,slt,sle}{i,r}le for the
+;; little-endian ISA.
+;; J{eq,gt,ge,lt,le,set,ne.sgt,sge,slt,sle}{i,r}be for the
+;; big-endian ISA.
+
+(define-pmacro (dcji x-cond x-op-code x-endian)
+ (begin
+ (dni (.sym j x-cond i x-endian)
+ (.str j x-cond "i")
+ ((ISA (.sym ebpf x-endian)))
+ (.str "j" x-cond " $dst" x-endian ",$imm32,$disp16")
+ (+ imm32 disp16 ((.sym f-src x-endian) 0) (.sym dst x-endian)
+ OP_CLASS_JMP OP_SRC_K (.sym OP_CODE_ x-op-code)) () ())
+ (dni (.sym j x-cond r x-endian)
+ (.str j x-cond "r")
+ ((ISA (.sym ebpf x-endian)))
+ (.str "j" x-cond " $dst" x-endian ",$src" x-endian ",$disp16")
+ (+ (f-imm32 0) disp16 (.sym src x-endian) (.sym dst x-endian)
+ OP_CLASS_JMP OP_SRC_X (.sym OP_CODE_ x-op-code)) () ())))
+
+(define-pmacro (define-condjump-insns x-endian)
+ (begin
+ (dcji "eq" JEQ x-endian)
+ (dcji "gt" JGT x-endian)
+ (dcji "ge" JGE x-endian)
+ (dcji "lt" JLT x-endian)
+ (dcji "le" JLE x-endian)
+ (dcji "set" JSET x-endian)
+ (dcji "ne" JNE x-endian)
+ (dcji "sgt" JSGT x-endian)
+ (dcji "sge" JSGE x-endian)
+ (dcji "slt" JSLT x-endian)
+ (dcji "sle" JSLE x-endian)))
+
+(define-condjump-insns le)
+(define-condjump-insns be)
+
+;; The jump-always, `call' and `exit' instructions dont make use of
+;; either source nor destination registers, so only one variant per
+;; instruction is defined.
+
+(dni ja "ja" (all-isas) "ja $disp16"
+ (+ (f-imm32 0) disp16 (f-regs 0)
+ OP_CLASS_JMP OP_SRC_K OP_CODE_JA) () ())
+
+(dni call "call" (all-isas) "call $disp32"
+ (+ disp32 (f-offset16 0) (f-regs 0)
+ OP_CLASS_JMP OP_SRC_K OP_CODE_CALL) () ())
+
+(dni "exit" "exit" (all-isas) "exit"
+ (+ (f-imm32 0) (f-offset16 0) (f-regs 0)
+ OP_CLASS_JMP (f-op-src 0) OP_CODE_EXIT) () ())
+
+;;; Atomic instructions
+
+;; The atomic exchange-and-add instructions come in two flavors: one
+;; for swapping 64-bit quantities and another for 32-bit quantities.
+
+(define-pmacro (define-atomic-insns x-endian)
+ (begin
+ (dni (.str "xadddw" x-endian)
+ "xadddw"
+ ((ISA (.sym ebpf x-endian)))
+ (.str "xadddw [$dst" x-endian "+$offset16],$src" x-endian)
+ (+ (f-imm32 0) (.sym src x-endian) (.sym dst x-endian)
+ offset16 OP_MODE_XADD OP_SIZE_DW OP_CLASS_STX) () ())
+ (dni (.str "xaddw" x-endian)
+ "xaddw"
+ ((ISA (.sym ebpf x-endian)))
+ (.str "xaddw [$dst" x-endian "+$offset16],$src" x-endian)
+ (+ (f-imm32 0) (.sym src x-endian) (.sym dst x-endian)
+ offset16 OP_MODE_XADD OP_SIZE_W OP_CLASS_STX) () ())))
+
+(define-atomic-insns le)
+(define-atomic-insns be)
diff --git a/cpu/bpf.opc b/cpu/bpf.opc
new file mode 100644
index 0000000000..e70ee04841
--- /dev/null
+++ b/cpu/bpf.opc
@@ -0,0 +1,191 @@
+/* EBPF opcode support. -*- c -*-
+
+ Copyright (C) 2019 Free Software Foundation, Inc.
+
+ Contributed by Oracle, Inc.
+
+ This file is part of the GNU Binutils and of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+/*
+ Each section is delimited with start and end markers.
+
+ <arch>-opc.h additions use: "-- opc.h"
+ <arch>-opc.c additions use: "-- opc.c"
+ <arch>-asm.c additions use: "-- asm.c"
+ <arch>-dis.c additions use: "-- dis.c"
+ <arch>-ibd.h additions use: "-- ibd.h". */
+\f
+/* -- opc.h */
+
+#undef CGEN_DIS_HASH_SIZE
+#define CGEN_DIS_HASH_SIZE 1
+
+#undef CGEN_DIS_HASH
+#define CGEN_DIS_HASH(buffer, value) 0
+
+/* Allows reason codes to be output when assembler errors occur. */
+#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+
+#define CGEN_VALIDATE_INSN_SUPPORTED
+extern int bpf_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
+
+\f
+/* -- opc.c */
+\f
+/* -- asm.c */
+
+/* Parse a signed 64-bit immediate. */
+
+static const char *
+parse_imm64 (CGEN_CPU_DESC cd,
+ const char **strp,
+ int opindex,
+ int64_t *valuep)
+{
+ bfd_vma value;
+ enum cgen_parse_operand_result result;
+ const char *errmsg;
+
+ errmsg = (* cd->parse_operand_fn)
+ (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE,
+ &result, &value);
+ if (!errmsg)
+ *valuep = value;
+
+ return errmsg;
+}
+
+/* Endianness size operands are integer immediates whose values can be
+ 16, 32 or 64. */
+
+static const char *
+parse_endsize (CGEN_CPU_DESC cd,
+ const char **strp,
+ int opindex,
+ unsigned long *valuep)
+{
+ const char *errmsg;
+
+ errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+ if (errmsg)
+ return errmsg;
+
+ switch (*valuep)
+ {
+ case 16:
+ case 32:
+ case 64:
+ break;
+ default:
+ return _("expected 16, 32 or 64 in");
+ }
+
+ return NULL;
+}
+
+/* Special check to ensure that the right instruction variant is used
+ for the given endianness induced by the ISA selected in the CPU.
+ See bpf.cpu for a discussion on how eBPF is really two instruction
+ sets. */
+
+int
+bpf_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
+{
+ CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA);
+
+ return cgen_bitset_intersect_p (&isas, cd->isas);
+}
+
+\f
+/* -- dis.c */
+
+/* We need to customize the disassembler a bit:
+ - Use 8 bytes per line by default.
+*/
+
+#define CGEN_PRINT_INSN bpf_print_insn
+
+static int
+bpf_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
+{
+ bfd_byte buf[CGEN_MAX_INSN_SIZE];
+ int buflen;
+ int status;
+
+ info->bytes_per_chunk = 1;
+ info->bytes_per_line = 8;
+
+ /* Attempt to read the base part of the insn. */
+ buflen = cd->base_insn_bitsize / 8;
+ status = (*info->read_memory_func) (pc, buf, buflen, info);
+
+ /* Try again with the minimum part, if min < base. */
+ if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
+ {
+ buflen = cd->min_insn_bitsize / 8;
+ status = (*info->read_memory_func) (pc, buf, buflen, info);
+ }
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
+ }
+
+ return print_insn (cd, pc, info, buf, buflen);
+}
+
+/* Signed immediates should be printed in hexadecimal. */
+
+static void
+print_immediate (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void *dis_info,
+ int64_t value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+ if (value <= 9)
+ (*info->fprintf_func) (info->stream, "%" PRId64, value);
+ else
+ (*info->fprintf_func) (info->stream, "%#" PRIx64, value);
+
+ /* This is to avoid -Wunused-function for print_normal. */
+ if (0)
+ print_normal (cd, dis_info, value, attrs, pc, length);
+}
+
+/* Endianness bit sizes should be printed in decimal. */
+
+static void
+print_endsize (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void *dis_info,
+ unsigned long value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+ (*info->fprintf_func) (info->stream, "%lu", value);
+}
+
+\f
+/* -- */
+
--
2.11.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH V2 3/9] bfd: add support for eBPF
2019-05-22 15:26 [PATCH V2 0/9] eBPF support for GNU binutils Jose E. Marchesi
` (2 preceding siblings ...)
2019-05-22 15:24 ` [PATCH V2 2/9] include: add elf/bpf.h Jose E. Marchesi
@ 2019-05-22 15:24 ` Jose E. Marchesi
2019-05-22 15:24 ` [PATCH V2 6/9] gas: " Jose E. Marchesi
` (6 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Jose E. Marchesi @ 2019-05-22 15:24 UTC (permalink / raw)
To: binutils
This patch adds support to BFD for elf64-bpf, in both little-endian
and big-endian variants.
bfd/ChangeLog:
2019-05-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* configure.ac: Add bpf_elf64_le_vec and bpf_elf64_be_vec.
* configure: Regenerated.
* Makefile.am (ALL_MACHINES): Add cpu-bpf.lo.
(ALL_MACHINES_CFILES): Add cpu-bpf.c.
(BFD64_BACKENDS): Add elf64-bpf.lo.
(BFD64_BACKENDS_CFILES): Add elf64-bpf.c.
* Makefile.in (SOURCE_HFILES): Regenerate.
* config.bfd (targ_cpu): Handle bpf-*-* targets.
* cpu-bpf.c: New file.
* elf64-bpf.c: Likewise.
* targets.c (_bfd_target_vector): Add bpf_elf64_be_vec and
bpf_elf64_le_vec.
* archures.c: Define architecture bfd_arch_bpf and machine
bfd_arch_bpf.
* reloc.c: Define BFD relocations used by the BPF target.
* bfd-in2.h: Regenerated.
* libbfd.h: Likewise.
---
bfd/ChangeLog | 20 +++
bfd/Makefile.am | 4 +
bfd/Makefile.in | 7 +
bfd/archures.c | 4 +
bfd/bfd-in2.h | 9 ++
bfd/config.bfd | 6 +
bfd/configure | 30 +++-
bfd/configure.ac | 2 +
bfd/cpu-bpf.c | 41 +++++
bfd/elf64-bpf.c | 463 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
bfd/libbfd.h | 5 +
bfd/reloc.c | 13 ++
bfd/targets.c | 7 +
13 files changed, 603 insertions(+), 8 deletions(-)
create mode 100644 bfd/cpu-bpf.c
create mode 100644 bfd/elf64-bpf.c
diff --git a/bfd/Makefile.am b/bfd/Makefile.am
index a9191555ad..4703955ee4 100644
--- a/bfd/Makefile.am
+++ b/bfd/Makefile.am
@@ -96,6 +96,7 @@ ALL_MACHINES = \
cpu-arm.lo \
cpu-avr.lo \
cpu-bfin.lo \
+ cpu-bpf.lo \
cpu-cr16.lo \
cpu-cr16c.lo \
cpu-cris.lo \
@@ -182,6 +183,7 @@ ALL_MACHINES_CFILES = \
cpu-arm.c \
cpu-avr.c \
cpu-bfin.c \
+ cpu-bpf.c \
cpu-cr16.c \
cpu-cr16c.c \
cpu-cris.c \
@@ -574,6 +576,7 @@ BFD64_BACKENDS = \
elf64-tilegx.lo \
elf64-x86-64.lo \
elfxx-x86.lo \
+ elf64-bpf.lo \
elf64.lo \
mach-o-aarch64.lo \
mach-o-x86-64.lo \
@@ -607,6 +610,7 @@ BFD64_BACKENDS_CFILES = \
elf64-tilegx.c \
elf64-x86-64.c \
elfxx-x86.c \
+ elf64-bpf.c \
elf64.c \
elfn32-mips.c \
elfxx-aarch64.c \
diff --git a/bfd/Makefile.in b/bfd/Makefile.in
index 896df52042..5578997e5d 100644
--- a/bfd/Makefile.in
+++ b/bfd/Makefile.in
@@ -438,6 +438,7 @@ pdfdir = @pdfdir@
prefix = @prefix@
program_transform_name = @program_transform_name@
psdir = @psdir@
+runstatedir = @runstatedir@
sbindir = @sbindir@
sharedstatedir = @sharedstatedir@
srcdir = @srcdir@
@@ -519,6 +520,7 @@ ALL_MACHINES = \
cpu-arm.lo \
cpu-avr.lo \
cpu-bfin.lo \
+ cpu-bpf.lo \
cpu-cr16.lo \
cpu-cr16c.lo \
cpu-cris.lo \
@@ -605,6 +607,7 @@ ALL_MACHINES_CFILES = \
cpu-arm.c \
cpu-avr.c \
cpu-bfin.c \
+ cpu-bpf.c \
cpu-cr16.c \
cpu-cr16c.c \
cpu-cris.c \
@@ -999,6 +1002,7 @@ BFD64_BACKENDS = \
elf64-tilegx.lo \
elf64-x86-64.lo \
elfxx-x86.lo \
+ elf64-bpf.lo \
elf64.lo \
mach-o-aarch64.lo \
mach-o-x86-64.lo \
@@ -1032,6 +1036,7 @@ BFD64_BACKENDS_CFILES = \
elf64-tilegx.c \
elf64-x86-64.c \
elfxx-x86.c \
+ elf64-bpf.c \
elf64.c \
elfn32-mips.c \
elfxx-aarch64.c \
@@ -1322,6 +1327,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-arm.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-avr.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-bfin.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-bpf.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-cr16.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-cr16c.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-cris.Plo@am__quote@
@@ -1484,6 +1490,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-aarch64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-alpha.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-bpf.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-gen.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-hppa.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ia64-vms.Plo@am__quote@
diff --git a/bfd/archures.c b/bfd/archures.c
index aaf2e112cf..3465406213 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -415,6 +415,8 @@ DESCRIPTION
. bfd_arch_iq2000, {* Vitesse IQ2000. *}
.#define bfd_mach_iq2000 1
.#define bfd_mach_iq10 2
+. bfd_arch_bpf, {* Linux eBPF. *}
+.#define bfd_mach_bpf 1
. bfd_arch_epiphany, {* Adapteva EPIPHANY. *}
.#define bfd_mach_epiphany16 1
.#define bfd_mach_epiphany32 2
@@ -601,6 +603,7 @@ extern const bfd_arch_info_type bfd_csky_arch;
extern const bfd_arch_info_type bfd_d10v_arch;
extern const bfd_arch_info_type bfd_d30v_arch;
extern const bfd_arch_info_type bfd_dlx_arch;
+extern const bfd_arch_info_type bfd_bpf_arch;
extern const bfd_arch_info_type bfd_epiphany_arch;
extern const bfd_arch_info_type bfd_fr30_arch;
extern const bfd_arch_info_type bfd_frv_arch;
@@ -692,6 +695,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
&bfd_d10v_arch,
&bfd_d30v_arch,
&bfd_dlx_arch,
+ &bfd_bpf_arch,
&bfd_epiphany_arch,
&bfd_fr30_arch,
&bfd_frv_arch,
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 65e2e01efe..03d644c61e 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -2357,6 +2357,8 @@ enum bfd_architecture
bfd_arch_iq2000, /* Vitesse IQ2000. */
#define bfd_mach_iq2000 1
#define bfd_mach_iq10 2
+ bfd_arch_bpf, /* Linux eBPF. */
+#define bfd_mach_bpf 1
bfd_arch_epiphany, /* Adapteva EPIPHANY. */
#define bfd_mach_epiphany16 1
#define bfd_mach_epiphany32 2
@@ -6651,6 +6653,13 @@ assembler and not (currently) written to any object files. */
BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD,
BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD,
+/* Linux eBPF relocations. */
+ BFD_RELOC_BPF_64,
+ BFD_RELOC_BPF_32,
+ BFD_RELOC_BPF_16,
+ BFD_RELOC_BPF_DISP16,
+ BFD_RELOC_BPF_DISP32,
+
/* Adapteva EPIPHANY - 8 bit signed pc-relative displacement */
BFD_RELOC_EPIPHANY_SIMM8,
diff --git a/bfd/config.bfd b/bfd/config.bfd
index 8977d2a2a2..157cc08eac 100644
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -480,6 +480,12 @@ case "${targ}" in
targ_defvec=d30v_elf32_vec
;;
+ bpf-*-*)
+ targ_defvec=bpf_elf64_le_vec
+ targ_selvecs=bpf_elf64_be_vec
+ targ_underscore=yes
+ ;;
+
epiphany-*-*)
targ_defvec=epiphany_elf32_vec
targ_underscore=yes
diff --git a/bfd/configure b/bfd/configure
index f99979faa0..f2f8735629 100755
--- a/bfd/configure
+++ b/bfd/configure
@@ -793,6 +793,7 @@ infodir
docdir
oldincludedir
includedir
+runstatedir
localstatedir
sharedstatedir
sysconfdir
@@ -889,6 +890,7 @@ datadir='${datarootdir}'
sysconfdir='${prefix}/etc'
sharedstatedir='${prefix}/com'
localstatedir='${prefix}/var'
+runstatedir='${localstatedir}/run'
includedir='${prefix}/include'
oldincludedir='/usr/include'
docdir='${datarootdir}/doc/${PACKAGE_TARNAME}'
@@ -1141,6 +1143,15 @@ do
| -silent | --silent | --silen | --sile | --sil)
silent=yes ;;
+ -runstatedir | --runstatedir | --runstatedi | --runstated \
+ | --runstate | --runstat | --runsta | --runst | --runs \
+ | --run | --ru | --r)
+ ac_prev=runstatedir ;;
+ -runstatedir=* | --runstatedir=* | --runstatedi=* | --runstated=* \
+ | --runstate=* | --runstat=* | --runsta=* | --runst=* | --runs=* \
+ | --run=* | --ru=* | --r=*)
+ runstatedir=$ac_optarg ;;
+
-sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
ac_prev=sbindir ;;
-sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
@@ -1278,7 +1289,7 @@ fi
for ac_var in exec_prefix prefix bindir sbindir libexecdir datarootdir \
datadir sysconfdir sharedstatedir localstatedir includedir \
oldincludedir docdir infodir htmldir dvidir pdfdir psdir \
- libdir localedir mandir
+ libdir localedir mandir runstatedir
do
eval ac_val=\$$ac_var
# Remove trailing slashes.
@@ -1431,6 +1442,7 @@ Fine tuning of the installation directories:
--sysconfdir=DIR read-only single-machine data [PREFIX/etc]
--sharedstatedir=DIR modifiable architecture-independent data [PREFIX/com]
--localstatedir=DIR modifiable single-machine data [PREFIX/var]
+ --runstatedir=DIR modifiable per-process data [LOCALSTATEDIR/run]
--libdir=DIR object code libraries [EPREFIX/lib]
--includedir=DIR C header files [PREFIX/include]
--oldincludedir=DIR C header files for non-gcc [/usr/include]
@@ -11728,7 +11740,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 11731 "configure"
+#line 11743 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -11834,7 +11846,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 11837 "configure"
+#line 11849 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -12223,7 +12235,7 @@ else
We can't simply define LARGE_OFF_T to be 9223372036854775807,
since some C++ compilers masquerading as C compilers
incorrectly reject 9223372036854775807. */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
&& LARGE_OFF_T % 2147483647 == 1)
? 1 : -1];
@@ -12269,7 +12281,7 @@ else
We can't simply define LARGE_OFF_T to be 9223372036854775807,
since some C++ compilers masquerading as C compilers
incorrectly reject 9223372036854775807. */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
&& LARGE_OFF_T % 2147483647 == 1)
? 1 : -1];
@@ -12293,7 +12305,7 @@ rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
We can't simply define LARGE_OFF_T to be 9223372036854775807,
since some C++ compilers masquerading as C compilers
incorrectly reject 9223372036854775807. */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
&& LARGE_OFF_T % 2147483647 == 1)
? 1 : -1];
@@ -12338,7 +12350,7 @@ else
We can't simply define LARGE_OFF_T to be 9223372036854775807,
since some C++ compilers masquerading as C compilers
incorrectly reject 9223372036854775807. */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
&& LARGE_OFF_T % 2147483647 == 1)
? 1 : -1];
@@ -12362,7 +12374,7 @@ rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
We can't simply define LARGE_OFF_T to be 9223372036854775807,
since some C++ compilers masquerading as C compilers
incorrectly reject 9223372036854775807. */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
&& LARGE_OFF_T % 2147483647 == 1)
? 1 : -1];
@@ -14740,6 +14752,8 @@ do
elf32_le_vec) tb="$tb elf32-gen.lo elf32.lo $elf" ;;
elf64_be_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
elf64_le_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
+ bpf_elf64_le_vec) tb="$tb elf64-bpf.lo elf64.lo $elf" ;;
+ bpf_elf64_be_vec) tb="$tb elf64-bpf.lo elf64.lo $elf" ;;
epiphany_elf32_vec) tb="$tb elf32-epiphany.lo elf32.lo $elf" ;;
fr30_elf32_vec) tb="$tb elf32-fr30.lo elf32.lo $elf" ;;
frv_elf32_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;;
diff --git a/bfd/configure.ac b/bfd/configure.ac
index 82aa5b1803..fe6754e789 100644
--- a/bfd/configure.ac
+++ b/bfd/configure.ac
@@ -476,6 +476,8 @@ do
elf32_le_vec) tb="$tb elf32-gen.lo elf32.lo $elf" ;;
elf64_be_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
elf64_le_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
+ bpf_elf64_le_vec) tb="$tb elf64-bpf.lo elf64.lo $elf" ;;
+ bpf_elf64_be_vec) tb="$tb elf64-bpf.lo elf64.lo $elf" ;;
epiphany_elf32_vec) tb="$tb elf32-epiphany.lo elf32.lo $elf" ;;
fr30_elf32_vec) tb="$tb elf32-fr30.lo elf32.lo $elf" ;;
frv_elf32_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;;
diff --git a/bfd/cpu-bpf.c b/bfd/cpu-bpf.c
new file mode 100644
index 0000000000..57fe7d7502
--- /dev/null
+++ b/bfd/cpu-bpf.c
@@ -0,0 +1,41 @@
+/* BFD support for the BPF processor.
+ Copyright (C) 2019 Free Software Foundation, Inc.
+ Contributed by Oracle Inc.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "libbfd.h"
+
+const bfd_arch_info_type bfd_bpf_arch =
+{
+ 64, /* Bits per word */
+ 64, /* Bits per address. */
+ 8, /* Bits per byte. */
+ bfd_arch_bpf, /* Architecture. */
+ bfd_mach_bpf, /* Machine. */
+ "bpf", /* Architecture name. */
+ "bpf", /* Machine name. */
+ 3, /* Section align power. */
+ TRUE, /* The default ? */
+ bfd_default_compatible, /* Architecture comparison fn. */
+ bfd_default_scan, /* String to architecture convert fn. */
+ bfd_arch_default_fill, /* Default fill. */
+ NULL /* Next in list. */
+};
diff --git a/bfd/elf64-bpf.c b/bfd/elf64-bpf.c
new file mode 100644
index 0000000000..3bfa25b54b
--- /dev/null
+++ b/bfd/elf64-bpf.c
@@ -0,0 +1,463 @@
+/* Linux bpf specific support for 64-bit ELF
+ Copyright (C) 2019 Free Software Foundation, Inc.
+ Contributed by Oracle Inc.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "libbfd.h"
+#include "elf-bfd.h"
+#include "elf/bpf.h"
+#include "libiberty.h"
+
+/* In case we're on a 32-bit machine, construct a 64-bit "-1" value. */
+#define MINUS_ONE (~ (bfd_vma) 0)
+
+#define BASEADDR(SEC) ((SEC)->output_section->vma + (SEC)->output_offset)
+
+/* Handler for PC-relative relocations, which must be handled in
+ 64-bit words. */
+
+static bfd_reloc_status_type
+bpf_elf_insn_disp_reloc (bfd *abfd,
+ arelent *reloc_entry,
+ asymbol *symbol,
+ void *data,
+ asection *input_section,
+ bfd *output_bfd,
+ char **error_message ATTRIBUTE_UNUSED)
+{
+ bfd_signed_vma relocation;
+ bfd_signed_vma addend;
+ reloc_howto_type *howto = reloc_entry->howto;
+
+ /* This part is from bfd_elf_generic_reloc. */
+ if (output_bfd != NULL
+ && (symbol->flags & BSF_SECTION_SYM) == 0
+ && (! reloc_entry->howto->partial_inplace
+ || reloc_entry->addend == 0))
+ {
+ reloc_entry->address += input_section->output_offset;
+ return bfd_reloc_ok;
+ }
+
+ /* This works because partial_inplace is FALSE. */
+ if (output_bfd != NULL)
+ return bfd_reloc_continue;
+
+ if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
+ return bfd_reloc_outofrange;
+
+ relocation = (symbol->value
+ + symbol->section->output_section->vma
+ + symbol->section->output_offset);
+ /* Make it PC relative. */
+ relocation -= (input_section->output_section->vma
+ + input_section->output_offset);
+ relocation -= reloc_entry->address;
+ /* Make it 64-bit words. */
+ relocation = relocation / 8;
+
+ /* Get the addend from the instruction and apply it. */
+ switch (howto->bitsize)
+ {
+ default:
+ abort ();
+ break;
+ case 16:
+ addend = bfd_get_16 (abfd, (bfd_byte *) data + reloc_entry->address + 2);
+ break;
+ case 32:
+ addend = bfd_get_32 (abfd, (bfd_byte *) data + reloc_entry->address + 4);
+ break;
+ }
+
+ if ((addend & (((~howto->src_mask) >> 1) & howto->src_mask)) != 0)
+ addend -= (((~howto->src_mask) >> 1) & howto->src_mask) << 1;
+ relocation += addend;
+
+ /* Write out the relocated value. */
+ switch (howto->bitsize)
+ {
+ default:
+ abort ();
+ break;
+ case 16:
+ bfd_put_16 (abfd, relocation, (bfd_byte *) data + reloc_entry->address + 2);
+ break;
+ case 32:
+ bfd_put_32 (abfd, relocation, (bfd_byte *) data + reloc_entry->address + 4);
+ break;
+ }
+
+ /* Check for overflow. */
+ if (howto->complain_on_overflow == complain_overflow_signed)
+ {
+ bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
+ bfd_signed_vma reloc_signed_min = ~reloc_signed_max;
+
+ if (relocation > reloc_signed_max || relocation < reloc_signed_min)
+ return bfd_reloc_overflow;
+ }
+ else
+ abort();
+
+ return bfd_reloc_ok;
+}
+
+/* Relocation tables. */
+static reloc_howto_type bpf_elf_howto_table [] =
+{
+ /* This reloc does nothing. */
+ HOWTO (R_BPF_NONE, /* type */
+ 0, /* rightshift */
+ 3, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_BPF_NONE", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* 64-immediate in LDDW instruction. */
+ HOWTO (R_BPF_INSN_64, /* type */
+ 0, /* rightshift */
+ 4, /* size (0 = byte, 1 = short, 2 = long) */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_BPF_INSN_64", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* 32-immediate in LDDW instruction. */
+ HOWTO (R_BPF_INSN_32, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_BPF_INSN_32", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* 16-bit offsets in instructions. */
+ HOWTO (R_BPF_INSN_16, /* type */
+ 0, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_BPF_INSN_16", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* 16-bit PC-relative address in jump instructions. */
+ HOWTO (R_BPF_INSN_DISP16, /* type */
+ 0, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ TRUE, /* pc_relative */
+ 32, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bpf_elf_insn_disp_reloc, /* special_function */
+ "R_BPF_INSN_DISP16", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ HOWTO (R_BPF_DATA_8_PCREL,
+ 0, /* rightshift */
+ 0, /* size (0 = byte, 1 = short, 2 = long) */
+ 8, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_BPF_8_PCREL", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0xff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ HOWTO (R_BPF_DATA_16_PCREL,
+ 0, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_BPF_16_PCREL", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0xffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ HOWTO (R_BPF_DATA_32_PCREL,
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_BPF_32_PCREL", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ HOWTO (R_BPF_DATA_8,
+ 0, /* rightshift */
+ 0, /* size (0 = byte, 1 = short, 2 = long) */
+ 8, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_unsigned, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_BPF_DATA_8", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0xff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_BPF_DATA_16,
+ 0, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_unsigned, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_BPF_DATA_16", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* 32-bit PC-relative address in call instructions. */
+ HOWTO (R_BPF_INSN_DISP32, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bpf_elf_insn_disp_reloc, /* special_function */
+ "R_BPF_INSN_DISP32", /* name */
+ FALSE, /* partial_inplace */
+ 0xffffffff, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* 32-bit data. */
+ HOWTO (R_BPF_DATA_32, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_BPF_DATA_32", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* 64-bit data. */
+ HOWTO (R_BPF_DATA_64, /* type */
+ 0, /* rightshift */
+ 4, /* size (0 = byte, 1 = short, 2 = long) */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_BPF_DATA_64", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ HOWTO (R_BPF_DATA_64_PCREL,
+ 0, /* rightshift */
+ 4, /* size (0 = byte, 1 = short, 2 = long) */
+ 64, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_BPF_64_PCREL", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ TRUE), /* pcrel_offset */
+};
+#undef AHOW
+
+/* Map BFD reloc types to bpf ELF reloc types. */
+
+static reloc_howto_type *
+bpf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+ bfd_reloc_code_real_type code)
+{
+ /* Note that the bpf_elf_howto_table is indxed by the R_
+ constants. Thus, the order that the howto records appear in the
+ table *must* match the order of the relocation types defined in
+ include/elf/bpf.h. */
+
+ switch (code)
+ {
+ case BFD_RELOC_NONE:
+ return &bpf_elf_howto_table[ (int) R_BPF_NONE];
+
+ case BFD_RELOC_8_PCREL:
+ return &bpf_elf_howto_table[ (int) R_BPF_DATA_8_PCREL];
+ case BFD_RELOC_16_PCREL:
+ return &bpf_elf_howto_table[ (int) R_BPF_DATA_16_PCREL];
+ case BFD_RELOC_32_PCREL:
+ return &bpf_elf_howto_table[ (int) R_BPF_DATA_32_PCREL];
+ case BFD_RELOC_64_PCREL:
+ return &bpf_elf_howto_table[ (int) R_BPF_DATA_64_PCREL];
+
+ case BFD_RELOC_8:
+ return &bpf_elf_howto_table[ (int) R_BPF_DATA_8];
+ case BFD_RELOC_16:
+ return &bpf_elf_howto_table[ (int) R_BPF_DATA_16];
+ case BFD_RELOC_32:
+ return &bpf_elf_howto_table[ (int) R_BPF_DATA_32];
+ case BFD_RELOC_64:
+ return &bpf_elf_howto_table[ (int) R_BPF_DATA_64];
+
+ case BFD_RELOC_BPF_64:
+ return &bpf_elf_howto_table[ (int) R_BPF_INSN_64];
+ case BFD_RELOC_BPF_32:
+ return &bpf_elf_howto_table[ (int) R_BPF_INSN_32];
+ case BFD_RELOC_BPF_16:
+ return &bpf_elf_howto_table[ (int) R_BPF_INSN_16];
+ case BFD_RELOC_BPF_DISP16:
+ return &bpf_elf_howto_table[ (int) R_BPF_INSN_DISP16];
+ case BFD_RELOC_BPF_DISP32:
+ return &bpf_elf_howto_table[ (int) R_BPF_INSN_DISP32];
+
+ default:
+ /* Pacify gcc -Wall. */
+ return NULL;
+ }
+ return NULL;
+}
+
+/* Map BFD reloc names to bpf ELF reloc names. */
+
+static reloc_howto_type *
+bpf_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE (bpf_elf_howto_table); i++)
+ if (bpf_elf_howto_table[i].name != NULL
+ && strcasecmp (bpf_elf_howto_table[i].name, r_name) == 0)
+ return &bpf_elf_howto_table[i];
+
+ return NULL;
+}
+
+/* Set the howto pointer for a bpf reloc. */
+
+static bfd_boolean
+bpf_info_to_howto (bfd *abfd, arelent *bfd_reloc,
+ Elf_Internal_Rela *elf_reloc)
+{
+ unsigned int r_type;
+
+ r_type = ELF64_R_TYPE (elf_reloc->r_info);
+ if (r_type >= (unsigned int) R_BPF_max)
+ {
+ /* xgettext:c-format */
+ _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
+ abfd, r_type);
+ bfd_set_error (bfd_error_bad_value);
+ return FALSE;
+ }
+
+ bfd_reloc->howto = &bpf_elf_howto_table [r_type];
+ return TRUE;
+}
+
+/* Merge backend specific data from an object file to the output
+ object file when linking. */
+
+static bfd_boolean
+elf64_bpf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
+{
+ /* Check if we have the same endianness. */
+ if (! _bfd_generic_verify_endian_match (ibfd, info))
+ return FALSE;
+
+ return TRUE;
+}
+
+/* The macros below configure the architecture. */
+
+#define TARGET_LITTLE_SYM bpf_elf64_le_vec
+#define TARGET_LITTLE_NAME "elf64-bpfle"
+
+#define TARGET_BIG_SYM bpf_elf64_be_vec
+#define TARGET_BIG_NAME "elf64-bpfbe"
+
+#define ELF_ARCH bfd_arch_bpf
+#define ELF_MACHINE_CODE EM_BPF
+
+#define ELF_MAXPAGESIZE 0x100000
+
+#define elf_info_to_howto_rel bpf_info_to_howto
+#define elf_info_to_howto bpf_info_to_howto
+
+#define elf_backend_may_use_rel_p 1
+#define elf_backend_may_use_rela_p 0
+#define elf_backend_default_use_rela_p 0
+
+#define elf_backend_can_gc_sections 0
+
+#define elf_symbol_leading_char '_'
+#define bfd_elf64_bfd_reloc_type_lookup bpf_reloc_type_lookup
+#define bfd_elf64_bfd_reloc_name_lookup bpf_reloc_name_lookup
+
+#define bfd_elf64_bfd_merge_private_bfd_data elf64_bpf_merge_private_bfd_data
+
+#include "elf64-target.h"
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index d9b7fb7fa5..da52a2b098 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -3238,6 +3238,11 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD",
"BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD",
"BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD",
+ "BFD_RELOC_BPF_64",
+ "BFD_RELOC_BPF_32",
+ "BFD_RELOC_BPF_16",
+ "BFD_RELOC_BPF_DISP16",
+ "BFD_RELOC_BPF_DISP32",
"BFD_RELOC_EPIPHANY_SIMM8",
"BFD_RELOC_EPIPHANY_SIMM24",
"BFD_RELOC_EPIPHANY_HIGH",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index f1465813f7..8f0263e354 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -7883,6 +7883,19 @@ ENUMDOC
Tilera TILE-Gx Relocations.
ENUM
+ BFD_RELOC_BPF_64
+ENUMX
+ BFD_RELOC_BPF_32
+ENUMX
+ BFD_RELOC_BPF_16
+ENUMX
+ BFD_RELOC_BPF_DISP16
+ENUMX
+ BFD_RELOC_BPF_DISP32
+ENUMDOC
+ Linux eBPF relocations.
+
+ENUM
BFD_RELOC_EPIPHANY_SIMM8
ENUMDOC
Adapteva EPIPHANY - 8 bit signed pc-relative displacement
diff --git a/bfd/targets.c b/bfd/targets.c
index 158168cb3b..d3d52a5e2a 100644
--- a/bfd/targets.c
+++ b/bfd/targets.c
@@ -639,6 +639,8 @@ extern const bfd_target elf32_be_vec;
extern const bfd_target elf32_le_vec;
extern const bfd_target elf64_be_vec;
extern const bfd_target elf64_le_vec;
+extern const bfd_target bpf_elf64_le_vec;
+extern const bfd_target bpf_elf64_be_vec;
extern const bfd_target epiphany_elf32_vec;
extern const bfd_target fr30_elf32_vec;
extern const bfd_target frv_elf32_vec;
@@ -1021,6 +1023,11 @@ static const bfd_target * const _bfd_target_vector[] =
&iamcu_elf32_vec,
#ifdef BFD64
+ &bpf_elf64_be_vec,
+ &bpf_elf64_le_vec,
+#endif
+
+#ifdef BFD64
#if 0
&ia64_elf32_be_vec,
#endif
--
2.11.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH V2 6/9] gas: add support for eBPF
2019-05-22 15:26 [PATCH V2 0/9] eBPF support for GNU binutils Jose E. Marchesi
` (3 preceding siblings ...)
2019-05-22 15:24 ` [PATCH V2 3/9] bfd: add support for eBPF Jose E. Marchesi
@ 2019-05-22 15:24 ` Jose E. Marchesi
2019-05-22 15:24 ` [PATCH V2 7/9] ld: " Jose E. Marchesi
` (5 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Jose E. Marchesi @ 2019-05-22 15:24 UTC (permalink / raw)
To: binutils
This patch adds a port for the Linux kernel eBPF to the GNU assembler.
A testsuite and documentation updates are included.
gas/ChangeLog:
2019-05-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* configure.ac: Handle bpf-*-* targets.
* configure.tgt (generic_target): Likewise.
* configure: Regenerate.
* Makefile.am (TARGET_CPU_CFILES): Add tc-bpf.c.
(TARGET_CPU_HFILES): Add tc-bpf.h.
* Makefile.in: Regenerated.
* config/tc-bpf.c: New file.
* config/tc-bpf.h: Likewise.
* doc/Makefile.am (CPU_DOCS): Add c-bpf.texi.
* doc/Makefile.in: Regenerated.
* doc/all.texi: set BPF.
* doc/as.texi: Add eBPF contents.
* doc/c-bpf.texi: New file.
* testsuite/gas/bpf/alu.d: New file.
* testsuite/gas/bpf/mem-be.d: Likewise.
* testsuite/gas/bpf/mem.s: Likewise.
* testsuite/gas/bpf/mem.d: Likewise.
* testsuite/gas/bpf/lddw-be.d: Likewise.
* testsuite/gas/bpf/lddw.s: Likewise.
* testsuite/gas/bpf/lddw.d: Likewise.
* testsuite/gas/bpf/jump-be.d: Likewise.
* testsuite/gas/bpf/jump.s: Likewise.
* testsuite/gas/bpf/jump.d: Likewise.
* testsuite/gas/bpf/exit-be.d: Likewise.
* testsuite/gas/bpf/exit.s: Likewise.
* testsuite/gas/bpf/exit.d: Likewise.
* testsuite/gas/bpf/call-be.d: Likewise.
* testsuite/gas/bpf/call.s: Likewise.
* testsuite/gas/bpf/call.d: Likewise.
* testsuite/gas/bpf/bpf.exp: Likewise.
* testsuite/gas/bpf/atomic-be.d: Likewise.
* testsuite/gas/bpf/atomic.s: Likewise.
* testsuite/gas/bpf/atomic.d: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu32-be.d: Likewise.
* testsuite/gas/bpf/alu32.s: Likewise.
* testsuite/gas/bpf/alu32.d: Likewise.
* testsuite/gas/bpf/alu.s: Likewise.
* testsuite/gas/all/gas.exp: Introduce a nop_type for eBPF.
* testsuite/gas/all/org-1.s: Support nop_type 6.
* testsuite/gas/all/org-1.l: Updated to reflect changes in
org-1.s.
---
gas/ChangeLog | 45 +++++
gas/Makefile.am | 2 +
gas/Makefile.in | 6 +
gas/config/tc-bpf.c | 354 ++++++++++++++++++++++++++++++++++++
gas/config/tc-bpf.h | 51 ++++++
gas/configure | 38 +++-
gas/configure.ac | 6 +
gas/configure.tgt | 1 +
gas/doc/Makefile.am | 1 +
gas/doc/Makefile.in | 2 +
gas/doc/all.texi | 1 +
gas/doc/as.texi | 34 ++++
gas/doc/c-bpf.texi | 364 ++++++++++++++++++++++++++++++++++++++
gas/testsuite/gas/all/gas.exp | 3 +
gas/testsuite/gas/all/org-1.l | 2 +-
gas/testsuite/gas/all/org-1.s | 2 +
gas/testsuite/gas/bpf/alu-be.d | 59 ++++++
gas/testsuite/gas/bpf/alu.d | 58 ++++++
gas/testsuite/gas/bpf/alu.s | 51 ++++++
gas/testsuite/gas/bpf/alu32-be.d | 65 +++++++
gas/testsuite/gas/bpf/alu32.d | 64 +++++++
gas/testsuite/gas/bpf/alu32.s | 57 ++++++
gas/testsuite/gas/bpf/atomic-be.d | 12 ++
gas/testsuite/gas/bpf/atomic.d | 11 ++
gas/testsuite/gas/bpf/atomic.s | 5 +
gas/testsuite/gas/bpf/bpf.exp | 38 ++++
gas/testsuite/gas/bpf/call-be.d | 19 ++
gas/testsuite/gas/bpf/call.d | 18 ++
gas/testsuite/gas/bpf/call.s | 11 ++
gas/testsuite/gas/bpf/exit-be.d | 11 ++
gas/testsuite/gas/bpf/exit.d | 10 ++
gas/testsuite/gas/bpf/exit.s | 2 +
gas/testsuite/gas/bpf/jump-be.d | 32 ++++
gas/testsuite/gas/bpf/jump.d | 31 ++++
gas/testsuite/gas/bpf/jump.s | 25 +++
gas/testsuite/gas/bpf/lddw-be.d | 18 ++
gas/testsuite/gas/bpf/lddw.d | 17 ++
gas/testsuite/gas/bpf/lddw.s | 6 +
gas/testsuite/gas/bpf/mem-be.d | 30 ++++
gas/testsuite/gas/bpf/mem.d | 29 +++
gas/testsuite/gas/bpf/mem.s | 24 +++
41 files changed, 1606 insertions(+), 9 deletions(-)
create mode 100644 gas/config/tc-bpf.c
create mode 100644 gas/config/tc-bpf.h
create mode 100644 gas/doc/c-bpf.texi
create mode 100644 gas/testsuite/gas/bpf/alu-be.d
create mode 100644 gas/testsuite/gas/bpf/alu.d
create mode 100644 gas/testsuite/gas/bpf/alu.s
create mode 100644 gas/testsuite/gas/bpf/alu32-be.d
create mode 100644 gas/testsuite/gas/bpf/alu32.d
create mode 100644 gas/testsuite/gas/bpf/alu32.s
create mode 100644 gas/testsuite/gas/bpf/atomic-be.d
create mode 100644 gas/testsuite/gas/bpf/atomic.d
create mode 100644 gas/testsuite/gas/bpf/atomic.s
create mode 100644 gas/testsuite/gas/bpf/bpf.exp
create mode 100644 gas/testsuite/gas/bpf/call-be.d
create mode 100644 gas/testsuite/gas/bpf/call.d
create mode 100644 gas/testsuite/gas/bpf/call.s
create mode 100644 gas/testsuite/gas/bpf/exit-be.d
create mode 100644 gas/testsuite/gas/bpf/exit.d
create mode 100644 gas/testsuite/gas/bpf/exit.s
create mode 100644 gas/testsuite/gas/bpf/jump-be.d
create mode 100644 gas/testsuite/gas/bpf/jump.d
create mode 100644 gas/testsuite/gas/bpf/jump.s
create mode 100644 gas/testsuite/gas/bpf/lddw-be.d
create mode 100644 gas/testsuite/gas/bpf/lddw.d
create mode 100644 gas/testsuite/gas/bpf/lddw.s
create mode 100644 gas/testsuite/gas/bpf/mem-be.d
create mode 100644 gas/testsuite/gas/bpf/mem.d
create mode 100644 gas/testsuite/gas/bpf/mem.s
diff --git a/gas/Makefile.am b/gas/Makefile.am
index 6f4276a7ef..2e95409671 100644
--- a/gas/Makefile.am
+++ b/gas/Makefile.am
@@ -134,6 +134,7 @@ TARGET_CPU_CFILES = \
config/tc-arm.c \
config/tc-avr.c \
config/tc-bfin.c \
+ config/tc-bpf.c \
config/tc-cr16.c \
config/tc-cris.c \
config/tc-crx.c \
@@ -209,6 +210,7 @@ TARGET_CPU_HFILES = \
config/tc-arm.h \
config/tc-avr.h \
config/tc-bfin.h \
+ config/tc-bpf.h \
config/tc-cr16.h \
config/tc-cris.h \
config/tc-crx.h \
diff --git a/gas/Makefile.in b/gas/Makefile.in
index 252dff9a69..595295e555 100644
--- a/gas/Makefile.in
+++ b/gas/Makefile.in
@@ -402,6 +402,7 @@ pdfdir = @pdfdir@
prefix = @prefix@
program_transform_name = @program_transform_name@
psdir = @psdir@
+runstatedir = @runstatedir@
sbindir = @sbindir@
sharedstatedir = @sharedstatedir@
srcdir = @srcdir@
@@ -523,6 +524,7 @@ TARGET_CPU_CFILES = \
config/tc-arm.c \
config/tc-avr.c \
config/tc-bfin.c \
+ config/tc-bpf.c \
config/tc-cr16.c \
config/tc-cris.c \
config/tc-crx.c \
@@ -598,6 +600,7 @@ TARGET_CPU_HFILES = \
config/tc-arm.h \
config/tc-avr.h \
config/tc-bfin.h \
+ config/tc-bpf.h \
config/tc-cr16.h \
config/tc-cris.h \
config/tc-crx.h \
@@ -896,6 +899,8 @@ config/tc-avr.$(OBJEXT): config/$(am__dirstamp) \
config/$(DEPDIR)/$(am__dirstamp)
config/tc-bfin.$(OBJEXT): config/$(am__dirstamp) \
config/$(DEPDIR)/$(am__dirstamp)
+config/tc-bpf.$(OBJEXT): config/$(am__dirstamp) \
+ config/$(DEPDIR)/$(am__dirstamp)
config/tc-cr16.$(OBJEXT): config/$(am__dirstamp) \
config/$(DEPDIR)/$(am__dirstamp)
config/tc-cris.$(OBJEXT): config/$(am__dirstamp) \
@@ -1151,6 +1156,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-arm.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-avr.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-bfin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-bpf.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-cr16.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-cris.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-crx.Po@am__quote@
diff --git a/gas/config/tc-bpf.c b/gas/config/tc-bpf.c
new file mode 100644
index 0000000000..9318c3563b
--- /dev/null
+++ b/gas/config/tc-bpf.c
@@ -0,0 +1,354 @@
+/* tc-bpf.c -- Assembler for the Linux eBPF.
+ Copyright (C) 2019 Free Software Foundation, Inc.
+ Contributed by Oracle, Inc.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to
+ the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+#include "as.h"
+#include "subsegs.h"
+#include "symcat.h"
+#include "opcodes/bpf-desc.h"
+#include "opcodes/bpf-opc.h"
+#include "cgen.h"
+#include "elf/common.h"
+#include "elf/bpf.h"
+#include "dwarf2dbg.h"
+
+const char comment_chars[] = ";";
+const char line_comment_chars[] = "#";
+const char line_separator_chars[] = "`";
+const char EXP_CHARS[] = "eE";
+const char FLT_CHARS[] = "fFdD";
+
+/* The target specific pseudo-ops which we support. */
+const pseudo_typeS md_pseudo_table[] =
+{
+ { NULL, NULL, 0 }
+};
+
+/* ISA handling. */
+static CGEN_BITSET *bpf_isa;
+
+\f
+
+/* Command-line options processing. */
+
+enum options
+{
+ OPTION_LITTLE_ENDIAN = OPTION_MD_BASE,
+ OPTION_BIG_ENDIAN
+};
+
+struct option md_longopts[] =
+{
+ { "EL", no_argument, NULL, OPTION_LITTLE_ENDIAN },
+ { "EB", no_argument, NULL, OPTION_BIG_ENDIAN },
+ { NULL, no_argument, NULL, 0 },
+};
+
+size_t md_longopts_size = sizeof (md_longopts);
+
+const char * md_shortopts = "";
+
+extern int target_big_endian;
+
+/* Whether target_big_endian has been set while parsing command-line
+ arguments. */
+static int set_target_endian = 0;
+
+int
+md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
+{
+ switch (c)
+ {
+ case OPTION_BIG_ENDIAN:
+ set_target_endian = 1;
+ target_big_endian = 1;
+ break;
+ case OPTION_LITTLE_ENDIAN:
+ set_target_endian = 1;
+ target_big_endian = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ return 1;
+}
+
+void
+md_show_usage (FILE * stream)
+{
+ fprintf (stream, _("\nBPF options:\n"));
+ fprintf (stream, _("\
+ --EL generate code for a little endian machine\n\
+ --EB generate code for a big endian machine\n"));
+}
+
+\f
+void
+md_begin (void)
+{
+ /* Initialize the `cgen' interface. */
+
+ /* If not specified in the command line, use the host
+ endianness. */
+ if (!set_target_endian)
+ {
+#ifdef WORDS_BIGENDIAN
+ target_big_endian = 1;
+#else
+ target_big_endian = 0;
+#endif
+ }
+
+ /* Set the ISA, which depends on the target endianness. */
+ bpf_isa = cgen_bitset_create (ISA_MAX);
+ if (target_big_endian)
+ cgen_bitset_set (bpf_isa, ISA_EBPFBE);
+ else
+ cgen_bitset_set (bpf_isa, ISA_EBPFLE);
+
+ /* Set the machine number and endian. */
+ gas_cgen_cpu_desc = bpf_cgen_cpu_open (CGEN_CPU_OPEN_ENDIAN,
+ target_big_endian ?
+ CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE,
+ CGEN_CPU_OPEN_ISAS,
+ bpf_isa,
+ CGEN_CPU_OPEN_END);
+ bpf_cgen_init_asm (gas_cgen_cpu_desc);
+
+ /* This is a callback from cgen to gas to parse operands. */
+ cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
+
+ /* Set the machine type. */
+ bfd_default_set_arch_mach (stdoutput, bfd_arch_bpf, bfd_mach_bpf);
+}
+
+valueT
+md_section_align (segT segment, valueT size)
+{
+ int align = bfd_get_section_alignment (stdoutput, segment);
+
+ return ((size + (1 << align) - 1) & -(1 << align));
+}
+
+\f
+/* Functions concerning relocs. */
+
+/* The location from which a PC relative jump should be calculated,
+ given a PC relative reloc. */
+
+long
+md_pcrel_from_section (fixS *fixP, segT sec)
+{
+ if (fixP->fx_addsy != (symbolS *) NULL
+ && (! S_IS_DEFINED (fixP->fx_addsy)
+ || (S_GET_SEGMENT (fixP->fx_addsy) != sec)
+ || S_IS_EXTERNAL (fixP->fx_addsy)
+ || S_IS_WEAK (fixP->fx_addsy)))
+ {
+ /* The symbol is undefined (or is defined but not in this section).
+ Let the linker figure it out. */
+ return 0;
+ }
+
+ return fixP->fx_where + fixP->fx_frag->fr_address;
+}
+
+/* Write a value out to the object file, using the appropriate endianness. */
+
+void
+md_number_to_chars (char * buf, valueT val, int n)
+{
+ if (target_big_endian)
+ number_to_chars_bigendian (buf, val, n);
+ else
+ number_to_chars_littleendian (buf, val, n);
+}
+
+arelent *
+tc_gen_reloc (asection *sec, fixS *fix)
+{
+ return gas_cgen_tc_gen_reloc (sec, fix);
+}
+
+/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. This
+ is called when the operand is an expression that couldn't be fully
+ resolved. Returns BFD_RELOC_NONE if no reloc type can be found.
+ *FIXP may be modified if desired. */
+
+bfd_reloc_code_real_type
+md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
+ const CGEN_OPERAND *operand,
+ fixS *fixP)
+{
+ switch (operand->type)
+ {
+ case BPF_OPERAND_OFFSET16:
+ return BFD_RELOC_BPF_16;
+ case BPF_OPERAND_IMM32:
+ return BFD_RELOC_BPF_32;
+ case BPF_OPERAND_IMM64:
+ return BFD_RELOC_BPF_64;
+ case BPF_OPERAND_DISP16:
+ fixP->fx_pcrel = 1;
+ return BFD_RELOC_BPF_DISP16;
+ case BPF_OPERAND_DISP32:
+ fixP->fx_pcrel = 1;
+ return BFD_RELOC_BPF_DISP32;
+ default:
+ break;
+ }
+ return BFD_RELOC_NONE;
+}
+\f
+/* *FRAGP has been relaxed to its final size, and now needs to have
+ the bytes inside it modified to conform to the new size.
+
+ Called after relaxation is finished.
+ fragP->fr_type == rs_machine_dependent.
+ fragP->fr_subtype is the subtype of what the address relaxed to. */
+
+void
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+ segT sec ATTRIBUTE_UNUSED,
+ fragS *fragP ATTRIBUTE_UNUSED)
+{
+ as_fatal (_("convert_frag called"));
+}
+
+int
+md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED,
+ segT segment ATTRIBUTE_UNUSED)
+{
+ as_fatal (_("estimate_size_before_relax called"));
+ return 0;
+}
+
+\f
+void
+md_apply_fix (fixS *fixP, valueT *valP, segT seg)
+{
+ /* Some fixups for instructions require special attention. This is
+ handled in the code block below. */
+ if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
+ {
+ int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
+ const CGEN_OPERAND *operand = cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
+ opindex);
+ char *where;
+
+ switch (operand->type)
+ {
+ case BPF_OPERAND_DISP32:
+ /* eBPF supports two kind of CALL instructions: the so
+ called pseudo calls ("bpf to bpf") and external calls
+ ("bpf to kernel").
+
+ Both kind of calls use the same instruction (CALL).
+ However, external calls are constructed by passing a
+ constant argument to the instruction, whereas pseudo
+ calls result from expressions involving symbols. In
+ practice, instructions requiring a fixup are interpreted
+ as pseudo-calls. If we are executing this code, this is
+ a pseudo call.
+
+ The kernel expects for pseudo-calls to be annotated by
+ having BPF_PSEUDO_CALL in the SRC field of the
+ instruction. But beware the infamous nibble-swapping of
+ eBPF and take endianness into account here.
+
+ Note that the CALL instruction has only one operand, so
+ this code is executed only once per instruction. */
+ where = fixP->fx_frag->fr_literal + fixP->fx_where;
+ cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) where + 1, 8,
+ target_big_endian ? 0x01 : 0x10);
+ /* Fallthrough. */
+ case BPF_OPERAND_DISP16:
+ /* The PC-relative displacement fields in jump instructions
+ shouldn't be in bytes. Instead, they hold the number of
+ 64-bit words to the target, _minus one_. */
+ *valP = (((long) (*valP)) - 8) / 8;
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* And now invoke CGEN's handler, which will eventually install
+ *valP into the corresponding operand. */
+ gas_cgen_md_apply_fix (fixP, valP, seg);
+}
+
+void
+md_assemble (char *str)
+{
+ const CGEN_INSN *insn;
+ char *errmsg;
+ CGEN_FIELDS fields;
+
+#if CGEN_INT_INSN_P
+ CGEN_INSN_INT buffer[CGEN_MAX_INSN_SIZE / sizeof (CGEN_INT_INSN_P)];
+#else
+ unsigned char buffer[CGEN_MAX_INSN_SIZE];
+ memset (buffer, 0, CGEN_MAX_INSN_SIZE); /* XXX to remove when CGEN
+ is fixed to handle
+ opcodes-in-words
+ properly. */
+#endif
+
+ gas_cgen_init_parse ();
+ insn = bpf_cgen_assemble_insn (gas_cgen_cpu_desc, str, &fields,
+ buffer, &errmsg);
+
+ if (insn == NULL)
+ {
+ as_bad ("%s", errmsg);
+ return;
+ }
+
+ gas_cgen_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (&fields),
+ 0, /* zero to ban relaxable insns. */
+ NULL); /* NULL so results not returned here. */
+}
+
+void
+md_operand (expressionS *expressionP)
+{
+ gas_cgen_md_operand (expressionP);
+}
+
+
+symbolS *
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
+{
+ return NULL;
+}
+
+\f
+/* Turn a string in input_line_pointer into a floating point constant
+ of type TYPE, and store the appropriate bytes in *LITP. The number
+ of LITTLENUMS emitted is stored in *SIZEP. An error message is
+ returned, or NULL on OK. */
+
+const char *
+md_atof (int type, char *litP, int *sizeP)
+{
+ return ieee_md_atof (type, litP, sizeP, FALSE);
+}
diff --git a/gas/config/tc-bpf.h b/gas/config/tc-bpf.h
new file mode 100644
index 0000000000..310cbc0a17
--- /dev/null
+++ b/gas/config/tc-bpf.h
@@ -0,0 +1,51 @@
+/* tc-bpf.h -- Header file for tc-ebpf.c.
+ Copyright (C) 2019 Free Software Foundation, Inc.
+ Contributed by Oracle, Inc.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+#define TC_BPF
+
+#define LISTING_HEADER "BPF GAS "
+
+/* The target BFD architecture. */
+#define TARGET_ARCH bfd_arch_bpf
+#define TARGET_MACH 0 /* The default. */
+
+#define TARGET_FORMAT \
+ (target_big_endian ? "elf64-bpfbe" : "elf64-bpfle")
+
+/* This is used to set the default value for `target_big_endian'. */
+#ifndef TARGET_BYTES_BIG_ENDIAN
+#define TARGET_BYTES_BIG_ENDIAN 0
+#endif
+
+/* .-foo gets turned into PC relative relocs. */
+#define DIFF_EXPR_OK 1
+#define GAS_CGEN_PCREL_R_TYPE(R_TYPE) gas_cgen_pcrel_r_type (R_TYPE)
+
+/* Call md_pcrel_from_section(), not md_pcrel_from(). */
+#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
+extern long md_pcrel_from_section (struct fix *, segT);
+
+/* We don't need to handle .word strangely. */
+#define WORKING_DOT_WORD
+
+/* Values passed to md_apply_fix don't include the symbol value. */
+#define MD_APPLY_SYM_VALUE(FIX) 0
+
diff --git a/gas/configure b/gas/configure
index 1aafa6b31d..8b921094c4 100755
--- a/gas/configure
+++ b/gas/configure
@@ -770,6 +770,7 @@ infodir
docdir
oldincludedir
includedir
+runstatedir
localstatedir
sharedstatedir
sysconfdir
@@ -867,6 +868,7 @@ datadir='${datarootdir}'
sysconfdir='${prefix}/etc'
sharedstatedir='${prefix}/com'
localstatedir='${prefix}/var'
+runstatedir='${localstatedir}/run'
includedir='${prefix}/include'
oldincludedir='/usr/include'
docdir='${datarootdir}/doc/${PACKAGE_TARNAME}'
@@ -1119,6 +1121,15 @@ do
| -silent | --silent | --silen | --sile | --sil)
silent=yes ;;
+ -runstatedir | --runstatedir | --runstatedi | --runstated \
+ | --runstate | --runstat | --runsta | --runst | --runs \
+ | --run | --ru | --r)
+ ac_prev=runstatedir ;;
+ -runstatedir=* | --runstatedir=* | --runstatedi=* | --runstated=* \
+ | --runstate=* | --runstat=* | --runsta=* | --runst=* | --runs=* \
+ | --run=* | --ru=* | --r=*)
+ runstatedir=$ac_optarg ;;
+
-sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
ac_prev=sbindir ;;
-sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
@@ -1256,7 +1267,7 @@ fi
for ac_var in exec_prefix prefix bindir sbindir libexecdir datarootdir \
datadir sysconfdir sharedstatedir localstatedir includedir \
oldincludedir docdir infodir htmldir dvidir pdfdir psdir \
- libdir localedir mandir
+ libdir localedir mandir runstatedir
do
eval ac_val=\$$ac_var
# Remove trailing slashes.
@@ -1409,6 +1420,7 @@ Fine tuning of the installation directories:
--sysconfdir=DIR read-only single-machine data [PREFIX/etc]
--sharedstatedir=DIR modifiable architecture-independent data [PREFIX/com]
--localstatedir=DIR modifiable single-machine data [PREFIX/var]
+ --runstatedir=DIR modifiable per-process data [LOCALSTATEDIR/run]
--libdir=DIR object code libraries [EPREFIX/lib]
--includedir=DIR C header files [PREFIX/include]
--oldincludedir=DIR C header files for non-gcc [/usr/include]
@@ -11343,7 +11355,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 11346 "configure"
+#line 11358 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -11449,7 +11461,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 11452 "configure"
+#line 11464 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -11836,7 +11848,7 @@ else
We can't simply define LARGE_OFF_T to be 9223372036854775807,
since some C++ compilers masquerading as C compilers
incorrectly reject 9223372036854775807. */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
&& LARGE_OFF_T % 2147483647 == 1)
? 1 : -1];
@@ -11882,7 +11894,7 @@ else
We can't simply define LARGE_OFF_T to be 9223372036854775807,
since some C++ compilers masquerading as C compilers
incorrectly reject 9223372036854775807. */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
&& LARGE_OFF_T % 2147483647 == 1)
? 1 : -1];
@@ -11906,7 +11918,7 @@ rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
We can't simply define LARGE_OFF_T to be 9223372036854775807,
since some C++ compilers masquerading as C compilers
incorrectly reject 9223372036854775807. */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
&& LARGE_OFF_T % 2147483647 == 1)
? 1 : -1];
@@ -11951,7 +11963,7 @@ else
We can't simply define LARGE_OFF_T to be 9223372036854775807,
since some C++ compilers masquerading as C compilers
incorrectly reject 9223372036854775807. */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
&& LARGE_OFF_T % 2147483647 == 1)
? 1 : -1];
@@ -11975,7 +11987,7 @@ rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
We can't simply define LARGE_OFF_T to be 9223372036854775807,
since some C++ compilers masquerading as C compilers
incorrectly reject 9223372036854775807. */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
&& LARGE_OFF_T % 2147483647 == 1)
? 1 : -1];
@@ -12831,6 +12843,16 @@ _ACEOF
done
;;
+ bpf)
+ if test $this_target = $target ; then
+
+cat >>confdefs.h <<_ACEOF
+#define DEFAULT_ARCH "${arch}"
+_ACEOF
+
+ fi
+ using_cgen=yes
+ ;;
epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k)
using_cgen=yes
;;
diff --git a/gas/configure.ac b/gas/configure.ac
index 4b25b7ca36..34e114aa08 100644
--- a/gas/configure.ac
+++ b/gas/configure.ac
@@ -430,6 +430,12 @@ changequote([,])dnl
done
;;
+ bpf)
+ if test $this_target = $target ; then
+ AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.])
+ fi
+ using_cgen=yes
+ ;;
epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k)
using_cgen=yes
;;
diff --git a/gas/configure.tgt b/gas/configure.tgt
index 2d08c09de9..a4828c4cae 100644
--- a/gas/configure.tgt
+++ b/gas/configure.tgt
@@ -182,6 +182,7 @@ case ${generic_target} in
d30v-*-*) fmt=elf ;;
dlx-*-*) fmt=elf ;;
+ bpf-*-*) fmt=elf ;;
epiphany-*-*) fmt=elf ;;
fr30-*-*) fmt=elf ;;
diff --git a/gas/doc/Makefile.am b/gas/doc/Makefile.am
index 8ee7b2bedd..9bd50f4b77 100644
--- a/gas/doc/Makefile.am
+++ b/gas/doc/Makefile.am
@@ -52,6 +52,7 @@ CPU_DOCS = \
c-arm.texi \
c-avr.texi \
c-bfin.texi \
+ c-bpf.texi \
c-cr16.texi \
c-cris.texi \
c-csky.texi \
diff --git a/gas/doc/Makefile.in b/gas/doc/Makefile.in
index 9d0520ec8e..854ee9daef 100644
--- a/gas/doc/Makefile.in
+++ b/gas/doc/Makefile.in
@@ -364,6 +364,7 @@ pdfdir = @pdfdir@
prefix = @prefix@
program_transform_name = @program_transform_name@
psdir = @psdir@
+runstatedir = @runstatedir@
sbindir = @sbindir@
sharedstatedir = @sharedstatedir@
srcdir = @srcdir@
@@ -407,6 +408,7 @@ CPU_DOCS = \
c-arm.texi \
c-avr.texi \
c-bfin.texi \
+ c-bpf.texi \
c-cr16.texi \
c-cris.texi \
c-csky.texi \
diff --git a/gas/doc/all.texi b/gas/doc/all.texi
index e5617222ff..f76fdf779f 100644
--- a/gas/doc/all.texi
+++ b/gas/doc/all.texi
@@ -30,6 +30,7 @@
@set ARM
@set AVR
@set Blackfin
+@set BPF
@set CR16
@set CRIS
@set CSKY
diff --git a/gas/doc/as.texi b/gas/doc/as.texi
index f0d91d0f78..763c9d2263 100644
--- a/gas/doc/as.texi
+++ b/gas/doc/as.texi
@@ -40,6 +40,9 @@
@ifset Blackfin
@set Blackfin
@end ifset
+@ifset BPF
+@set BPF
+@end ifset
@ifset H8/300
@set H8
@end ifset
@@ -296,6 +299,11 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
[@b{-mno-fdpic}]
[@b{-mnopic}]
@end ifset
+@ifset BPF
+
+@emph{Target BPF options:}
+ [@b{-EL}] [@b{-EB}]
+@end ifset
@ifset CRIS
@emph{Target CRIS options:}
@@ -1001,6 +1009,25 @@ the Blackfin processor family.
@end ifset
+@ifset BPF
+
+@ifclear man
+@xref{BPF Options}, for the options available when @value{AS} is
+configured for the Linux kernel BPF processor family.
+@end ifclear
+
+@ifset man
+@c man begin OPTIONS
+The following options are available when @value{AS} is configured for
+the Linux kernel BPF processor family.
+@c man end
+@c man begin INCLUDE
+@include c-bpf.texi
+@c ended inside the included file
+@end ifset
+
+@end ifset
+
@c man begin OPTIONS
@ifset CRIS
See the info pages for documentation of the CRIS-specific options.
@@ -7615,6 +7642,9 @@ subject, see the hardware manufacturer's manual.
@ifset Blackfin
* Blackfin-Dependent:: Blackfin Dependent Features
@end ifset
+@ifset BPF
+* BPF-Dependent:: BPF Dependent Features
+@end ifset
@ifset CR16
* CR16-Dependent:: CR16 Dependent Features
@end ifset
@@ -7802,6 +7832,10 @@ subject, see the hardware manufacturer's manual.
@include c-bfin.texi
@end ifset
+@ifset BPF
+@include c-bpf.texi
+@end ifset
+
@ifset CR16
@include c-cr16.texi
@end ifset
diff --git a/gas/doc/c-bpf.texi b/gas/doc/c-bpf.texi
new file mode 100644
index 0000000000..a7a694f3bd
--- /dev/null
+++ b/gas/doc/c-bpf.texi
@@ -0,0 +1,364 @@
+@c Copyright (C) 2019 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+
+@ifset GENERIC
+@page
+@node BPF-Dependent
+@chapter BPF Dependent Features
+@end ifset
+
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter BPF Dependent Features
+@end ifclear
+
+@cindex BPF support
+@menu
+* BPF Options:: Options
+* BPF Syntax:: Syntax
+* BPF Opcodes:: Opcodes
+@end menu
+
+@node BPF Options
+@section Options
+@cindex BPF options (none)
+@cindex options for BPF (none)
+
+@c man begin OPTIONS
+@table @gcctabopt
+
+@cindex @option{-EB} command-line option, BPF
+@item -EB
+This option specifies that the assembler should emit big-endian eBPF.
+
+@cindex @option{-EL} command-line option, BPF
+@item -EL
+This option specifies that the assembler should emit little-endian
+eBPF.
+@end table
+
+Note that if no endianness option is specified in the command line,
+the host endianness is used.
+@c man end
+
+@node BPF Syntax
+@section Syntax
+@menu
+* BPF-Chars:: Special Characters
+* BPF-Regs:: Register Names
+* BPF-Pseudo-Maps:: Pseudo map fds
+@end menu
+
+@node BPF-Chars
+@subsection Special Characters
+
+@cindex line comment character, BPF
+@cindex BPF line comment character
+The presence of a @samp{;} on a line indicates the start of a comment
+that extends to the end of the current line. If a @samp{#} appears as
+the first character of a line, the whole line is treated as a comment.
+
+@cindex statement separator, BPF
+Statements and assembly directives are separated by newlines.
+
+@node BPF-Regs
+@subsection Register Names
+
+@cindex BPF register names
+@cindex register names, BPF
+The eBPF processor provides ten general-purpose 64-bit registers,
+which are read-write, and a read-only frame pointer register:
+
+@table @samp
+@item %r0 .. %r9
+General-purpose registers.
+@item %r10
+Frame pointer register.
+@end table
+
+Some registers have additional names, to reflect their role in the
+eBPF ABI:
+
+@table @samp
+@item %a
+This is @samp{%r0}.
+@item %ctx
+This is @samp{%r6}.
+@item %fp
+This is @samp{%r10}.
+@end table
+
+@node BPF-Pseudo-Maps
+@subsection Pseudo Maps
+
+@cindex pseudo map fd, BPF
+The @samp{LDDW} instruction can take a literal pseudo map file
+descriptor as its second argument. This uses the syntax
+@samp{%map_fd(N)} where @samp{N} is a signed number.
+
+For example, to load the address of the pseudo map with file
+descriptor @samp{2} in register @samp{r1} we would do:
+
+@smallexample
+ lddw %r1, %map_fd(2)
+@end smallexample
+
+@node BPF Opcodes
+@section Opcodes
+
+@cindex BPF opcodes
+@cindex opcodes for BPF
+In the instruction descriptions below the following field descriptors
+are used:
+
+@table @code
+@item %d
+Destination general-purpose register whose role is to be destination
+of an operation.
+@item %s
+Source general-purpose register whose role is to be the source of an
+operation.
+@item disp16
+16-bit signed PC-relative offset, measured in number of 64-bit words,
+minus one.
+@item disp32
+32-bit signed PC-relative offset, measured in number of 64-bit words,
+minus one.
+@item offset16
+Signed 16-bit immediate.
+@item imm32
+Signed 32-bit immediate.
+@item imm64
+Signed 64-bit immediate.
+@end table
+
+@subsubsection Arithmetic instructions
+
+The destination register in these instructions act like an
+accumulator.
+
+@table @code
+@item add %d, (%s|imm32)
+64-bit arithmetic addition.
+@item sub %d, (%s|imm32)
+64-bit arithmetic subtraction.
+@item mul %d, (%s|imm32)
+64-bit arithmetic multiplication.
+@item div %d, (%s|imm32)
+64-bit arithmetic integer division.
+@item mod %d, (%s|imm32)
+64-bit integer remainder.
+@item and %d, (%s|imm32)
+64-bit bit-wise ``and'' operation.
+@item or %d, (%s|imm32)
+64-bit bit-wise ``or'' operation.
+@item xor %d, (%s|imm32)
+64-bit bit-wise exclusive-or operation.
+@item lsh %d, (%s|imm32)
+64-bit left shift, by @code{%s} or @code{imm32} bits.
+@item rsh %d, (%s|imm32)
+64-bit right logical shift, by @code{%s} or @code{imm32} bits.
+@item arsh %d, (%s|imm32)
+64-bit right arithmetic shift, by @code{%s} or @code{imm32} bits.
+@item neg %d
+64-bit arithmetic negation.
+@item mov %d, (%s|imm32)
+Move the 64-bit value of @code{%s} in @code{%d}, or load @code{imm32}
+in @code{%d}.
+@end table
+
+@subsubsection 32-bit arithmetic instructions
+
+The destination register in these instructions act as an accumulator.
+
+@table @code
+@item add32 %d, (%s|imm32)
+32-bit arithmetic addition.
+@item sub32 %d, (%s|imm32)
+32-bit arithmetic subtraction.
+@item mul32 %d, (%s|imm32)
+32-bit arithmetic multiplication.
+@item div32 %d, (%s|imm32)
+32-bit arithmetic integer division.
+@item mod32 %d, (%s|imm32)
+32-bit integer remainder.
+@item and32 %d, (%s|imm32)
+32-bit bit-wise ``and'' operation.
+@item or32 %d, (%s|imm32)
+32-bit bit-wise ``or'' operation.
+@item xor32 %d, (%s|imm32)
+32-bit bit-wise exclusive-or operation.
+@item lsh32 %d, (%s|imm32)
+32-bit left shift, by @code{%s} or @code{imm32} bits.
+@item rsh32 %d, (%s|imm32)
+32-bit right logical shift, by @code{%s} or @code{imm32} bits.
+@item arsh32 %d, (%s|imm32)
+32-bit right arithmetic shift, by @code{%s} or @code{imm32} bits.
+@item neg32 %d
+32-bit arithmetic negation.
+@item mov32 %d, (%s|imm32)
+Move the 32-bit value of @code{%s} in @code{%d}, or load @code{imm32}
+in @code{%d}.
+@end table
+
+@subsubsection Endianness conversion instructions
+
+@table @code
+@item endle %d, (8|16|32)
+Convert the 8-bit, 16-bit or 32-bit value in @code{%d} to
+little-endian.
+@item endbe %d, (8|16|32)
+Convert the 8-bit, 16-bit or 32-bit value in @code{%d} to big-endian.
+@end table
+
+@subsubsection 64-bit load and pseudo maps
+
+@table @code
+@item lddw %d, imm64
+Load the given signed 64-bit immediate, or pseudo map descriptor, to
+the destination register @code{%d}.
+@item lddw %d, %map_fd(N)
+Load the address of the given pseudo map fd @emph{N} to the
+destination register @code{%d}.
+@end table
+
+@subsubsection Load instructions for socket filters
+
+The following instructions are intended to be used in socket filters,
+and are therefore not general-purpose: they make assumptions on the
+contents of several registers. See the file
+@file{Documentation/networking/filter.txt} in the Linux kernel source
+tree for more information.
+
+Absolute loads:
+
+@table @code
+@item ldabsdw %d, %s, imm32
+Absolute 64-bit load.
+@item ldabsw %d, %s, imm32
+Absolute 32-bit load.
+@item ldabsh %d, %s, imm32
+Absolute 16-bit load.
+@item ldabsb %d, %s, imm32
+Absolute 8-bit load.
+@end table
+
+Indirect loads:
+
+@table @code
+@item ldinddw %d, %s, imm32
+Indirect 64-bit load.
+@item ldindw %d, %s, imm32
+Indirect 32-bit load.
+@item ldindh %d, %s, imm32
+Indirect 16-bit load.
+@item ldindb %d, %s, imm32
+Indirect 8-bit load.
+@end table
+
+@subsubsection Generic load/store instructions
+
+General-purpose load and store instructions are provided for several
+word sizes.
+
+Load to register instructions:
+
+@table @code
+@item ldxdw %d, [%s+offset16]
+Generic 64-bit load.
+@item ldxw %d, [%s+offset16]
+Generic 32-bit load.
+@item ldxh %d, [%s+offset16]
+Generic 16-bit load.
+@item ldxb %d, [%s+offset16]
+Generic 8-bit load.
+@end table
+
+Store from register instructions:
+
+@table @code
+@item stxdw [%d+offset16], %s
+Generic 64-bit store.
+@item stxw [%d+offset16], %s
+Generic 32-bit store.
+@item stxh [%d+offset16], %s
+Generic 16-bit store.
+@item stxb [%d+offset16], %s
+Generic 8-bit store.
+@end table
+
+Store from immediates instructions:
+
+@table @code
+@item stddw [%d+offset16], imm32
+Store immediate as 64-bit.
+@item stdw [%d+offset16], imm32
+Store immediate as 32-bit.
+@item stdh [%d+offset16], imm32
+Store immediate as 16-bit.
+@item stdb [%d+offset16], imm32
+Store immediate as 8-bit.
+@end table
+
+@subsubsection Jump instructions
+
+eBPF provides the following compare-and-jump instructions, which
+compare the values of the two given registers, or the values of a
+register and an immediate, and perform a branch in case the comparison
+holds true.
+
+@table @code
+@item ja %d,(%s|imm32),disp16
+Jump-always.
+@item jeq %d,(%s|imm32),disp16
+Jump if equal.
+@item jgt %d,(%s|imm32),disp16
+Jump if greater.
+@item jge %d,(%s|imm32),disp16
+Jump if greater or equal.
+@item jlt %d,(%s|imm32),disp16
+Jump if lesser.
+@item jle %d,(%s|imm32),disp16
+Jump if lesser or equal.
+@item jset %d,(%s|imm32),disp16
+Jump if signed equal.
+@item jne %d,(%s|imm32),disp16
+Jump if not equal.
+@item jsgt %d,(%s|imm32),disp16
+Jump if signed greater.
+@item jsge %d,(%s|imm32),disp16
+Jump if signed greater or equal.
+@item jslt %d,(%s|imm32),disp16
+Jump if signed lesser.
+@item jsle %d,(%s|imm32),disp16
+Jump if signed lesser or equal.
+@end table
+
+A call instruction is provided in order to perform calls to other eBPF
+functions, or to external kernel helpers:
+
+@table @code
+@item call (disp32|imm32)
+Jump and link to the offset @emph{disp32}, or to the kernel helper
+function identified by @emph{imm32}.
+@end table
+
+Finally:
+
+@table @code
+@item exit
+Terminate the eBPF program.
+@end table
+
+@subsubsection Atomic instructions
+
+Atomic exchange-and-add instructions are provided in two flavors: one
+for swapping 64-bit quantities and another for 32-bit quantities.
+
+@table @code
+@item xadddw [%d+offset16],%s
+Exchange-and-add a 64-bit value at the specified location.
+@item xaddw [%d+offset16],%s
+Exchange-and-add a 32-bit value at the specified location.
+@end table
diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp
index abae8b15a6..4f0e98029c 100644
--- a/gas/testsuite/gas/all/gas.exp
+++ b/gas/testsuite/gas/all/gas.exp
@@ -427,6 +427,9 @@ dg-finish
# Set $nop_type appropriately to indicate the NOP instruction mnemonic.
case $target_triplet in {
+ { "bpf-*-*" } {
+ set nop_type 6
+ }
{ "mmix-*-*" } {
set nop_type 5
}
diff --git a/gas/testsuite/gas/all/org-1.l b/gas/testsuite/gas/all/org-1.l
index 79932c0c91..e95dd18e47 100644
--- a/gas/testsuite/gas/all/org-1.l
+++ b/gas/testsuite/gas/all/org-1.l
@@ -1,2 +1,2 @@
.*: Assembler messages:
-.*:22: Error: attempt to move \.org backwards
+.*:24: Error: attempt to move \.org backwards
diff --git a/gas/testsuite/gas/all/org-1.s b/gas/testsuite/gas/all/org-1.s
index 4d7b12bff8..7dccbe3d6f 100644
--- a/gas/testsuite/gas/all/org-1.s
+++ b/gas/testsuite/gas/all/org-1.s
@@ -9,6 +9,8 @@
mov g0, g0
.elseif nop_type == 5
set $0, $0
+ .elseif nop_type == 6
+ mov %r1,%r1
.else
nop
.endif
diff --git a/gas/testsuite/gas/bpf/alu-be.d b/gas/testsuite/gas/bpf/alu-be.d
new file mode 100644
index 0000000000..9aab7fb5b4
--- /dev/null
+++ b/gas/testsuite/gas/bpf/alu-be.d
@@ -0,0 +1,59 @@
+#as: --EB
+#source: alu.s
+#objdump: -dr
+#name: eBPF ALU64 instructions, big endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 07 20 00 00 00 00 02 9a add %r2,0x29a
+ 8: 07 30 00 00 ff ff fd 66 add %r3,-666
+ 10: 07 40 00 00 7e ad be ef add %r4,0x7eadbeef
+ 18: 0f 56 00 00 00 00 00 00 add %r5,%ctx
+ 20: 17 20 00 00 00 00 02 9a sub %r2,0x29a
+ 28: 17 30 00 00 ff ff fd 66 sub %r3,-666
+ 30: 17 40 00 00 7e ad be ef sub %r4,0x7eadbeef
+ 38: 1f 56 00 00 00 00 00 00 sub %r5,%ctx
+ 40: 27 20 00 00 00 00 02 9a mul %r2,0x29a
+ 48: 27 30 00 00 ff ff fd 66 mul %r3,-666
+ 50: 27 40 00 00 7e ad be ef mul %r4,0x7eadbeef
+ 58: 2f 56 00 00 00 00 00 00 mul %r5,%ctx
+ 60: 37 20 00 00 00 00 02 9a div %r2,0x29a
+ 68: 37 30 00 00 ff ff fd 66 div %r3,-666
+ 70: 37 40 00 00 7e ad be ef div %r4,0x7eadbeef
+ 78: 3f 56 00 00 00 00 00 00 div %r5,%ctx
+ 80: 47 20 00 00 00 00 02 9a or %r2,0x29a
+ 88: 47 30 00 00 ff ff fd 66 or %r3,-666
+ 90: 47 40 00 00 7e ad be ef or %r4,0x7eadbeef
+ 98: 4f 56 00 00 00 00 00 00 or %r5,%ctx
+ a0: 57 20 00 00 00 00 02 9a and %r2,0x29a
+ a8: 57 30 00 00 ff ff fd 66 and %r3,-666
+ b0: 57 40 00 00 7e ad be ef and %r4,0x7eadbeef
+ b8: 5f 56 00 00 00 00 00 00 and %r5,%ctx
+ c0: 67 20 00 00 00 00 02 9a lsh %r2,0x29a
+ c8: 67 30 00 00 ff ff fd 66 lsh %r3,-666
+ d0: 67 40 00 00 7e ad be ef lsh %r4,0x7eadbeef
+ d8: 6f 56 00 00 00 00 00 00 lsh %r5,%ctx
+ e0: 77 20 00 00 00 00 02 9a rsh %r2,0x29a
+ e8: 77 30 00 00 ff ff fd 66 rsh %r3,-666
+ f0: 77 40 00 00 7e ad be ef rsh %r4,0x7eadbeef
+ f8: 7f 56 00 00 00 00 00 00 rsh %r5,%ctx
+ 100: 97 20 00 00 00 00 02 9a mod %r2,0x29a
+ 108: 97 30 00 00 ff ff fd 66 mod %r3,-666
+ 110: 97 40 00 00 7e ad be ef mod %r4,0x7eadbeef
+ 118: 9f 56 00 00 00 00 00 00 mod %r5,%ctx
+ 120: a7 20 00 00 00 00 02 9a xor %r2,0x29a
+ 128: a7 30 00 00 ff ff fd 66 xor %r3,-666
+ 130: a7 40 00 00 7e ad be ef xor %r4,0x7eadbeef
+ 138: af 56 00 00 00 00 00 00 xor %r5,%ctx
+ 140: b7 20 00 00 00 00 02 9a mov %r2,0x29a
+ 148: b7 30 00 00 ff ff fd 66 mov %r3,-666
+ 150: b7 40 00 00 7e ad be ef mov %r4,0x7eadbeef
+ 158: bf 56 00 00 00 00 00 00 mov %r5,%ctx
+ 160: c7 20 00 00 00 00 02 9a arsh %r2,0x29a
+ 168: c7 30 00 00 ff ff fd 66 arsh %r3,-666
+ 170: c7 40 00 00 7e ad be ef arsh %r4,0x7eadbeef
+ 178: cf 56 00 00 00 00 00 00 arsh %r5,%ctx
+ 180: 8f 20 00 00 00 00 00 00 neg %r2
diff --git a/gas/testsuite/gas/bpf/alu.d b/gas/testsuite/gas/bpf/alu.d
new file mode 100644
index 0000000000..c1ad2e0136
--- /dev/null
+++ b/gas/testsuite/gas/bpf/alu.d
@@ -0,0 +1,58 @@
+#as: --EL
+#objdump: -dr
+#name: eBPF ALU64 instructions
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 07 02 00 00 9a 02 00 00 add %r2,0x29a
+ 8: 07 03 00 00 66 fd ff ff add %r3,-666
+ 10: 07 04 00 00 ef be ad 7e add %r4,0x7eadbeef
+ 18: 0f 65 00 00 00 00 00 00 add %r5,%ctx
+ 20: 17 02 00 00 9a 02 00 00 sub %r2,0x29a
+ 28: 17 03 00 00 66 fd ff ff sub %r3,-666
+ 30: 17 04 00 00 ef be ad 7e sub %r4,0x7eadbeef
+ 38: 1f 65 00 00 00 00 00 00 sub %r5,%ctx
+ 40: 27 02 00 00 9a 02 00 00 mul %r2,0x29a
+ 48: 27 03 00 00 66 fd ff ff mul %r3,-666
+ 50: 27 04 00 00 ef be ad 7e mul %r4,0x7eadbeef
+ 58: 2f 65 00 00 00 00 00 00 mul %r5,%ctx
+ 60: 37 02 00 00 9a 02 00 00 div %r2,0x29a
+ 68: 37 03 00 00 66 fd ff ff div %r3,-666
+ 70: 37 04 00 00 ef be ad 7e div %r4,0x7eadbeef
+ 78: 3f 65 00 00 00 00 00 00 div %r5,%ctx
+ 80: 47 02 00 00 9a 02 00 00 or %r2,0x29a
+ 88: 47 03 00 00 66 fd ff ff or %r3,-666
+ 90: 47 04 00 00 ef be ad 7e or %r4,0x7eadbeef
+ 98: 4f 65 00 00 00 00 00 00 or %r5,%ctx
+ a0: 57 02 00 00 9a 02 00 00 and %r2,0x29a
+ a8: 57 03 00 00 66 fd ff ff and %r3,-666
+ b0: 57 04 00 00 ef be ad 7e and %r4,0x7eadbeef
+ b8: 5f 65 00 00 00 00 00 00 and %r5,%ctx
+ c0: 67 02 00 00 9a 02 00 00 lsh %r2,0x29a
+ c8: 67 03 00 00 66 fd ff ff lsh %r3,-666
+ d0: 67 04 00 00 ef be ad 7e lsh %r4,0x7eadbeef
+ d8: 6f 65 00 00 00 00 00 00 lsh %r5,%ctx
+ e0: 77 02 00 00 9a 02 00 00 rsh %r2,0x29a
+ e8: 77 03 00 00 66 fd ff ff rsh %r3,-666
+ f0: 77 04 00 00 ef be ad 7e rsh %r4,0x7eadbeef
+ f8: 7f 65 00 00 00 00 00 00 rsh %r5,%ctx
+ 100: 97 02 00 00 9a 02 00 00 mod %r2,0x29a
+ 108: 97 03 00 00 66 fd ff ff mod %r3,-666
+ 110: 97 04 00 00 ef be ad 7e mod %r4,0x7eadbeef
+ 118: 9f 65 00 00 00 00 00 00 mod %r5,%ctx
+ 120: a7 02 00 00 9a 02 00 00 xor %r2,0x29a
+ 128: a7 03 00 00 66 fd ff ff xor %r3,-666
+ 130: a7 04 00 00 ef be ad 7e xor %r4,0x7eadbeef
+ 138: af 65 00 00 00 00 00 00 xor %r5,%ctx
+ 140: b7 02 00 00 9a 02 00 00 mov %r2,0x29a
+ 148: b7 03 00 00 66 fd ff ff mov %r3,-666
+ 150: b7 04 00 00 ef be ad 7e mov %r4,0x7eadbeef
+ 158: bf 65 00 00 00 00 00 00 mov %r5,%ctx
+ 160: c7 02 00 00 9a 02 00 00 arsh %r2,0x29a
+ 168: c7 03 00 00 66 fd ff ff arsh %r3,-666
+ 170: c7 04 00 00 ef be ad 7e arsh %r4,0x7eadbeef
+ 178: cf 65 00 00 00 00 00 00 arsh %r5,%ctx
+ 180: 8f 02 00 00 00 00 00 00 neg %r2
diff --git a/gas/testsuite/gas/bpf/alu.s b/gas/testsuite/gas/bpf/alu.s
new file mode 100644
index 0000000000..18e60d5eae
--- /dev/null
+++ b/gas/testsuite/gas/bpf/alu.s
@@ -0,0 +1,51 @@
+# Tests for the ALU64 eBPF instructions
+ .text
+ add %r2, 666
+ add %r3, -666
+ add %r4, 0x7eadbeef
+ add %r5, %r6
+ sub %r2, 666
+ sub %r3, -666
+ sub %r4, 0x7eadbeef
+ sub %r5, %r6
+ mul %r2, 666
+ mul %r3, -666
+ mul %r4, 0x7eadbeef
+ mul %r5, %r6
+ div %r2, 666
+ div %r3, -666
+ div %r4, 0x7eadbeef
+ div %r5, %r6
+ or %r2, 666
+ or %r3, -666
+ or %r4, 0x7eadbeef
+ or %r5, %r6
+ and %r2, 666
+ and %r3, -666
+ and %r4, 0x7eadbeef
+ and %r5, %r6
+ lsh %r2, 666
+ lsh %r3, -666
+ lsh %r4, 0x7eadbeef
+ lsh %r5, %r6
+ rsh %r2, 666
+ rsh %r3, -666
+ rsh %r4, 0x7eadbeef
+ rsh %r5, %r6
+ mod %r2, 666
+ mod %r3, -666
+ mod %r4, 0x7eadbeef
+ mod %r5, %r6
+ xor %r2, 666
+ xor %r3, -666
+ xor %r4, 0x7eadbeef
+ xor %r5, %r6
+ mov %r2, 666
+ mov %r3, -666
+ mov %r4, 0x7eadbeef
+ mov %r5, %r6
+ arsh %r2, 666
+ arsh %r3, -666
+ arsh %r4, 0x7eadbeef
+ arsh %r5, %r6
+ neg %r2
diff --git a/gas/testsuite/gas/bpf/alu32-be.d b/gas/testsuite/gas/bpf/alu32-be.d
new file mode 100644
index 0000000000..8cebbbfbc9
--- /dev/null
+++ b/gas/testsuite/gas/bpf/alu32-be.d
@@ -0,0 +1,65 @@
+#as: --EB
+#source: alu32.s
+#objdump: -dr
+#name: eBPF ALU instructions, big-endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 04 20 00 00 00 00 02 9a add32 %r2,0x29a
+ 8: 04 30 00 00 ff ff fd 66 add32 %r3,-666
+ 10: 04 40 00 00 7e ad be ef add32 %r4,0x7eadbeef
+ 18: 0c 56 00 00 00 00 00 00 add32 %r5,%ctx
+ 20: 14 20 00 00 00 00 02 9a sub32 %r2,0x29a
+ 28: 14 30 00 00 ff ff fd 66 sub32 %r3,-666
+ 30: 14 40 00 00 7e ad be ef sub32 %r4,0x7eadbeef
+ 38: 1c 56 00 00 00 00 00 00 sub32 %r5,%ctx
+ 40: 24 20 00 00 00 00 02 9a mul32 %r2,0x29a
+ 48: 24 30 00 00 ff ff fd 66 mul32 %r3,-666
+ 50: 24 40 00 00 7e ad be ef mul32 %r4,0x7eadbeef
+ 58: 2c 56 00 00 00 00 00 00 mul32 %r5,%ctx
+ 60: 34 20 00 00 00 00 02 9a div32 %r2,0x29a
+ 68: 34 30 00 00 ff ff fd 66 div32 %r3,-666
+ 70: 34 40 00 00 7e ad be ef div32 %r4,0x7eadbeef
+ 78: 3c 56 00 00 00 00 00 00 div32 %r5,%ctx
+ 80: 44 20 00 00 00 00 02 9a or32 %r2,0x29a
+ 88: 44 30 00 00 ff ff fd 66 or32 %r3,-666
+ 90: 44 40 00 00 7e ad be ef or32 %r4,0x7eadbeef
+ 98: 4c 56 00 00 00 00 00 00 or32 %r5,%ctx
+ a0: 54 20 00 00 00 00 02 9a and32 %r2,0x29a
+ a8: 54 30 00 00 ff ff fd 66 and32 %r3,-666
+ b0: 54 40 00 00 7e ad be ef and32 %r4,0x7eadbeef
+ b8: 5c 56 00 00 00 00 00 00 and32 %r5,%ctx
+ c0: 64 20 00 00 00 00 02 9a lsh32 %r2,0x29a
+ c8: 64 30 00 00 ff ff fd 66 lsh32 %r3,-666
+ d0: 64 40 00 00 7e ad be ef lsh32 %r4,0x7eadbeef
+ d8: 6c 56 00 00 00 00 00 00 lsh32 %r5,%ctx
+ e0: 74 20 00 00 00 00 02 9a rsh32 %r2,0x29a
+ e8: 74 30 00 00 ff ff fd 66 rsh32 %r3,-666
+ f0: 74 40 00 00 7e ad be ef rsh32 %r4,0x7eadbeef
+ f8: 7c 56 00 00 00 00 00 00 rsh32 %r5,%ctx
+ 100: 94 20 00 00 00 00 02 9a mod32 %r2,0x29a
+ 108: 94 30 00 00 ff ff fd 66 mod32 %r3,-666
+ 110: 94 40 00 00 7e ad be ef mod32 %r4,0x7eadbeef
+ 118: 9c 56 00 00 00 00 00 00 mod32 %r5,%ctx
+ 120: a4 20 00 00 00 00 02 9a xor32 %r2,0x29a
+ 128: a4 30 00 00 ff ff fd 66 xor32 %r3,-666
+ 130: a4 40 00 00 7e ad be ef xor32 %r4,0x7eadbeef
+ 138: ac 56 00 00 00 00 00 00 xor32 %r5,%ctx
+ 140: b4 20 00 00 00 00 02 9a mov32 %r2,0x29a
+ 148: b4 30 00 00 ff ff fd 66 mov32 %r3,-666
+ 150: b4 40 00 00 7e ad be ef mov32 %r4,0x7eadbeef
+ 158: bc 56 00 00 00 00 00 00 mov32 %r5,%ctx
+ 160: c4 20 00 00 00 00 02 9a arsh32 %r2,0x29a
+ 168: c4 30 00 00 ff ff fd 66 arsh32 %r3,-666
+ 170: c4 40 00 00 7e ad be ef arsh32 %r4,0x7eadbeef
+ 178: cc 56 00 00 00 00 00 00 arsh32 %r5,%ctx
+ 180: 8c 20 00 00 00 00 00 00 neg32 %r2
+ 188: d4 90 00 00 00 00 00 10 endle %r9,16
+ 190: d4 80 00 00 00 00 00 20 endle %r8,32
+ 198: d4 70 00 00 00 00 00 40 endle %r7,64
+ 1a0: dc 60 00 00 00 00 00 10 endbe %ctx,16
+ 1a8: dc 50 00 00 00 00 00 20 endbe %r5,32
+ 1b0: dc 40 00 00 00 00 00 40 endbe %r4,64
diff --git a/gas/testsuite/gas/bpf/alu32.d b/gas/testsuite/gas/bpf/alu32.d
new file mode 100644
index 0000000000..655a71b14b
--- /dev/null
+++ b/gas/testsuite/gas/bpf/alu32.d
@@ -0,0 +1,64 @@
+#as: --EL
+#objdump: -dr
+#name: eBPF ALU instructions
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 04 02 00 00 9a 02 00 00 add32 %r2,0x29a
+ 8: 04 03 00 00 66 fd ff ff add32 %r3,-666
+ 10: 04 04 00 00 ef be ad 7e add32 %r4,0x7eadbeef
+ 18: 0c 65 00 00 00 00 00 00 add32 %r5,%ctx
+ 20: 14 02 00 00 9a 02 00 00 sub32 %r2,0x29a
+ 28: 14 03 00 00 66 fd ff ff sub32 %r3,-666
+ 30: 14 04 00 00 ef be ad 7e sub32 %r4,0x7eadbeef
+ 38: 1c 65 00 00 00 00 00 00 sub32 %r5,%ctx
+ 40: 24 02 00 00 9a 02 00 00 mul32 %r2,0x29a
+ 48: 24 03 00 00 66 fd ff ff mul32 %r3,-666
+ 50: 24 04 00 00 ef be ad 7e mul32 %r4,0x7eadbeef
+ 58: 2c 65 00 00 00 00 00 00 mul32 %r5,%ctx
+ 60: 34 02 00 00 9a 02 00 00 div32 %r2,0x29a
+ 68: 34 03 00 00 66 fd ff ff div32 %r3,-666
+ 70: 34 04 00 00 ef be ad 7e div32 %r4,0x7eadbeef
+ 78: 3c 65 00 00 00 00 00 00 div32 %r5,%ctx
+ 80: 44 02 00 00 9a 02 00 00 or32 %r2,0x29a
+ 88: 44 03 00 00 66 fd ff ff or32 %r3,-666
+ 90: 44 04 00 00 ef be ad 7e or32 %r4,0x7eadbeef
+ 98: 4c 65 00 00 00 00 00 00 or32 %r5,%ctx
+ a0: 54 02 00 00 9a 02 00 00 and32 %r2,0x29a
+ a8: 54 03 00 00 66 fd ff ff and32 %r3,-666
+ b0: 54 04 00 00 ef be ad 7e and32 %r4,0x7eadbeef
+ b8: 5c 65 00 00 00 00 00 00 and32 %r5,%ctx
+ c0: 64 02 00 00 9a 02 00 00 lsh32 %r2,0x29a
+ c8: 64 03 00 00 66 fd ff ff lsh32 %r3,-666
+ d0: 64 04 00 00 ef be ad 7e lsh32 %r4,0x7eadbeef
+ d8: 6c 65 00 00 00 00 00 00 lsh32 %r5,%ctx
+ e0: 74 02 00 00 9a 02 00 00 rsh32 %r2,0x29a
+ e8: 74 03 00 00 66 fd ff ff rsh32 %r3,-666
+ f0: 74 04 00 00 ef be ad 7e rsh32 %r4,0x7eadbeef
+ f8: 7c 65 00 00 00 00 00 00 rsh32 %r5,%ctx
+ 100: 94 02 00 00 9a 02 00 00 mod32 %r2,0x29a
+ 108: 94 03 00 00 66 fd ff ff mod32 %r3,-666
+ 110: 94 04 00 00 ef be ad 7e mod32 %r4,0x7eadbeef
+ 118: 9c 65 00 00 00 00 00 00 mod32 %r5,%ctx
+ 120: a4 02 00 00 9a 02 00 00 xor32 %r2,0x29a
+ 128: a4 03 00 00 66 fd ff ff xor32 %r3,-666
+ 130: a4 04 00 00 ef be ad 7e xor32 %r4,0x7eadbeef
+ 138: ac 65 00 00 00 00 00 00 xor32 %r5,%ctx
+ 140: b4 02 00 00 9a 02 00 00 mov32 %r2,0x29a
+ 148: b4 03 00 00 66 fd ff ff mov32 %r3,-666
+ 150: b4 04 00 00 ef be ad 7e mov32 %r4,0x7eadbeef
+ 158: bc 65 00 00 00 00 00 00 mov32 %r5,%ctx
+ 160: c4 02 00 00 9a 02 00 00 arsh32 %r2,0x29a
+ 168: c4 03 00 00 66 fd ff ff arsh32 %r3,-666
+ 170: c4 04 00 00 ef be ad 7e arsh32 %r4,0x7eadbeef
+ 178: cc 65 00 00 00 00 00 00 arsh32 %r5,%ctx
+ 180: 8c 02 00 00 00 00 00 00 neg32 %r2
+ 188: d4 09 00 00 10 00 00 00 endle %r9,16
+ 190: d4 08 00 00 20 00 00 00 endle %r8,32
+ 198: d4 07 00 00 40 00 00 00 endle %r7,64
+ 1a0: dc 06 00 00 10 00 00 00 endbe %ctx,16
+ 1a8: dc 05 00 00 20 00 00 00 endbe %r5,32
+ 1b0: dc 04 00 00 40 00 00 00 endbe %r4,64
diff --git a/gas/testsuite/gas/bpf/alu32.s b/gas/testsuite/gas/bpf/alu32.s
new file mode 100644
index 0000000000..7b6f014e8b
--- /dev/null
+++ b/gas/testsuite/gas/bpf/alu32.s
@@ -0,0 +1,57 @@
+# Tests for the ALU eBPF instructions
+ .text
+ add32 %r2, 666
+ add32 %r3, -666
+ add32 %r4, 0x7eadbeef
+ add32 %r5, %r6
+ sub32 %r2, 666
+ sub32 %r3, -666
+ sub32 %r4, 0x7eadbeef
+ sub32 %r5, %r6
+ mul32 %r2, 666
+ mul32 %r3, -666
+ mul32 %r4, 0x7eadbeef
+ mul32 %r5, %r6
+ div32 %r2, 666
+ div32 %r3, -666
+ div32 %r4, 0x7eadbeef
+ div32 %r5, %r6
+ or32 %r2, 666
+ or32 %r3, -666
+ or32 %r4, 0x7eadbeef
+ or32 %r5, %r6
+ and32 %r2, 666
+ and32 %r3, -666
+ and32 %r4, 0x7eadbeef
+ and32 %r5, %r6
+ lsh32 %r2, 666
+ lsh32 %r3, -666
+ lsh32 %r4, 0x7eadbeef
+ lsh32 %r5, %r6
+ rsh32 %r2, 666
+ rsh32 %r3, -666
+ rsh32 %r4, 0x7eadbeef
+ rsh32 %r5, %r6
+ mod32 %r2, 666
+ mod32 %r3, -666
+ mod32 %r4, 0x7eadbeef
+ mod32 %r5, %r6
+ xor32 %r2, 666
+ xor32 %r3, -666
+ xor32 %r4, 0x7eadbeef
+ xor32 %r5, %r6
+ mov32 %r2, 666
+ mov32 %r3, -666
+ mov32 %r4, 0x7eadbeef
+ mov32 %r5, %r6
+ arsh32 %r2, 666
+ arsh32 %r3, -666
+ arsh32 %r4, 0x7eadbeef
+ arsh32 %r5, %r6
+ neg32 %r2
+ endle %r9,16
+ endle %r8,32
+ endle %r7,64
+ endbe %r6,16
+ endbe %r5,32
+ endbe %r4,64
diff --git a/gas/testsuite/gas/bpf/atomic-be.d b/gas/testsuite/gas/bpf/atomic-be.d
new file mode 100644
index 0000000000..04161e08ac
--- /dev/null
+++ b/gas/testsuite/gas/bpf/atomic-be.d
@@ -0,0 +1,12 @@
+#as: --EB
+#source: atomic.s
+#objdump: -dr
+#name: eBPF atomic instructions, big endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: db 12 1e ef 00 00 00 00 xadddw \[%r1\+0x1eef\],%r2
+ 8: c3 12 1e ef 00 00 00 00 xaddw \[%r1\+0x1eef\],%r2
diff --git a/gas/testsuite/gas/bpf/atomic.d b/gas/testsuite/gas/bpf/atomic.d
new file mode 100644
index 0000000000..1c83cb582a
--- /dev/null
+++ b/gas/testsuite/gas/bpf/atomic.d
@@ -0,0 +1,11 @@
+#as: --EL
+#objdump: -dr
+#name: eBPF atomic instructions
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: db 21 ef 1e 00 00 00 00 xadddw \[%r1\+0x1eef\],%r2
+ 8: c3 21 ef 1e 00 00 00 00 xaddw \[%r1\+0x1eef\],%r2
diff --git a/gas/testsuite/gas/bpf/atomic.s b/gas/testsuite/gas/bpf/atomic.s
new file mode 100644
index 0000000000..0119b24c8b
--- /dev/null
+++ b/gas/testsuite/gas/bpf/atomic.s
@@ -0,0 +1,5 @@
+ # Test for eBPF ADDW and ADDDW instructions
+ .text
+ xadddw [%r1+0x1eef], %r2
+ xaddw [%r1+0x1eef], %r2
+
diff --git a/gas/testsuite/gas/bpf/bpf.exp b/gas/testsuite/gas/bpf/bpf.exp
new file mode 100644
index 0000000000..e228fd4d1b
--- /dev/null
+++ b/gas/testsuite/gas/bpf/bpf.exp
@@ -0,0 +1,38 @@
+# GAS testsuite for the Linux eBPF -*- Tcl -*-
+#
+# Copyright (C) 2019 Free Software Foundation, Inc.
+# Contributed by Oracle, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+if {[istarget bpf*-*-*]} {
+ run_dump_test lddw
+ run_dump_test alu
+ run_dump_test alu32
+ run_dump_test mem
+ run_dump_test jump
+ run_dump_test call
+ run_dump_test exit
+ run_dump_test atomic
+
+ run_dump_test lddw-be
+ run_dump_test alu-be
+ run_dump_test alu32-be
+ run_dump_test mem-be
+ run_dump_test jump-be
+ run_dump_test call-be
+ run_dump_test exit-be
+ run_dump_test atomic-be
+}
diff --git a/gas/testsuite/gas/bpf/call-be.d b/gas/testsuite/gas/bpf/call-be.d
new file mode 100644
index 0000000000..bd3b50f36b
--- /dev/null
+++ b/gas/testsuite/gas/bpf/call-be.d
@@ -0,0 +1,19 @@
+#as: --EB
+#source: call.s
+#objdump: -dr
+#name: eBPF CALL instruction, big endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+ 0: 85 00 00 00 00 00 00 00 call 0
+ 8: 85 00 00 00 00 00 00 01 call 1
+ 10: 85 00 00 00 ff ff ff fe call -2
+ 18: 85 00 00 00 00 00 00 0a call 10
+ 20: 85 01 00 00 00 00 00 00 call 0
+[0-9a-f]+ <foo>:
+ 28: 85 01 00 00 ff ff ff ff call -1
+ 30: 85 01 00 00 ff ff ff fe call -2
+ 38: 85 01 00 00 ff ff ff fd call -3
\ No newline at end of file
diff --git a/gas/testsuite/gas/bpf/call.d b/gas/testsuite/gas/bpf/call.d
new file mode 100644
index 0000000000..daefbd0802
--- /dev/null
+++ b/gas/testsuite/gas/bpf/call.d
@@ -0,0 +1,18 @@
+#as: --EL
+#objdump: -dr
+#name: eBPF CALL instruction
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+ 0: 85 00 00 00 00 00 00 00 call 0
+ 8: 85 00 00 00 01 00 00 00 call 1
+ 10: 85 00 00 00 fe ff ff ff call -2
+ 18: 85 00 00 00 0a 00 00 00 call 10
+ 20: 85 10 00 00 00 00 00 00 call 0
+[0-9a-f]+ <foo>:
+ 28: 85 10 00 00 ff ff ff ff call -1
+ 30: 85 10 00 00 fe ff ff ff call -2
+ 38: 85 10 00 00 fd ff ff ff call -3
diff --git a/gas/testsuite/gas/bpf/call.s b/gas/testsuite/gas/bpf/call.s
new file mode 100644
index 0000000000..45c8ca5f80
--- /dev/null
+++ b/gas/testsuite/gas/bpf/call.s
@@ -0,0 +1,11 @@
+ # eBPF tests for the CALL instruction
+
+ .text
+ call 0
+ call 1
+ call -2
+ call 0xa
+ call foo
+foo: call foo
+ call foo
+ call foo
diff --git a/gas/testsuite/gas/bpf/exit-be.d b/gas/testsuite/gas/bpf/exit-be.d
new file mode 100644
index 0000000000..d3b88c7373
--- /dev/null
+++ b/gas/testsuite/gas/bpf/exit-be.d
@@ -0,0 +1,11 @@
+#as: --EB
+#source: exit.s
+#objdump: -dr
+#name: eBPF EXIT instruction, big endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 95 00 00 00 00 00 00 00 exit
\ No newline at end of file
diff --git a/gas/testsuite/gas/bpf/exit.d b/gas/testsuite/gas/bpf/exit.d
new file mode 100644
index 0000000000..87bc91b2d2
--- /dev/null
+++ b/gas/testsuite/gas/bpf/exit.d
@@ -0,0 +1,10 @@
+#as: --EL
+#objdump: -dr
+#name: eBPF EXIT instruction
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 95 00 00 00 00 00 00 00 exit
\ No newline at end of file
diff --git a/gas/testsuite/gas/bpf/exit.s b/gas/testsuite/gas/bpf/exit.s
new file mode 100644
index 0000000000..5a4c4f1963
--- /dev/null
+++ b/gas/testsuite/gas/bpf/exit.s
@@ -0,0 +1,2 @@
+ .text
+ exit
diff --git a/gas/testsuite/gas/bpf/jump-be.d b/gas/testsuite/gas/bpf/jump-be.d
new file mode 100644
index 0000000000..65632e0813
--- /dev/null
+++ b/gas/testsuite/gas/bpf/jump-be.d
@@ -0,0 +1,32 @@
+#as: --EB
+#source: jump.s
+#objdump: -dr
+#name: eBPF JUMP instructions, big endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 05 00 00 03 00 00 00 00 ja 3
+ 8: 0f 11 00 00 00 00 00 00 add %r1,%r1
+ 10: 15 30 00 01 00 00 00 03 jeq %r3,3,1
+ 18: 1d 34 00 00 00 00 00 00 jeq %r3,%r4,0
+ 20: 35 30 ff fd 00 00 00 03 jge %r3,3,-3
+ 28: 3d 34 ff fc 00 00 00 00 jge %r3,%r4,-4
+ 30: a5 30 00 01 00 00 00 03 jlt %r3,3,1
+ 38: ad 34 00 00 00 00 00 00 jlt %r3,%r4,0
+ 40: b5 30 00 01 00 00 00 03 jle %r3,3,1
+ 48: bd 34 00 00 00 00 00 00 jle %r3,%r4,0
+ 50: 45 30 00 01 00 00 00 03 jset %r3,3,1
+ 58: 4d 34 00 00 00 00 00 00 jset %r3,%r4,0
+ 60: 55 30 00 01 00 00 00 03 jne %r3,3,1
+ 68: 5d 34 00 00 00 00 00 00 jne %r3,%r4,0
+ 70: 65 30 00 01 00 00 00 03 jsgt %r3,3,1
+ 78: 6d 34 00 00 00 00 00 00 jsgt %r3,%r4,0
+ 80: 75 30 00 01 00 00 00 03 jsge %r3,3,1
+ 88: 7d 34 00 00 00 00 00 00 jsge %r3,%r4,0
+ 90: c5 30 00 01 00 00 00 03 jslt %r3,3,1
+ 98: cd 34 00 00 00 00 00 00 jslt %r3,%r4,0
+ a0: d5 30 00 01 00 00 00 03 jsle %r3,3,1
+ a8: dd 34 00 00 00 00 00 00 jsle %r3,%r4,0
diff --git a/gas/testsuite/gas/bpf/jump.d b/gas/testsuite/gas/bpf/jump.d
new file mode 100644
index 0000000000..ca600f602b
--- /dev/null
+++ b/gas/testsuite/gas/bpf/jump.d
@@ -0,0 +1,31 @@
+#as: --EL
+#objdump: -dr
+#name: eBPF JUMP instructions
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 05 00 03 00 00 00 00 00 ja 3
+ 8: 0f 11 00 00 00 00 00 00 add %r1,%r1
+ 10: 15 03 01 00 03 00 00 00 jeq %r3,3,1
+ 18: 1d 43 00 00 00 00 00 00 jeq %r3,%r4,0
+ 20: 35 03 fd ff 03 00 00 00 jge %r3,3,-3
+ 28: 3d 43 fc ff 00 00 00 00 jge %r3,%r4,-4
+ 30: a5 03 01 00 03 00 00 00 jlt %r3,3,1
+ 38: ad 43 00 00 00 00 00 00 jlt %r3,%r4,0
+ 40: b5 03 01 00 03 00 00 00 jle %r3,3,1
+ 48: bd 43 00 00 00 00 00 00 jle %r3,%r4,0
+ 50: 45 03 01 00 03 00 00 00 jset %r3,3,1
+ 58: 4d 43 00 00 00 00 00 00 jset %r3,%r4,0
+ 60: 55 03 01 00 03 00 00 00 jne %r3,3,1
+ 68: 5d 43 00 00 00 00 00 00 jne %r3,%r4,0
+ 70: 65 03 01 00 03 00 00 00 jsgt %r3,3,1
+ 78: 6d 43 00 00 00 00 00 00 jsgt %r3,%r4,0
+ 80: 75 03 01 00 03 00 00 00 jsge %r3,3,1
+ 88: 7d 43 00 00 00 00 00 00 jsge %r3,%r4,0
+ 90: c5 03 01 00 03 00 00 00 jslt %r3,3,1
+ 98: cd 43 00 00 00 00 00 00 jslt %r3,%r4,0
+ a0: d5 03 01 00 03 00 00 00 jsle %r3,3,1
+ a8: dd 43 00 00 00 00 00 00 jsle %r3,%r4,0
\ No newline at end of file
diff --git a/gas/testsuite/gas/bpf/jump.s b/gas/testsuite/gas/bpf/jump.s
new file mode 100644
index 0000000000..aae4295e16
--- /dev/null
+++ b/gas/testsuite/gas/bpf/jump.s
@@ -0,0 +1,25 @@
+# Tests for the JUMP instructions
+ .text
+ ja 2f
+ add %r1,%r1
+1: jeq %r3,3,2f
+ jeq %r3,%r4,2f
+2: jge %r3,3,1b
+ jge %r3,%r4,1b
+1: jlt %r3,3,1f
+ jlt %r3,%r4,1f
+1: jle %r3,3,1f
+ jle %r3,%r4,1f
+1: jset %r3,3,1f
+ jset %r3,%r4,1f
+1: jne %r3,3,1f
+ jne %r3,%r4,1f
+1: jsgt %r3,3,1f
+ jsgt %r3,%r4,1f
+1: jsge %r3,3,1f
+ jsge %r3,%r4,1f
+1: jslt %r3,3,1f
+ jslt %r3,%r4,1f
+1: jsle %r3,3,1f
+ jsle %r3,%r4,1f
+1:
diff --git a/gas/testsuite/gas/bpf/lddw-be.d b/gas/testsuite/gas/bpf/lddw-be.d
new file mode 100644
index 0000000000..1d722fa569
--- /dev/null
+++ b/gas/testsuite/gas/bpf/lddw-be.d
@@ -0,0 +1,18 @@
+#as: --EB
+#source: lddw.s
+#objdump: -dr
+#name: eBPF LDDW, big-endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 18 30 00 00 00 00 00 01 lddw %r3,1
+ 8: 00 00 00 00 00 00 00 00
+ 10: 18 40 00 00 de ad be ef lddw %r4,0xdeadbeef
+ 18: 00 00 00 00 00 00 00 00
+ 20: 18 50 00 00 55 66 77 88 lddw %r5,0x1122334455667788
+ 28: 00 00 00 00 11 22 33 44
+ 30: 18 60 00 00 ff ff ff fe lddw %ctx,-2
+ 38: 00 00 00 00 ff ff ff ff
diff --git a/gas/testsuite/gas/bpf/lddw.d b/gas/testsuite/gas/bpf/lddw.d
new file mode 100644
index 0000000000..2ab4f73ac5
--- /dev/null
+++ b/gas/testsuite/gas/bpf/lddw.d
@@ -0,0 +1,17 @@
+#as: --EL
+#objdump: -dr
+#name: eBPF LDDW
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 18 03 00 00 01 00 00 00 lddw %r3,1
+ 8: 00 00 00 00 00 00 00 00
+ 10: 18 04 00 00 ef be ad de lddw %r4,0xdeadbeef
+ 18: 00 00 00 00 00 00 00 00
+ 20: 18 05 00 00 88 77 66 55 lddw %r5,0x1122334455667788
+ 28: 00 00 00 00 44 33 22 11
+ 30: 18 06 00 00 fe ff ff ff lddw %ctx,-2
+ 38: 00 00 00 00 ff ff ff ff
diff --git a/gas/testsuite/gas/bpf/lddw.s b/gas/testsuite/gas/bpf/lddw.s
new file mode 100644
index 0000000000..9e65e4a607
--- /dev/null
+++ b/gas/testsuite/gas/bpf/lddw.s
@@ -0,0 +1,6 @@
+# Tests for the LDDW instruction
+ .text
+ lddw %r3, 1
+ lddw %r4, 0xdeadbeef
+ lddw %r5, 0x1122334455667788
+ lddw %r6, -2
diff --git a/gas/testsuite/gas/bpf/mem-be.d b/gas/testsuite/gas/bpf/mem-be.d
new file mode 100644
index 0000000000..70d8806bc5
--- /dev/null
+++ b/gas/testsuite/gas/bpf/mem-be.d
@@ -0,0 +1,30 @@
+#as: --EB
+#source: mem.s
+#objdump: -dr
+#name: eBPF MEM instructions, modulus lddw, big endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 20 23 00 00 00 00 be ef ldabsw %r2,%r3,0xbeef
+ 8: 28 45 00 00 00 00 be ef ldabsh %r4,%r5,0xbeef
+ 10: 30 67 00 00 00 00 be ef ldabsb %ctx,%r7,0xbeef
+ 18: 38 89 00 00 00 00 be ef ldabsdw %r8,%r9,0xbeef
+ 20: 40 23 00 00 00 00 be ef ldindw %r2,%r3,0xbeef
+ 28: 48 45 00 00 00 00 be ef ldindh %r4,%r5,0xbeef
+ 30: 50 67 00 00 00 00 be ef ldindb %ctx,%r7,0xbeef
+ 38: 58 89 00 00 00 00 be ef ldinddw %r8,%r9,0xbeef
+ 40: 61 21 7e ef 00 00 00 00 ldxw %r2,\[%r1\+0x7eef\]
+ 48: 69 21 7e ef 00 00 00 00 ldxh %r2,\[%r1\+0x7eef\]
+ 50: 71 21 7e ef 00 00 00 00 ldxb %r2,\[%r1\+0x7eef\]
+ 58: 79 21 ff fe 00 00 00 00 ldxdw %r2,\[%r1\+-2\]
+ 60: 63 12 7e ef 00 00 00 00 stxw \[%r1\+0x7eef\],%r2
+ 68: 6b 12 7e ef 00 00 00 00 stxh \[%r1\+0x7eef\],%r2
+ 70: 73 12 7e ef 00 00 00 00 stxb \[%r1\+0x7eef\],%r2
+ 78: 7b 12 ff fe 00 00 00 00 stxdw \[%r1\+-2\],%r2
+ 80: 72 10 7e ef 11 22 33 44 stb \[%r1\+0x7eef\],0x11223344
+ 88: 6a 10 7e ef 11 22 33 44 sth \[%r1\+0x7eef\],0x11223344
+ 90: 62 10 7e ef 11 22 33 44 stw \[%r1\+0x7eef\],0x11223344
+ 98: 7a 10 ff fe 11 22 33 44 stdw \[%r1\+-2\],0x11223344
\ No newline at end of file
diff --git a/gas/testsuite/gas/bpf/mem.d b/gas/testsuite/gas/bpf/mem.d
new file mode 100644
index 0000000000..53492767fd
--- /dev/null
+++ b/gas/testsuite/gas/bpf/mem.d
@@ -0,0 +1,29 @@
+#as: --EL
+#objdump: -dr
+#name: eBPF MEM instructions, modulus lddw
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 20 32 00 00 ef be 00 00 ldabsw %r2,%r3,0xbeef
+ 8: 28 54 00 00 ef be 00 00 ldabsh %r4,%r5,0xbeef
+ 10: 30 76 00 00 ef be 00 00 ldabsb %ctx,%r7,0xbeef
+ 18: 38 98 00 00 ef be 00 00 ldabsdw %r8,%r9,0xbeef
+ 20: 40 32 00 00 ef be 00 00 ldindw %r2,%r3,0xbeef
+ 28: 48 54 00 00 ef be 00 00 ldindh %r4,%r5,0xbeef
+ 30: 50 76 00 00 ef be 00 00 ldindb %ctx,%r7,0xbeef
+ 38: 58 98 00 00 ef be 00 00 ldinddw %r8,%r9,0xbeef
+ 40: 61 12 ef 7e 00 00 00 00 ldxw %r2,\[%r1\+0x7eef\]
+ 48: 69 12 ef 7e 00 00 00 00 ldxh %r2,\[%r1\+0x7eef\]
+ 50: 71 12 ef 7e 00 00 00 00 ldxb %r2,\[%r1\+0x7eef\]
+ 58: 79 12 fe ff 00 00 00 00 ldxdw %r2,\[%r1\+-2\]
+ 60: 63 21 ef 7e 00 00 00 00 stxw \[%r1\+0x7eef\],%r2
+ 68: 6b 21 ef 7e 00 00 00 00 stxh \[%r1\+0x7eef\],%r2
+ 70: 73 21 ef 7e 00 00 00 00 stxb \[%r1\+0x7eef\],%r2
+ 78: 7b 21 fe ff 00 00 00 00 stxdw \[%r1\+-2\],%r2
+ 80: 72 01 ef 7e 44 33 22 11 stb \[%r1\+0x7eef\],0x11223344
+ 88: 6a 01 ef 7e 44 33 22 11 sth \[%r1\+0x7eef\],0x11223344
+ 90: 62 01 ef 7e 44 33 22 11 stw \[%r1\+0x7eef\],0x11223344
+ 98: 7a 01 fe ff 44 33 22 11 stdw \[%r1\+-2\],0x11223344
diff --git a/gas/testsuite/gas/bpf/mem.s b/gas/testsuite/gas/bpf/mem.s
new file mode 100644
index 0000000000..cc5329c4ca
--- /dev/null
+++ b/gas/testsuite/gas/bpf/mem.s
@@ -0,0 +1,24 @@
+# eBPF tests for MEM instructions, modulus lddw.
+
+ .text
+
+ ldabsw %r2, %r3, 0xbeef
+ ldabsh %r4, %r5, 0xbeef
+ ldabsb %r6, %r7, 0xbeef
+ ldabsdw %r8, %r9, 0xbeef
+ ldindw %r2, %r3, 0xbeef
+ ldindh %r4, %r5, 0xbeef
+ ldindb %r6, %r7, 0xbeef
+ ldinddw %r8, %r9, 0xbeef
+ ldxw %r2, [%r1+0x7eef]
+ ldxh %r2, [%r1+0x7eef]
+ ldxb %r2, [%r1+0x7eef]
+ ldxdw %r2, [%r1+-2]
+ stxw [%r1+0x7eef], %r2
+ stxh [%r1+0x7eef], %r2
+ stxb [%r1+0x7eef], %r2
+ stxdw [%r1+-2], %r2
+ stb [%r1+0x7eef], 0x11223344
+ sth [%r1+0x7eef], 0x11223344
+ stw [%r1+0x7eef], 0x11223344
+ stdw [%r1+-2], 0x11223344
--
2.11.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH V2 9/9] binutils: add myself as the maintainer for BPF
2019-05-22 15:26 [PATCH V2 0/9] eBPF support for GNU binutils Jose E. Marchesi
@ 2019-05-22 15:24 ` Jose E. Marchesi
2019-05-22 15:24 ` [PATCH V2 5/9] opcodes: add support for eBPF Jose E. Marchesi
` (9 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Jose E. Marchesi @ 2019-05-22 15:24 UTC (permalink / raw)
To: binutils
binutils/ChangeLog:
2019-05-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* MAINTAINERS: Add myself as the maintainer for BPF.
---
binutils/ChangeLog | 4 ++++
binutils/MAINTAINERS | 1 +
2 files changed, 5 insertions(+)
diff --git a/binutils/MAINTAINERS b/binutils/MAINTAINERS
index b057435ef6..0094ba4150 100644
--- a/binutils/MAINTAINERS
+++ b/binutils/MAINTAINERS
@@ -69,6 +69,7 @@ responsibility among the other maintainers.
AVR Marek Michalkiewicz <marekm@amelek.gda.pl>
BFIN Jie Zhang <jzhang918@gmail.com>
BFIN Mike Frysinger <vapier@gentoo.org>
+ BPF Jose E. Marchesi <jose.marchesi@oracle.com>
BUILD SYSTEM Daniel Jacobowitz <drow@false.org>
CR16 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
CRIS Hans-Peter Nilsson <hp@axis.com>
--
2.11.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH V2 2/9] include: add elf/bpf.h
2019-05-22 15:26 [PATCH V2 0/9] eBPF support for GNU binutils Jose E. Marchesi
2019-05-22 15:24 ` [PATCH V2 9/9] binutils: add myself as the maintainer for BPF Jose E. Marchesi
2019-05-22 15:24 ` [PATCH V2 5/9] opcodes: add support for eBPF Jose E. Marchesi
@ 2019-05-22 15:24 ` Jose E. Marchesi
2019-05-22 15:24 ` [PATCH V2 3/9] bfd: add support for eBPF Jose E. Marchesi
` (7 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Jose E. Marchesi @ 2019-05-22 15:24 UTC (permalink / raw)
To: binutils
This patch adds a header file with BPF-specific ELF definitions. In
particular, the architecture relocations.
include/ChangeLog:
2019-05-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* elf/bpf.h: New file.
---
include/ChangeLog | 4 ++++
include/elf/bpf.h | 45 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 49 insertions(+)
create mode 100644 include/elf/bpf.h
diff --git a/include/elf/bpf.h b/include/elf/bpf.h
new file mode 100644
index 0000000000..a7165cd8ae
--- /dev/null
+++ b/include/elf/bpf.h
@@ -0,0 +1,45 @@
+/* Linux eBPF support for BFD.
+ Copyright (C) 2019 Free Software Foundation, Inc.
+
+ Contributed by Oracle, Inc.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+#ifndef _ELF_BPF_H
+#define _ELF_BPF_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations. */
+START_RELOC_NUMBERS (elf_bpf_reloc_type)
+ RELOC_NUMBER (R_BPF_NONE, 0)
+ RELOC_NUMBER (R_BPF_INSN_64, 1)
+ RELOC_NUMBER (R_BPF_INSN_32, 2)
+ RELOC_NUMBER (R_BPF_INSN_16, 3)
+ RELOC_NUMBER (R_BPF_INSN_DISP16, 4)
+ RELOC_NUMBER (R_BPF_DATA_8_PCREL, 5)
+ RELOC_NUMBER (R_BPF_DATA_16_PCREL, 6)
+ RELOC_NUMBER (R_BPF_DATA_32_PCREL, 7)
+ RELOC_NUMBER (R_BPF_DATA_8, 8)
+ RELOC_NUMBER (R_BPF_DATA_16, 9)
+ RELOC_NUMBER (R_BPF_INSN_DISP32, 10)
+ RELOC_NUMBER (R_BPF_DATA_32, 11)
+ RELOC_NUMBER (R_BPF_DATA_64, 12)
+ RELOC_NUMBER (R_BPF_DATA_64_PCREL, 13)
+END_RELOC_NUMBERS (R_BPF_max)
+
+#endif /* _ELF_BPF_H */
--
2.11.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH V2 0/9] eBPF support for GNU binutils
@ 2019-05-22 15:26 Jose E. Marchesi
2019-05-22 15:24 ` [PATCH V2 9/9] binutils: add myself as the maintainer for BPF Jose E. Marchesi
` (10 more replies)
0 siblings, 11 replies; 16+ messages in thread
From: Jose E. Marchesi @ 2019-05-22 15:26 UTC (permalink / raw)
To: binutils
[Changes from V1:
- Rebased to today's master.
- Add missing (C)s to cpu/bpf.cpu and cpu/bpf.opc.
- Use the right version of automake to generate gas/doc/Makefile.in.
- Remove an spurious comment from gas/config/tc-bpf.c.]
Hi people!
This patch series introduces support for eBPF, which is a virtual
machine that resides in the Linux kernel. Initially intended for
user-level packet capture and filtering, eBPF is nowadays generalized
to serve as a general-purpose infrastructure also for non-networking
purposes.
The first patch is preparatory, and adds support to config.guess to
recognize bpf-*-* triplets. This will be submitted as a patch to the
`config' project as soon as this series gets upstreamed.
The second and third patches add support for an ELF64 based eBPF
target to BFD, in both little-endian and big-endian vectors.
The fourth patch adds a CGEN cpu description for eBPF, plus support
code. This description covers the full eBPF ISA. Due to the 64-bit
instruction fields used in some instructions, we needed to fix a
bug/limitation in CGEN impacting 32-bit hosts. The fix is in a patch
submitted to CGEN last week, that is still waiting for review:
http://www.sourceware.org/ml/cgen/2019-q2/msg00008.html None of the
existing CGEN ports in binutils are impacted by that patch: the code
generated for these remains exactly the same.
The fifth patch adds opcodes and disassembler support for eBPF, based
on the CGEN description.
The sixth patch adds a GAS port, including a testsuite and manual
updates. By default the assembler generates objects using the same
endianness than the host. This can be overrided by the usual -EB and
-EB command-line options.
Support for linking eBPF ELF files with ld/bfd is provided in the
seventh patch. A couple of simple tests are included.
The eighth patch adds support for eBPF to readelf, and makes a little
adjustment in the `nm' testsuite to not fail in bpf-*-* targets.
Finally, the last patch adds myself as the maintainer of the BPF
target. We are committing to maintain this port.
Future work on the binutils port:
* Support for semantic actions in bpf.cpu, and support code for a
simulator in sim/.
* Support for ld.gold.
Next stop is GCC. An eBPF backend is on the works. We plan to
upstream it before September.
Regressions tested in all targets.
Regressions tested with --enable-targets=all
Tested in 64-bit x86_64 host.
Tested in 32-bit x86 host.
Oh, a little note regarding interoperability:
There is a clang/llvm based toolchain for eBPF. However, at this
moment compiled eBPF doesn't have established conventions. The
details on what is expected to be in an ELF file containing eBPF is
determined, in practice, by what the llvm BPF backend supports and
what the sample bpf_load.c in the Linux kernel source tree expects
[1].
Despite using a different syntax for the assembler (the llvm assembler
uses a C-ish expression-based syntax while the GNU assembler opts for
a more classic assembly-language syntax) this implementation tries to
provide inter-operability with clang/llvm generated objects.
In particular, the numbers of the relocations used for instruction
fields are the same. These are R_BPF_INSN_64 and R_BPF_INSN_DISP32.
The later is resolved at load-time by bpf_load.c.
[1] We expect/hope that the addition of eBPF support to the GNU
toolchain will help to mature the domain of compiled eBPF. We
will certainly be working with the kernel people to that effect.
Salud!
Jose E. Marchesi (9):
config: recognize eBPF triplets
include: add elf/bpf.h
bfd: add support for eBPF
cpu: add eBPF cpu description
opcodes: add support for eBPF
gas: add support for eBPF
ld: add support for eBPF
binutils: add support for eBPF
binutils: add myself as the maintainer for BPF
ChangeLog | 4 +
bfd/ChangeLog | 20 +
bfd/Makefile.am | 4 +
bfd/Makefile.in | 7 +
bfd/archures.c | 4 +
bfd/bfd-in2.h | 9 +
bfd/config.bfd | 6 +
bfd/configure | 30 +-
bfd/configure.ac | 2 +
bfd/cpu-bpf.c | 41 +
bfd/elf64-bpf.c | 463 +++++++++
bfd/libbfd.h | 5 +
bfd/reloc.c | 13 +
bfd/targets.c | 7 +
binutils/ChangeLog | 13 +
binutils/MAINTAINERS | 1 +
binutils/readelf.c | 8 +
binutils/testsuite/binutils-all/nm.exp | 3 +-
config.sub | 4 +-
cpu/ChangeLog | 5 +
cpu/bpf.cpu | 647 +++++++++++++
cpu/bpf.opc | 191 ++++
gas/ChangeLog | 45 +
gas/Makefile.am | 2 +
gas/Makefile.in | 6 +
gas/config/tc-bpf.c | 354 +++++++
gas/config/tc-bpf.h | 51 +
gas/configure | 38 +-
gas/configure.ac | 6 +
gas/configure.tgt | 1 +
gas/doc/Makefile.am | 1 +
gas/doc/Makefile.in | 2 +
gas/doc/all.texi | 1 +
gas/doc/as.texi | 34 +
gas/doc/c-bpf.texi | 364 +++++++
gas/testsuite/gas/all/gas.exp | 3 +
gas/testsuite/gas/all/org-1.l | 2 +-
gas/testsuite/gas/all/org-1.s | 2 +
gas/testsuite/gas/bpf/alu-be.d | 59 ++
gas/testsuite/gas/bpf/alu.d | 58 ++
gas/testsuite/gas/bpf/alu.s | 51 +
gas/testsuite/gas/bpf/alu32-be.d | 65 ++
gas/testsuite/gas/bpf/alu32.d | 64 ++
gas/testsuite/gas/bpf/alu32.s | 57 ++
gas/testsuite/gas/bpf/atomic-be.d | 12 +
gas/testsuite/gas/bpf/atomic.d | 11 +
gas/testsuite/gas/bpf/atomic.s | 5 +
gas/testsuite/gas/bpf/bpf.exp | 38 +
gas/testsuite/gas/bpf/call-be.d | 19 +
gas/testsuite/gas/bpf/call.d | 18 +
gas/testsuite/gas/bpf/call.s | 11 +
gas/testsuite/gas/bpf/exit-be.d | 11 +
gas/testsuite/gas/bpf/exit.d | 10 +
gas/testsuite/gas/bpf/exit.s | 2 +
gas/testsuite/gas/bpf/jump-be.d | 32 +
gas/testsuite/gas/bpf/jump.d | 31 +
gas/testsuite/gas/bpf/jump.s | 25 +
gas/testsuite/gas/bpf/lddw-be.d | 18 +
gas/testsuite/gas/bpf/lddw.d | 17 +
gas/testsuite/gas/bpf/lddw.s | 6 +
gas/testsuite/gas/bpf/mem-be.d | 30 +
gas/testsuite/gas/bpf/mem.d | 29 +
gas/testsuite/gas/bpf/mem.s | 24 +
include/ChangeLog | 4 +
include/elf/bpf.h | 45 +
ld/ChangeLog | 15 +
ld/Makefile.am | 2 +
ld/Makefile.in | 4 +
ld/configure | 28 +-
ld/configure.tgt | 1 +
ld/emulparams/elf64bpf.sh | 10 +
ld/testsuite/ld-bpf/bar.s | 5 +
ld/testsuite/ld-bpf/baz.s | 5 +
ld/testsuite/ld-bpf/bpf.exp | 29 +
ld/testsuite/ld-bpf/call-1.d | 23 +
ld/testsuite/ld-bpf/foo.s | 5 +
ld/testsuite/ld-bpf/jump-1.d | 23 +
ld/testsuite/lib/ld-lib.exp | 1 +
opcodes/ChangeLog | 24 +
opcodes/Makefile.am | 17 +
opcodes/Makefile.in | 23 +
opcodes/bpf-asm.c | 590 ++++++++++++
opcodes/bpf-desc.c | 1638 ++++++++++++++++++++++++++++++++
opcodes/bpf-desc.h | 266 ++++++
opcodes/bpf-dis.c | 624 ++++++++++++
opcodes/bpf-ibld.c | 956 +++++++++++++++++++
opcodes/bpf-opc.c | 1495 +++++++++++++++++++++++++++++
opcodes/bpf-opc.h | 151 +++
opcodes/configure | 19 +-
opcodes/configure.ac | 1 +
opcodes/disassemble.c | 35 +
opcodes/disassemble.h | 1 +
92 files changed, 9111 insertions(+), 31 deletions(-)
create mode 100644 bfd/cpu-bpf.c
create mode 100644 bfd/elf64-bpf.c
create mode 100644 cpu/bpf.cpu
create mode 100644 cpu/bpf.opc
create mode 100644 gas/config/tc-bpf.c
create mode 100644 gas/config/tc-bpf.h
create mode 100644 gas/doc/c-bpf.texi
create mode 100644 gas/testsuite/gas/bpf/alu-be.d
create mode 100644 gas/testsuite/gas/bpf/alu.d
create mode 100644 gas/testsuite/gas/bpf/alu.s
create mode 100644 gas/testsuite/gas/bpf/alu32-be.d
create mode 100644 gas/testsuite/gas/bpf/alu32.d
create mode 100644 gas/testsuite/gas/bpf/alu32.s
create mode 100644 gas/testsuite/gas/bpf/atomic-be.d
create mode 100644 gas/testsuite/gas/bpf/atomic.d
create mode 100644 gas/testsuite/gas/bpf/atomic.s
create mode 100644 gas/testsuite/gas/bpf/bpf.exp
create mode 100644 gas/testsuite/gas/bpf/call-be.d
create mode 100644 gas/testsuite/gas/bpf/call.d
create mode 100644 gas/testsuite/gas/bpf/call.s
create mode 100644 gas/testsuite/gas/bpf/exit-be.d
create mode 100644 gas/testsuite/gas/bpf/exit.d
create mode 100644 gas/testsuite/gas/bpf/exit.s
create mode 100644 gas/testsuite/gas/bpf/jump-be.d
create mode 100644 gas/testsuite/gas/bpf/jump.d
create mode 100644 gas/testsuite/gas/bpf/jump.s
create mode 100644 gas/testsuite/gas/bpf/lddw-be.d
create mode 100644 gas/testsuite/gas/bpf/lddw.d
create mode 100644 gas/testsuite/gas/bpf/lddw.s
create mode 100644 gas/testsuite/gas/bpf/mem-be.d
create mode 100644 gas/testsuite/gas/bpf/mem.d
create mode 100644 gas/testsuite/gas/bpf/mem.s
create mode 100644 include/elf/bpf.h
create mode 100644 ld/emulparams/elf64bpf.sh
create mode 100644 ld/testsuite/ld-bpf/bar.s
create mode 100644 ld/testsuite/ld-bpf/baz.s
create mode 100644 ld/testsuite/ld-bpf/bpf.exp
create mode 100644 ld/testsuite/ld-bpf/call-1.d
create mode 100644 ld/testsuite/ld-bpf/foo.s
create mode 100644 ld/testsuite/ld-bpf/jump-1.d
create mode 100644 opcodes/bpf-asm.c
create mode 100644 opcodes/bpf-desc.c
create mode 100644 opcodes/bpf-desc.h
create mode 100644 opcodes/bpf-dis.c
create mode 100644 opcodes/bpf-ibld.c
create mode 100644 opcodes/bpf-opc.c
create mode 100644 opcodes/bpf-opc.h
--
2.11.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH V2 1/9] config: recognize eBPF triplets
2019-05-22 15:26 [PATCH V2 0/9] eBPF support for GNU binutils Jose E. Marchesi
` (6 preceding siblings ...)
2019-05-22 15:24 ` [PATCH V2 4/9] cpu: add eBPF cpu description Jose E. Marchesi
@ 2019-05-22 15:26 ` Jose E. Marchesi
2019-05-22 19:43 ` Hans-Peter Nilsson
2019-05-22 15:26 ` [PATCH V2 8/9] binutils: add support for eBPF Jose E. Marchesi
` (2 subsequent siblings)
10 siblings, 1 reply; 16+ messages in thread
From: Jose E. Marchesi @ 2019-05-22 15:26 UTC (permalink / raw)
To: binutils
ChangeLog:
2019-05-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* config.sub: Recognize bpf-unknown-none targets.
---
ChangeLog | 4 ++++
config.sub | 4 ++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/config.sub b/config.sub
index 75bb6a3135..2d032b8f2a 100755
--- a/config.sub
+++ b/config.sub
@@ -2,7 +2,7 @@
# Configuration validation subroutine script.
# Copyright 1992-2019 Free Software Foundation, Inc.
-timestamp='2019-01-01'
+timestamp='2019-05-02'
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by
@@ -1170,7 +1170,7 @@ case $cpu-$vendor in
| asmjs \
| ba \
| be32 | be64 \
- | bfin | bs2000 \
+ | bfin | bpf | bs2000 \
| c[123]* | c30 | [cjt]90 | c4x \
| c8051 | clipper | craynv | csky | cydra \
| d10v | d30v | dlx | dsp16xx \
--
2.11.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH V2 8/9] binutils: add support for eBPF
2019-05-22 15:26 [PATCH V2 0/9] eBPF support for GNU binutils Jose E. Marchesi
` (7 preceding siblings ...)
2019-05-22 15:26 ` [PATCH V2 1/9] config: recognize eBPF triplets Jose E. Marchesi
@ 2019-05-22 15:26 ` Jose E. Marchesi
2019-05-22 18:55 ` [PATCH V2 0/9] eBPF support for GNU binutils Jose E. Marchesi
2019-05-23 13:01 ` Nick Clifton
10 siblings, 0 replies; 16+ messages in thread
From: Jose E. Marchesi @ 2019-05-22 15:26 UTC (permalink / raw)
To: binutils
This patch adds support for ELF64 eBPF to readelf, and fixes a `nm'
test to run properly in bpf-*-* targets.
binutils/ChangeLog:
2019-05-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* readelf.c: Include elf/bpf.h.
(guess_is_rela): Hanle EM_BPF.
(dump_relocations): Likewise.
(is_32bit_abs_reloc): Likewise.
* testsuite/binutils-all/nm.exp: Add bpf-*-* to the list of
ELF targets.
---
binutils/ChangeLog | 9 +++++++++
binutils/readelf.c | 8 ++++++++
binutils/testsuite/binutils-all/nm.exp | 3 ++-
3 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/binutils/readelf.c b/binutils/readelf.c
index c31a5c1266..9d2810437e 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -102,6 +102,7 @@
#include "elf/d10v.h"
#include "elf/d30v.h"
#include "elf/dlx.h"
+#include "elf/bpf.h"
#include "elf/epiphany.h"
#include "elf/fr30.h"
#include "elf/frv.h"
@@ -781,6 +782,7 @@ guess_is_rela (unsigned int e_machine)
case EM_SCORE:
case EM_XGATE:
case EM_NFP:
+ case EM_BPF:
return FALSE;
/* Targets that use RELA relocations. */
@@ -1482,6 +1484,10 @@ dump_relocations (Filedata * filedata,
rtype = elf_visium_reloc_type (type);
break;
+ case EM_BPF:
+ rtype = elf_bpf_reloc_type (type);
+ break;
+
case EM_ADAPTEVA_EPIPHANY:
rtype = elf_epiphany_reloc_type (type);
break;
@@ -12410,6 +12416,8 @@ is_32bit_abs_reloc (Filedata * filedata, unsigned int reloc_type)
case EM_AARCH64:
return (reloc_type == 258
|| reloc_type == 1); /* R_AARCH64_ABS32 || R_AARCH64_P32_ABS32 */
+ case EM_BPF:
+ return reloc_type == 11; /* R_BPF_DATA_32 */
case EM_ADAPTEVA_EPIPHANY:
return reloc_type == 3;
case EM_ALPHA:
diff --git a/binutils/testsuite/binutils-all/nm.exp b/binutils/testsuite/binutils-all/nm.exp
index 64a969e191..5dbdcbfd35 100644
--- a/binutils/testsuite/binutils-all/nm.exp
+++ b/binutils/testsuite/binutils-all/nm.exp
@@ -160,7 +160,8 @@ if { [is_elf_format]
|| [istarget *-*-uclinux*]
|| [istarget ia64-*-*vms*]
|| [istarget *-*-vxworks*]
- || [istarget wasm32-*-*] } {
+ || [istarget wasm32-*-*]
+ || [istarget bpf-*-*]} {
set nm_1_src "nm-elf-1.s"
} else {
set nm_1_src "nm-1.s"
--
2.11.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH V2 0/9] eBPF support for GNU binutils
2019-05-22 15:26 [PATCH V2 0/9] eBPF support for GNU binutils Jose E. Marchesi
` (8 preceding siblings ...)
2019-05-22 15:26 ` [PATCH V2 8/9] binutils: add support for eBPF Jose E. Marchesi
@ 2019-05-22 18:55 ` Jose E. Marchesi
2019-05-23 13:01 ` Nick Clifton
10 siblings, 0 replies; 16+ messages in thread
From: Jose E. Marchesi @ 2019-05-22 18:55 UTC (permalink / raw)
To: binutils
The fourth patch adds a CGEN cpu description for eBPF, plus support
code. This description covers the full eBPF ISA. Due to the 64-bit
instruction fields used in some instructions, we needed to fix a
bug/limitation in CGEN impacting 32-bit hosts. The fix is in a patch
submitted to CGEN last week, that is still waiting for review:
http://www.sourceware.org/ml/cgen/2019-q2/msg00008.html None of the
existing CGEN ports in binutils are impacted by that patch: the code
generated for these remains exactly the same.
The CGEN patch referred above was just merged upstream.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH V2 1/9] config: recognize eBPF triplets
2019-05-22 15:26 ` [PATCH V2 1/9] config: recognize eBPF triplets Jose E. Marchesi
@ 2019-05-22 19:43 ` Hans-Peter Nilsson
2019-05-23 1:28 ` Ben Elliston
0 siblings, 1 reply; 16+ messages in thread
From: Hans-Peter Nilsson @ 2019-05-22 19:43 UTC (permalink / raw)
To: Jose E. Marchesi; +Cc: binutils, config-patches
Wrong list, but I cc:ed them.
See MAINTAINERS for proper import into the binutils/gdb/sim
repo.
On Wed, 22 May 2019, Jose E. Marchesi wrote:
> ChangeLog:
>
> 2019-05-22 Jose E. Marchesi <jose.marchesi@oracle.com>
>
> * config.sub: Recognize bpf-unknown-none targets.
> ---
> ChangeLog | 4 ++++
> config.sub | 4 ++--
> 2 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/config.sub b/config.sub
> index 75bb6a3135..2d032b8f2a 100755
> --- a/config.sub
> +++ b/config.sub
> @@ -2,7 +2,7 @@
> # Configuration validation subroutine script.
> # Copyright 1992-2019 Free Software Foundation, Inc.
>
> -timestamp='2019-01-01'
> +timestamp='2019-05-02'
>
> # This file is free software; you can redistribute it and/or modify it
> # under the terms of the GNU General Public License as published by
> @@ -1170,7 +1170,7 @@ case $cpu-$vendor in
> | asmjs \
> | ba \
> | be32 | be64 \
> - | bfin | bs2000 \
> + | bfin | bpf | bs2000 \
> | c[123]* | c30 | [cjt]90 | c4x \
> | c8051 | clipper | craynv | csky | cydra \
> | d10v | d30v | dlx | dsp16xx \
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH V2 1/9] config: recognize eBPF triplets
2019-05-22 19:43 ` Hans-Peter Nilsson
@ 2019-05-23 1:28 ` Ben Elliston
2019-05-23 1:56 ` Jose E. Marchesi
0 siblings, 1 reply; 16+ messages in thread
From: Ben Elliston @ 2019-05-23 1:28 UTC (permalink / raw)
To: Hans-Peter Nilsson; +Cc: Jose E. Marchesi, binutils, config-patches
[-- Attachment #1: Type: text/plain, Size: 212 bytes --]
On Wed, May 22, 2019 at 03:43:08PM -0400, Hans-Peter Nilsson wrote:
> > 2019-05-22 Jose E. Marchesi <jose.marchesi@oracle.com>
> >
> > * config.sub: Recognize bpf-unknown-none targets.
Applied.
Cheers,
Ben
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH V2 1/9] config: recognize eBPF triplets
2019-05-23 1:28 ` Ben Elliston
@ 2019-05-23 1:56 ` Jose E. Marchesi
0 siblings, 0 replies; 16+ messages in thread
From: Jose E. Marchesi @ 2019-05-23 1:56 UTC (permalink / raw)
To: Ben Elliston; +Cc: Hans-Peter Nilsson, binutils, config-patches
> > 2019-05-22 Jose E. Marchesi <jose.marchesi@oracle.com>
> >
> > * config.sub: Recognize bpf-unknown-none targets.
Applied.
Thanks.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH V2 0/9] eBPF support for GNU binutils
2019-05-22 15:26 [PATCH V2 0/9] eBPF support for GNU binutils Jose E. Marchesi
` (9 preceding siblings ...)
2019-05-22 18:55 ` [PATCH V2 0/9] eBPF support for GNU binutils Jose E. Marchesi
@ 2019-05-23 13:01 ` Nick Clifton
2019-05-23 17:49 ` Jose E. Marchesi
10 siblings, 1 reply; 16+ messages in thread
From: Nick Clifton @ 2019-05-23 13:01 UTC (permalink / raw)
To: Jose E. Marchesi, binutils
Hi Jose,
The patch series is approved. (Well the binutils parts of it anyway.
I see that the other parts have also been approved, so it looks like
it is good to go).
If you do wish to tweak the bpf entry in the bfd/config.bfd file as
I suggested in a previous email then such a change is also approved.
Cheers
Nick
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH V2 0/9] eBPF support for GNU binutils
2019-05-23 13:01 ` Nick Clifton
@ 2019-05-23 17:49 ` Jose E. Marchesi
0 siblings, 0 replies; 16+ messages in thread
From: Jose E. Marchesi @ 2019-05-23 17:49 UTC (permalink / raw)
To: Nick Clifton; +Cc: binutils
Hi Nick.
The patch series is approved. (Well the binutils parts of it anyway.
I see that the other parts have also been approved, so it looks like
it is good to go).
If you do wish to tweak the bpf entry in the bfd/config.bfd file as
I suggested in a previous email then such a change is also approved.
Thanks for the review.
I just pushed the series, with two minor changes:
- The update to config.sub is gone, as I synchronized both
config.{sub,guess} with config master in a separated commit.
- Changed bfd/config.bfd to only accept bpf-*-none (config.sub expands
bpf to bpf-unknown-none) and reject any other bpf-*-* target name as
not fully functional, as you suggested. [1]
Thanks!
[1] I added an extra case just after the `# END OF targmatch.h' marker.
If you would prefer a new case after the main block instead, let me
know and I will change it.
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2019-05-23 17:49 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
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2019-05-22 15:26 [PATCH V2 0/9] eBPF support for GNU binutils Jose E. Marchesi
2019-05-22 15:24 ` [PATCH V2 9/9] binutils: add myself as the maintainer for BPF Jose E. Marchesi
2019-05-22 15:24 ` [PATCH V2 5/9] opcodes: add support for eBPF Jose E. Marchesi
2019-05-22 15:24 ` [PATCH V2 2/9] include: add elf/bpf.h Jose E. Marchesi
2019-05-22 15:24 ` [PATCH V2 3/9] bfd: add support for eBPF Jose E. Marchesi
2019-05-22 15:24 ` [PATCH V2 6/9] gas: " Jose E. Marchesi
2019-05-22 15:24 ` [PATCH V2 7/9] ld: " Jose E. Marchesi
2019-05-22 15:24 ` [PATCH V2 4/9] cpu: add eBPF cpu description Jose E. Marchesi
2019-05-22 15:26 ` [PATCH V2 1/9] config: recognize eBPF triplets Jose E. Marchesi
2019-05-22 19:43 ` Hans-Peter Nilsson
2019-05-23 1:28 ` Ben Elliston
2019-05-23 1:56 ` Jose E. Marchesi
2019-05-22 15:26 ` [PATCH V2 8/9] binutils: add support for eBPF Jose E. Marchesi
2019-05-22 18:55 ` [PATCH V2 0/9] eBPF support for GNU binutils Jose E. Marchesi
2019-05-23 13:01 ` Nick Clifton
2019-05-23 17:49 ` Jose E. Marchesi
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