* [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support
@ 2019-06-08 21:32 Stafford Horne
2019-06-08 21:32 ` [PATCH v3 02/11] cpu/or1k: Define unordered comparisons Stafford Horne
` (10 more replies)
0 siblings, 11 replies; 15+ messages in thread
From: Stafford Horne @ 2019-06-08 21:32 UTC (permalink / raw)
To: GDB patches, GNU Binutils
Cc: Andrey Bacherov, Nick Clifton, Andrew Burgess, Richard Henderson,
Openrisc, Stafford Horne
Hello,
Its been a while since v2, but we have been busy changing direction a bit.
Instead of just adding the orfpx64a32 extension support we have created a new
architecture specification [0] and this series includes some of those changes.
Changes from v2:
- Use explicit register pairs in orfpx64a32 extension instead of implicit
suggestioned by rth.
- Add unordered FPU comparison instructions.
- Add test for the previously added l.adrp instruction.
- A few non material cgen comment/symbol updates.
Changes from v1:
- Rebased
- Note Andrey is working on doing his FSF copyright assignment for binutils,
sim
The orfpx64a32 extension patches are to the OpenRISC assembler and simulator to
support 64-bit floating point operations on 32-bit cores using register pairs,
see orfpx64a32 [1].
The original patches were written by Andrey Bacherov and I have made some
updates to get the simulator working and to match ABI updates for the final
architecture 1.3 specification.
Example of orfpx64a32 operations:
lf.add.d r3,r4, r5,r6, r7,r8 ; {r3,r4} <= {r5,r6} + {r7,r8}
lf.add.d r16,r18, r20,r22, r24,r26 ; {r16,r18} <= {r20,r22} + {r24,r26}
Note, on 64-bit architectures the instructions will be written with 64-bit
registers.
lf.add.d r3, r5, r7 ; r3 <= r5 + r7
lf.add.d r16, r20 r24 ; r16 <= r20 + r24
The new unordered comparison instructions allow the OpenRISC FPU to do
comparisons where input may include NaNs [2]
These binutil patches have been used along with the GCC FPU patches [3] on the
OpenRISC GCC 9 toolchain to test single and double precision floating point
support including unordered comparisons. The main 'real' implementation of this
hardware is Andrey's or1k_marocchino [4] core implementation which we have been
using along with simulators for verification.
This whole patch series can be found on my github repo [5] as well.
[0] https://github.com/openrisc/doc/blob/master/openrisc-arch-1.3-rev1.pdf
[1] https://openrisc.io/proposals/orfpx64a32
[2] https://openrisc.io/proposals/lfsf
[3] git@github.com:stffrdhrn/gcc.git or1k-fpu-2
[4] https://github.com/openrisc/or1k_marocchino
[5] git@github.com:stffrdhrn/binutils-gdb.git orfpx64a32-3
-Stafford
Stafford Horne (11):
cpu/or1k: Add support for orfp64a32 spec
cpu/or1k: Define unordered comparisons
cpu/or1k: Document no branch delay slot architectures and l.adrp
cpu/or1k: Update fpu compare symbols to imply set flag
opcodes/or1k: Regenerate opcodes
sim/or1k: Regenerate sim
sim/common: Wire in df/di conversion
sim/common: wire up new unordered comparisons
sim/testsuite/or1k: Add test for 64-bit fpu operations
sim/testsuite/or1k: Add test case for l.adrp instruction
sim/testsuite/or1k: Add tests for unordered compares
cpu/or1k.cpu | 21 +-
cpu/or1k.opc | 92 ++
cpu/or1kcommon.cpu | 113 +-
cpu/or1korbis.cpu | 3 +-
cpu/or1korfpx.cpu | 214 ++-
opcodes/or1k-asm.c | 72 +-
opcodes/or1k-desc.c | 309 +++-
opcodes/or1k-desc.h | 341 ++---
opcodes/or1k-dis.c | 43 +-
opcodes/or1k-ibld.c | 234 ++-
opcodes/or1k-opc.c | 319 +++-
opcodes/or1k-opc.h | 39 +-
opcodes/or1k-opinst.c | 100 +-
sim/common/cgen-accfp.c | 49 +
sim/common/cgen-fpu.h | 2 +
sim/or1k/arch.c | 2 +-
sim/or1k/arch.h | 2 +-
sim/or1k/cpu.c | 78 +-
sim/or1k/cpu.h | 174 ++-
sim/or1k/cpuall.h | 2 +-
sim/or1k/decode.c | 568 ++++++--
sim/or1k/decode.h | 21 +-
sim/or1k/model.c | 1456 ++++++++++++++++---
sim/or1k/sem-switch.c | 602 +++++++-
sim/or1k/sem.c | 672 ++++++++-
sim/testsuite/sim/or1k/adrp.S | 73 +
sim/testsuite/sim/or1k/fpu-unordered.S | 97 ++
sim/testsuite/sim/or1k/fpu64a32-unordered.S | 100 ++
sim/testsuite/sim/or1k/fpu64a32.S | 172 +++
29 files changed, 5253 insertions(+), 717 deletions(-)
create mode 100644 sim/testsuite/sim/or1k/adrp.S
create mode 100644 sim/testsuite/sim/or1k/fpu-unordered.S
create mode 100644 sim/testsuite/sim/or1k/fpu64a32-unordered.S
create mode 100644 sim/testsuite/sim/or1k/fpu64a32.S
--
2.21.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 01/11] cpu/or1k: Add support for orfp64a32 spec
2019-06-08 21:32 [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Stafford Horne
2019-06-08 21:32 ` [PATCH v3 02/11] cpu/or1k: Define unordered comparisons Stafford Horne
2019-06-08 21:32 ` [PATCH v3 04/11] cpu/or1k: Update fpu compare symbols to imply set flag Stafford Horne
@ 2019-06-08 21:32 ` Stafford Horne
2019-06-08 21:32 ` [PATCH v3 03/11] cpu/or1k: Document no branch delay slot architectures and l.adrp Stafford Horne
` (7 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Stafford Horne @ 2019-06-08 21:32 UTC (permalink / raw)
To: GDB patches, GNU Binutils
Cc: Andrey Bacherov, Nick Clifton, Andrew Burgess, Richard Henderson,
Openrisc, Stafford Horne
This patch adds support for OpenRISC 64-bit FPU operations on 32-bit cores by
using register pairs. The functionality has been added to OpenRISC architecture
specification version 1.3 as per architecture proposal 14[0].
For supporting assembly of both 64-bit and 32-bit precision instructions we have
defined CGEN_VALIDATE_INSN_SUPPORTED. This allows cgen to use 64-bit bit
architecture assembly parsing on 64-bit toolchains and 32-bit architecture
assembly parsing on 32-bit toolchains. Without this the assembler has issues
parsing register pairs.
This patch also contains a few fixes to the symantics for existing OpenRISC
single and double precision FPU operations.
[0] https://openrisc.io/proposals/orfpx64a32
cpu/ChangeLog:
yyyy-mm-dd Andrey Bacherov <avbacherov@opencores.org>
Stafford Horne <shorne@gmail.com>
* or1k.cpu (ORFPX64A32-MACHS): New pmacro.
(ORFPX-MACHS): Removed pmacro.
* or1k.opc (or1k_cgen_insn_supported): New function.
(CGEN_VALIDATE_INSN_SUPPORTED): Define macro.
(parse_regpair, print_regpair): New functions.
* or1kcommon.cpu (h-spr, spr-shift, spr-address, h-gpr): Reorder
and add comments.
(h-fdr): Update comment to indicate or64.
(reg-pair-reg-lo, reg-pair-reg-hi): New pmacros for register pairs.
(h-fd32r): New hardware for 64-bit fpu registers.
(h-i64r): New hardware for 64-bit int registers.
* or1korbis.cpu (f-resv-8-1): New field.
* or1korfpx.cpu (rDSF, rASF, rBSF): Update attribute to ORFPX32-MACHS.
(rDDF, rADF, rBDF): Update operand comment to indicate or64.
(f-rdoff-10-1, f-raoff-9-1, f-rboff-8-1): New fields.
(h-roff1): New hardware.
(double-field-and-ops mnemonic): New pmacro to generate operations
rDD32F, rAD32F, rBD32F, rDDI and rADI.
(float-regreg-insn): Update single precision generator to MACH
ORFPX32-MACHS. Add generator for or32 64-bit instructions.
(float-setflag-insn): Update single precision generator to MACH
ORFPX32-MACHS. Fix double instructions from single to double
precision. Add generator for or32 64-bit instructions.
(float-cust-insn cust-num): Update single precision generator to MACH
ORFPX32-MACHS. Add generator for or32 64-bit instructions.
(lf-rem-s, lf-itof-s, lf-ftoi-s, lf-madd-s): Update MACH to
ORFPX32-MACHS.
(lf-rem-d): Fix operation from mod to rem.
(lf-rem-d32, lf-itof-d32, lf-ftoi-d32, lf-madd-d32): New instruction.
(lf-itof-d): Fix operands from single to double.
(lf-ftoi-d): Update operand mode from DI to WI.
---
Changes since v2:
- switch from implicit to explicit reg pairs (new functions parse_regpair
print_regpair)
cpu/or1k.cpu | 15 +++--
cpu/or1k.opc | 92 +++++++++++++++++++++++++
cpu/or1kcommon.cpu | 113 +++++++++++++++++++++++++------
cpu/or1korbis.cpu | 1 +
cpu/or1korfpx.cpu | 165 +++++++++++++++++++++++++++++++++++++++------
5 files changed, 340 insertions(+), 46 deletions(-)
diff --git a/cpu/or1k.cpu b/cpu/or1k.cpu
index 3a932bcb90..e1ae1b8c88 100644
--- a/cpu/or1k.cpu
+++ b/cpu/or1k.cpu
@@ -1,8 +1,9 @@
; OpenRISC 1000 architecture. -*- Scheme -*-
-; Copyright 2000-2014 Free Software Foundation, Inc.
+; Copyright 2000-2019 Free Software Foundation, Inc.
; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org
; Modified by Julius Baxter, juliusbaxter@gmail.com
; Modified by Peter Gavin, pgavin@gmail.com
+; Modified by Andrey Bacherov, avbacherov@opencores.org
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
@@ -42,12 +43,12 @@
(base-insn-bitsize 32)
)
-(define-pmacro OR32-MACHS or32,or32nd)
-(define-pmacro OR64-MACHS or64,or64nd)
-(define-pmacro ORBIS-MACHS or32,or32nd,or64,or64nd)
-(define-pmacro ORFPX-MACHS or32,or32nd,or64,or64nd)
-(define-pmacro ORFPX32-MACHS or32,or32nd,or64,or64nd)
-(define-pmacro ORFPX64-MACHS or64,or64nd)
+(define-pmacro OR32-MACHS or32,or32nd)
+(define-pmacro OR64-MACHS or64,or64nd)
+(define-pmacro ORBIS-MACHS or32,or32nd,or64,or64nd)
+(define-pmacro ORFPX32-MACHS or32,or32nd,or64,or64nd)
+(define-pmacro ORFPX64-MACHS or64,or64nd)
+(define-pmacro ORFPX64A32-MACHS or32,or32nd) ; float64 for 32-bit machs
(define-attr
(for model)
diff --git a/cpu/or1k.opc b/cpu/or1k.opc
index 5082a30cee..f0adcbb00a 100644
--- a/cpu/or1k.opc
+++ b/cpu/or1k.opc
@@ -40,9 +40,29 @@
#undef CGEN_DIS_HASH
#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2)
+/* Check applicability of instructions against machines. */
+#define CGEN_VALIDATE_INSN_SUPPORTED
+
+extern int or1k_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
+
/* -- */
/* -- opc.c */
+
+/* Special check to ensure that instruction exists for given machine. */
+
+int
+or1k_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
+{
+ int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
+
+ /* No mach attribute? Assume it's supported for all machs. */
+ if (machs == 0)
+ return 1;
+
+ return ((machs & cd->machs) != 0);
+}
+
/* -- */
/* -- asm.c */
@@ -415,6 +435,78 @@ parse_uimm16_split (CGEN_CPU_DESC cd, const char **strp, int opindex,
return errmsg;
}
+/* Parse register pairs with syntax rA,rB to a flag + rA value. */
+
+static const char *
+parse_regpair (CGEN_CPU_DESC cd, const char **strp,
+ int opindex ATTRIBUTE_UNUSED, unsigned long *valuep)
+{
+ long reg1_index;
+ long reg2_index;
+ const char *errmsg;
+
+ /* The first part should just be a register. */
+ errmsg = cgen_parse_keyword (cd, strp, &or1k_cgen_opval_h_gpr,
+ ®1_index);
+
+ /* If that worked skip the comma separator. */
+ if (errmsg == NULL)
+ {
+ if (**strp == ',')
+ ++*strp;
+ else
+ errmsg = "Unexpected character, expected ','";
+ }
+
+ /* If that worked the next part is just another register. */
+ if (errmsg == NULL)
+ errmsg = cgen_parse_keyword (cd, strp, &or1k_cgen_opval_h_gpr,
+ ®2_index);
+
+ /* Validate the register pair is valid and create the output value. */
+ if (errmsg == NULL)
+ {
+ int regoffset = reg2_index - reg1_index;
+
+ if (regoffset == 1 || regoffset == 2)
+ {
+ unsigned short offsetmask;
+ unsigned short value;
+
+ offsetmask = ((regoffset == 2 ? 1 : 0) << 5);
+ value = offsetmask | reg1_index;
+
+ *valuep = value;
+ }
+ else
+ errmsg = "Invalid register pair, offset not 1 or 2.";
+ }
+
+ return errmsg;
+}
+
+/* -- */
+
+/* -- dis.c */
+
+static void
+print_regpair (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void * dis_info,
+ long value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = dis_info;
+ char reg1_index;
+ char reg2_index;
+
+ reg1_index = value & 0x1f;
+ reg2_index = reg1_index + ((value & (1 << 5)) ? 2 : 1);
+
+ (*info->fprintf_func) (info->stream, "r%d,r%d", reg1_index, reg2_index);
+}
+
/* -- */
/* -- ibd.h */
diff --git a/cpu/or1kcommon.cpu b/cpu/or1kcommon.cpu
index c0e4f316ad..65154407df 100644
--- a/cpu/or1kcommon.cpu
+++ b/cpu/or1kcommon.cpu
@@ -1,7 +1,8 @@
; OpenRISC 1000 32-bit CPU hardware description. -*- Scheme -*-
-; Copyright 2000-2014 Free Software Foundation, Inc.
+; Copyright 2000-2019 Free Software Foundation, Inc.
; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org
; Modified by Julius Baxter, juliusbaxter@gmail.com
+; Modified by Andrey Bacherov, avbacherov@opencores.org
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
@@ -71,6 +72,38 @@
(fp 2))
)
+;
+; Hardware: [S]pecial [P]urpose [R]egisters
+;
+(define-hardware
+ (name h-spr) (comment "special purpose registers")
+ (attrs VIRTUAL (MACH ORBIS-MACHS))
+ (type register UWI (#x20000))
+ (get (index) (c-call UWI "@cpu@_h_spr_get_raw" index))
+ (set (index newval) (c-call VOID "@cpu@_h_spr_set_raw" index newval))
+)
+
+(define-pmacro spr-shift 11)
+(define-pmacro (spr-address spr-group spr-index)
+ (or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift)
+ (enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index))))
+
+;
+; Hardware: [G]enepral [P]urpose [R]egisters
+;
+(define-hardware
+ (name h-gpr) (comment "general registers")
+ (attrs (MACH ORBIS-MACHS))
+ (type register UWI (32))
+ (indices keyword "" REG-INDICES)
+ (get (index) (reg UWI h-spr (add index (spr-address SYS GPR0))))
+ (set (index newval) (set UWI (reg UWI h-spr (add index (spr-address SYS GPR0))) newval))
+ )
+
+;
+; Hardware: virtual registerts for FPU (single precision)
+; mapped to GPRs
+;
(define-hardware
(name h-fsr)
(comment "floating point registers (single, virtual)")
@@ -81,8 +114,13 @@
(set (index newval) (set UWI (reg h-gpr index) (zext UWI (subword SI newval 0))))
)
+;
+; Hardware: virtual registerts for FPU (double precision)
+; mapped to GPRs
+;
(define-hardware
- (name h-fdr) (comment "floating point registers (double, virtual)")
+ (name h-fdr)
+ (comment "or64 floating point registers (double, virtual)")
(attrs VIRTUAL (MACH ORFPX64-MACHS))
(type register DF (32))
(indices keyword "" REG-INDICES)
@@ -90,27 +128,64 @@
(set (index newval) (set UDI (reg h-gpr index) (zext UDI (subword DI newval 0))))
)
-(define-hardware
- (name h-spr) (comment "special purpose registers")
- (attrs VIRTUAL (MACH ORBIS-MACHS))
- (type register UWI (#x20000))
- (get (index) (c-call UWI "@cpu@_h_spr_get_raw" index))
- (set (index newval) (c-call VOID "@cpu@_h_spr_set_raw" index newval))
+;
+; Register pairs are offset by 2 for registers r16 and above. This is to
+; be able to allow registers to be call saved in GCC across function calls.
+;
+(define-pmacro (reg-pair-reg-lo index)
+ (and index (const #x1f))
)
-(define-pmacro spr-shift 11)
-(define-pmacro (spr-address spr-group spr-index)
- (or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift)
- (enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index))))
+(define-pmacro (reg-pair-reg-hi index)
+ (add (and index (const #x1f))
+ (if (eq (sra index (const 5))
+ (const 1))
+ (const 2)
+ (const 1)
+ )
+ )
+)
+
+;
+; Hardware: vrtual registers for double precision floating point
+; operands on 32-bit machines
+; mapped to GPRs
+;
+(define-hardware
+ (name h-fd32r)
+ (comment "or32 floating point registers (double, virtual)")
+ (attrs VIRTUAL (MACH ORFPX64A32-MACHS))
+ (type register DF (32))
+ (get (index) (join DF SI
+ (reg h-gpr (reg-pair-reg-lo index))
+ (reg h-gpr (reg-pair-reg-hi index))))
+ (set (index newval)
+ (sequence ()
+ (set (reg h-gpr (reg-pair-reg-lo index)) (subword SI newval 0))
+ (set (reg h-gpr (reg-pair-reg-hi index))
+ (subword SI newval 1))))
+)
+;
+; Hardware: vrtual 64-bit integer registers for conversions
+; float64 <-> int64 on 32-bit machines
+; mapped to GPRs
+;
(define-hardware
- (name h-gpr) (comment "general registers")
- (attrs (MACH ORBIS-MACHS))
- (type register UWI (32))
- (indices keyword "" REG-INDICES)
- (get (index) (reg UWI h-spr (add index (spr-address SYS GPR0))))
- (set (index newval) (set UWI (reg UWI h-spr (add index (spr-address SYS GPR0))) newval))
- )
+ (name h-i64r)
+ (comment "or32 double word registers (int64, virtual)")
+ (attrs VIRTUAL (MACH ORFPX64A32-MACHS))
+ (type register DI (32))
+ (get (index) (join DI SI
+ (reg h-gpr (reg-pair-reg-lo index))
+ (reg h-gpr (reg-pair-reg-hi index))))
+ (set (index newval)
+ (sequence ()
+ (set (reg h-gpr (reg-pair-reg-lo index)) (subword SI newval 0))
+ (set (reg h-gpr (reg-pair-reg-hi index))
+ (subword SI newval 1))))
+)
+
(define-normal-enum
except-number
diff --git a/cpu/or1korbis.cpu b/cpu/or1korbis.cpu
index 094f0185a7..308f37861d 100644
--- a/cpu/or1korbis.cpu
+++ b/cpu/or1korbis.cpu
@@ -61,6 +61,7 @@
(dnf f-resv-10-7 "resv-10-7" ((MACH ORBIS-MACHS) RESERVED) 10 7)
(dnf f-resv-10-3 "resv-10-3" ((MACH ORBIS-MACHS) RESERVED) 10 3)
(dnf f-resv-10-1 "resv-10-1" ((MACH ORBIS-MACHS) RESERVED) 10 1)
+(dnf f-resv-8-1 "resv-8-1" ((MACH ORBIS-MACHS) RESERVED) 8 1)
(dnf f-resv-7-4 "resv-7-4" ((MACH ORBIS-MACHS) RESERVED) 7 4)
(dnf f-resv-5-2 "resv-5-2" ((MACH ORBIS-MACHS) RESERVED) 5 2)
diff --git a/cpu/or1korfpx.cpu b/cpu/or1korfpx.cpu
index 1a128a97b2..eb01f1ca66 100644
--- a/cpu/or1korfpx.cpu
+++ b/cpu/or1korfpx.cpu
@@ -1,6 +1,7 @@
; OpenRISC 1000 architecture. -*- Scheme -*-
-; Copyright 2000-2014 Free Software Foundation, Inc.
+; Copyright 2000-2019 Free Software Foundation, Inc.
; Contributed by Peter Gavin, pgavin@gmail.com
+; Modified by Andrey Bacherov, avbacherov@opencores.org
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
@@ -58,19 +59,80 @@
)
)
-(dnop rDSF "destination register (single floating point mode)" () h-fsr f-r1)
-(dnop rASF "source register A (single floating point mode)" () h-fsr f-r2)
-(dnop rBSF "source register B (single floating point mode)" () h-fsr f-r3)
+; Register offset flags, if set offset is 2 otherwise offset is 1
+(dnf f-rdoff-10-1 "destination register pair offset flag" ((MACH ORFPX64A32-MACHS)) 10 1)
+(dnf f-raoff-9-1 "source register A pair offset flag" ((MACH ORFPX64A32-MACHS)) 9 1)
+(dnf f-rboff-8-1 "source register B pair offset flag" ((MACH ORFPX64A32-MACHS)) 8 1)
-(dnop rDDF "destination register (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
-(dnop rADF "source register A (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
-(dnop rBDF "source register B (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
+(dsh h-roff1 "1-bit offset flag" () (register BI))
+
+(dnop rDSF "destination register (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r1)
+(dnop rASF "source register A (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r2)
+(dnop rBSF "source register B (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r3)
+
+(dnop rDDF "or64 destination register (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
+(dnop rADF "or64 source register A (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r2)
+(dnop rBDF "or64 source register B (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r3)
+
+(define-pmacro (double-field-and-ops mnemonic reg offbit op-comment)
+ (begin
+ (define-multi-ifield
+ (name (.sym "f-r" (.downcase mnemonic) "d32"))
+ (comment op-comment)
+ (attrs (MACH ORFPX64A32-MACHS))
+ (mode SI)
+ (subfields reg offbit)
+ ; From the multi-ifield insert the bits into subfields
+ (insert (sequence
+ ()
+ (set (ifield reg)
+ (and (ifield (.sym "f-r" (.downcase mnemonic) "d32"))
+ (const #x1f))
+ )
+ (set (ifield offbit)
+ (and (sra (ifield (.sym "f-r" (.downcase mnemonic) "d32"))
+ (const 5))
+ (const 1))
+ )
+ )
+ )
+ ; Extract the multi-ifield from the subfield bits
+ (extract
+ (set (ifield (.sym "f-r" (.downcase mnemonic) "d32"))
+ (or (ifield reg)
+ (sll (ifield offbit)
+ (const 5)))
+ )
+ )
+ )
+ (define-operand
+ (name (.sym "r" (.upcase mnemonic) "D32F"))
+ (comment (.str op-comment " (double floating point pair)"))
+ (attrs (MACH ORFPX64A32-MACHS))
+ (type h-fd32r)
+ (index (.sym "f-r" (.downcase mnemonic) "d32"))
+ (handlers (parse "regpair") (print "regpair"))
+ )
+ (define-operand
+ (name (.sym "r" (.upcase mnemonic) "DI"))
+ (comment (.str op-comment " (double integer pair)"))
+ (attrs (MACH ORFPX64A32-MACHS))
+ (type h-i64r)
+ (index (.sym "f-r" (.downcase mnemonic) "d32"))
+ (handlers (parse "regpair") (print "regpair"))
+ )
+ )
+ )
+
+(double-field-and-ops D f-r1 f-rdoff-10-1 "destination register")
+(double-field-and-ops A f-r2 f-raoff-9-1 "source register A")
+(double-field-and-ops B f-r3 f-rboff-8-1 "source register B")
(define-pmacro (float-regreg-insn mnemonic)
(begin
(dni (.sym lf- mnemonic -s)
(.str "lf." mnemonic ".s reg/reg/reg")
- ((MACH ORFPX-MACHS))
+ ((MACH ORFPX32-MACHS))
(.str "lf." mnemonic ".s $rDSF,$rASF,$rBSF")
(+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _S))
(set SF rDSF (mnemonic SF rASF rBSF))
@@ -84,6 +146,14 @@
(set DF rDDF (mnemonic DF rADF rBDF))
()
)
+ (dni (.sym lf- mnemonic -d32)
+ (.str "lf." mnemonic ".d regpair/regpair/regpair")
+ ((MACH ORFPX64A32-MACHS))
+ (.str "lf." mnemonic ".d $rDD32F,$rAD32F,$rBD32F")
+ (+ OPC_FLOAT rDD32F rAD32F rBD32F (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _D))
+ (set DF rDD32F (mnemonic DF rAD32F rBD32F))
+ ()
+ )
)
)
@@ -94,18 +164,28 @@
(dni lf-rem-s
"lf.rem.s reg/reg/reg"
- ((MACH ORFPX-MACHS))
+ ((MACH ORFPX32-MACHS))
"lf.rem.s $rDSF,$rASF,$rBSF"
(+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_S)
(set SF rDSF (rem SF rASF rBSF))
()
)
+
(dni lf-rem-d
"lf.rem.d reg/reg/reg"
((MACH ORFPX64-MACHS))
"lf.rem.d $rDDF,$rADF,$rBDF"
(+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_D)
- (set DF rDDF (mod DF rADF rBDF))
+ (set DF rDDF (rem DF rADF rBDF))
+ ()
+ )
+
+(dni lf-rem-d32
+ "lf.rem.d regpair/regpair/regpair"
+ ((MACH ORFPX64A32-MACHS))
+ "lf.rem.d $rDD32F,$rAD32F,$rBD32F"
+ (+ OPC_FLOAT rDD32F rAD32F rBD32F OPC_FLOAT_REGREG_REM_D)
+ (set DF rDD32F (rem DF rAD32F rBD32F))
()
)
@@ -120,24 +200,34 @@
(dni lf-itof-s
"lf.itof.s reg/reg"
- ((MACH ORFPX-MACHS))
+ ((MACH ORFPX32-MACHS))
"lf.itof.s $rDSF,$rA"
(+ OPC_FLOAT rDSF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_S)
(set SF rDSF (float SF (get-rounding-mode) (trunc SI rA)))
()
)
+
(dni lf-itof-d
"lf.itof.d reg/reg"
((MACH ORFPX64-MACHS))
- "lf.itof.d $rDSF,$rA"
- (+ OPC_FLOAT rDSF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_D)
+ "lf.itof.d $rDDF,$rA"
+ (+ OPC_FLOAT rDDF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_D)
(set DF rDDF (float DF (get-rounding-mode) rA))
()
)
+(dni lf-itof-d32
+ "lf.itof.d regpair/regpair"
+ ((MACH ORFPX64A32-MACHS))
+ "lf.itof.d $rDD32F,$rADI"
+ (+ OPC_FLOAT rDD32F rADI (f-r3 0) (f-resv-8-1 0) OPC_FLOAT_REGREG_ITOF_D)
+ (set DF rDD32F (float DF (get-rounding-mode) rADI))
+ ()
+ )
+
(dni lf-ftoi-s
"lf.ftoi.s reg/reg"
- ((MACH ORFPX-MACHS))
+ ((MACH ORFPX32-MACHS))
"lf.ftoi.s $rD,$rASF"
(+ OPC_FLOAT rD rASF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_S)
(set WI rD (ext WI (fix SI (get-rounding-mode) rASF)))
@@ -149,7 +239,16 @@
((MACH ORFPX64-MACHS))
"lf.ftoi.d $rD,$rADF"
(+ OPC_FLOAT rD rADF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_D)
- (set DI rD (fix DI (get-rounding-mode) rADF))
+ (set WI rD (fix WI (get-rounding-mode) rADF))
+ ()
+ )
+
+(dni lf-ftoi-d32
+ "lf.ftoi.d regpair/regpair"
+ ((MACH ORFPX64A32-MACHS))
+ "lf.ftoi.d $rDDI,$rAD32F"
+ (+ OPC_FLOAT rDDI rAD32F (f-r3 0) (f-resv-8-1 0) OPC_FLOAT_REGREG_FTOI_D)
+ (set DI rDDI (fix DI (get-rounding-mode) rAD32F))
()
)
@@ -157,7 +256,7 @@
(begin
(dni (.sym lf- mnemonic -s)
(.str "lf.sf" mnemonic ".s reg/reg")
- ((MACH ORFPX-MACHS))
+ ((MACH ORFPX32-MACHS))
(.str "lf.sf" mnemonic ".s $rASF,$rBSF")
(+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _S))
(set BI sys-sr-f (mnemonic SF rASF rBSF))
@@ -166,11 +265,19 @@
(dni (.sym lf- mnemonic -d)
(.str "lf.sf" mnemonic ".d reg/reg")
((MACH ORFPX64-MACHS))
- (.str "lf.sf" mnemonic ".d $rASF,$rBSF")
- (+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
+ (.str "lf.sf" mnemonic ".d $rADF,$rBDF")
+ (+ OPC_FLOAT (f-r1 0) rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
(set BI sys-sr-f (mnemonic DF rADF rBDF))
()
)
+ (dni (.sym lf- mnemonic -d32)
+ (.str "lf.sf" mnemonic ".d regpair/regpair")
+ ((MACH ORFPX64A32-MACHS))
+ (.str "lf.sf" mnemonic ".d $rAD32F,$rBD32F")
+ (+ OPC_FLOAT (f-r1 0) rAD32F rBD32F (f-resv-10-1 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
+ (set BI sys-sr-f (mnemonic DF rAD32F rBD32F))
+ ()
+ )
)
)
@@ -183,12 +290,13 @@
(dni lf-madd-s
"lf.madd.s reg/reg/reg"
- ((MACH ORFPX-MACHS))
+ ((MACH ORFPX32-MACHS))
"lf.madd.s $rDSF,$rASF,$rBSF"
(+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_S)
(set SF rDSF (add SF (mul SF rASF rBSF) rDSF))
()
)
+
(dni lf-madd-d
"lf.madd.d reg/reg/reg"
((MACH ORFPX64-MACHS))
@@ -198,11 +306,20 @@
()
)
+(dni lf-madd-d32
+ "lf.madd.d regpair/regpair/regpair"
+ ((MACH ORFPX64A32-MACHS))
+ "lf.madd.d $rDD32F,$rAD32F,$rBD32F"
+ (+ OPC_FLOAT rDD32F rAD32F rBD32F OPC_FLOAT_REGREG_MADD_D)
+ (set DF rDD32F (add DF (mul DF rAD32F rBD32F) rDD32F))
+ ()
+ )
+
(define-pmacro (float-cust-insn cust-num)
(begin
(dni (.sym "lf-cust" cust-num "-s")
(.str "lf.cust" cust-num ".s")
- ((MACH ORFPX-MACHS))
+ ((MACH ORFPX32-MACHS))
(.str "lf.cust" cust-num ".s $rASF,$rBSF")
(+ OPC_FLOAT (f-resv-25-5 0) rASF rBSF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_S"))
(nop)
@@ -216,6 +333,14 @@
(nop)
()
)
+ (dni (.sym "lf-cust" cust-num "-d32")
+ (.str "lf.cust" cust-num ".d")
+ ((MACH ORFPX64A32-MACHS))
+ (.str "lf.cust" cust-num ".d")
+ (+ OPC_FLOAT (f-resv-25-5 0) rAD32F rBD32F (f-resv-10-1 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_D"))
+ (nop)
+ ()
+ )
)
)
--
2.21.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 03/11] cpu/or1k: Document no branch delay slot architectures and l.adrp
2019-06-08 21:32 [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Stafford Horne
` (2 preceding siblings ...)
2019-06-08 21:32 ` [PATCH v3 01/11] cpu/or1k: Add support for orfp64a32 spec Stafford Horne
@ 2019-06-08 21:32 ` Stafford Horne
2019-06-08 21:33 ` [PATCH v3 05/11] opcodes/or1k: Regenerate opcodes Stafford Horne
` (6 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Stafford Horne @ 2019-06-08 21:32 UTC (permalink / raw)
To: GDB patches, GNU Binutils
Cc: Andrey Bacherov, Nick Clifton, Andrew Burgess, Richard Henderson,
Openrisc, Stafford Horne
The 'nd' architectures did not mention what the 'nd' stands for.
Document that these mean 'no brach delay slot'.
cpu/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k.cpu (or64nd, or32nd, or1200nd): Update comment.a
(l-adrp): Improve comment.
---
cpu/or1k.cpu | 6 +++---
cpu/or1korbis.cpu | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/cpu/or1k.cpu b/cpu/or1k.cpu
index e1ae1b8c88..b796862d1b 100644
--- a/cpu/or1k.cpu
+++ b/cpu/or1k.cpu
@@ -77,7 +77,7 @@
(define-mach
(name or32nd)
- (comment "Generic OpenRISC 1000 32-bit CPU")
+ (comment "Generic OpenRISC 1000 32-bit CPU with no branch delay slot")
(cpu or1k32bf)
(bfd-name "or1knd")
)
@@ -92,7 +92,7 @@
; OpenRISC 1200 - 32-bit or1k CPU implementation
(define-model
- (name or1200nd) (comment "OpenRISC 1200 model")
+ (name or1200nd) (comment "OpenRISC 1200 model with no branch delay slot")
(attrs NO-DELAY-SLOT)
(mach or32nd)
(unit u-exec "Execution Unit" () 1 1 () () () ())
@@ -120,7 +120,7 @@
(define-mach
(name or64nd)
- (comment "Generic OpenRISC 1000 ND 64-bit CPU")
+ (comment "Generic OpenRISC 1000 ND 64-bit CPU with no branch delay slot")
(cpu or1k64bf)
(bfd-name "or1k64nd")
)
diff --git a/cpu/or1korbis.cpu b/cpu/or1korbis.cpu
index 308f37861d..3741d4c8f7 100644
--- a/cpu/or1korbis.cpu
+++ b/cpu/or1korbis.cpu
@@ -433,7 +433,7 @@
)
)
-(dni l-adrp "adrp reg/disp21"
+(dni l-adrp "load pc-relative page address"
((MACH ORBIS-MACHS))
"l.adrp $rD,${disp21}"
(+ OPC_ADRP rD disp21)
--
2.21.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 04/11] cpu/or1k: Update fpu compare symbols to imply set flag
2019-06-08 21:32 [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Stafford Horne
2019-06-08 21:32 ` [PATCH v3 02/11] cpu/or1k: Define unordered comparisons Stafford Horne
@ 2019-06-08 21:32 ` Stafford Horne
2019-06-08 21:32 ` [PATCH v3 01/11] cpu/or1k: Add support for orfp64a32 spec Stafford Horne
` (8 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Stafford Horne @ 2019-06-08 21:32 UTC (permalink / raw)
To: GDB patches, GNU Binutils
Cc: Andrey Bacherov, Nick Clifton, Andrew Burgess, Richard Henderson,
Openrisc, Stafford Horne
The fpu compare symbols where not including 'sf' in the mnemonic. So
instead of `lf-sfeq` (implying set flag if operands are equal) we were
having `lf-eq`. This patch adds the 'sf'. This helps with making the
generated CGEN documentation consistent and ordered correctly.
cpu/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1korfpx.cpu (float-setflag-insn-base): Add 'sf' to symbol.
---
cpu/or1korfpx.cpu | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/cpu/or1korfpx.cpu b/cpu/or1korfpx.cpu
index 5e33b82a44..f43522f2e6 100644
--- a/cpu/or1korfpx.cpu
+++ b/cpu/or1korfpx.cpu
@@ -268,7 +268,7 @@
(define-pmacro (float-setflag-insn-base mnemonic rtx-mnemonic symantics)
(begin
- (dni (.sym lf- mnemonic -s)
+ (dni (.sym lf-sf mnemonic -s)
(.str "lf.sf" mnemonic ".s reg/reg")
((MACH ORFPX32-MACHS))
(.str "lf.sf" mnemonic ".s $rASF,$rBSF")
@@ -276,7 +276,7 @@
(symantics rtx-mnemonic SF rASF rBSF)
()
)
- (dni (.sym lf- mnemonic -d)
+ (dni (.sym lf-sf mnemonic -d)
(.str "lf.sf" mnemonic ".d reg/reg")
((MACH ORFPX64-MACHS))
(.str "lf.sf" mnemonic ".d $rADF,$rBDF")
@@ -284,7 +284,7 @@
(symantics rtx-mnemonic DF rADF rBDF)
()
)
- (dni (.sym lf- mnemonic -d32)
+ (dni (.sym lf-sf mnemonic -d32)
(.str "lf.sf" mnemonic ".d regpair/regpair")
((MACH ORFPX64A32-MACHS))
(.str "lf.sf" mnemonic ".d $rAD32F,$rBD32F")
--
2.21.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 02/11] cpu/or1k: Define unordered comparisons
2019-06-08 21:32 [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Stafford Horne
@ 2019-06-08 21:32 ` Stafford Horne
2019-06-08 21:32 ` [PATCH v3 04/11] cpu/or1k: Update fpu compare symbols to imply set flag Stafford Horne
` (9 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Stafford Horne @ 2019-06-08 21:32 UTC (permalink / raw)
To: GDB patches, GNU Binutils
Cc: Andrey Bacherov, Nick Clifton, Andrew Burgess, Richard Henderson,
Openrisc, Stafford Horne
Add support for new floating point unordered comparisons. These have been
defined in OpenRISC architecture proposal 7[0] and are now included in the
architecture specification 1.3.
These new instructions provide the ability for floating point comparisons to
detect NaNs.
[0] https://openrisc.io/proposals/lfsf
cpu/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1korfpx.cpu (insn-opcode-float-regreg): Add SFUEQ_S, SFUNE_S,
SFUGT_S, SFUGE_S, SFULT_S, SFULE_S, SFUN_S, SFUEQ_D, SFUNE_D, SFUGT_D,
SFUGE_D, SFULT_D, SFULE_D, SFUN_D opcodes.
(float-setflag-insn-base): New pmacro based on float-setflag-insn.
(float-setflag-symantics, float-setflag-unordered-cmp-symantics,
float-setflag-unordered-symantics): New pmacro for instruction
symantics.
(float-setflag-insn): Update to use float-setflag-insn-base.
(float-setflag-unordered-insn): New pmacro for generating instructions.
---
cpu/or1korfpx.cpu | 47 +++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 43 insertions(+), 4 deletions(-)
diff --git a/cpu/or1korfpx.cpu b/cpu/or1korfpx.cpu
index eb01f1ca66..5e33b82a44 100644
--- a/cpu/or1korfpx.cpu
+++ b/cpu/or1korfpx.cpu
@@ -54,6 +54,20 @@
("SFGE_D" #x1b)
("SFLT_D" #x1c)
("SFLE_D" #x1d)
+ ("SFUEQ_S" #x28)
+ ("SFUNE_S" #x29)
+ ("SFUGT_S" #x2a)
+ ("SFUGE_S" #x2b)
+ ("SFULT_S" #x2c)
+ ("SFULE_S" #x2d)
+ ("SFUN_S" #x2e)
+ ("SFUEQ_D" #x38)
+ ("SFUNE_D" #x39)
+ ("SFUGT_D" #x3a)
+ ("SFUGE_D" #x3b)
+ ("SFULT_D" #x3c)
+ ("SFULE_D" #x3d)
+ ("SFUN_D" #x3e)
("CUST1_S" #xd0)
("CUST1_D" #xe0)
)
@@ -252,14 +266,14 @@
()
)
-(define-pmacro (float-setflag-insn mnemonic)
+(define-pmacro (float-setflag-insn-base mnemonic rtx-mnemonic symantics)
(begin
(dni (.sym lf- mnemonic -s)
(.str "lf.sf" mnemonic ".s reg/reg")
((MACH ORFPX32-MACHS))
(.str "lf.sf" mnemonic ".s $rASF,$rBSF")
(+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _S))
- (set BI sys-sr-f (mnemonic SF rASF rBSF))
+ (symantics rtx-mnemonic SF rASF rBSF)
()
)
(dni (.sym lf- mnemonic -d)
@@ -267,7 +281,7 @@
((MACH ORFPX64-MACHS))
(.str "lf.sf" mnemonic ".d $rADF,$rBDF")
(+ OPC_FLOAT (f-r1 0) rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
- (set BI sys-sr-f (mnemonic DF rADF rBDF))
+ (symantics rtx-mnemonic DF rADF rBDF)
()
)
(dni (.sym lf- mnemonic -d32)
@@ -275,18 +289,43 @@
((MACH ORFPX64A32-MACHS))
(.str "lf.sf" mnemonic ".d $rAD32F,$rBD32F")
(+ OPC_FLOAT (f-r1 0) rAD32F rBD32F (f-resv-10-1 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
- (set BI sys-sr-f (mnemonic DF rAD32F rBD32F))
+ (symantics rtx-mnemonic DF rAD32F rBD32F)
()
)
)
)
+(define-pmacro (float-setflag-symantics mnemonic mode r1 r2)
+ (set BI sys-sr-f (mnemonic mode r1 r2)))
+
+(define-pmacro (float-setflag-insn mnemonic)
+ (float-setflag-insn-base mnemonic mnemonic float-setflag-symantics))
+
+(define-pmacro (float-setflag-unordered-cmp-symantics mnemonic mode r1 r2)
+ (set BI sys-sr-f (or (unordered mode r1 r2)
+ (mnemonic mode r1 r2))))
+
+(define-pmacro (float-setflag-unordered-symantics mnemonic mode r1 r2)
+ (set BI sys-sr-f (unordered mode r1 r2)))
+
+(define-pmacro (float-setflag-unordered-insn mnemonic)
+ (float-setflag-insn-base (.str "u" mnemonic)
+ mnemonic
+ float-setflag-unordered-cmp-symantics))
+
(float-setflag-insn eq)
(float-setflag-insn ne)
(float-setflag-insn ge)
(float-setflag-insn gt)
(float-setflag-insn lt)
(float-setflag-insn le)
+(float-setflag-unordered-insn eq)
+(float-setflag-unordered-insn ne)
+(float-setflag-unordered-insn gt)
+(float-setflag-unordered-insn ge)
+(float-setflag-unordered-insn lt)
+(float-setflag-unordered-insn le)
+(float-setflag-insn-base un () float-setflag-unordered-symantics)
(dni lf-madd-s
"lf.madd.s reg/reg/reg"
--
2.21.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 06/11] sim/or1k: Regenerate sim
2019-06-08 21:32 [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Stafford Horne
` (7 preceding siblings ...)
2019-06-08 21:33 ` [PATCH v3 07/11] sim/common: Wire in df/di conversion Stafford Horne
@ 2019-06-08 21:33 ` Stafford Horne
2019-06-10 15:08 ` [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Nick Clifton
2019-06-11 16:03 ` Nick Clifton
10 siblings, 0 replies; 15+ messages in thread
From: Stafford Horne @ 2019-06-08 21:33 UTC (permalink / raw)
To: GDB patches, GNU Binutils
Cc: Andrey Bacherov, Nick Clifton, Andrew Burgess, Richard Henderson,
Openrisc, Stafford Horne
This picks up changes for:
- new orfpx64a32 spec
- new unordered instructions
- documentation and symbol updates
sim/ChangeLog:
* or1k/cpu.c: Regenerate.
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate.
---
Changes since v2:
- Now regenerating for new unordered instructions and documentation.
sim/or1k/arch.c | 2 +-
sim/or1k/arch.h | 2 +-
sim/or1k/cpu.c | 78 ++-
sim/or1k/cpu.h | 174 ++++-
sim/or1k/cpuall.h | 2 +-
sim/or1k/decode.c | 568 +++++++++++++---
sim/or1k/decode.h | 21 +-
sim/or1k/model.c | 1456 ++++++++++++++++++++++++++++++++++-------
sim/or1k/sem-switch.c | 602 ++++++++++++++++-
sim/or1k/sem.c | 672 ++++++++++++++++++-
10 files changed, 3188 insertions(+), 389 deletions(-)
diff --git a/sim/or1k/arch.c b/sim/or1k/arch.c
index 8ff891d96d..ad317d6a90 100644
--- a/sim/or1k/arch.c
+++ b/sim/or1k/arch.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2019 Free Software Foundation, Inc.
+Copyright (C) 1996-2019 Free Software Foundation, Inc.
This file is part of the GNU simulators.
diff --git a/sim/or1k/arch.h b/sim/or1k/arch.h
index 66a41b9c62..1e8f90a561 100644
--- a/sim/or1k/arch.h
+++ b/sim/or1k/arch.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2019 Free Software Foundation, Inc.
+Copyright (C) 1996-2019 Free Software Foundation, Inc.
This file is part of the GNU simulators.
diff --git a/sim/or1k/cpu.c b/sim/or1k/cpu.c
index f93b51276e..a668ac4811 100644
--- a/sim/or1k/cpu.c
+++ b/sim/or1k/cpu.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2019 Free Software Foundation, Inc.
+Copyright (C) 1996-2019 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -44,6 +44,38 @@ or1k32bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
SET_H_PC (newval);
}
+/* Get the value of h-spr. */
+
+USI
+or1k32bf_h_spr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_SPR (regno);
+}
+
+/* Set a value for h-spr. */
+
+void
+or1k32bf_h_spr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
+{
+ SET_H_SPR (regno, newval);
+}
+
+/* Get the value of h-gpr. */
+
+USI
+or1k32bf_h_gpr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_GPR (regno);
+}
+
+/* Set a value for h-gpr. */
+
+void
+or1k32bf_h_gpr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
+{
+ SET_H_GPR (regno, newval);
+}
+
/* Get the value of h-fsr. */
SF
@@ -60,36 +92,36 @@ or1k32bf_h_fsr_set (SIM_CPU *current_cpu, UINT regno, SF newval)
SET_H_FSR (regno, newval);
}
-/* Get the value of h-spr. */
+/* Get the value of h-fd32r. */
-USI
-or1k32bf_h_spr_get (SIM_CPU *current_cpu, UINT regno)
+DF
+or1k32bf_h_fd32r_get (SIM_CPU *current_cpu, UINT regno)
{
- return GET_H_SPR (regno);
+ return GET_H_FD32R (regno);
}
-/* Set a value for h-spr. */
+/* Set a value for h-fd32r. */
void
-or1k32bf_h_spr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
+or1k32bf_h_fd32r_set (SIM_CPU *current_cpu, UINT regno, DF newval)
{
- SET_H_SPR (regno, newval);
+ SET_H_FD32R (regno, newval);
}
-/* Get the value of h-gpr. */
+/* Get the value of h-i64r. */
-USI
-or1k32bf_h_gpr_get (SIM_CPU *current_cpu, UINT regno)
+DI
+or1k32bf_h_i64r_get (SIM_CPU *current_cpu, UINT regno)
{
- return GET_H_GPR (regno);
+ return GET_H_I64R (regno);
}
-/* Set a value for h-gpr. */
+/* Set a value for h-i64r. */
void
-or1k32bf_h_gpr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
+or1k32bf_h_i64r_set (SIM_CPU *current_cpu, UINT regno, DI newval)
{
- SET_H_GPR (regno, newval);
+ SET_H_I64R (regno, newval);
}
/* Get the value of h-sys-vr. */
@@ -10172,6 +10204,22 @@ or1k32bf_h_atomic_address_set (SIM_CPU *current_cpu, SI newval)
CPU (h_atomic_address) = newval;
}
+/* Get the value of h-roff1. */
+
+BI
+or1k32bf_h_roff1_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_roff1);
+}
+
+/* Set a value for h-roff1. */
+
+void
+or1k32bf_h_roff1_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_roff1) = newval;
+}
+
/* Record trace results for INSN. */
void
diff --git a/sim/or1k/cpu.h b/sim/or1k/cpu.h
index 199c93bce3..730392f411 100644
--- a/sim/or1k/cpu.h
+++ b/sim/or1k/cpu.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2019 Free Software Foundation, Inc.
+Copyright (C) 1996-2019 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -67,21 +67,41 @@ SET_H_SPR ((((index)) + (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR0))),
SI h_atomic_address;
#define GET_H_ATOMIC_ADDRESS() CPU (h_atomic_address)
#define SET_H_ATOMIC_ADDRESS(x) (CPU (h_atomic_address) = (x))
+ /* 1-bit offset flag */
+ BI h_roff1;
+#define GET_H_ROFF1() CPU (h_roff1)
+#define SET_H_ROFF1(x) (CPU (h_roff1) = (x))
} hardware;
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
} OR1K32BF_CPU_DATA;
/* Virtual regs. */
+#define GET_H_SPR(index) or1k32bf_h_spr_get_raw (current_cpu, index)
+#define SET_H_SPR(index, x) \
+do { \
+or1k32bf_h_spr_set_raw (current_cpu, (index), (x));\
+;} while (0)
#define GET_H_FSR(index) SUBWORDSISF (TRUNCSISI (GET_H_GPR (index)))
#define SET_H_FSR(index, x) \
do { \
SET_H_GPR ((index), ZEXTSISI (SUBWORDSFSI ((x))));\
;} while (0)
-#define GET_H_SPR(index) or1k32bf_h_spr_get_raw (current_cpu, index)
-#define SET_H_SPR(index, x) \
+#define GET_H_FD32R(index) JOINSIDF (GET_H_GPR (((index) & (31))), GET_H_GPR (((((index) & (31))) + (((((((INT) (index) >> (5))) == (1))) ? (2) : (1))))))
+#define SET_H_FD32R(index, x) \
do { \
-or1k32bf_h_spr_set_raw (current_cpu, (index), (x));\
+{\
+SET_H_GPR ((((index)) & (31)), SUBWORDDFSI ((x), 0));\
+SET_H_GPR ((((((index)) & (31))) + (((((((INT) ((index)) >> (5))) == (1))) ? (2) : (1)))), SUBWORDDFSI ((x), 1));\
+}\
+;} while (0)
+#define GET_H_I64R(index) JOINSIDI (GET_H_GPR (((index) & (31))), GET_H_GPR (((((index) & (31))) + (((((((INT) (index) >> (5))) == (1))) ? (2) : (1))))))
+#define SET_H_I64R(index, x) \
+do { \
+{\
+SET_H_GPR ((((index)) & (31)), SUBWORDDISI ((x), 0));\
+SET_H_GPR ((((((index)) & (31))) + (((((((INT) ((index)) >> (5))) == (1))) ? (2) : (1)))), SUBWORDDISI ((x), 1));\
+}\
;} while (0)
#define GET_H_SYS_VR() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_VR))
#define SET_H_SYS_VR(x) \
@@ -3227,12 +3247,16 @@ or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_
/* Cover fns for register access. */
USI or1k32bf_h_pc_get (SIM_CPU *);
void or1k32bf_h_pc_set (SIM_CPU *, USI);
-SF or1k32bf_h_fsr_get (SIM_CPU *, UINT);
-void or1k32bf_h_fsr_set (SIM_CPU *, UINT, SF);
USI or1k32bf_h_spr_get (SIM_CPU *, UINT);
void or1k32bf_h_spr_set (SIM_CPU *, UINT, USI);
USI or1k32bf_h_gpr_get (SIM_CPU *, UINT);
void or1k32bf_h_gpr_set (SIM_CPU *, UINT, USI);
+SF or1k32bf_h_fsr_get (SIM_CPU *, UINT);
+void or1k32bf_h_fsr_set (SIM_CPU *, UINT, SF);
+DF or1k32bf_h_fd32r_get (SIM_CPU *, UINT);
+void or1k32bf_h_fd32r_set (SIM_CPU *, UINT, DF);
+DI or1k32bf_h_i64r_get (SIM_CPU *, UINT);
+void or1k32bf_h_i64r_set (SIM_CPU *, UINT, DI);
USI or1k32bf_h_sys_vr_get (SIM_CPU *);
void or1k32bf_h_sys_vr_set (SIM_CPU *, USI);
USI or1k32bf_h_sys_upr_get (SIM_CPU *);
@@ -4493,6 +4517,8 @@ BI or1k32bf_h_atomic_reserve_get (SIM_CPU *);
void or1k32bf_h_atomic_reserve_set (SIM_CPU *, BI);
SI or1k32bf_h_atomic_address_get (SIM_CPU *);
void or1k32bf_h_atomic_address_set (SIM_CPU *, SI);
+BI or1k32bf_h_roff1_get (SIM_CPU *);
+void or1k32bf_h_roff1_set (SIM_CPU *, BI);
/* These must be hand-written. */
extern CPUREG_FETCH_FN or1k32bf_fetch_register;
@@ -4519,6 +4545,11 @@ union sem_fields {
IADDR i_disp21;
UINT f_r1;
} sfmt_l_adrp;
+ struct { /* */
+ SI f_rad32;
+ SI f_rbd32;
+ SI f_rdd32;
+ } sfmt_lf_add_d32;
struct { /* */
UINT f_r1;
UINT f_r2;
@@ -4978,6 +5009,33 @@ struct scache {
f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+#define EXTRACT_IFMT_LF_ADD_D32_VARS \
+ UINT f_opcode; \
+ UINT f_r1; \
+ UINT f_rdoff_10_1; \
+ SI f_rdd32; \
+ UINT f_r2; \
+ UINT f_raoff_9_1; \
+ SI f_rad32; \
+ UINT f_r3; \
+ UINT f_rboff_8_1; \
+ SI f_rbd32; \
+ UINT f_op_7_8; \
+ unsigned int length;
+#define EXTRACT_IFMT_LF_ADD_D32_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_rdoff_10_1 = EXTRACT_LSB0_UINT (insn, 32, 10, 1); \
+ f_rdd32 = ((f_r1) | (((f_rdoff_10_1) << (5))));\
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_raoff_9_1 = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \
+ f_rad32 = ((f_r2) | (((f_raoff_9_1) << (5))));\
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_rboff_8_1 = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+ f_rbd32 = ((f_r3) | (((f_rboff_8_1) << (5))));\
+ f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+
#define EXTRACT_IFMT_LF_ITOF_S_VARS \
UINT f_opcode; \
UINT f_r1; \
@@ -4995,6 +5053,31 @@ struct scache {
f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+#define EXTRACT_IFMT_LF_ITOF_D32_VARS \
+ UINT f_opcode; \
+ UINT f_r3; \
+ UINT f_r1; \
+ UINT f_rdoff_10_1; \
+ SI f_rdd32; \
+ UINT f_r2; \
+ UINT f_raoff_9_1; \
+ SI f_rad32; \
+ UINT f_resv_8_1; \
+ UINT f_op_7_8; \
+ unsigned int length;
+#define EXTRACT_IFMT_LF_ITOF_D32_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_rdoff_10_1 = EXTRACT_LSB0_UINT (insn, 32, 10, 1); \
+ f_rdd32 = ((f_r1) | (((f_rdoff_10_1) << (5))));\
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_raoff_9_1 = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \
+ f_rad32 = ((f_r2) | (((f_raoff_9_1) << (5))));\
+ f_resv_8_1 = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+ f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+
#define EXTRACT_IFMT_LF_FTOI_S_VARS \
UINT f_opcode; \
UINT f_r1; \
@@ -5012,7 +5095,32 @@ struct scache {
f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
-#define EXTRACT_IFMT_LF_EQ_S_VARS \
+#define EXTRACT_IFMT_LF_FTOI_D32_VARS \
+ UINT f_opcode; \
+ UINT f_r3; \
+ UINT f_r1; \
+ UINT f_rdoff_10_1; \
+ SI f_rdd32; \
+ UINT f_r2; \
+ UINT f_raoff_9_1; \
+ SI f_rad32; \
+ UINT f_resv_8_1; \
+ UINT f_op_7_8; \
+ unsigned int length;
+#define EXTRACT_IFMT_LF_FTOI_D32_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_rdoff_10_1 = EXTRACT_LSB0_UINT (insn, 32, 10, 1); \
+ f_rdd32 = ((f_r1) | (((f_rdoff_10_1) << (5))));\
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_raoff_9_1 = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \
+ f_rad32 = ((f_r2) | (((f_raoff_9_1) << (5))));\
+ f_resv_8_1 = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+ f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+
+#define EXTRACT_IFMT_LF_SFEQ_S_VARS \
UINT f_opcode; \
UINT f_r1; \
UINT f_r2; \
@@ -5020,7 +5128,7 @@ struct scache {
UINT f_resv_10_3; \
UINT f_op_7_8; \
unsigned int length;
-#define EXTRACT_IFMT_LF_EQ_S_CODE \
+#define EXTRACT_IFMT_LF_SFEQ_S_CODE \
length = 4; \
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
@@ -5029,6 +5137,31 @@ struct scache {
f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+#define EXTRACT_IFMT_LF_SFEQ_D32_VARS \
+ UINT f_opcode; \
+ UINT f_r1; \
+ UINT f_resv_10_1; \
+ UINT f_r2; \
+ UINT f_raoff_9_1; \
+ SI f_rad32; \
+ UINT f_r3; \
+ UINT f_rboff_8_1; \
+ SI f_rbd32; \
+ UINT f_op_7_8; \
+ unsigned int length;
+#define EXTRACT_IFMT_LF_SFEQ_D32_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_resv_10_1 = EXTRACT_LSB0_UINT (insn, 32, 10, 1); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_raoff_9_1 = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \
+ f_rad32 = ((f_r2) | (((f_raoff_9_1) << (5))));\
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_rboff_8_1 = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+ f_rbd32 = ((f_r3) | (((f_rboff_8_1) << (5))));\
+ f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+
#define EXTRACT_IFMT_LF_CUST1_S_VARS \
UINT f_opcode; \
UINT f_resv_25_5; \
@@ -5046,6 +5179,31 @@ struct scache {
f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+#define EXTRACT_IFMT_LF_CUST1_D32_VARS \
+ UINT f_opcode; \
+ UINT f_resv_25_5; \
+ UINT f_resv_10_1; \
+ UINT f_r2; \
+ UINT f_raoff_9_1; \
+ SI f_rad32; \
+ UINT f_r3; \
+ UINT f_rboff_8_1; \
+ SI f_rbd32; \
+ UINT f_op_7_8; \
+ unsigned int length;
+#define EXTRACT_IFMT_LF_CUST1_D32_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_resv_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_resv_10_1 = EXTRACT_LSB0_UINT (insn, 32, 10, 1); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_raoff_9_1 = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \
+ f_rad32 = ((f_r2) | (((f_raoff_9_1) << (5))));\
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_rboff_8_1 = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+ f_rbd32 = ((f_r3) | (((f_rboff_8_1) << (5))));\
+ f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+
/* Collection of various things for the trace handler to use. */
typedef struct trace_record {
diff --git a/sim/or1k/cpuall.h b/sim/or1k/cpuall.h
index 8fc8eef61a..a6371ccb3f 100644
--- a/sim/or1k/cpuall.h
+++ b/sim/or1k/cpuall.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2019 Free Software Foundation, Inc.
+Copyright (C) 1996-2019 Free Software Foundation, Inc.
This file is part of the GNU simulators.
diff --git a/sim/or1k/decode.c b/sim/or1k/decode.c
index 153e00f82f..779594b6cf 100644
--- a/sim/or1k/decode.c
+++ b/sim/or1k/decode.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2019 Free Software Foundation, Inc.
+Copyright (C) 1996-2019 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -144,20 +144,49 @@ static const struct insn_sem or1k32bf_insn_sem[] =
{ OR1K_INSN_L_CUST7, OR1K32BF_INSN_L_CUST7, OR1K32BF_SFMT_L_MSYNC },
{ OR1K_INSN_L_CUST8, OR1K32BF_INSN_L_CUST8, OR1K32BF_SFMT_L_MSYNC },
{ OR1K_INSN_LF_ADD_S, OR1K32BF_INSN_LF_ADD_S, OR1K32BF_SFMT_LF_ADD_S },
+ { OR1K_INSN_LF_ADD_D32, OR1K32BF_INSN_LF_ADD_D32, OR1K32BF_SFMT_LF_ADD_D32 },
{ OR1K_INSN_LF_SUB_S, OR1K32BF_INSN_LF_SUB_S, OR1K32BF_SFMT_LF_ADD_S },
+ { OR1K_INSN_LF_SUB_D32, OR1K32BF_INSN_LF_SUB_D32, OR1K32BF_SFMT_LF_ADD_D32 },
{ OR1K_INSN_LF_MUL_S, OR1K32BF_INSN_LF_MUL_S, OR1K32BF_SFMT_LF_ADD_S },
+ { OR1K_INSN_LF_MUL_D32, OR1K32BF_INSN_LF_MUL_D32, OR1K32BF_SFMT_LF_ADD_D32 },
{ OR1K_INSN_LF_DIV_S, OR1K32BF_INSN_LF_DIV_S, OR1K32BF_SFMT_LF_ADD_S },
+ { OR1K_INSN_LF_DIV_D32, OR1K32BF_INSN_LF_DIV_D32, OR1K32BF_SFMT_LF_ADD_D32 },
{ OR1K_INSN_LF_REM_S, OR1K32BF_INSN_LF_REM_S, OR1K32BF_SFMT_LF_ADD_S },
+ { OR1K_INSN_LF_REM_D32, OR1K32BF_INSN_LF_REM_D32, OR1K32BF_SFMT_LF_ADD_D32 },
{ OR1K_INSN_LF_ITOF_S, OR1K32BF_INSN_LF_ITOF_S, OR1K32BF_SFMT_LF_ITOF_S },
+ { OR1K_INSN_LF_ITOF_D32, OR1K32BF_INSN_LF_ITOF_D32, OR1K32BF_SFMT_LF_ITOF_D32 },
{ OR1K_INSN_LF_FTOI_S, OR1K32BF_INSN_LF_FTOI_S, OR1K32BF_SFMT_LF_FTOI_S },
- { OR1K_INSN_LF_EQ_S, OR1K32BF_INSN_LF_EQ_S, OR1K32BF_SFMT_LF_EQ_S },
- { OR1K_INSN_LF_NE_S, OR1K32BF_INSN_LF_NE_S, OR1K32BF_SFMT_LF_EQ_S },
- { OR1K_INSN_LF_GE_S, OR1K32BF_INSN_LF_GE_S, OR1K32BF_SFMT_LF_EQ_S },
- { OR1K_INSN_LF_GT_S, OR1K32BF_INSN_LF_GT_S, OR1K32BF_SFMT_LF_EQ_S },
- { OR1K_INSN_LF_LT_S, OR1K32BF_INSN_LF_LT_S, OR1K32BF_SFMT_LF_EQ_S },
- { OR1K_INSN_LF_LE_S, OR1K32BF_INSN_LF_LE_S, OR1K32BF_SFMT_LF_EQ_S },
+ { OR1K_INSN_LF_FTOI_D32, OR1K32BF_INSN_LF_FTOI_D32, OR1K32BF_SFMT_LF_FTOI_D32 },
+ { OR1K_INSN_LF_SFEQ_S, OR1K32BF_INSN_LF_SFEQ_S, OR1K32BF_SFMT_LF_SFEQ_S },
+ { OR1K_INSN_LF_SFEQ_D32, OR1K32BF_INSN_LF_SFEQ_D32, OR1K32BF_SFMT_LF_SFEQ_D32 },
+ { OR1K_INSN_LF_SFNE_S, OR1K32BF_INSN_LF_SFNE_S, OR1K32BF_SFMT_LF_SFEQ_S },
+ { OR1K_INSN_LF_SFNE_D32, OR1K32BF_INSN_LF_SFNE_D32, OR1K32BF_SFMT_LF_SFEQ_D32 },
+ { OR1K_INSN_LF_SFGE_S, OR1K32BF_INSN_LF_SFGE_S, OR1K32BF_SFMT_LF_SFEQ_S },
+ { OR1K_INSN_LF_SFGE_D32, OR1K32BF_INSN_LF_SFGE_D32, OR1K32BF_SFMT_LF_SFEQ_D32 },
+ { OR1K_INSN_LF_SFGT_S, OR1K32BF_INSN_LF_SFGT_S, OR1K32BF_SFMT_LF_SFEQ_S },
+ { OR1K_INSN_LF_SFGT_D32, OR1K32BF_INSN_LF_SFGT_D32, OR1K32BF_SFMT_LF_SFEQ_D32 },
+ { OR1K_INSN_LF_SFLT_S, OR1K32BF_INSN_LF_SFLT_S, OR1K32BF_SFMT_LF_SFEQ_S },
+ { OR1K_INSN_LF_SFLT_D32, OR1K32BF_INSN_LF_SFLT_D32, OR1K32BF_SFMT_LF_SFEQ_D32 },
+ { OR1K_INSN_LF_SFLE_S, OR1K32BF_INSN_LF_SFLE_S, OR1K32BF_SFMT_LF_SFEQ_S },
+ { OR1K_INSN_LF_SFLE_D32, OR1K32BF_INSN_LF_SFLE_D32, OR1K32BF_SFMT_LF_SFEQ_D32 },
+ { OR1K_INSN_LF_SFUEQ_S, OR1K32BF_INSN_LF_SFUEQ_S, OR1K32BF_SFMT_LF_SFEQ_S },
+ { OR1K_INSN_LF_SFUEQ_D32, OR1K32BF_INSN_LF_SFUEQ_D32, OR1K32BF_SFMT_LF_SFEQ_D32 },
+ { OR1K_INSN_LF_SFUNE_S, OR1K32BF_INSN_LF_SFUNE_S, OR1K32BF_SFMT_LF_SFEQ_S },
+ { OR1K_INSN_LF_SFUNE_D32, OR1K32BF_INSN_LF_SFUNE_D32, OR1K32BF_SFMT_LF_SFEQ_D32 },
+ { OR1K_INSN_LF_SFUGT_S, OR1K32BF_INSN_LF_SFUGT_S, OR1K32BF_SFMT_LF_SFEQ_S },
+ { OR1K_INSN_LF_SFUGT_D32, OR1K32BF_INSN_LF_SFUGT_D32, OR1K32BF_SFMT_LF_SFEQ_D32 },
+ { OR1K_INSN_LF_SFUGE_S, OR1K32BF_INSN_LF_SFUGE_S, OR1K32BF_SFMT_LF_SFEQ_S },
+ { OR1K_INSN_LF_SFUGE_D32, OR1K32BF_INSN_LF_SFUGE_D32, OR1K32BF_SFMT_LF_SFEQ_D32 },
+ { OR1K_INSN_LF_SFULT_S, OR1K32BF_INSN_LF_SFULT_S, OR1K32BF_SFMT_LF_SFEQ_S },
+ { OR1K_INSN_LF_SFULT_D32, OR1K32BF_INSN_LF_SFULT_D32, OR1K32BF_SFMT_LF_SFEQ_D32 },
+ { OR1K_INSN_LF_SFULE_S, OR1K32BF_INSN_LF_SFULE_S, OR1K32BF_SFMT_LF_SFEQ_S },
+ { OR1K_INSN_LF_SFULE_D32, OR1K32BF_INSN_LF_SFULE_D32, OR1K32BF_SFMT_LF_SFEQ_D32 },
+ { OR1K_INSN_LF_SFUN_S, OR1K32BF_INSN_LF_SFUN_S, OR1K32BF_SFMT_LF_SFEQ_S },
+ { OR1K_INSN_LF_SFUN_D32, OR1K32BF_INSN_LF_SFUN_D32, OR1K32BF_SFMT_LF_SFEQ_D32 },
{ OR1K_INSN_LF_MADD_S, OR1K32BF_INSN_LF_MADD_S, OR1K32BF_SFMT_LF_MADD_S },
+ { OR1K_INSN_LF_MADD_D32, OR1K32BF_INSN_LF_MADD_D32, OR1K32BF_SFMT_LF_MADD_D32 },
{ OR1K_INSN_LF_CUST1_S, OR1K32BF_INSN_LF_CUST1_S, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_LF_CUST1_D32, OR1K32BF_INSN_LF_CUST1_D32, OR1K32BF_SFMT_L_MSYNC },
};
static const struct insn_sem or1k32bf_insn_sem_invalid =
@@ -235,7 +264,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
CGEN_INSN_WORD insn = base_insn;
{
- unsigned int val = (((insn >> 21) & (63 << 5)) | ((insn >> 2) & (1 << 4)) | ((insn >> 0) & (15 << 0)));
+ unsigned int val = (((insn >> 21) & (63 << 5)) | ((insn >> 0) & (31 << 0)));
switch (val)
{
case 0 : /* fall through */
@@ -1083,22 +1112,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
case 1484 : /* fall through */
case 1485 : /* fall through */
case 1486 : /* fall through */
- case 1487 :
- {
- unsigned int val = (((insn >> 7) & (1 << 0)));
- switch (val)
- {
- case 0 :
- if ((entire_insn & 0xfc00ffc0) == 0xb8000000)
- { itype = OR1K32BF_INSN_L_SLLI; goto extract_sfmt_l_slli; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- case 1 :
- if ((entire_insn & 0xfc00ffc0) == 0xb8000080)
- { itype = OR1K32BF_INSN_L_SRAI; goto extract_sfmt_l_slli; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- }
- }
+ case 1487 : /* fall through */
case 1488 : /* fall through */
case 1489 : /* fall through */
case 1490 : /* fall through */
@@ -1116,14 +1130,22 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
case 1502 : /* fall through */
case 1503 :
{
- unsigned int val = (((insn >> 7) & (1 << 0)));
+ unsigned int val = (((insn >> 6) & (3 << 0)));
switch (val)
{
case 0 :
+ if ((entire_insn & 0xfc00ffc0) == 0xb8000000)
+ { itype = OR1K32BF_INSN_L_SLLI; goto extract_sfmt_l_slli; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
if ((entire_insn & 0xfc00ffc0) == 0xb8000040)
{ itype = OR1K32BF_INSN_L_SRLI; goto extract_sfmt_l_slli; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- case 1 :
+ case 2 :
+ if ((entire_insn & 0xfc00ffc0) == 0xb8000080)
+ { itype = OR1K32BF_INSN_L_SRAI; goto extract_sfmt_l_slli; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
if ((entire_insn & 0xfc00ffc0) == 0xb80000c0)
{ itype = OR1K32BF_INSN_L_RORI; goto extract_sfmt_l_slli; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
@@ -1258,9 +1280,21 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
{ itype = OR1K32BF_INSN_L_MSBU; goto extract_sfmt_l_macu; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1600 :
- if ((entire_insn & 0xfc0007ff) == 0xc8000000)
- { itype = OR1K32BF_INSN_LF_ADD_S; goto extract_sfmt_lf_add_s; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ {
+ unsigned int val = (((insn >> 5) & (7 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xfc0007ff) == 0xc8000000)
+ { itype = OR1K32BF_INSN_LF_ADD_S; goto extract_sfmt_lf_add_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 7 :
+ if ((entire_insn & 0xffe004ff) == 0xc80000e0)
+ { itype = OR1K32BF_INSN_LF_CUST1_D32; goto extract_sfmt_l_msync; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
case 1601 :
if ((entire_insn & 0xfc0007ff) == 0xc8000001)
{ itype = OR1K32BF_INSN_LF_SUB_S; goto extract_sfmt_lf_add_s; }
@@ -1290,32 +1324,248 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
{ itype = OR1K32BF_INSN_LF_MADD_S; goto extract_sfmt_lf_madd_s; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1608 :
- if ((entire_insn & 0xffe007ff) == 0xc8000008)
- { itype = OR1K32BF_INSN_LF_EQ_S; goto extract_sfmt_lf_eq_s; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ {
+ unsigned int val = (((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xffe007ff) == 0xc8000008)
+ { itype = OR1K32BF_INSN_LF_SFEQ_S; goto extract_sfmt_lf_sfeq_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xffe007ff) == 0xc8000028)
+ { itype = OR1K32BF_INSN_LF_SFUEQ_S; goto extract_sfmt_lf_sfeq_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
case 1609 :
- if ((entire_insn & 0xffe007ff) == 0xc8000009)
- { itype = OR1K32BF_INSN_LF_NE_S; goto extract_sfmt_lf_eq_s; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ {
+ unsigned int val = (((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xffe007ff) == 0xc8000009)
+ { itype = OR1K32BF_INSN_LF_SFNE_S; goto extract_sfmt_lf_sfeq_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xffe007ff) == 0xc8000029)
+ { itype = OR1K32BF_INSN_LF_SFUNE_S; goto extract_sfmt_lf_sfeq_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
case 1610 :
- if ((entire_insn & 0xffe007ff) == 0xc800000a)
- { itype = OR1K32BF_INSN_LF_GT_S; goto extract_sfmt_lf_eq_s; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ {
+ unsigned int val = (((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xffe007ff) == 0xc800000a)
+ { itype = OR1K32BF_INSN_LF_SFGT_S; goto extract_sfmt_lf_sfeq_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xffe007ff) == 0xc800002a)
+ { itype = OR1K32BF_INSN_LF_SFUGT_S; goto extract_sfmt_lf_sfeq_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
case 1611 :
- if ((entire_insn & 0xffe007ff) == 0xc800000b)
- { itype = OR1K32BF_INSN_LF_GE_S; goto extract_sfmt_lf_eq_s; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ {
+ unsigned int val = (((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xffe007ff) == 0xc800000b)
+ { itype = OR1K32BF_INSN_LF_SFGE_S; goto extract_sfmt_lf_sfeq_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xffe007ff) == 0xc800002b)
+ { itype = OR1K32BF_INSN_LF_SFUGE_S; goto extract_sfmt_lf_sfeq_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
case 1612 :
- if ((entire_insn & 0xffe007ff) == 0xc800000c)
- { itype = OR1K32BF_INSN_LF_LT_S; goto extract_sfmt_lf_eq_s; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ {
+ unsigned int val = (((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xffe007ff) == 0xc800000c)
+ { itype = OR1K32BF_INSN_LF_SFLT_S; goto extract_sfmt_lf_sfeq_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xffe007ff) == 0xc800002c)
+ { itype = OR1K32BF_INSN_LF_SFULT_S; goto extract_sfmt_lf_sfeq_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
case 1613 :
- if ((entire_insn & 0xffe007ff) == 0xc800000d)
- { itype = OR1K32BF_INSN_LF_LE_S; goto extract_sfmt_lf_eq_s; }
+ {
+ unsigned int val = (((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xffe007ff) == 0xc800000d)
+ { itype = OR1K32BF_INSN_LF_SFLE_S; goto extract_sfmt_lf_sfeq_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xffe007ff) == 0xc800002d)
+ { itype = OR1K32BF_INSN_LF_SFULE_S; goto extract_sfmt_lf_sfeq_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1614 :
+ if ((entire_insn & 0xffe007ff) == 0xc800002e)
+ { itype = OR1K32BF_INSN_LF_SFUN_S; goto extract_sfmt_lf_sfeq_s; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1616 :
- if ((entire_insn & 0xffe007ff) == 0xc80000d0)
- { itype = OR1K32BF_INSN_LF_CUST1_S; goto extract_sfmt_l_msync; }
+ {
+ unsigned int val = (((insn >> 6) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xfc0000ff) == 0xc8000010)
+ { itype = OR1K32BF_INSN_LF_ADD_D32; goto extract_sfmt_lf_add_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xffe007ff) == 0xc80000d0)
+ { itype = OR1K32BF_INSN_LF_CUST1_S; goto extract_sfmt_l_msync; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1617 :
+ if ((entire_insn & 0xfc0000ff) == 0xc8000011)
+ { itype = OR1K32BF_INSN_LF_SUB_D32; goto extract_sfmt_lf_add_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1618 :
+ if ((entire_insn & 0xfc0000ff) == 0xc8000012)
+ { itype = OR1K32BF_INSN_LF_MUL_D32; goto extract_sfmt_lf_add_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1619 :
+ if ((entire_insn & 0xfc0000ff) == 0xc8000013)
+ { itype = OR1K32BF_INSN_LF_DIV_D32; goto extract_sfmt_lf_add_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1620 :
+ if ((entire_insn & 0xfc00f9ff) == 0xc8000014)
+ { itype = OR1K32BF_INSN_LF_ITOF_D32; goto extract_sfmt_lf_itof_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1621 :
+ if ((entire_insn & 0xfc00f9ff) == 0xc8000015)
+ { itype = OR1K32BF_INSN_LF_FTOI_D32; goto extract_sfmt_lf_ftoi_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1622 :
+ if ((entire_insn & 0xfc0000ff) == 0xc8000016)
+ { itype = OR1K32BF_INSN_LF_REM_D32; goto extract_sfmt_lf_add_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1623 :
+ if ((entire_insn & 0xfc0000ff) == 0xc8000017)
+ { itype = OR1K32BF_INSN_LF_MADD_D32; goto extract_sfmt_lf_madd_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1624 :
+ {
+ unsigned int val = (((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xffe004ff) == 0xc8000018)
+ { itype = OR1K32BF_INSN_LF_SFEQ_D32; goto extract_sfmt_lf_sfeq_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xffe004ff) == 0xc8000038)
+ { itype = OR1K32BF_INSN_LF_SFUEQ_D32; goto extract_sfmt_lf_sfeq_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1625 :
+ {
+ unsigned int val = (((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xffe004ff) == 0xc8000019)
+ { itype = OR1K32BF_INSN_LF_SFNE_D32; goto extract_sfmt_lf_sfeq_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xffe004ff) == 0xc8000039)
+ { itype = OR1K32BF_INSN_LF_SFUNE_D32; goto extract_sfmt_lf_sfeq_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1626 :
+ {
+ unsigned int val = (((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xffe004ff) == 0xc800001a)
+ { itype = OR1K32BF_INSN_LF_SFGT_D32; goto extract_sfmt_lf_sfeq_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xffe004ff) == 0xc800003a)
+ { itype = OR1K32BF_INSN_LF_SFUGT_D32; goto extract_sfmt_lf_sfeq_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1627 :
+ {
+ unsigned int val = (((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xffe004ff) == 0xc800001b)
+ { itype = OR1K32BF_INSN_LF_SFGE_D32; goto extract_sfmt_lf_sfeq_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xffe004ff) == 0xc800003b)
+ { itype = OR1K32BF_INSN_LF_SFUGE_D32; goto extract_sfmt_lf_sfeq_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1628 :
+ {
+ unsigned int val = (((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xffe004ff) == 0xc800001c)
+ { itype = OR1K32BF_INSN_LF_SFLT_D32; goto extract_sfmt_lf_sfeq_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xffe004ff) == 0xc800003c)
+ { itype = OR1K32BF_INSN_LF_SFULT_D32; goto extract_sfmt_lf_sfeq_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1629 :
+ {
+ unsigned int val = (((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xffe004ff) == 0xc800001d)
+ { itype = OR1K32BF_INSN_LF_SFLE_D32; goto extract_sfmt_lf_sfeq_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xffe004ff) == 0xc800003d)
+ { itype = OR1K32BF_INSN_LF_SFULE_D32; goto extract_sfmt_lf_sfeq_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1630 :
+ if ((entire_insn & 0xffe004ff) == 0xc800003e)
+ { itype = OR1K32BF_INSN_LF_SFUN_D32; goto extract_sfmt_lf_sfeq_d32; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1632 : /* fall through */
case 1633 : /* fall through */
@@ -1479,7 +1729,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1800 :
{
- unsigned int val = (((insn >> 7) & (1 << 0)));
+ unsigned int val = (((insn >> 6) & (3 << 0)));
switch (val)
{
case 0 :
@@ -1487,9 +1737,17 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
{ itype = OR1K32BF_INSN_L_SLL; goto extract_sfmt_l_sll; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1 :
+ if ((entire_insn & 0xfc0007ff) == 0xe0000048)
+ { itype = OR1K32BF_INSN_L_SRL; goto extract_sfmt_l_sll; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
if ((entire_insn & 0xfc0007ff) == 0xe0000088)
{ itype = OR1K32BF_INSN_L_SRA; goto extract_sfmt_l_sll; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xfc0007ff) == 0xe00000c8)
+ { itype = OR1K32BF_INSN_L_ROR; goto extract_sfmt_l_sll; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
@@ -1507,7 +1765,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1804 :
{
- unsigned int val = (((insn >> 7) & (1 << 0)));
+ unsigned int val = (((insn >> 6) & (3 << 0)));
switch (val)
{
case 0 :
@@ -1515,22 +1773,34 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
{ itype = OR1K32BF_INSN_L_EXTHS; goto extract_sfmt_l_exths; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1 :
+ if ((entire_insn & 0xfc00ffff) == 0xe000004c)
+ { itype = OR1K32BF_INSN_L_EXTBS; goto extract_sfmt_l_exths; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
if ((entire_insn & 0xfc00ffff) == 0xe000008c)
{ itype = OR1K32BF_INSN_L_EXTHZ; goto extract_sfmt_l_exths; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xfc00ffff) == 0xe00000cc)
+ { itype = OR1K32BF_INSN_L_EXTBZ; goto extract_sfmt_l_exths; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
case 1805 :
{
- unsigned int val = (((insn >> 8) & (3 << 0)));
+ unsigned int val = (((insn >> 7) & (3 << 1)) | ((insn >> 6) & (1 << 0)));
switch (val)
{
case 0 :
if ((entire_insn & 0xfc00ffff) == 0xe000000d)
{ itype = OR1K32BF_INSN_L_EXTWS; goto extract_sfmt_l_exths; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- case 3 :
+ case 1 :
+ if ((entire_insn & 0xfc00ffff) == 0xe000004d)
+ { itype = OR1K32BF_INSN_L_EXTWZ; goto extract_sfmt_l_exths; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
if ((entire_insn & 0xffe007ff) == 0xe000030d)
{ itype = OR1K32BF_INSN_L_MULDU; goto extract_sfmt_l_muld; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
@@ -1557,42 +1827,6 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
- case 1816 :
- {
- unsigned int val = (((insn >> 7) & (1 << 0)));
- switch (val)
- {
- case 0 :
- if ((entire_insn & 0xfc0007ff) == 0xe0000048)
- { itype = OR1K32BF_INSN_L_SRL; goto extract_sfmt_l_sll; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- case 1 :
- if ((entire_insn & 0xfc0007ff) == 0xe00000c8)
- { itype = OR1K32BF_INSN_L_ROR; goto extract_sfmt_l_sll; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- }
- }
- case 1820 :
- {
- unsigned int val = (((insn >> 7) & (1 << 0)));
- switch (val)
- {
- case 0 :
- if ((entire_insn & 0xfc00ffff) == 0xe000004c)
- { itype = OR1K32BF_INSN_L_EXTBS; goto extract_sfmt_l_exths; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- case 1 :
- if ((entire_insn & 0xfc00ffff) == 0xe00000cc)
- { itype = OR1K32BF_INSN_L_EXTBZ; goto extract_sfmt_l_exths; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- }
- }
- case 1821 :
- if ((entire_insn & 0xfc00ffff) == 0xe000004d)
- { itype = OR1K32BF_INSN_L_EXTWZ; goto extract_sfmt_l_exths; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1824 :
{
unsigned int val = (((insn >> 21) & (15 << 0)));
@@ -2682,6 +2916,41 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
FLD (f_r1) = f_r1;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_add_s", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lf_add_d32:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_r3;
+ UINT f_rdoff_10_1;
+ UINT f_raoff_9_1;
+ UINT f_rboff_8_1;
+ SI f_rdd32;
+ SI f_rad32;
+ SI f_rbd32;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+ f_rdoff_10_1 = EXTRACT_LSB0_UINT (insn, 32, 10, 1);
+ f_raoff_9_1 = EXTRACT_LSB0_UINT (insn, 32, 9, 1);
+ f_rboff_8_1 = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+ f_rdd32 = ((f_r1) | (((f_rdoff_10_1) << (5))));
+ f_rad32 = ((f_r2) | (((f_raoff_9_1) << (5))));
+ f_rbd32 = ((f_r3) | (((f_rboff_8_1) << (5))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rad32) = f_rad32;
+ FLD (f_rbd32) = f_rbd32;
+ FLD (f_rdd32) = f_rdd32;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_add_d32", "f_rad32 0x%x", 'x', f_rad32, "f_rbd32 0x%x", 'x', f_rbd32, "f_rdd32 0x%x", 'x', f_rdd32, (char *) 0));
+
#undef FLD
return idesc;
}
@@ -2702,6 +2971,34 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
FLD (f_r1) = f_r1;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_itof_s", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lf_itof_d32:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_rdoff_10_1;
+ UINT f_raoff_9_1;
+ SI f_rdd32;
+ SI f_rad32;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_rdoff_10_1 = EXTRACT_LSB0_UINT (insn, 32, 10, 1);
+ f_raoff_9_1 = EXTRACT_LSB0_UINT (insn, 32, 9, 1);
+ f_rdd32 = ((f_r1) | (((f_rdoff_10_1) << (5))));
+ f_rad32 = ((f_r2) | (((f_raoff_9_1) << (5))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rad32) = f_rad32;
+ FLD (f_rdd32) = f_rdd32;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_itof_d32", "f_rad32 0x%x", 'x', f_rad32, "f_rdd32 0x%x", 'x', f_rdd32, (char *) 0));
+
#undef FLD
return idesc;
}
@@ -2726,7 +3023,35 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
return idesc;
}
- extract_sfmt_lf_eq_s:
+ extract_sfmt_lf_ftoi_d32:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_rdoff_10_1;
+ UINT f_raoff_9_1;
+ SI f_rdd32;
+ SI f_rad32;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_rdoff_10_1 = EXTRACT_LSB0_UINT (insn, 32, 10, 1);
+ f_raoff_9_1 = EXTRACT_LSB0_UINT (insn, 32, 9, 1);
+ f_rdd32 = ((f_r1) | (((f_rdoff_10_1) << (5))));
+ f_rad32 = ((f_r2) | (((f_raoff_9_1) << (5))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rad32) = f_rad32;
+ FLD (f_rdd32) = f_rdd32;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_ftoi_d32", "f_rad32 0x%x", 'x', f_rad32, "f_rdd32 0x%x", 'x', f_rdd32, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lf_sfeq_s:
{
const IDESC *idesc = &or1k32bf_insn_data[itype];
CGEN_INSN_WORD insn = entire_insn;
@@ -2740,7 +3065,35 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
/* Record the fields for the semantic handler. */
FLD (f_r2) = f_r2;
FLD (f_r3) = f_r3;
- TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_eq_s", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, (char *) 0));
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_sfeq_s", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lf_sfeq_d32:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ UINT f_r2;
+ UINT f_r3;
+ UINT f_raoff_9_1;
+ UINT f_rboff_8_1;
+ SI f_rad32;
+ SI f_rbd32;
+
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+ f_raoff_9_1 = EXTRACT_LSB0_UINT (insn, 32, 9, 1);
+ f_rboff_8_1 = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+ f_rad32 = ((f_r2) | (((f_raoff_9_1) << (5))));
+ f_rbd32 = ((f_r3) | (((f_rboff_8_1) << (5))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rad32) = f_rad32;
+ FLD (f_rbd32) = f_rbd32;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_sfeq_d32", "f_rad32 0x%x", 'x', f_rad32, "f_rbd32 0x%x", 'x', f_rbd32, (char *) 0));
#undef FLD
return idesc;
@@ -2765,6 +3118,41 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
FLD (f_r1) = f_r1;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_madd_s", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lf_madd_d32:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_r3;
+ UINT f_rdoff_10_1;
+ UINT f_raoff_9_1;
+ UINT f_rboff_8_1;
+ SI f_rdd32;
+ SI f_rad32;
+ SI f_rbd32;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+ f_rdoff_10_1 = EXTRACT_LSB0_UINT (insn, 32, 10, 1);
+ f_raoff_9_1 = EXTRACT_LSB0_UINT (insn, 32, 9, 1);
+ f_rboff_8_1 = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+ f_rdd32 = ((f_r1) | (((f_rdoff_10_1) << (5))));
+ f_rad32 = ((f_r2) | (((f_raoff_9_1) << (5))));
+ f_rbd32 = ((f_r3) | (((f_rboff_8_1) << (5))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rad32) = f_rad32;
+ FLD (f_rbd32) = f_rbd32;
+ FLD (f_rdd32) = f_rdd32;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_madd_d32", "f_rad32 0x%x", 'x', f_rad32, "f_rbd32 0x%x", 'x', f_rbd32, "f_rdd32 0x%x", 'x', f_rdd32, (char *) 0));
+
#undef FLD
return idesc;
}
diff --git a/sim/or1k/decode.h b/sim/or1k/decode.h
index 8650bdfa0e..b338ba69c2 100644
--- a/sim/or1k/decode.h
+++ b/sim/or1k/decode.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2019 Free Software Foundation, Inc.
+Copyright (C) 1996-2019 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -60,10 +60,17 @@ typedef enum or1k32bf_insn_type {
, OR1K32BF_INSN_L_MACU, OR1K32BF_INSN_L_MSB, OR1K32BF_INSN_L_MSBU, OR1K32BF_INSN_L_CUST1
, OR1K32BF_INSN_L_CUST2, OR1K32BF_INSN_L_CUST3, OR1K32BF_INSN_L_CUST4, OR1K32BF_INSN_L_CUST5
, OR1K32BF_INSN_L_CUST6, OR1K32BF_INSN_L_CUST7, OR1K32BF_INSN_L_CUST8, OR1K32BF_INSN_LF_ADD_S
- , OR1K32BF_INSN_LF_SUB_S, OR1K32BF_INSN_LF_MUL_S, OR1K32BF_INSN_LF_DIV_S, OR1K32BF_INSN_LF_REM_S
- , OR1K32BF_INSN_LF_ITOF_S, OR1K32BF_INSN_LF_FTOI_S, OR1K32BF_INSN_LF_EQ_S, OR1K32BF_INSN_LF_NE_S
- , OR1K32BF_INSN_LF_GE_S, OR1K32BF_INSN_LF_GT_S, OR1K32BF_INSN_LF_LT_S, OR1K32BF_INSN_LF_LE_S
- , OR1K32BF_INSN_LF_MADD_S, OR1K32BF_INSN_LF_CUST1_S, OR1K32BF_INSN__MAX
+ , OR1K32BF_INSN_LF_ADD_D32, OR1K32BF_INSN_LF_SUB_S, OR1K32BF_INSN_LF_SUB_D32, OR1K32BF_INSN_LF_MUL_S
+ , OR1K32BF_INSN_LF_MUL_D32, OR1K32BF_INSN_LF_DIV_S, OR1K32BF_INSN_LF_DIV_D32, OR1K32BF_INSN_LF_REM_S
+ , OR1K32BF_INSN_LF_REM_D32, OR1K32BF_INSN_LF_ITOF_S, OR1K32BF_INSN_LF_ITOF_D32, OR1K32BF_INSN_LF_FTOI_S
+ , OR1K32BF_INSN_LF_FTOI_D32, OR1K32BF_INSN_LF_SFEQ_S, OR1K32BF_INSN_LF_SFEQ_D32, OR1K32BF_INSN_LF_SFNE_S
+ , OR1K32BF_INSN_LF_SFNE_D32, OR1K32BF_INSN_LF_SFGE_S, OR1K32BF_INSN_LF_SFGE_D32, OR1K32BF_INSN_LF_SFGT_S
+ , OR1K32BF_INSN_LF_SFGT_D32, OR1K32BF_INSN_LF_SFLT_S, OR1K32BF_INSN_LF_SFLT_D32, OR1K32BF_INSN_LF_SFLE_S
+ , OR1K32BF_INSN_LF_SFLE_D32, OR1K32BF_INSN_LF_SFUEQ_S, OR1K32BF_INSN_LF_SFUEQ_D32, OR1K32BF_INSN_LF_SFUNE_S
+ , OR1K32BF_INSN_LF_SFUNE_D32, OR1K32BF_INSN_LF_SFUGT_S, OR1K32BF_INSN_LF_SFUGT_D32, OR1K32BF_INSN_LF_SFUGE_S
+ , OR1K32BF_INSN_LF_SFUGE_D32, OR1K32BF_INSN_LF_SFULT_S, OR1K32BF_INSN_LF_SFULT_D32, OR1K32BF_INSN_LF_SFULE_S
+ , OR1K32BF_INSN_LF_SFULE_D32, OR1K32BF_INSN_LF_SFUN_S, OR1K32BF_INSN_LF_SFUN_D32, OR1K32BF_INSN_LF_MADD_S
+ , OR1K32BF_INSN_LF_MADD_D32, OR1K32BF_INSN_LF_CUST1_S, OR1K32BF_INSN_LF_CUST1_D32, OR1K32BF_INSN__MAX
} OR1K32BF_INSN_TYPE;
/* Enum declaration for semantic formats in cpu family or1k32bf. */
@@ -80,7 +87,9 @@ typedef enum or1k32bf_sfmt_type {
, OR1K32BF_SFMT_L_XORI, OR1K32BF_SFMT_L_ADDI, OR1K32BF_SFMT_L_ADDIC, OR1K32BF_SFMT_L_MULI
, OR1K32BF_SFMT_L_EXTHS, OR1K32BF_SFMT_L_CMOV, OR1K32BF_SFMT_L_SFGTS, OR1K32BF_SFMT_L_SFGTSI
, OR1K32BF_SFMT_L_MAC, OR1K32BF_SFMT_L_MACI, OR1K32BF_SFMT_L_MACU, OR1K32BF_SFMT_LF_ADD_S
- , OR1K32BF_SFMT_LF_ITOF_S, OR1K32BF_SFMT_LF_FTOI_S, OR1K32BF_SFMT_LF_EQ_S, OR1K32BF_SFMT_LF_MADD_S
+ , OR1K32BF_SFMT_LF_ADD_D32, OR1K32BF_SFMT_LF_ITOF_S, OR1K32BF_SFMT_LF_ITOF_D32, OR1K32BF_SFMT_LF_FTOI_S
+ , OR1K32BF_SFMT_LF_FTOI_D32, OR1K32BF_SFMT_LF_SFEQ_S, OR1K32BF_SFMT_LF_SFEQ_D32, OR1K32BF_SFMT_LF_MADD_S
+ , OR1K32BF_SFMT_LF_MADD_D32
} OR1K32BF_SFMT_TYPE;
/* Function unit handlers (user written). */
diff --git a/sim/or1k/model.c b/sim/or1k/model.c
index 461ba4bb00..255023d4c2 100644
--- a/sim/or1k/model.c
+++ b/sim/or1k/model.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2019 Free Software Foundation, Inc.
+Copyright (C) 1996-2019 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -1602,6 +1602,22 @@ model_or1200_lf_add_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_add_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200_lf_sub_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -1618,6 +1634,22 @@ model_or1200_lf_sub_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_sub_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200_lf_mul_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -1634,6 +1666,22 @@ model_or1200_lf_mul_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_mul_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200_lf_div_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -1650,6 +1698,22 @@ model_or1200_lf_div_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_div_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200_lf_rem_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -1666,6 +1730,22 @@ model_or1200_lf_rem_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_rem_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200_lf_itof_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -1682,6 +1762,22 @@ model_or1200_lf_itof_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_itof_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200_lf_ftoi_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -1699,9 +1795,9 @@ model_or1200_lf_ftoi_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_lf_eq_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_ftoi_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1715,7 +1811,7 @@ model_or1200_lf_eq_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_lf_ne_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sfeq_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -1731,9 +1827,9 @@ model_or1200_lf_ne_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_lf_ge_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sfeq_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1747,7 +1843,7 @@ model_or1200_lf_ge_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_lf_gt_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sfne_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -1763,7 +1859,23 @@ model_or1200_lf_gt_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_lf_lt_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sfne_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_lf_sfge_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -1779,7 +1891,23 @@ model_or1200_lf_lt_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_lf_le_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sfge_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_lf_sfgt_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -1795,7 +1923,23 @@ model_or1200_lf_le_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_lf_madd_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sfgt_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_lf_sflt_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -1811,9 +1955,9 @@ model_or1200_lf_madd_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_lf_cust1_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sflt_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_empty.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1827,55 +1971,71 @@ model_or1200_lf_cust1_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_j (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sfle_s (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_j.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_or1200nd_l_adrp (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sfle_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_adrp.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_or1200nd_l_jal (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sfueq_s (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_j.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_or1200nd_l_jr (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sfueq_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_lf_sfune_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -1884,14 +2044,30 @@ model_or1200nd_l_jr (SIM_CPU *current_cpu, void *sem_arg)
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_or1200nd_l_jalr (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sfune_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_lf_sfugt_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -1900,208 +2076,224 @@ model_or1200nd_l_jalr (SIM_CPU *current_cpu, void *sem_arg)
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_or1200nd_l_bnf (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sfugt_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_j.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_or1200nd_l_bf (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sfuge_s (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_j.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_or1200nd_l_trap (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sfuge_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_empty.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_or1200nd_l_sys (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sfult_s (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_empty.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_or1200nd_l_msync (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sfult_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_empty.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_or1200nd_l_psync (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sfule_s (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_empty.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_or1200nd_l_csync (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sfule_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_empty.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_or1200nd_l_rfe (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sfun_s (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_empty.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_or1200nd_l_nop_imm (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_sfun_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_or1200nd_l_movhi (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_madd_s (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_or1200nd_l_macrc (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_madd_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_adrp.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_or1200nd_l_mfspr (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_cust1_s (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_or1200nd_l_mtspr (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_lf_cust1_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mtspr.f
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_j (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_j.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2115,7 +2307,375 @@ model_or1200nd_l_mtspr (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_lwz (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_adrp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_adrp.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_jal (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_jr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_jalr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_bnf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_bf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_trap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sys (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_msync (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_psync (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_csync (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_rfe (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_nop_imm (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_movhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_macrc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_adrp.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_mfspr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_mtspr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mtspr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_lwz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_lws (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_lwa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_lbz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_lbs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_lhz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_lhs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2131,9 +2691,377 @@ model_or1200nd_l_lwz (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_lws (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_swa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_slli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_srl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_srli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_srai (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_ror (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_rori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_and (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_or (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_xor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_add (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_addc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_mul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_muld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_mulu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_muldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_div (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_divu (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2147,9 +3075,9 @@ model_or1200nd_l_lws (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_lwa (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_ff1 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_l_slli.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2163,9 +3091,9 @@ model_or1200nd_l_lwa (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_lbz (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_fl1 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_l_slli.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2179,9 +3107,9 @@ model_or1200nd_l_lbz (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_lbs (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_andi (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2195,9 +3123,9 @@ model_or1200nd_l_lbs (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_lhz (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_ori (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2211,7 +3139,7 @@ model_or1200nd_l_lhz (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_lhs (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_xori (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2227,9 +3155,9 @@ model_or1200nd_l_lhs (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sw (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_addi (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sw.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2243,9 +3171,9 @@ model_or1200nd_l_sw (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sb (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_addic (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sw.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2259,9 +3187,9 @@ model_or1200nd_l_sb (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sh (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_muli (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sw.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2275,9 +3203,9 @@ model_or1200nd_l_sh (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_swa (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_exths (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sw.f
+#define FLD(f) abuf->fields.sfmt_l_slli.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2291,9 +3219,9 @@ model_or1200nd_l_swa (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sll (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_extbs (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_slli.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2307,7 +3235,7 @@ model_or1200nd_l_sll (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_slli (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_exthz (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_slli.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2323,9 +3251,9 @@ model_or1200nd_l_slli (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_srl (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_extbz (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_slli.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2339,7 +3267,7 @@ model_or1200nd_l_srl (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_srli (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_extws (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_slli.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2355,9 +3283,9 @@ model_or1200nd_l_srli (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sra (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_extwz (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_slli.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2371,9 +3299,9 @@ model_or1200nd_l_sra (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_srai (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_cmov (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_slli.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2387,7 +3315,7 @@ model_or1200nd_l_srai (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_ror (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfgts (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2403,9 +3331,9 @@ model_or1200nd_l_ror (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_rori (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfgtsi (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_slli.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2419,7 +3347,7 @@ model_or1200nd_l_rori (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_and (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfgtu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2435,9 +3363,9 @@ model_or1200nd_l_and (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_or (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfgtui (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2451,7 +3379,7 @@ model_or1200nd_l_or (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_xor (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfges (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2467,9 +3395,9 @@ model_or1200nd_l_xor (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_add (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfgesi (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2483,7 +3411,7 @@ model_or1200nd_l_add (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sub (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfgeu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2499,9 +3427,9 @@ model_or1200nd_l_sub (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_addc (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfgeui (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2515,7 +3443,7 @@ model_or1200nd_l_addc (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_mul (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sflts (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2531,9 +3459,9 @@ model_or1200nd_l_mul (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_muld (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfltsi (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2547,7 +3475,7 @@ model_or1200nd_l_muld (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_mulu (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfltu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2563,9 +3491,9 @@ model_or1200nd_l_mulu (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_muldu (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfltui (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2579,7 +3507,7 @@ model_or1200nd_l_muldu (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_div (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfles (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2595,9 +3523,9 @@ model_or1200nd_l_div (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_divu (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sflesi (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2611,9 +3539,9 @@ model_or1200nd_l_divu (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_ff1 (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfleu (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_slli.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2627,9 +3555,9 @@ model_or1200nd_l_ff1 (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_fl1 (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfleui (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_slli.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2643,9 +3571,9 @@ model_or1200nd_l_fl1 (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_andi (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfeq (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2659,9 +3587,9 @@ model_or1200nd_l_andi (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_ori (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfeqi (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2675,9 +3603,9 @@ model_or1200nd_l_ori (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_xori (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfne (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2691,7 +3619,7 @@ model_or1200nd_l_xori (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_addi (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfnei (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2707,9 +3635,9 @@ model_or1200nd_l_addi (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_addic (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_mac (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2723,7 +3651,7 @@ model_or1200nd_l_addic (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_muli (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_maci (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2739,9 +3667,9 @@ model_or1200nd_l_muli (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_exths (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_macu (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_slli.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2755,9 +3683,9 @@ model_or1200nd_l_exths (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_extbs (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_msb (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_slli.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2771,9 +3699,9 @@ model_or1200nd_l_extbs (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_exthz (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_msbu (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_slli.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2787,9 +3715,9 @@ model_or1200nd_l_exthz (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_extbz (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_cust1 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_slli.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2803,9 +3731,9 @@ model_or1200nd_l_extbz (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_extws (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_cust2 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_slli.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2819,9 +3747,9 @@ model_or1200nd_l_extws (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_extwz (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_cust3 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_slli.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2835,9 +3763,9 @@ model_or1200nd_l_extwz (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_cmov (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_cust4 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2851,9 +3779,9 @@ model_or1200nd_l_cmov (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfgts (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_cust5 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2867,9 +3795,9 @@ model_or1200nd_l_sfgts (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfgtsi (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_cust6 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2883,9 +3811,9 @@ model_or1200nd_l_sfgtsi (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfgtu (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_cust7 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2899,9 +3827,9 @@ model_or1200nd_l_sfgtu (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfgtui (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_cust8 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2915,7 +3843,7 @@ model_or1200nd_l_sfgtui (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfges (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_add_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2931,9 +3859,9 @@ model_or1200nd_l_sfges (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfgesi (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_add_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2947,7 +3875,7 @@ model_or1200nd_l_sfgesi (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfgeu (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sub_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2963,9 +3891,9 @@ model_or1200nd_l_sfgeu (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfgeui (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sub_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2979,7 +3907,7 @@ model_or1200nd_l_sfgeui (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sflts (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_mul_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2995,9 +3923,9 @@ model_or1200nd_l_sflts (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfltsi (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_mul_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3011,7 +3939,7 @@ model_or1200nd_l_sfltsi (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfltu (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_div_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -3027,9 +3955,9 @@ model_or1200nd_l_sfltu (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfltui (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_div_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3043,7 +3971,7 @@ model_or1200nd_l_sfltui (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfles (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_rem_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -3059,9 +3987,9 @@ model_or1200nd_l_sfles (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sflesi (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_rem_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3075,9 +4003,9 @@ model_or1200nd_l_sflesi (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfleu (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_itof_s (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_slli.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3091,9 +4019,9 @@ model_or1200nd_l_sfleu (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfleui (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_itof_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3107,9 +4035,9 @@ model_or1200nd_l_sfleui (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfeq (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_ftoi_s (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_slli.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3123,9 +4051,9 @@ model_or1200nd_l_sfeq (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfeqi (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_ftoi_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3139,7 +4067,7 @@ model_or1200nd_l_sfeqi (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfne (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfeq_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -3155,9 +4083,9 @@ model_or1200nd_l_sfne (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfnei (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfeq_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3171,7 +4099,7 @@ model_or1200nd_l_sfnei (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_mac (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfne_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -3187,9 +4115,9 @@ model_or1200nd_l_mac (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_maci (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfne_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3203,7 +4131,7 @@ model_or1200nd_l_maci (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_macu (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfge_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -3219,9 +4147,9 @@ model_or1200nd_l_macu (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_msb (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfge_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3235,7 +4163,7 @@ model_or1200nd_l_msb (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_msbu (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfgt_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -3251,9 +4179,9 @@ model_or1200nd_l_msbu (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_cust1 (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfgt_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_empty.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3267,9 +4195,9 @@ model_or1200nd_l_cust1 (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_cust2 (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sflt_s (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_empty.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3283,9 +4211,9 @@ model_or1200nd_l_cust2 (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_cust3 (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sflt_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_empty.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3299,9 +4227,9 @@ model_or1200nd_l_cust3 (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_cust4 (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfle_s (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_empty.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3315,9 +4243,9 @@ model_or1200nd_l_cust4 (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_cust5 (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfle_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_empty.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3331,9 +4259,9 @@ model_or1200nd_l_cust5 (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_cust6 (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfueq_s (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_empty.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3347,9 +4275,9 @@ model_or1200nd_l_cust6 (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_cust7 (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfueq_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_empty.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3363,9 +4291,9 @@ model_or1200nd_l_cust7 (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_cust8 (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfune_s (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_empty.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3379,9 +4307,9 @@ model_or1200nd_l_cust8 (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_lf_add_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfune_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3395,7 +4323,7 @@ model_or1200nd_lf_add_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_lf_sub_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfugt_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -3411,9 +4339,9 @@ model_or1200nd_lf_sub_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_lf_mul_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfugt_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3427,7 +4355,7 @@ model_or1200nd_lf_mul_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_lf_div_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfuge_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -3443,9 +4371,9 @@ model_or1200nd_lf_div_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_lf_rem_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfuge_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3459,9 +4387,9 @@ model_or1200nd_lf_rem_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_lf_itof_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfult_s (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_slli.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3475,9 +4403,9 @@ model_or1200nd_lf_itof_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_lf_ftoi_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfult_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_slli.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3491,7 +4419,7 @@ model_or1200nd_lf_ftoi_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_lf_eq_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfule_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -3507,9 +4435,9 @@ model_or1200nd_lf_eq_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_lf_ne_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfule_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3523,7 +4451,7 @@ model_or1200nd_lf_ne_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_lf_ge_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfun_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -3539,9 +4467,9 @@ model_or1200nd_lf_ge_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_lf_gt_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_sfun_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3555,7 +4483,7 @@ model_or1200nd_lf_gt_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_lf_lt_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_madd_s (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -3571,9 +4499,9 @@ model_or1200nd_lf_lt_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_lf_le_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_madd_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3587,9 +4515,9 @@ model_or1200nd_lf_le_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_lf_madd_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_cust1_s (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3603,7 +4531,7 @@ model_or1200nd_lf_madd_s (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_lf_cust1_s (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_lf_cust1_d32 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -3728,20 +4656,49 @@ static const INSN_TIMING or1200_timing[] = {
{ OR1K32BF_INSN_L_CUST7, model_or1200_l_cust7, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_CUST8, model_or1200_l_cust8, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_ADD_S, model_or1200_lf_add_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_ADD_D32, model_or1200_lf_add_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_SUB_S, model_or1200_lf_sub_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SUB_D32, model_or1200_lf_sub_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_MUL_S, model_or1200_lf_mul_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_MUL_D32, model_or1200_lf_mul_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_DIV_S, model_or1200_lf_div_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_DIV_D32, model_or1200_lf_div_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_REM_S, model_or1200_lf_rem_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_REM_D32, model_or1200_lf_rem_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_ITOF_S, model_or1200_lf_itof_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_ITOF_D32, model_or1200_lf_itof_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_FTOI_S, model_or1200_lf_ftoi_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_LF_EQ_S, model_or1200_lf_eq_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_LF_NE_S, model_or1200_lf_ne_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_LF_GE_S, model_or1200_lf_ge_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_LF_GT_S, model_or1200_lf_gt_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_LF_LT_S, model_or1200_lf_lt_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_LF_LE_S, model_or1200_lf_le_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_FTOI_D32, model_or1200_lf_ftoi_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFEQ_S, model_or1200_lf_sfeq_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFEQ_D32, model_or1200_lf_sfeq_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFNE_S, model_or1200_lf_sfne_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFNE_D32, model_or1200_lf_sfne_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFGE_S, model_or1200_lf_sfge_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFGE_D32, model_or1200_lf_sfge_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFGT_S, model_or1200_lf_sfgt_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFGT_D32, model_or1200_lf_sfgt_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFLT_S, model_or1200_lf_sflt_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFLT_D32, model_or1200_lf_sflt_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFLE_S, model_or1200_lf_sfle_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFLE_D32, model_or1200_lf_sfle_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFUEQ_S, model_or1200_lf_sfueq_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFUEQ_D32, model_or1200_lf_sfueq_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFUNE_S, model_or1200_lf_sfune_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFUNE_D32, model_or1200_lf_sfune_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFUGT_S, model_or1200_lf_sfugt_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFUGT_D32, model_or1200_lf_sfugt_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFUGE_S, model_or1200_lf_sfuge_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFUGE_D32, model_or1200_lf_sfuge_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFULT_S, model_or1200_lf_sfult_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFULT_D32, model_or1200_lf_sfult_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFULE_S, model_or1200_lf_sfule_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFULE_D32, model_or1200_lf_sfule_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFUN_S, model_or1200_lf_sfun_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFUN_D32, model_or1200_lf_sfun_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_MADD_S, model_or1200_lf_madd_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_MADD_D32, model_or1200_lf_madd_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_CUST1_S, model_or1200_lf_cust1_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_CUST1_D32, model_or1200_lf_cust1_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
};
/* Model timing data for `or1200nd'. */
@@ -3851,20 +4808,49 @@ static const INSN_TIMING or1200nd_timing[] = {
{ OR1K32BF_INSN_L_CUST7, model_or1200nd_l_cust7, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_CUST8, model_or1200nd_l_cust8, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_ADD_S, model_or1200nd_lf_add_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_ADD_D32, model_or1200nd_lf_add_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_SUB_S, model_or1200nd_lf_sub_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SUB_D32, model_or1200nd_lf_sub_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_MUL_S, model_or1200nd_lf_mul_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_MUL_D32, model_or1200nd_lf_mul_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_DIV_S, model_or1200nd_lf_div_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_DIV_D32, model_or1200nd_lf_div_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_REM_S, model_or1200nd_lf_rem_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_REM_D32, model_or1200nd_lf_rem_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_ITOF_S, model_or1200nd_lf_itof_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_ITOF_D32, model_or1200nd_lf_itof_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_FTOI_S, model_or1200nd_lf_ftoi_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_LF_EQ_S, model_or1200nd_lf_eq_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_LF_NE_S, model_or1200nd_lf_ne_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_LF_GE_S, model_or1200nd_lf_ge_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_LF_GT_S, model_or1200nd_lf_gt_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_LF_LT_S, model_or1200nd_lf_lt_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_LF_LE_S, model_or1200nd_lf_le_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_FTOI_D32, model_or1200nd_lf_ftoi_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFEQ_S, model_or1200nd_lf_sfeq_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFEQ_D32, model_or1200nd_lf_sfeq_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFNE_S, model_or1200nd_lf_sfne_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFNE_D32, model_or1200nd_lf_sfne_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFGE_S, model_or1200nd_lf_sfge_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFGE_D32, model_or1200nd_lf_sfge_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFGT_S, model_or1200nd_lf_sfgt_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFGT_D32, model_or1200nd_lf_sfgt_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFLT_S, model_or1200nd_lf_sflt_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFLT_D32, model_or1200nd_lf_sflt_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFLE_S, model_or1200nd_lf_sfle_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFLE_D32, model_or1200nd_lf_sfle_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFUEQ_S, model_or1200nd_lf_sfueq_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFUEQ_D32, model_or1200nd_lf_sfueq_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFUNE_S, model_or1200nd_lf_sfune_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFUNE_D32, model_or1200nd_lf_sfune_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFUGT_S, model_or1200nd_lf_sfugt_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFUGT_D32, model_or1200nd_lf_sfugt_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFUGE_S, model_or1200nd_lf_sfuge_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFUGE_D32, model_or1200nd_lf_sfuge_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFULT_S, model_or1200nd_lf_sfult_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFULT_D32, model_or1200nd_lf_sfult_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFULE_S, model_or1200nd_lf_sfule_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFULE_D32, model_or1200nd_lf_sfule_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFUN_S, model_or1200nd_lf_sfun_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SFUN_D32, model_or1200nd_lf_sfun_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_MADD_S, model_or1200nd_lf_madd_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_MADD_D32, model_or1200nd_lf_madd_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_CUST1_S, model_or1200nd_lf_cust1_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_CUST1_D32, model_or1200nd_lf_cust1_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
};
#endif /* WITH_PROFILE_MODEL_P */
diff --git a/sim/or1k/sem-switch.c b/sim/or1k/sem-switch.c
index e250e45c60..ac29177057 100644
--- a/sim/or1k/sem-switch.c
+++ b/sim/or1k/sem-switch.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2019 Free Software Foundation, Inc.
+Copyright (C) 1996-2019 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -136,20 +136,49 @@ This file is part of the GNU simulators.
{ OR1K32BF_INSN_L_CUST7, && case_sem_INSN_L_CUST7 },
{ OR1K32BF_INSN_L_CUST8, && case_sem_INSN_L_CUST8 },
{ OR1K32BF_INSN_LF_ADD_S, && case_sem_INSN_LF_ADD_S },
+ { OR1K32BF_INSN_LF_ADD_D32, && case_sem_INSN_LF_ADD_D32 },
{ OR1K32BF_INSN_LF_SUB_S, && case_sem_INSN_LF_SUB_S },
+ { OR1K32BF_INSN_LF_SUB_D32, && case_sem_INSN_LF_SUB_D32 },
{ OR1K32BF_INSN_LF_MUL_S, && case_sem_INSN_LF_MUL_S },
+ { OR1K32BF_INSN_LF_MUL_D32, && case_sem_INSN_LF_MUL_D32 },
{ OR1K32BF_INSN_LF_DIV_S, && case_sem_INSN_LF_DIV_S },
+ { OR1K32BF_INSN_LF_DIV_D32, && case_sem_INSN_LF_DIV_D32 },
{ OR1K32BF_INSN_LF_REM_S, && case_sem_INSN_LF_REM_S },
+ { OR1K32BF_INSN_LF_REM_D32, && case_sem_INSN_LF_REM_D32 },
{ OR1K32BF_INSN_LF_ITOF_S, && case_sem_INSN_LF_ITOF_S },
+ { OR1K32BF_INSN_LF_ITOF_D32, && case_sem_INSN_LF_ITOF_D32 },
{ OR1K32BF_INSN_LF_FTOI_S, && case_sem_INSN_LF_FTOI_S },
- { OR1K32BF_INSN_LF_EQ_S, && case_sem_INSN_LF_EQ_S },
- { OR1K32BF_INSN_LF_NE_S, && case_sem_INSN_LF_NE_S },
- { OR1K32BF_INSN_LF_GE_S, && case_sem_INSN_LF_GE_S },
- { OR1K32BF_INSN_LF_GT_S, && case_sem_INSN_LF_GT_S },
- { OR1K32BF_INSN_LF_LT_S, && case_sem_INSN_LF_LT_S },
- { OR1K32BF_INSN_LF_LE_S, && case_sem_INSN_LF_LE_S },
+ { OR1K32BF_INSN_LF_FTOI_D32, && case_sem_INSN_LF_FTOI_D32 },
+ { OR1K32BF_INSN_LF_SFEQ_S, && case_sem_INSN_LF_SFEQ_S },
+ { OR1K32BF_INSN_LF_SFEQ_D32, && case_sem_INSN_LF_SFEQ_D32 },
+ { OR1K32BF_INSN_LF_SFNE_S, && case_sem_INSN_LF_SFNE_S },
+ { OR1K32BF_INSN_LF_SFNE_D32, && case_sem_INSN_LF_SFNE_D32 },
+ { OR1K32BF_INSN_LF_SFGE_S, && case_sem_INSN_LF_SFGE_S },
+ { OR1K32BF_INSN_LF_SFGE_D32, && case_sem_INSN_LF_SFGE_D32 },
+ { OR1K32BF_INSN_LF_SFGT_S, && case_sem_INSN_LF_SFGT_S },
+ { OR1K32BF_INSN_LF_SFGT_D32, && case_sem_INSN_LF_SFGT_D32 },
+ { OR1K32BF_INSN_LF_SFLT_S, && case_sem_INSN_LF_SFLT_S },
+ { OR1K32BF_INSN_LF_SFLT_D32, && case_sem_INSN_LF_SFLT_D32 },
+ { OR1K32BF_INSN_LF_SFLE_S, && case_sem_INSN_LF_SFLE_S },
+ { OR1K32BF_INSN_LF_SFLE_D32, && case_sem_INSN_LF_SFLE_D32 },
+ { OR1K32BF_INSN_LF_SFUEQ_S, && case_sem_INSN_LF_SFUEQ_S },
+ { OR1K32BF_INSN_LF_SFUEQ_D32, && case_sem_INSN_LF_SFUEQ_D32 },
+ { OR1K32BF_INSN_LF_SFUNE_S, && case_sem_INSN_LF_SFUNE_S },
+ { OR1K32BF_INSN_LF_SFUNE_D32, && case_sem_INSN_LF_SFUNE_D32 },
+ { OR1K32BF_INSN_LF_SFUGT_S, && case_sem_INSN_LF_SFUGT_S },
+ { OR1K32BF_INSN_LF_SFUGT_D32, && case_sem_INSN_LF_SFUGT_D32 },
+ { OR1K32BF_INSN_LF_SFUGE_S, && case_sem_INSN_LF_SFUGE_S },
+ { OR1K32BF_INSN_LF_SFUGE_D32, && case_sem_INSN_LF_SFUGE_D32 },
+ { OR1K32BF_INSN_LF_SFULT_S, && case_sem_INSN_LF_SFULT_S },
+ { OR1K32BF_INSN_LF_SFULT_D32, && case_sem_INSN_LF_SFULT_D32 },
+ { OR1K32BF_INSN_LF_SFULE_S, && case_sem_INSN_LF_SFULE_S },
+ { OR1K32BF_INSN_LF_SFULE_D32, && case_sem_INSN_LF_SFULE_D32 },
+ { OR1K32BF_INSN_LF_SFUN_S, && case_sem_INSN_LF_SFUN_S },
+ { OR1K32BF_INSN_LF_SFUN_D32, && case_sem_INSN_LF_SFUN_D32 },
{ OR1K32BF_INSN_LF_MADD_S, && case_sem_INSN_LF_MADD_S },
+ { OR1K32BF_INSN_LF_MADD_D32, && case_sem_INSN_LF_MADD_D32 },
{ OR1K32BF_INSN_LF_CUST1_S, && case_sem_INSN_LF_CUST1_S },
+ { OR1K32BF_INSN_LF_CUST1_D32, && case_sem_INSN_LF_CUST1_D32 },
{ 0, 0 }
};
int i;
@@ -2646,6 +2675,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_ADD_D32) : /* lf.add.d $rDD32F,$rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_FD32R (FLD (f_rdd32), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2665,6 +2713,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SUB_D32) : /* lf.sub.d $rDD32F,$rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->subdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_FD32R (FLD (f_rdd32), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2684,6 +2751,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_MUL_D32) : /* lf.mul.d $rDD32F,$rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_FD32R (FLD (f_rdd32), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2703,6 +2789,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_DIV_D32) : /* lf.div.d $rDD32F,$rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->divdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_FD32R (FLD (f_rdd32), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2722,6 +2827,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_REM_D32) : /* lf.rem.d $rDD32F,$rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->remdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_FD32R (FLD (f_rdd32), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2741,6 +2865,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_ITOF_D32) : /* lf.itof.d $rDD32F,$rADI */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->floatdidf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_I64R (FLD (f_rad32)));
+ SET_H_FD32R (FLD (f_rdd32), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2764,7 +2907,26 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
}
NEXT (vpc);
- CASE (sem, INSN_LF_EQ_S) : /* lf.sfeq.s $rASF,$rBSF */
+ CASE (sem, INSN_LF_FTOI_D32) : /* lf.ftoi.d $rDDI,$rAD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = CGEN_CPU_FPU (current_cpu)->ops->fixdfdi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FD32R (FLD (f_rad32)));
+ SET_H_I64R (FLD (f_rdd32), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "i64r", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFEQ_S) : /* lf.sfeq.s $rASF,$rBSF */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -2783,7 +2945,26 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
}
NEXT (vpc);
- CASE (sem, INSN_LF_NE_S) : /* lf.sfne.s $rASF,$rBSF */
+ CASE (sem, INSN_LF_SFEQ_D32) : /* lf.sfeq.d $rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFNE_S) : /* lf.sfne.s $rASF,$rBSF */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -2802,7 +2983,26 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
}
NEXT (vpc);
- CASE (sem, INSN_LF_GE_S) : /* lf.sfge.s $rASF,$rBSF */
+ CASE (sem, INSN_LF_SFNE_D32) : /* lf.sfne.d $rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->nedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFGE_S) : /* lf.sfge.s $rASF,$rBSF */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -2821,7 +3021,26 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
}
NEXT (vpc);
- CASE (sem, INSN_LF_GT_S) : /* lf.sfgt.s $rASF,$rBSF */
+ CASE (sem, INSN_LF_SFGE_D32) : /* lf.sfge.d $rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->gedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFGT_S) : /* lf.sfgt.s $rASF,$rBSF */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -2840,7 +3059,26 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
}
NEXT (vpc);
- CASE (sem, INSN_LF_LT_S) : /* lf.sflt.s $rASF,$rBSF */
+ CASE (sem, INSN_LF_SFGT_D32) : /* lf.sfgt.d $rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFLT_S) : /* lf.sflt.s $rASF,$rBSF */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -2859,7 +3097,26 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
}
NEXT (vpc);
- CASE (sem, INSN_LF_LE_S) : /* lf.sfle.s $rASF,$rBSF */
+ CASE (sem, INSN_LF_SFLT_D32) : /* lf.sflt.d $rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFLE_S) : /* lf.sfle.s $rASF,$rBSF */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -2874,6 +3131,291 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFLE_D32) : /* lf.sfle.d $rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->ledf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFUEQ_S) : /* lf.sfueq.s $rASF,$rBSF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFUEQ_D32) : /* lf.sfueq.d $rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->eqdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFUNE_S) : /* lf.sfune.s $rASF,$rBSF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->nesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFUNE_D32) : /* lf.sfune.d $rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->nedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFUGT_S) : /* lf.sfugt.s $rASF,$rBSF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFUGT_D32) : /* lf.sfugt.d $rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->gtdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFUGE_S) : /* lf.sfuge.s $rASF,$rBSF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->gesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFUGE_D32) : /* lf.sfuge.d $rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->gedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFULT_S) : /* lf.sfult.s $rASF,$rBSF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFULT_D32) : /* lf.sfult.d $rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->ltdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFULE_S) : /* lf.sfule.s $rASF,$rBSF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->lesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFULE_D32) : /* lf.sfule.d $rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->ledf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFUN_S) : /* lf.sfun.s $rASF,$rBSF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SFUN_D32) : /* lf.sfun.d $rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2893,6 +3435,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_MADD_D32) : /* lf.madd.d $rDD32F,$rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), GET_H_FD32R (FLD (f_rdd32)));
+ SET_H_FD32R (FLD (f_rdd32), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2908,6 +3469,21 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
((void) 0); /*nop*/
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_CUST1_D32) : /* lf.cust1.d */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
#undef FLD
}
NEXT (vpc);
diff --git a/sim/or1k/sem.c b/sim/or1k/sem.c
index 15ef24c079..ff3886b8a5 100644
--- a/sim/or1k/sem.c
+++ b/sim/or1k/sem.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2019 Free Software Foundation, Inc.
+Copyright (C) 1996-2019 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -2694,6 +2694,27 @@ SEM_FN_NAME (or1k32bf,lf_add_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-add-d32: lf.add.d $rDD32F,$rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_add_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_FD32R (FLD (f_rdd32), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-sub-s: lf.sub.s $rDSF,$rASF,$rBSF */
static SEM_PC
@@ -2715,6 +2736,27 @@ SEM_FN_NAME (or1k32bf,lf_sub_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-sub-d32: lf.sub.d $rDD32F,$rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sub_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->subdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_FD32R (FLD (f_rdd32), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-mul-s: lf.mul.s $rDSF,$rASF,$rBSF */
static SEM_PC
@@ -2736,6 +2778,27 @@ SEM_FN_NAME (or1k32bf,lf_mul_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-mul-d32: lf.mul.d $rDD32F,$rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_mul_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_FD32R (FLD (f_rdd32), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-div-s: lf.div.s $rDSF,$rASF,$rBSF */
static SEM_PC
@@ -2757,6 +2820,27 @@ SEM_FN_NAME (or1k32bf,lf_div_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-div-d32: lf.div.d $rDD32F,$rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_div_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->divdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_FD32R (FLD (f_rdd32), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-rem-s: lf.rem.s $rDSF,$rASF,$rBSF */
static SEM_PC
@@ -2778,6 +2862,27 @@ SEM_FN_NAME (or1k32bf,lf_rem_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-rem-d32: lf.rem.d $rDD32F,$rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_rem_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->remdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_FD32R (FLD (f_rdd32), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-itof-s: lf.itof.s $rDSF,$rA */
static SEM_PC
@@ -2799,6 +2904,27 @@ SEM_FN_NAME (or1k32bf,lf_itof_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-itof-d32: lf.itof.d $rDD32F,$rADI */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_itof_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->floatdidf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_I64R (FLD (f_rad32)));
+ SET_H_FD32R (FLD (f_rdd32), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-ftoi-s: lf.ftoi.s $rD,$rASF */
static SEM_PC
@@ -2820,10 +2946,31 @@ SEM_FN_NAME (or1k32bf,lf_ftoi_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* lf-eq-s: lf.sfeq.s $rASF,$rBSF */
+/* lf-ftoi-d32: lf.ftoi.d $rDDI,$rAD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_ftoi_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = CGEN_CPU_FPU (current_cpu)->ops->fixdfdi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FD32R (FLD (f_rad32)));
+ SET_H_I64R (FLD (f_rdd32), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "i64r", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sfeq-s: lf.sfeq.s $rASF,$rBSF */
static SEM_PC
-SEM_FN_NAME (or1k32bf,lf_eq_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,lf_sfeq_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -2841,10 +2988,31 @@ SEM_FN_NAME (or1k32bf,lf_eq_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* lf-ne-s: lf.sfne.s $rASF,$rBSF */
+/* lf-sfeq-d32: lf.sfeq.d $rAD32F,$rBD32F */
static SEM_PC
-SEM_FN_NAME (or1k32bf,lf_ne_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,lf_sfeq_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sfne-s: lf.sfne.s $rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sfne_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -2862,10 +3030,31 @@ SEM_FN_NAME (or1k32bf,lf_ne_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* lf-ge-s: lf.sfge.s $rASF,$rBSF */
+/* lf-sfne-d32: lf.sfne.d $rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sfne_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->nedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sfge-s: lf.sfge.s $rASF,$rBSF */
static SEM_PC
-SEM_FN_NAME (or1k32bf,lf_ge_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,lf_sfge_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -2883,10 +3072,31 @@ SEM_FN_NAME (or1k32bf,lf_ge_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* lf-gt-s: lf.sfgt.s $rASF,$rBSF */
+/* lf-sfge-d32: lf.sfge.d $rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sfge_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->gedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sfgt-s: lf.sfgt.s $rASF,$rBSF */
static SEM_PC
-SEM_FN_NAME (or1k32bf,lf_gt_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,lf_sfgt_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -2904,10 +3114,31 @@ SEM_FN_NAME (or1k32bf,lf_gt_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* lf-lt-s: lf.sflt.s $rASF,$rBSF */
+/* lf-sfgt-d32: lf.sfgt.d $rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sfgt_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sflt-s: lf.sflt.s $rASF,$rBSF */
static SEM_PC
-SEM_FN_NAME (or1k32bf,lf_lt_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,lf_sflt_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -2925,10 +3156,31 @@ SEM_FN_NAME (or1k32bf,lf_lt_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* lf-le-s: lf.sfle.s $rASF,$rBSF */
+/* lf-sflt-d32: lf.sflt.d $rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sflt_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sfle-s: lf.sfle.s $rASF,$rBSF */
static SEM_PC
-SEM_FN_NAME (or1k32bf,lf_le_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,lf_sfle_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -2946,6 +3198,321 @@ SEM_FN_NAME (or1k32bf,lf_le_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-sfle-d32: lf.sfle.d $rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sfle_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->ledf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sfueq-s: lf.sfueq.s $rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sfueq_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sfueq-d32: lf.sfueq.d $rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sfueq_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->eqdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sfune-s: lf.sfune.s $rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sfune_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->nesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sfune-d32: lf.sfune.d $rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sfune_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->nedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sfugt-s: lf.sfugt.s $rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sfugt_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sfugt-d32: lf.sfugt.d $rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sfugt_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->gtdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sfuge-s: lf.sfuge.s $rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sfuge_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->gesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sfuge-d32: lf.sfuge.d $rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sfuge_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->gedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sfult-s: lf.sfult.s $rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sfult_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sfult-d32: lf.sfult.d $rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sfult_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->ltdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sfule-s: lf.sfule.s $rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sfule_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->lesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sfule-d32: lf.sfule.d $rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sfule_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->ledf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sfun-s: lf.sfun.s $rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sfun_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sfun-d32: lf.sfun.d $rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sfun_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-madd-s: lf.madd.s $rDSF,$rASF,$rBSF */
static SEM_PC
@@ -2967,6 +3534,27 @@ SEM_FN_NAME (or1k32bf,lf_madd_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-madd-d32: lf.madd.d $rDD32F,$rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_madd_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lf_add_d32.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), GET_H_FD32R (FLD (f_rdd32)));
+ SET_H_FD32R (FLD (f_rdd32), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-cust1-s: lf.cust1.s $rASF,$rBSF */
static SEM_PC
@@ -2984,6 +3572,23 @@ SEM_FN_NAME (or1k32bf,lf_cust1_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-cust1-d32: lf.cust1.d */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_cust1_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
/* Table of all semantic fns. */
static const struct sem_fn_desc sem_fns[] = {
@@ -3091,20 +3696,49 @@ static const struct sem_fn_desc sem_fns[] = {
{ OR1K32BF_INSN_L_CUST7, SEM_FN_NAME (or1k32bf,l_cust7) },
{ OR1K32BF_INSN_L_CUST8, SEM_FN_NAME (or1k32bf,l_cust8) },
{ OR1K32BF_INSN_LF_ADD_S, SEM_FN_NAME (or1k32bf,lf_add_s) },
+ { OR1K32BF_INSN_LF_ADD_D32, SEM_FN_NAME (or1k32bf,lf_add_d32) },
{ OR1K32BF_INSN_LF_SUB_S, SEM_FN_NAME (or1k32bf,lf_sub_s) },
+ { OR1K32BF_INSN_LF_SUB_D32, SEM_FN_NAME (or1k32bf,lf_sub_d32) },
{ OR1K32BF_INSN_LF_MUL_S, SEM_FN_NAME (or1k32bf,lf_mul_s) },
+ { OR1K32BF_INSN_LF_MUL_D32, SEM_FN_NAME (or1k32bf,lf_mul_d32) },
{ OR1K32BF_INSN_LF_DIV_S, SEM_FN_NAME (or1k32bf,lf_div_s) },
+ { OR1K32BF_INSN_LF_DIV_D32, SEM_FN_NAME (or1k32bf,lf_div_d32) },
{ OR1K32BF_INSN_LF_REM_S, SEM_FN_NAME (or1k32bf,lf_rem_s) },
+ { OR1K32BF_INSN_LF_REM_D32, SEM_FN_NAME (or1k32bf,lf_rem_d32) },
{ OR1K32BF_INSN_LF_ITOF_S, SEM_FN_NAME (or1k32bf,lf_itof_s) },
+ { OR1K32BF_INSN_LF_ITOF_D32, SEM_FN_NAME (or1k32bf,lf_itof_d32) },
{ OR1K32BF_INSN_LF_FTOI_S, SEM_FN_NAME (or1k32bf,lf_ftoi_s) },
- { OR1K32BF_INSN_LF_EQ_S, SEM_FN_NAME (or1k32bf,lf_eq_s) },
- { OR1K32BF_INSN_LF_NE_S, SEM_FN_NAME (or1k32bf,lf_ne_s) },
- { OR1K32BF_INSN_LF_GE_S, SEM_FN_NAME (or1k32bf,lf_ge_s) },
- { OR1K32BF_INSN_LF_GT_S, SEM_FN_NAME (or1k32bf,lf_gt_s) },
- { OR1K32BF_INSN_LF_LT_S, SEM_FN_NAME (or1k32bf,lf_lt_s) },
- { OR1K32BF_INSN_LF_LE_S, SEM_FN_NAME (or1k32bf,lf_le_s) },
+ { OR1K32BF_INSN_LF_FTOI_D32, SEM_FN_NAME (or1k32bf,lf_ftoi_d32) },
+ { OR1K32BF_INSN_LF_SFEQ_S, SEM_FN_NAME (or1k32bf,lf_sfeq_s) },
+ { OR1K32BF_INSN_LF_SFEQ_D32, SEM_FN_NAME (or1k32bf,lf_sfeq_d32) },
+ { OR1K32BF_INSN_LF_SFNE_S, SEM_FN_NAME (or1k32bf,lf_sfne_s) },
+ { OR1K32BF_INSN_LF_SFNE_D32, SEM_FN_NAME (or1k32bf,lf_sfne_d32) },
+ { OR1K32BF_INSN_LF_SFGE_S, SEM_FN_NAME (or1k32bf,lf_sfge_s) },
+ { OR1K32BF_INSN_LF_SFGE_D32, SEM_FN_NAME (or1k32bf,lf_sfge_d32) },
+ { OR1K32BF_INSN_LF_SFGT_S, SEM_FN_NAME (or1k32bf,lf_sfgt_s) },
+ { OR1K32BF_INSN_LF_SFGT_D32, SEM_FN_NAME (or1k32bf,lf_sfgt_d32) },
+ { OR1K32BF_INSN_LF_SFLT_S, SEM_FN_NAME (or1k32bf,lf_sflt_s) },
+ { OR1K32BF_INSN_LF_SFLT_D32, SEM_FN_NAME (or1k32bf,lf_sflt_d32) },
+ { OR1K32BF_INSN_LF_SFLE_S, SEM_FN_NAME (or1k32bf,lf_sfle_s) },
+ { OR1K32BF_INSN_LF_SFLE_D32, SEM_FN_NAME (or1k32bf,lf_sfle_d32) },
+ { OR1K32BF_INSN_LF_SFUEQ_S, SEM_FN_NAME (or1k32bf,lf_sfueq_s) },
+ { OR1K32BF_INSN_LF_SFUEQ_D32, SEM_FN_NAME (or1k32bf,lf_sfueq_d32) },
+ { OR1K32BF_INSN_LF_SFUNE_S, SEM_FN_NAME (or1k32bf,lf_sfune_s) },
+ { OR1K32BF_INSN_LF_SFUNE_D32, SEM_FN_NAME (or1k32bf,lf_sfune_d32) },
+ { OR1K32BF_INSN_LF_SFUGT_S, SEM_FN_NAME (or1k32bf,lf_sfugt_s) },
+ { OR1K32BF_INSN_LF_SFUGT_D32, SEM_FN_NAME (or1k32bf,lf_sfugt_d32) },
+ { OR1K32BF_INSN_LF_SFUGE_S, SEM_FN_NAME (or1k32bf,lf_sfuge_s) },
+ { OR1K32BF_INSN_LF_SFUGE_D32, SEM_FN_NAME (or1k32bf,lf_sfuge_d32) },
+ { OR1K32BF_INSN_LF_SFULT_S, SEM_FN_NAME (or1k32bf,lf_sfult_s) },
+ { OR1K32BF_INSN_LF_SFULT_D32, SEM_FN_NAME (or1k32bf,lf_sfult_d32) },
+ { OR1K32BF_INSN_LF_SFULE_S, SEM_FN_NAME (or1k32bf,lf_sfule_s) },
+ { OR1K32BF_INSN_LF_SFULE_D32, SEM_FN_NAME (or1k32bf,lf_sfule_d32) },
+ { OR1K32BF_INSN_LF_SFUN_S, SEM_FN_NAME (or1k32bf,lf_sfun_s) },
+ { OR1K32BF_INSN_LF_SFUN_D32, SEM_FN_NAME (or1k32bf,lf_sfun_d32) },
{ OR1K32BF_INSN_LF_MADD_S, SEM_FN_NAME (or1k32bf,lf_madd_s) },
+ { OR1K32BF_INSN_LF_MADD_D32, SEM_FN_NAME (or1k32bf,lf_madd_d32) },
{ OR1K32BF_INSN_LF_CUST1_S, SEM_FN_NAME (or1k32bf,lf_cust1_s) },
+ { OR1K32BF_INSN_LF_CUST1_D32, SEM_FN_NAME (or1k32bf,lf_cust1_d32) },
{ 0, 0 }
};
--
2.21.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 07/11] sim/common: Wire in df/di conversion
2019-06-08 21:32 [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Stafford Horne
` (6 preceding siblings ...)
2019-06-08 21:33 ` [PATCH v3 08/11] sim/common: wire up new unordered comparisons Stafford Horne
@ 2019-06-08 21:33 ` Stafford Horne
2019-06-08 21:33 ` [PATCH v3 06/11] sim/or1k: Regenerate sim Stafford Horne
` (2 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Stafford Horne @ 2019-06-08 21:33 UTC (permalink / raw)
To: GDB patches, GNU Binutils
Cc: Andrey Bacherov, Nick Clifton, Andrew Burgess, Richard Henderson,
Openrisc, Stafford Horne
Up until now these have not been used in any CGEN targets, add them as
they are now used by OpenRISC.
sim/common/ChangeLog:
* cgen-accfp.c (floatdidf, fixdfdi): New functions.
(cgen_init_accurate_fpu): Add floatdidf and fixdfdi.
---
Changes since v2:
- none
sim/common/cgen-accfp.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/sim/common/cgen-accfp.c b/sim/common/cgen-accfp.c
index 5d600c6e41..51f5a29fe2 100644
--- a/sim/common/cgen-accfp.c
+++ b/sim/common/cgen-accfp.c
@@ -349,6 +349,17 @@ floatsidf (CGEN_FPU* fpu, int how UNUSED, SI x)
return res;
}
+static DF
+floatdidf (CGEN_FPU* fpu, int how UNUSED, DI x)
+{
+ sim_fpu ans;
+ unsigned64 res;
+
+ sim_fpu_i64to (&ans, x, sim_fpu_round_near);
+ sim_fpu_to64 (&res, &ans);
+ return res;
+}
+
static SF
ufloatsisf (CGEN_FPU* fpu, int how UNUSED, USI x)
{
@@ -382,6 +393,17 @@ fixdfsi (CGEN_FPU* fpu, int how UNUSED, DF x)
return res;
}
+static DI
+fixdfdi (CGEN_FPU* fpu, int how UNUSED, DF x)
+{
+ sim_fpu op1;
+ unsigned64 res;
+
+ sim_fpu_64to (&op1, x);
+ sim_fpu_to64i (&res, &op1, sim_fpu_round_near);
+ return res;
+}
+
static USI
ufixsfsi (CGEN_FPU* fpu, int how UNUSED, SF x)
{
@@ -739,8 +761,10 @@ cgen_init_accurate_fpu (SIM_CPU* cpu, CGEN_FPU* fpu, CGEN_FPU_ERROR_FN* error)
o->ftruncdfsf = ftruncdfsf;
o->floatsisf = floatsisf;
o->floatsidf = floatsidf;
+ o->floatdidf = floatdidf;
o->ufloatsisf = ufloatsisf;
o->fixsfsi = fixsfsi;
o->fixdfsi = fixdfsi;
+ o->fixdfdi = fixdfdi;
o->ufixsfsi = ufixsfsi;
}
--
2.21.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 05/11] opcodes/or1k: Regenerate opcodes
2019-06-08 21:32 [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Stafford Horne
` (3 preceding siblings ...)
2019-06-08 21:32 ` [PATCH v3 03/11] cpu/or1k: Document no branch delay slot architectures and l.adrp Stafford Horne
@ 2019-06-08 21:33 ` Stafford Horne
2019-06-08 21:33 ` [PATCH v3 09/11] sim/testsuite/or1k: Add test for 64-bit fpu operations Stafford Horne
` (5 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Stafford Horne @ 2019-06-08 21:33 UTC (permalink / raw)
To: GDB patches, GNU Binutils
Cc: Andrey Bacherov, Nick Clifton, Andrew Burgess, Richard Henderson,
Openrisc, Stafford Horne
This picks up changes for:
- new orfpx64a32 spec additions
- new unordered instructions
- symbol and documentation updates
opcodes/ChangeLog:
* or1k-asm.c: Regenerated.
* or1k-desc.c: Regenerated.
* or1k-desc.h: Regenerated.
* or1k-dis.c: Regenerated.
* or1k-ibld.c: Regenerated.
* or1k-opc.c: Regenerated.
* or1k-opc.h: Regenerated.
* or1k-opinst.c: Regenerated.
---
Changes since v2:
- Now regenerating for new unordered instructions and documentation.
opcodes/or1k-asm.c | 72 ++++++++-
opcodes/or1k-desc.c | 309 +++++++++++++++++++++++++++++++++-----
opcodes/or1k-desc.h | 341 +++++++++++++++++++++---------------------
opcodes/or1k-dis.c | 43 +++++-
opcodes/or1k-ibld.c | 234 +++++++++++++++++++++++++++--
opcodes/or1k-opc.c | 319 +++++++++++++++++++++++++++++++++++----
opcodes/or1k-opc.h | 39 +++--
opcodes/or1k-opinst.c | 100 +++++++++++--
8 files changed, 1184 insertions(+), 273 deletions(-)
diff --git a/opcodes/or1k-asm.c b/opcodes/or1k-asm.c
index 7d058d03f5..55668afee5 100644
--- a/opcodes/or1k-asm.c
+++ b/opcodes/or1k-asm.c
@@ -419,6 +419,56 @@ parse_uimm16_split (CGEN_CPU_DESC cd, const char **strp, int opindex,
return errmsg;
}
+/* Parse register pairs with syntax rA,rB to a flag + rA value. */
+
+static const char *
+parse_regpair (CGEN_CPU_DESC cd, const char **strp,
+ int opindex ATTRIBUTE_UNUSED, unsigned long *valuep)
+{
+ long reg1_index;
+ long reg2_index;
+ const char *errmsg;
+
+ /* The first part should just be a register. */
+ errmsg = cgen_parse_keyword (cd, strp, &or1k_cgen_opval_h_gpr,
+ ®1_index);
+
+ /* If that worked skip the comma separator. */
+ if (errmsg == NULL)
+ {
+ if (**strp == ',')
+ ++*strp;
+ else
+ errmsg = "Unexpected character, expected ','";
+ }
+
+ /* If that worked the next part is just another register. */
+ if (errmsg == NULL)
+ errmsg = cgen_parse_keyword (cd, strp, &or1k_cgen_opval_h_gpr,
+ ®2_index);
+
+ /* Validate the register pair is valid and create the output value. */
+ if (errmsg == NULL)
+ {
+ int regoffset = reg2_index - reg1_index;
+
+ if (regoffset == 1 || regoffset == 2)
+ {
+ unsigned short offsetmask;
+ unsigned short value;
+
+ offsetmask = ((regoffset == 2 ? 1 : 0) << 5);
+ value = offsetmask | reg1_index;
+
+ *valuep = value;
+ }
+ else
+ errmsg = "Invalid register pair, offset not 1 or 2.";
+ }
+
+ return errmsg;
+}
+
/* -- */
const char * or1k_cgen_parse_operand
@@ -466,8 +516,14 @@ or1k_cgen_parse_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RA :
errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_gpr, & fields->f_r2);
break;
+ case OR1K_OPERAND_RAD32F :
+ errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RAD32F, (unsigned long *) (& fields->f_rad32));
+ break;
case OR1K_OPERAND_RADF :
- errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r1);
+ errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r2);
+ break;
+ case OR1K_OPERAND_RADI :
+ errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RADI, (unsigned long *) (& fields->f_rad32));
break;
case OR1K_OPERAND_RASF :
errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fsr, & fields->f_r2);
@@ -475,8 +531,14 @@ or1k_cgen_parse_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RB :
errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_gpr, & fields->f_r3);
break;
+ case OR1K_OPERAND_RBD32F :
+ errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RBD32F, (unsigned long *) (& fields->f_rbd32));
+ break;
case OR1K_OPERAND_RBDF :
- errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r1);
+ errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r3);
+ break;
+ case OR1K_OPERAND_RBDI :
+ errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RBDI, (unsigned long *) (& fields->f_rbd32));
break;
case OR1K_OPERAND_RBSF :
errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fsr, & fields->f_r3);
@@ -484,9 +546,15 @@ or1k_cgen_parse_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RD :
errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_gpr, & fields->f_r1);
break;
+ case OR1K_OPERAND_RDD32F :
+ errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RDD32F, (unsigned long *) (& fields->f_rdd32));
+ break;
case OR1K_OPERAND_RDDF :
errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r1);
break;
+ case OR1K_OPERAND_RDDI :
+ errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RDDI, (unsigned long *) (& fields->f_rdd32));
+ break;
case OR1K_OPERAND_RDSF :
errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fsr, & fields->f_r1);
break;
diff --git a/opcodes/or1k-desc.c b/opcodes/or1k-desc.c
index 486b0f2626..3357849a27 100644
--- a/opcodes/or1k-desc.c
+++ b/opcodes/or1k-desc.c
@@ -134,7 +134,7 @@ static const CGEN_MACH or1k_cgen_mach_table[] = {
{ 0, 0, 0, 0 }
};
-static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fsr_entries[] =
+static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_gpr_entries[] =
{
{ "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
{ "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
@@ -173,14 +173,14 @@ static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fsr_entries[] =
{ "fp", 2, {0, {{{0, 0}}}}, 0, 0 }
};
-CGEN_KEYWORD or1k_cgen_opval_h_fsr =
+CGEN_KEYWORD or1k_cgen_opval_h_gpr =
{
- & or1k_cgen_opval_h_fsr_entries[0],
+ & or1k_cgen_opval_h_gpr_entries[0],
35,
0, 0, 0, 0, ""
};
-static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fdr_entries[] =
+static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fsr_entries[] =
{
{ "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
{ "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
@@ -219,14 +219,14 @@ static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fdr_entries[] =
{ "fp", 2, {0, {{{0, 0}}}}, 0, 0 }
};
-CGEN_KEYWORD or1k_cgen_opval_h_fdr =
+CGEN_KEYWORD or1k_cgen_opval_h_fsr =
{
- & or1k_cgen_opval_h_fdr_entries[0],
+ & or1k_cgen_opval_h_fsr_entries[0],
35,
0, 0, 0, 0, ""
};
-static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_gpr_entries[] =
+static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fdr_entries[] =
{
{ "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
{ "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
@@ -265,9 +265,9 @@ static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_gpr_entries[] =
{ "fp", 2, {0, {{{0, 0}}}}, 0, 0 }
};
-CGEN_KEYWORD or1k_cgen_opval_h_gpr =
+CGEN_KEYWORD or1k_cgen_opval_h_fdr =
{
- & or1k_cgen_opval_h_gpr_entries[0],
+ & or1k_cgen_opval_h_fdr_entries[0],
35,
0, 0, 0, 0, ""
};
@@ -285,10 +285,12 @@ const CGEN_HW_ENTRY or1k_cgen_hw_table[] =
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
- { "h-fsr", HW_H_FSR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fsr, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
- { "h-fdr", HW_H_FDR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fdr, { 0|A(VIRTUAL), { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ "h-spr", HW_H_SPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_gpr, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+ { "h-fsr", HW_H_FSR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fsr, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+ { "h-fdr", HW_H_FDR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fdr, { 0|A(VIRTUAL), { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+ { "h-fd32r", HW_H_FD32R, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
+ { "h-i64r", HW_H_I64R, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
{ "h-sys-vr", HW_H_SYS_VR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ "h-sys-upr", HW_H_SYS_UPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ "h-sys-cpucfgr", HW_H_SYS_CPUCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
@@ -922,6 +924,7 @@ const CGEN_HW_ENTRY or1k_cgen_hw_table[] =
{ "h-uimm6", HW_H_UIMM6, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-atomic-reserve", HW_H_ATOMIC_RESERVE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-atomic-address", HW_H_ATOMIC_ADDRESS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-roff1", HW_H_ROFF1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
};
@@ -962,6 +965,7 @@ const CGEN_IFLD or1k_cgen_ifld_table[] =
{ OR1K_F_RESV_10_7, "f-resv-10-7", 0, 32, 10, 7, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ OR1K_F_RESV_10_3, "f-resv-10-3", 0, 32, 10, 3, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ OR1K_F_RESV_10_1, "f-resv-10-1", 0, 32, 10, 1, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+ { OR1K_F_RESV_8_1, "f-resv-8-1", 0, 32, 8, 1, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ OR1K_F_RESV_7_4, "f-resv-7-4", 0, 32, 7, 4, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ OR1K_F_RESV_5_2, "f-resv-5-2", 0, 32, 5, 2, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ OR1K_F_IMM16_25_5, "f-imm16-25-5", 0, 32, 25, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
@@ -973,6 +977,12 @@ const CGEN_IFLD or1k_cgen_ifld_table[] =
{ OR1K_F_UIMM6, "f-uimm6", 0, 32, 5, 6, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ OR1K_F_UIMM16_SPLIT, "f-uimm16-split", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ OR1K_F_SIMM16_SPLIT, "f-simm16-split", 0, 0, 0, 0,{ 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+ { OR1K_F_RDOFF_10_1, "f-rdoff-10-1", 0, 32, 10, 1, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
+ { OR1K_F_RAOFF_9_1, "f-raoff-9-1", 0, 32, 9, 1, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
+ { OR1K_F_RBOFF_8_1, "f-rboff-8-1", 0, 32, 8, 1, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
+ { OR1K_F_RDD32, "f-rdd32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
+ { OR1K_F_RAD32, "f-rad32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
+ { OR1K_F_RBD32, "f-rbd32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
{ 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
};
@@ -984,6 +994,9 @@ const CGEN_IFLD or1k_cgen_ifld_table[] =
const CGEN_MAYBE_MULTI_IFLD OR1K_F_UIMM16_SPLIT_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD OR1K_F_SIMM16_SPLIT_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD OR1K_F_RDD32_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD OR1K_F_RAD32_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD OR1K_F_RBD32_MULTI_IFIELD [];
/* multi ifield definitions */
@@ -1000,6 +1013,24 @@ const CGEN_MAYBE_MULTI_IFLD OR1K_F_SIMM16_SPLIT_MULTI_IFIELD [] =
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_IMM16_10_11] } },
{ 0, { (const PTR) 0 } }
};
+const CGEN_MAYBE_MULTI_IFLD OR1K_F_RDD32_MULTI_IFIELD [] =
+{
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_RDOFF_10_1] } },
+ { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD OR1K_F_RAD32_MULTI_IFIELD [] =
+{
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_RAOFF_9_1] } },
+ { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD OR1K_F_RBD32_MULTI_IFIELD [] =
+{
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_RBOFF_8_1] } },
+ { 0, { (const PTR) 0 } }
+};
/* The operand table. */
@@ -1124,18 +1155,42 @@ const CGEN_OPERAND or1k_cgen_operand_table[] =
{ "rBSF", OR1K_OPERAND_RBSF, HW_H_FSR, 15, 5,
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
-/* rDDF: destination register (double floating point mode) */
+/* rDDF: or64 destination register (double floating point mode) */
{ "rDDF", OR1K_OPERAND_RDDF, HW_H_FDR, 25, 5,
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
-/* rADF: source register A (double floating point mode) */
- { "rADF", OR1K_OPERAND_RADF, HW_H_FDR, 25, 5,
- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+/* rADF: or64 source register A (double floating point mode) */
+ { "rADF", OR1K_OPERAND_RADF, HW_H_FDR, 20, 5,
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
-/* rBDF: source register B (double floating point mode) */
- { "rBDF", OR1K_OPERAND_RBDF, HW_H_FDR, 25, 5,
- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+/* rBDF: or64 source register B (double floating point mode) */
+ { "rBDF", OR1K_OPERAND_RBDF, HW_H_FDR, 15, 5,
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+/* rDD32F: destination register (double floating point pair) */
+ { "rDD32F", OR1K_OPERAND_RDD32F, HW_H_FD32R, 10, 6,
+ { 2, { (const PTR) &OR1K_F_RDD32_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
+/* rDDI: destination register (double integer pair) */
+ { "rDDI", OR1K_OPERAND_RDDI, HW_H_I64R, 10, 6,
+ { 2, { (const PTR) &OR1K_F_RDD32_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
+/* rAD32F: source register A (double floating point pair) */
+ { "rAD32F", OR1K_OPERAND_RAD32F, HW_H_FD32R, 9, 6,
+ { 2, { (const PTR) &OR1K_F_RAD32_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
+/* rADI: source register A (double integer pair) */
+ { "rADI", OR1K_OPERAND_RADI, HW_H_I64R, 9, 6,
+ { 2, { (const PTR) &OR1K_F_RAD32_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
+/* rBD32F: source register B (double floating point pair) */
+ { "rBD32F", OR1K_OPERAND_RBD32F, HW_H_FD32R, 8, 6,
+ { 2, { (const PTR) &OR1K_F_RBD32_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
+/* rBDI: source register B (double integer pair) */
+ { "rBDI", OR1K_OPERAND_RBDI, HW_H_I64R, 8, 6,
+ { 2, { (const PTR) &OR1K_F_RBD32_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
@@ -1656,6 +1711,11 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
OR1K_INSN_LF_ADD_D, "lf-add-d", "lf.add.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.add.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_ADD_D32, "lf-add-d32", "lf.add.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.sub.s $rDSF,$rASF,$rBSF */
{
OR1K_INSN_LF_SUB_S, "lf-sub-s", "lf.sub.s", 32,
@@ -1666,6 +1726,11 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
OR1K_INSN_LF_SUB_D, "lf-sub-d", "lf.sub.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.sub.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_SUB_D32, "lf-sub-d32", "lf.sub.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.mul.s $rDSF,$rASF,$rBSF */
{
OR1K_INSN_LF_MUL_S, "lf-mul-s", "lf.mul.s", 32,
@@ -1676,6 +1741,11 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
OR1K_INSN_LF_MUL_D, "lf-mul-d", "lf.mul.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.mul.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_MUL_D32, "lf-mul-d32", "lf.mul.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.div.s $rDSF,$rASF,$rBSF */
{
OR1K_INSN_LF_DIV_S, "lf-div-s", "lf.div.s", 32,
@@ -1686,6 +1756,11 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
OR1K_INSN_LF_DIV_D, "lf-div-d", "lf.div.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.div.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_DIV_D32, "lf-div-d32", "lf.div.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.rem.s $rDSF,$rASF,$rBSF */
{
OR1K_INSN_LF_REM_S, "lf-rem-s", "lf.rem.s", 32,
@@ -1696,16 +1771,26 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
OR1K_INSN_LF_REM_D, "lf-rem-d", "lf.rem.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.rem.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_REM_D32, "lf-rem-d32", "lf.rem.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.itof.s $rDSF,$rA */
{
OR1K_INSN_LF_ITOF_S, "lf-itof-s", "lf.itof.s", 32,
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
-/* lf.itof.d $rDSF,$rA */
+/* lf.itof.d $rDDF,$rA */
{
OR1K_INSN_LF_ITOF_D, "lf-itof-d", "lf.itof.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.itof.d $rDD32F,$rADI */
+ {
+ OR1K_INSN_LF_ITOF_D32, "lf-itof-d32", "lf.itof.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.ftoi.s $rD,$rASF */
{
OR1K_INSN_LF_FTOI_S, "lf-ftoi-s", "lf.ftoi.s", 32,
@@ -1716,66 +1801,206 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
OR1K_INSN_LF_FTOI_D, "lf-ftoi-d", "lf.ftoi.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.ftoi.d $rDDI,$rAD32F */
+ {
+ OR1K_INSN_LF_FTOI_D32, "lf-ftoi-d32", "lf.ftoi.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.sfeq.s $rASF,$rBSF */
{
- OR1K_INSN_LF_EQ_S, "lf-eq-s", "lf.sfeq.s", 32,
+ OR1K_INSN_LF_SFEQ_S, "lf-sfeq-s", "lf.sfeq.s", 32,
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
-/* lf.sfeq.d $rASF,$rBSF */
+/* lf.sfeq.d $rADF,$rBDF */
{
- OR1K_INSN_LF_EQ_D, "lf-eq-d", "lf.sfeq.d", 32,
+ OR1K_INSN_LF_SFEQ_D, "lf-sfeq-d", "lf.sfeq.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.sfeq.d $rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_SFEQ_D32, "lf-sfeq-d32", "lf.sfeq.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.sfne.s $rASF,$rBSF */
{
- OR1K_INSN_LF_NE_S, "lf-ne-s", "lf.sfne.s", 32,
+ OR1K_INSN_LF_SFNE_S, "lf-sfne-s", "lf.sfne.s", 32,
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
-/* lf.sfne.d $rASF,$rBSF */
+/* lf.sfne.d $rADF,$rBDF */
{
- OR1K_INSN_LF_NE_D, "lf-ne-d", "lf.sfne.d", 32,
+ OR1K_INSN_LF_SFNE_D, "lf-sfne-d", "lf.sfne.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.sfne.d $rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_SFNE_D32, "lf-sfne-d32", "lf.sfne.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.sfge.s $rASF,$rBSF */
{
- OR1K_INSN_LF_GE_S, "lf-ge-s", "lf.sfge.s", 32,
+ OR1K_INSN_LF_SFGE_S, "lf-sfge-s", "lf.sfge.s", 32,
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
-/* lf.sfge.d $rASF,$rBSF */
+/* lf.sfge.d $rADF,$rBDF */
{
- OR1K_INSN_LF_GE_D, "lf-ge-d", "lf.sfge.d", 32,
+ OR1K_INSN_LF_SFGE_D, "lf-sfge-d", "lf.sfge.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.sfge.d $rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_SFGE_D32, "lf-sfge-d32", "lf.sfge.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.sfgt.s $rASF,$rBSF */
{
- OR1K_INSN_LF_GT_S, "lf-gt-s", "lf.sfgt.s", 32,
+ OR1K_INSN_LF_SFGT_S, "lf-sfgt-s", "lf.sfgt.s", 32,
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
-/* lf.sfgt.d $rASF,$rBSF */
+/* lf.sfgt.d $rADF,$rBDF */
{
- OR1K_INSN_LF_GT_D, "lf-gt-d", "lf.sfgt.d", 32,
+ OR1K_INSN_LF_SFGT_D, "lf-sfgt-d", "lf.sfgt.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.sfgt.d $rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_SFGT_D32, "lf-sfgt-d32", "lf.sfgt.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.sflt.s $rASF,$rBSF */
{
- OR1K_INSN_LF_LT_S, "lf-lt-s", "lf.sflt.s", 32,
+ OR1K_INSN_LF_SFLT_S, "lf-sflt-s", "lf.sflt.s", 32,
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
-/* lf.sflt.d $rASF,$rBSF */
+/* lf.sflt.d $rADF,$rBDF */
{
- OR1K_INSN_LF_LT_D, "lf-lt-d", "lf.sflt.d", 32,
+ OR1K_INSN_LF_SFLT_D, "lf-sflt-d", "lf.sflt.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.sflt.d $rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_SFLT_D32, "lf-sflt-d32", "lf.sflt.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.sfle.s $rASF,$rBSF */
{
- OR1K_INSN_LF_LE_S, "lf-le-s", "lf.sfle.s", 32,
+ OR1K_INSN_LF_SFLE_S, "lf-sfle-s", "lf.sfle.s", 32,
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
-/* lf.sfle.d $rASF,$rBSF */
+/* lf.sfle.d $rADF,$rBDF */
{
- OR1K_INSN_LF_LE_D, "lf-le-d", "lf.sfle.d", 32,
+ OR1K_INSN_LF_SFLE_D, "lf-sfle-d", "lf.sfle.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.sfle.d $rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_SFLE_D32, "lf-sfle-d32", "lf.sfle.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
+/* lf.sfueq.s $rASF,$rBSF */
+ {
+ OR1K_INSN_LF_SFUEQ_S, "lf-sfueq-s", "lf.sfueq.s", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
+/* lf.sfueq.d $rADF,$rBDF */
+ {
+ OR1K_INSN_LF_SFUEQ_D, "lf-sfueq-d", "lf.sfueq.d", 32,
+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
+/* lf.sfueq.d $rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_SFUEQ_D32, "lf-sfueq-d32", "lf.sfueq.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
+/* lf.sfune.s $rASF,$rBSF */
+ {
+ OR1K_INSN_LF_SFUNE_S, "lf-sfune-s", "lf.sfune.s", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
+/* lf.sfune.d $rADF,$rBDF */
+ {
+ OR1K_INSN_LF_SFUNE_D, "lf-sfune-d", "lf.sfune.d", 32,
+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
+/* lf.sfune.d $rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_SFUNE_D32, "lf-sfune-d32", "lf.sfune.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
+/* lf.sfugt.s $rASF,$rBSF */
+ {
+ OR1K_INSN_LF_SFUGT_S, "lf-sfugt-s", "lf.sfugt.s", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
+/* lf.sfugt.d $rADF,$rBDF */
+ {
+ OR1K_INSN_LF_SFUGT_D, "lf-sfugt-d", "lf.sfugt.d", 32,
+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
+/* lf.sfugt.d $rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_SFUGT_D32, "lf-sfugt-d32", "lf.sfugt.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
+/* lf.sfuge.s $rASF,$rBSF */
+ {
+ OR1K_INSN_LF_SFUGE_S, "lf-sfuge-s", "lf.sfuge.s", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
+/* lf.sfuge.d $rADF,$rBDF */
+ {
+ OR1K_INSN_LF_SFUGE_D, "lf-sfuge-d", "lf.sfuge.d", 32,
+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
+/* lf.sfuge.d $rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_SFUGE_D32, "lf-sfuge-d32", "lf.sfuge.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
+/* lf.sfult.s $rASF,$rBSF */
+ {
+ OR1K_INSN_LF_SFULT_S, "lf-sfult-s", "lf.sfult.s", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
+/* lf.sfult.d $rADF,$rBDF */
+ {
+ OR1K_INSN_LF_SFULT_D, "lf-sfult-d", "lf.sfult.d", 32,
+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
+/* lf.sfult.d $rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_SFULT_D32, "lf-sfult-d32", "lf.sfult.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
+/* lf.sfule.s $rASF,$rBSF */
+ {
+ OR1K_INSN_LF_SFULE_S, "lf-sfule-s", "lf.sfule.s", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
+/* lf.sfule.d $rADF,$rBDF */
+ {
+ OR1K_INSN_LF_SFULE_D, "lf-sfule-d", "lf.sfule.d", 32,
+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
+/* lf.sfule.d $rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_SFULE_D32, "lf-sfule-d32", "lf.sfule.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
+/* lf.sfun.s $rASF,$rBSF */
+ {
+ OR1K_INSN_LF_SFUN_S, "lf-sfun-s", "lf.sfun.s", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
+/* lf.sfun.d $rADF,$rBDF */
+ {
+ OR1K_INSN_LF_SFUN_D, "lf-sfun-d", "lf.sfun.d", 32,
+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
+/* lf.sfun.d $rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_SFUN_D32, "lf-sfun-d32", "lf.sfun.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.madd.s $rDSF,$rASF,$rBSF */
{
OR1K_INSN_LF_MADD_S, "lf-madd-s", "lf.madd.s", 32,
@@ -1786,6 +2011,11 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
OR1K_INSN_LF_MADD_D, "lf-madd-d", "lf.madd.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.madd.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_MADD_D32, "lf-madd-d32", "lf.madd.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.cust1.s $rASF,$rBSF */
{
OR1K_INSN_LF_CUST1_S, "lf-cust1-s", "lf.cust1.s", 32,
@@ -1796,6 +2026,11 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
OR1K_INSN_LF_CUST1_D, "lf-cust1-d", "lf.cust1.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.cust1.d */
+ {
+ OR1K_INSN_LF_CUST1_D32, "lf-cust1-d32", "lf.cust1.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
};
#undef OP
diff --git a/opcodes/or1k-desc.h b/opcodes/or1k-desc.h
index ade9241a93..1121c99e49 100644
--- a/opcodes/or1k-desc.h
+++ b/opcodes/or1k-desc.h
@@ -349,7 +349,10 @@ typedef enum insn_opcode_float_regreg {
, OPC_FLOAT_REGREG_MUL_D = 18, OPC_FLOAT_REGREG_DIV_D = 19, OPC_FLOAT_REGREG_ITOF_D = 20, OPC_FLOAT_REGREG_FTOI_D = 21
, OPC_FLOAT_REGREG_REM_D = 22, OPC_FLOAT_REGREG_MADD_D = 23, OPC_FLOAT_REGREG_SFEQ_D = 24, OPC_FLOAT_REGREG_SFNE_D = 25
, OPC_FLOAT_REGREG_SFGT_D = 26, OPC_FLOAT_REGREG_SFGE_D = 27, OPC_FLOAT_REGREG_SFLT_D = 28, OPC_FLOAT_REGREG_SFLE_D = 29
- , OPC_FLOAT_REGREG_CUST1_S = 208, OPC_FLOAT_REGREG_CUST1_D = 224
+ , OPC_FLOAT_REGREG_SFUEQ_S = 40, OPC_FLOAT_REGREG_SFUNE_S = 41, OPC_FLOAT_REGREG_SFUGT_S = 42, OPC_FLOAT_REGREG_SFUGE_S = 43
+ , OPC_FLOAT_REGREG_SFULT_S = 44, OPC_FLOAT_REGREG_SFULE_S = 45, OPC_FLOAT_REGREG_SFUN_S = 46, OPC_FLOAT_REGREG_SFUEQ_D = 56
+ , OPC_FLOAT_REGREG_SFUNE_D = 57, OPC_FLOAT_REGREG_SFUGT_D = 58, OPC_FLOAT_REGREG_SFUGE_D = 59, OPC_FLOAT_REGREG_SFULT_D = 60
+ , OPC_FLOAT_REGREG_SFULE_D = 61, OPC_FLOAT_REGREG_SFUN_D = 62, OPC_FLOAT_REGREG_CUST1_S = 208, OPC_FLOAT_REGREG_CUST1_D = 224
} INSN_OPCODE_FLOAT_REGREG;
/* Attributes. */
@@ -401,9 +404,11 @@ typedef enum ifield_type {
, OR1K_F_RESV_25_10, OR1K_F_RESV_25_5, OR1K_F_RESV_23_8, OR1K_F_RESV_20_21
, OR1K_F_RESV_20_5, OR1K_F_RESV_20_4, OR1K_F_RESV_15_8, OR1K_F_RESV_15_6
, OR1K_F_RESV_10_11, OR1K_F_RESV_10_7, OR1K_F_RESV_10_3, OR1K_F_RESV_10_1
- , OR1K_F_RESV_7_4, OR1K_F_RESV_5_2, OR1K_F_IMM16_25_5, OR1K_F_IMM16_10_11
- , OR1K_F_DISP26, OR1K_F_DISP21, OR1K_F_UIMM16, OR1K_F_SIMM16
- , OR1K_F_UIMM6, OR1K_F_UIMM16_SPLIT, OR1K_F_SIMM16_SPLIT, OR1K_F_MAX
+ , OR1K_F_RESV_8_1, OR1K_F_RESV_7_4, OR1K_F_RESV_5_2, OR1K_F_IMM16_25_5
+ , OR1K_F_IMM16_10_11, OR1K_F_DISP26, OR1K_F_DISP21, OR1K_F_UIMM16
+ , OR1K_F_SIMM16, OR1K_F_UIMM6, OR1K_F_UIMM16_SPLIT, OR1K_F_SIMM16_SPLIT
+ , OR1K_F_RDOFF_10_1, OR1K_F_RAOFF_9_1, OR1K_F_RBOFF_8_1, OR1K_F_RDD32
+ , OR1K_F_RAD32, OR1K_F_RBD32, OR1K_F_MAX
} IFIELD_TYPE;
#define MAX_IFLD ((int) OR1K_F_MAX)
@@ -429,166 +434,167 @@ typedef enum cgen_hw_attr {
/* Enum declaration for or1k hardware types. */
typedef enum cgen_hw_type {
HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
- , HW_H_IADDR, HW_H_PC, HW_H_FSR, HW_H_FDR
- , HW_H_SPR, HW_H_GPR, HW_H_SYS_VR, HW_H_SYS_UPR
- , HW_H_SYS_CPUCFGR, HW_H_SYS_DMMUCFGR, HW_H_SYS_IMMUCFGR, HW_H_SYS_DCCFGR
- , HW_H_SYS_ICCFGR, HW_H_SYS_DCFGR, HW_H_SYS_PCCFGR, HW_H_SYS_NPC
- , HW_H_SYS_SR, HW_H_SYS_PPC, HW_H_SYS_FPCSR, HW_H_SYS_EPCR0
- , HW_H_SYS_EPCR1, HW_H_SYS_EPCR2, HW_H_SYS_EPCR3, HW_H_SYS_EPCR4
- , HW_H_SYS_EPCR5, HW_H_SYS_EPCR6, HW_H_SYS_EPCR7, HW_H_SYS_EPCR8
- , HW_H_SYS_EPCR9, HW_H_SYS_EPCR10, HW_H_SYS_EPCR11, HW_H_SYS_EPCR12
- , HW_H_SYS_EPCR13, HW_H_SYS_EPCR14, HW_H_SYS_EPCR15, HW_H_SYS_EEAR0
- , HW_H_SYS_EEAR1, HW_H_SYS_EEAR2, HW_H_SYS_EEAR3, HW_H_SYS_EEAR4
- , HW_H_SYS_EEAR5, HW_H_SYS_EEAR6, HW_H_SYS_EEAR7, HW_H_SYS_EEAR8
- , HW_H_SYS_EEAR9, HW_H_SYS_EEAR10, HW_H_SYS_EEAR11, HW_H_SYS_EEAR12
- , HW_H_SYS_EEAR13, HW_H_SYS_EEAR14, HW_H_SYS_EEAR15, HW_H_SYS_ESR0
- , HW_H_SYS_ESR1, HW_H_SYS_ESR2, HW_H_SYS_ESR3, HW_H_SYS_ESR4
- , HW_H_SYS_ESR5, HW_H_SYS_ESR6, HW_H_SYS_ESR7, HW_H_SYS_ESR8
- , HW_H_SYS_ESR9, HW_H_SYS_ESR10, HW_H_SYS_ESR11, HW_H_SYS_ESR12
- , HW_H_SYS_ESR13, HW_H_SYS_ESR14, HW_H_SYS_ESR15, HW_H_SYS_GPR0
- , HW_H_SYS_GPR1, HW_H_SYS_GPR2, HW_H_SYS_GPR3, HW_H_SYS_GPR4
- , HW_H_SYS_GPR5, HW_H_SYS_GPR6, HW_H_SYS_GPR7, HW_H_SYS_GPR8
- , HW_H_SYS_GPR9, HW_H_SYS_GPR10, HW_H_SYS_GPR11, HW_H_SYS_GPR12
- , HW_H_SYS_GPR13, HW_H_SYS_GPR14, HW_H_SYS_GPR15, HW_H_SYS_GPR16
- , HW_H_SYS_GPR17, HW_H_SYS_GPR18, HW_H_SYS_GPR19, HW_H_SYS_GPR20
- , HW_H_SYS_GPR21, HW_H_SYS_GPR22, HW_H_SYS_GPR23, HW_H_SYS_GPR24
- , HW_H_SYS_GPR25, HW_H_SYS_GPR26, HW_H_SYS_GPR27, HW_H_SYS_GPR28
- , HW_H_SYS_GPR29, HW_H_SYS_GPR30, HW_H_SYS_GPR31, HW_H_SYS_GPR32
- , HW_H_SYS_GPR33, HW_H_SYS_GPR34, HW_H_SYS_GPR35, HW_H_SYS_GPR36
- , HW_H_SYS_GPR37, HW_H_SYS_GPR38, HW_H_SYS_GPR39, HW_H_SYS_GPR40
- , HW_H_SYS_GPR41, HW_H_SYS_GPR42, HW_H_SYS_GPR43, HW_H_SYS_GPR44
- , HW_H_SYS_GPR45, HW_H_SYS_GPR46, HW_H_SYS_GPR47, HW_H_SYS_GPR48
- , HW_H_SYS_GPR49, HW_H_SYS_GPR50, HW_H_SYS_GPR51, HW_H_SYS_GPR52
- , HW_H_SYS_GPR53, HW_H_SYS_GPR54, HW_H_SYS_GPR55, HW_H_SYS_GPR56
- , HW_H_SYS_GPR57, HW_H_SYS_GPR58, HW_H_SYS_GPR59, HW_H_SYS_GPR60
- , HW_H_SYS_GPR61, HW_H_SYS_GPR62, HW_H_SYS_GPR63, HW_H_SYS_GPR64
- , HW_H_SYS_GPR65, HW_H_SYS_GPR66, HW_H_SYS_GPR67, HW_H_SYS_GPR68
- , HW_H_SYS_GPR69, HW_H_SYS_GPR70, HW_H_SYS_GPR71, HW_H_SYS_GPR72
- , HW_H_SYS_GPR73, HW_H_SYS_GPR74, HW_H_SYS_GPR75, HW_H_SYS_GPR76
- , HW_H_SYS_GPR77, HW_H_SYS_GPR78, HW_H_SYS_GPR79, HW_H_SYS_GPR80
- , HW_H_SYS_GPR81, HW_H_SYS_GPR82, HW_H_SYS_GPR83, HW_H_SYS_GPR84
- , HW_H_SYS_GPR85, HW_H_SYS_GPR86, HW_H_SYS_GPR87, HW_H_SYS_GPR88
- , HW_H_SYS_GPR89, HW_H_SYS_GPR90, HW_H_SYS_GPR91, HW_H_SYS_GPR92
- , HW_H_SYS_GPR93, HW_H_SYS_GPR94, HW_H_SYS_GPR95, HW_H_SYS_GPR96
- , HW_H_SYS_GPR97, HW_H_SYS_GPR98, HW_H_SYS_GPR99, HW_H_SYS_GPR100
- , HW_H_SYS_GPR101, HW_H_SYS_GPR102, HW_H_SYS_GPR103, HW_H_SYS_GPR104
- , HW_H_SYS_GPR105, HW_H_SYS_GPR106, HW_H_SYS_GPR107, HW_H_SYS_GPR108
- , HW_H_SYS_GPR109, HW_H_SYS_GPR110, HW_H_SYS_GPR111, HW_H_SYS_GPR112
- , HW_H_SYS_GPR113, HW_H_SYS_GPR114, HW_H_SYS_GPR115, HW_H_SYS_GPR116
- , HW_H_SYS_GPR117, HW_H_SYS_GPR118, HW_H_SYS_GPR119, HW_H_SYS_GPR120
- , HW_H_SYS_GPR121, HW_H_SYS_GPR122, HW_H_SYS_GPR123, HW_H_SYS_GPR124
- , HW_H_SYS_GPR125, HW_H_SYS_GPR126, HW_H_SYS_GPR127, HW_H_SYS_GPR128
- , HW_H_SYS_GPR129, HW_H_SYS_GPR130, HW_H_SYS_GPR131, HW_H_SYS_GPR132
- , HW_H_SYS_GPR133, HW_H_SYS_GPR134, HW_H_SYS_GPR135, HW_H_SYS_GPR136
- , HW_H_SYS_GPR137, HW_H_SYS_GPR138, HW_H_SYS_GPR139, HW_H_SYS_GPR140
- , HW_H_SYS_GPR141, HW_H_SYS_GPR142, HW_H_SYS_GPR143, HW_H_SYS_GPR144
- , HW_H_SYS_GPR145, HW_H_SYS_GPR146, HW_H_SYS_GPR147, HW_H_SYS_GPR148
- , HW_H_SYS_GPR149, HW_H_SYS_GPR150, HW_H_SYS_GPR151, HW_H_SYS_GPR152
- , HW_H_SYS_GPR153, HW_H_SYS_GPR154, HW_H_SYS_GPR155, HW_H_SYS_GPR156
- , HW_H_SYS_GPR157, HW_H_SYS_GPR158, HW_H_SYS_GPR159, HW_H_SYS_GPR160
- , HW_H_SYS_GPR161, HW_H_SYS_GPR162, HW_H_SYS_GPR163, HW_H_SYS_GPR164
- , HW_H_SYS_GPR165, HW_H_SYS_GPR166, HW_H_SYS_GPR167, HW_H_SYS_GPR168
- , HW_H_SYS_GPR169, HW_H_SYS_GPR170, HW_H_SYS_GPR171, HW_H_SYS_GPR172
- , HW_H_SYS_GPR173, HW_H_SYS_GPR174, HW_H_SYS_GPR175, HW_H_SYS_GPR176
- , HW_H_SYS_GPR177, HW_H_SYS_GPR178, HW_H_SYS_GPR179, HW_H_SYS_GPR180
- , HW_H_SYS_GPR181, HW_H_SYS_GPR182, HW_H_SYS_GPR183, HW_H_SYS_GPR184
- , HW_H_SYS_GPR185, HW_H_SYS_GPR186, HW_H_SYS_GPR187, HW_H_SYS_GPR188
- , HW_H_SYS_GPR189, HW_H_SYS_GPR190, HW_H_SYS_GPR191, HW_H_SYS_GPR192
- , HW_H_SYS_GPR193, HW_H_SYS_GPR194, HW_H_SYS_GPR195, HW_H_SYS_GPR196
- , HW_H_SYS_GPR197, HW_H_SYS_GPR198, HW_H_SYS_GPR199, HW_H_SYS_GPR200
- , HW_H_SYS_GPR201, HW_H_SYS_GPR202, HW_H_SYS_GPR203, HW_H_SYS_GPR204
- , HW_H_SYS_GPR205, HW_H_SYS_GPR206, HW_H_SYS_GPR207, HW_H_SYS_GPR208
- , HW_H_SYS_GPR209, HW_H_SYS_GPR210, HW_H_SYS_GPR211, HW_H_SYS_GPR212
- , HW_H_SYS_GPR213, HW_H_SYS_GPR214, HW_H_SYS_GPR215, HW_H_SYS_GPR216
- , HW_H_SYS_GPR217, HW_H_SYS_GPR218, HW_H_SYS_GPR219, HW_H_SYS_GPR220
- , HW_H_SYS_GPR221, HW_H_SYS_GPR222, HW_H_SYS_GPR223, HW_H_SYS_GPR224
- , HW_H_SYS_GPR225, HW_H_SYS_GPR226, HW_H_SYS_GPR227, HW_H_SYS_GPR228
- , HW_H_SYS_GPR229, HW_H_SYS_GPR230, HW_H_SYS_GPR231, HW_H_SYS_GPR232
- , HW_H_SYS_GPR233, HW_H_SYS_GPR234, HW_H_SYS_GPR235, HW_H_SYS_GPR236
- , HW_H_SYS_GPR237, HW_H_SYS_GPR238, HW_H_SYS_GPR239, HW_H_SYS_GPR240
- , HW_H_SYS_GPR241, HW_H_SYS_GPR242, HW_H_SYS_GPR243, HW_H_SYS_GPR244
- , HW_H_SYS_GPR245, HW_H_SYS_GPR246, HW_H_SYS_GPR247, HW_H_SYS_GPR248
- , HW_H_SYS_GPR249, HW_H_SYS_GPR250, HW_H_SYS_GPR251, HW_H_SYS_GPR252
- , HW_H_SYS_GPR253, HW_H_SYS_GPR254, HW_H_SYS_GPR255, HW_H_SYS_GPR256
- , HW_H_SYS_GPR257, HW_H_SYS_GPR258, HW_H_SYS_GPR259, HW_H_SYS_GPR260
- , HW_H_SYS_GPR261, HW_H_SYS_GPR262, HW_H_SYS_GPR263, HW_H_SYS_GPR264
- , HW_H_SYS_GPR265, HW_H_SYS_GPR266, HW_H_SYS_GPR267, HW_H_SYS_GPR268
- , HW_H_SYS_GPR269, HW_H_SYS_GPR270, HW_H_SYS_GPR271, HW_H_SYS_GPR272
- , HW_H_SYS_GPR273, HW_H_SYS_GPR274, HW_H_SYS_GPR275, HW_H_SYS_GPR276
- , HW_H_SYS_GPR277, HW_H_SYS_GPR278, HW_H_SYS_GPR279, HW_H_SYS_GPR280
- , HW_H_SYS_GPR281, HW_H_SYS_GPR282, HW_H_SYS_GPR283, HW_H_SYS_GPR284
- , HW_H_SYS_GPR285, HW_H_SYS_GPR286, HW_H_SYS_GPR287, HW_H_SYS_GPR288
- , HW_H_SYS_GPR289, HW_H_SYS_GPR290, HW_H_SYS_GPR291, HW_H_SYS_GPR292
- , HW_H_SYS_GPR293, HW_H_SYS_GPR294, HW_H_SYS_GPR295, HW_H_SYS_GPR296
- , HW_H_SYS_GPR297, HW_H_SYS_GPR298, HW_H_SYS_GPR299, HW_H_SYS_GPR300
- , HW_H_SYS_GPR301, HW_H_SYS_GPR302, HW_H_SYS_GPR303, HW_H_SYS_GPR304
- , HW_H_SYS_GPR305, HW_H_SYS_GPR306, HW_H_SYS_GPR307, HW_H_SYS_GPR308
- , HW_H_SYS_GPR309, HW_H_SYS_GPR310, HW_H_SYS_GPR311, HW_H_SYS_GPR312
- , HW_H_SYS_GPR313, HW_H_SYS_GPR314, HW_H_SYS_GPR315, HW_H_SYS_GPR316
- , HW_H_SYS_GPR317, HW_H_SYS_GPR318, HW_H_SYS_GPR319, HW_H_SYS_GPR320
- , HW_H_SYS_GPR321, HW_H_SYS_GPR322, HW_H_SYS_GPR323, HW_H_SYS_GPR324
- , HW_H_SYS_GPR325, HW_H_SYS_GPR326, HW_H_SYS_GPR327, HW_H_SYS_GPR328
- , HW_H_SYS_GPR329, HW_H_SYS_GPR330, HW_H_SYS_GPR331, HW_H_SYS_GPR332
- , HW_H_SYS_GPR333, HW_H_SYS_GPR334, HW_H_SYS_GPR335, HW_H_SYS_GPR336
- , HW_H_SYS_GPR337, HW_H_SYS_GPR338, HW_H_SYS_GPR339, HW_H_SYS_GPR340
- , HW_H_SYS_GPR341, HW_H_SYS_GPR342, HW_H_SYS_GPR343, HW_H_SYS_GPR344
- , HW_H_SYS_GPR345, HW_H_SYS_GPR346, HW_H_SYS_GPR347, HW_H_SYS_GPR348
- , HW_H_SYS_GPR349, HW_H_SYS_GPR350, HW_H_SYS_GPR351, HW_H_SYS_GPR352
- , HW_H_SYS_GPR353, HW_H_SYS_GPR354, HW_H_SYS_GPR355, HW_H_SYS_GPR356
- , HW_H_SYS_GPR357, HW_H_SYS_GPR358, HW_H_SYS_GPR359, HW_H_SYS_GPR360
- , HW_H_SYS_GPR361, HW_H_SYS_GPR362, HW_H_SYS_GPR363, HW_H_SYS_GPR364
- , HW_H_SYS_GPR365, HW_H_SYS_GPR366, HW_H_SYS_GPR367, HW_H_SYS_GPR368
- , HW_H_SYS_GPR369, HW_H_SYS_GPR370, HW_H_SYS_GPR371, HW_H_SYS_GPR372
- , HW_H_SYS_GPR373, HW_H_SYS_GPR374, HW_H_SYS_GPR375, HW_H_SYS_GPR376
- , HW_H_SYS_GPR377, HW_H_SYS_GPR378, HW_H_SYS_GPR379, HW_H_SYS_GPR380
- , HW_H_SYS_GPR381, HW_H_SYS_GPR382, HW_H_SYS_GPR383, HW_H_SYS_GPR384
- , HW_H_SYS_GPR385, HW_H_SYS_GPR386, HW_H_SYS_GPR387, HW_H_SYS_GPR388
- , HW_H_SYS_GPR389, HW_H_SYS_GPR390, HW_H_SYS_GPR391, HW_H_SYS_GPR392
- , HW_H_SYS_GPR393, HW_H_SYS_GPR394, HW_H_SYS_GPR395, HW_H_SYS_GPR396
- , HW_H_SYS_GPR397, HW_H_SYS_GPR398, HW_H_SYS_GPR399, HW_H_SYS_GPR400
- , HW_H_SYS_GPR401, HW_H_SYS_GPR402, HW_H_SYS_GPR403, HW_H_SYS_GPR404
- , HW_H_SYS_GPR405, HW_H_SYS_GPR406, HW_H_SYS_GPR407, HW_H_SYS_GPR408
- , HW_H_SYS_GPR409, HW_H_SYS_GPR410, HW_H_SYS_GPR411, HW_H_SYS_GPR412
- , HW_H_SYS_GPR413, HW_H_SYS_GPR414, HW_H_SYS_GPR415, HW_H_SYS_GPR416
- , HW_H_SYS_GPR417, HW_H_SYS_GPR418, HW_H_SYS_GPR419, HW_H_SYS_GPR420
- , HW_H_SYS_GPR421, HW_H_SYS_GPR422, HW_H_SYS_GPR423, HW_H_SYS_GPR424
- , HW_H_SYS_GPR425, HW_H_SYS_GPR426, HW_H_SYS_GPR427, HW_H_SYS_GPR428
- , HW_H_SYS_GPR429, HW_H_SYS_GPR430, HW_H_SYS_GPR431, HW_H_SYS_GPR432
- , HW_H_SYS_GPR433, HW_H_SYS_GPR434, HW_H_SYS_GPR435, HW_H_SYS_GPR436
- , HW_H_SYS_GPR437, HW_H_SYS_GPR438, HW_H_SYS_GPR439, HW_H_SYS_GPR440
- , HW_H_SYS_GPR441, HW_H_SYS_GPR442, HW_H_SYS_GPR443, HW_H_SYS_GPR444
- , HW_H_SYS_GPR445, HW_H_SYS_GPR446, HW_H_SYS_GPR447, HW_H_SYS_GPR448
- , HW_H_SYS_GPR449, HW_H_SYS_GPR450, HW_H_SYS_GPR451, HW_H_SYS_GPR452
- , HW_H_SYS_GPR453, HW_H_SYS_GPR454, HW_H_SYS_GPR455, HW_H_SYS_GPR456
- , HW_H_SYS_GPR457, HW_H_SYS_GPR458, HW_H_SYS_GPR459, HW_H_SYS_GPR460
- , HW_H_SYS_GPR461, HW_H_SYS_GPR462, HW_H_SYS_GPR463, HW_H_SYS_GPR464
- , HW_H_SYS_GPR465, HW_H_SYS_GPR466, HW_H_SYS_GPR467, HW_H_SYS_GPR468
- , HW_H_SYS_GPR469, HW_H_SYS_GPR470, HW_H_SYS_GPR471, HW_H_SYS_GPR472
- , HW_H_SYS_GPR473, HW_H_SYS_GPR474, HW_H_SYS_GPR475, HW_H_SYS_GPR476
- , HW_H_SYS_GPR477, HW_H_SYS_GPR478, HW_H_SYS_GPR479, HW_H_SYS_GPR480
- , HW_H_SYS_GPR481, HW_H_SYS_GPR482, HW_H_SYS_GPR483, HW_H_SYS_GPR484
- , HW_H_SYS_GPR485, HW_H_SYS_GPR486, HW_H_SYS_GPR487, HW_H_SYS_GPR488
- , HW_H_SYS_GPR489, HW_H_SYS_GPR490, HW_H_SYS_GPR491, HW_H_SYS_GPR492
- , HW_H_SYS_GPR493, HW_H_SYS_GPR494, HW_H_SYS_GPR495, HW_H_SYS_GPR496
- , HW_H_SYS_GPR497, HW_H_SYS_GPR498, HW_H_SYS_GPR499, HW_H_SYS_GPR500
- , HW_H_SYS_GPR501, HW_H_SYS_GPR502, HW_H_SYS_GPR503, HW_H_SYS_GPR504
- , HW_H_SYS_GPR505, HW_H_SYS_GPR506, HW_H_SYS_GPR507, HW_H_SYS_GPR508
- , HW_H_SYS_GPR509, HW_H_SYS_GPR510, HW_H_SYS_GPR511, HW_H_MAC_MACLO
- , HW_H_MAC_MACHI, HW_H_TICK_TTMR, HW_H_SYS_VR_REV, HW_H_SYS_VR_CFG
- , HW_H_SYS_VR_VER, HW_H_SYS_UPR_UP, HW_H_SYS_UPR_DCP, HW_H_SYS_UPR_ICP
- , HW_H_SYS_UPR_DMP, HW_H_SYS_UPR_MP, HW_H_SYS_UPR_IMP, HW_H_SYS_UPR_DUP
- , HW_H_SYS_UPR_PCUP, HW_H_SYS_UPR_PICP, HW_H_SYS_UPR_PMP, HW_H_SYS_UPR_TTP
- , HW_H_SYS_UPR_CUP, HW_H_SYS_CPUCFGR_NSGR, HW_H_SYS_CPUCFGR_CGF, HW_H_SYS_CPUCFGR_OB32S
- , HW_H_SYS_CPUCFGR_OB64S, HW_H_SYS_CPUCFGR_OF32S, HW_H_SYS_CPUCFGR_OF64S, HW_H_SYS_CPUCFGR_OV64S
- , HW_H_SYS_CPUCFGR_ND, HW_H_SYS_SR_SM, HW_H_SYS_SR_TEE, HW_H_SYS_SR_IEE
- , HW_H_SYS_SR_DCE, HW_H_SYS_SR_ICE, HW_H_SYS_SR_DME, HW_H_SYS_SR_IME
- , HW_H_SYS_SR_LEE, HW_H_SYS_SR_CE, HW_H_SYS_SR_F, HW_H_SYS_SR_CY
- , HW_H_SYS_SR_OV, HW_H_SYS_SR_OVE, HW_H_SYS_SR_DSX, HW_H_SYS_SR_EPH
- , HW_H_SYS_SR_FO, HW_H_SYS_SR_SUMRA, HW_H_SYS_SR_CID, HW_H_SYS_FPCSR_FPEE
- , HW_H_SYS_FPCSR_RM, HW_H_SYS_FPCSR_OVF, HW_H_SYS_FPCSR_UNF, HW_H_SYS_FPCSR_SNF
- , HW_H_SYS_FPCSR_QNF, HW_H_SYS_FPCSR_ZF, HW_H_SYS_FPCSR_IXF, HW_H_SYS_FPCSR_IVF
- , HW_H_SYS_FPCSR_INF, HW_H_SYS_FPCSR_DZF, HW_H_SIMM16, HW_H_UIMM16
- , HW_H_UIMM6, HW_H_ATOMIC_RESERVE, HW_H_ATOMIC_ADDRESS, HW_MAX
+ , HW_H_IADDR, HW_H_PC, HW_H_SPR, HW_H_GPR
+ , HW_H_FSR, HW_H_FDR, HW_H_FD32R, HW_H_I64R
+ , HW_H_SYS_VR, HW_H_SYS_UPR, HW_H_SYS_CPUCFGR, HW_H_SYS_DMMUCFGR
+ , HW_H_SYS_IMMUCFGR, HW_H_SYS_DCCFGR, HW_H_SYS_ICCFGR, HW_H_SYS_DCFGR
+ , HW_H_SYS_PCCFGR, HW_H_SYS_NPC, HW_H_SYS_SR, HW_H_SYS_PPC
+ , HW_H_SYS_FPCSR, HW_H_SYS_EPCR0, HW_H_SYS_EPCR1, HW_H_SYS_EPCR2
+ , HW_H_SYS_EPCR3, HW_H_SYS_EPCR4, HW_H_SYS_EPCR5, HW_H_SYS_EPCR6
+ , HW_H_SYS_EPCR7, HW_H_SYS_EPCR8, HW_H_SYS_EPCR9, HW_H_SYS_EPCR10
+ , HW_H_SYS_EPCR11, HW_H_SYS_EPCR12, HW_H_SYS_EPCR13, HW_H_SYS_EPCR14
+ , HW_H_SYS_EPCR15, HW_H_SYS_EEAR0, HW_H_SYS_EEAR1, HW_H_SYS_EEAR2
+ , HW_H_SYS_EEAR3, HW_H_SYS_EEAR4, HW_H_SYS_EEAR5, HW_H_SYS_EEAR6
+ , HW_H_SYS_EEAR7, HW_H_SYS_EEAR8, HW_H_SYS_EEAR9, HW_H_SYS_EEAR10
+ , HW_H_SYS_EEAR11, HW_H_SYS_EEAR12, HW_H_SYS_EEAR13, HW_H_SYS_EEAR14
+ , HW_H_SYS_EEAR15, HW_H_SYS_ESR0, HW_H_SYS_ESR1, HW_H_SYS_ESR2
+ , HW_H_SYS_ESR3, HW_H_SYS_ESR4, HW_H_SYS_ESR5, HW_H_SYS_ESR6
+ , HW_H_SYS_ESR7, HW_H_SYS_ESR8, HW_H_SYS_ESR9, HW_H_SYS_ESR10
+ , HW_H_SYS_ESR11, HW_H_SYS_ESR12, HW_H_SYS_ESR13, HW_H_SYS_ESR14
+ , HW_H_SYS_ESR15, HW_H_SYS_GPR0, HW_H_SYS_GPR1, HW_H_SYS_GPR2
+ , HW_H_SYS_GPR3, HW_H_SYS_GPR4, HW_H_SYS_GPR5, HW_H_SYS_GPR6
+ , HW_H_SYS_GPR7, HW_H_SYS_GPR8, HW_H_SYS_GPR9, HW_H_SYS_GPR10
+ , HW_H_SYS_GPR11, HW_H_SYS_GPR12, HW_H_SYS_GPR13, HW_H_SYS_GPR14
+ , HW_H_SYS_GPR15, HW_H_SYS_GPR16, HW_H_SYS_GPR17, HW_H_SYS_GPR18
+ , HW_H_SYS_GPR19, HW_H_SYS_GPR20, HW_H_SYS_GPR21, HW_H_SYS_GPR22
+ , HW_H_SYS_GPR23, HW_H_SYS_GPR24, HW_H_SYS_GPR25, HW_H_SYS_GPR26
+ , HW_H_SYS_GPR27, HW_H_SYS_GPR28, HW_H_SYS_GPR29, HW_H_SYS_GPR30
+ , HW_H_SYS_GPR31, HW_H_SYS_GPR32, HW_H_SYS_GPR33, HW_H_SYS_GPR34
+ , HW_H_SYS_GPR35, HW_H_SYS_GPR36, HW_H_SYS_GPR37, HW_H_SYS_GPR38
+ , HW_H_SYS_GPR39, HW_H_SYS_GPR40, HW_H_SYS_GPR41, HW_H_SYS_GPR42
+ , HW_H_SYS_GPR43, HW_H_SYS_GPR44, HW_H_SYS_GPR45, HW_H_SYS_GPR46
+ , HW_H_SYS_GPR47, HW_H_SYS_GPR48, HW_H_SYS_GPR49, HW_H_SYS_GPR50
+ , HW_H_SYS_GPR51, HW_H_SYS_GPR52, HW_H_SYS_GPR53, HW_H_SYS_GPR54
+ , HW_H_SYS_GPR55, HW_H_SYS_GPR56, HW_H_SYS_GPR57, HW_H_SYS_GPR58
+ , HW_H_SYS_GPR59, HW_H_SYS_GPR60, HW_H_SYS_GPR61, HW_H_SYS_GPR62
+ , HW_H_SYS_GPR63, HW_H_SYS_GPR64, HW_H_SYS_GPR65, HW_H_SYS_GPR66
+ , HW_H_SYS_GPR67, HW_H_SYS_GPR68, HW_H_SYS_GPR69, HW_H_SYS_GPR70
+ , HW_H_SYS_GPR71, HW_H_SYS_GPR72, HW_H_SYS_GPR73, HW_H_SYS_GPR74
+ , HW_H_SYS_GPR75, HW_H_SYS_GPR76, HW_H_SYS_GPR77, HW_H_SYS_GPR78
+ , HW_H_SYS_GPR79, HW_H_SYS_GPR80, HW_H_SYS_GPR81, HW_H_SYS_GPR82
+ , HW_H_SYS_GPR83, HW_H_SYS_GPR84, HW_H_SYS_GPR85, HW_H_SYS_GPR86
+ , HW_H_SYS_GPR87, HW_H_SYS_GPR88, HW_H_SYS_GPR89, HW_H_SYS_GPR90
+ , HW_H_SYS_GPR91, HW_H_SYS_GPR92, HW_H_SYS_GPR93, HW_H_SYS_GPR94
+ , HW_H_SYS_GPR95, HW_H_SYS_GPR96, HW_H_SYS_GPR97, HW_H_SYS_GPR98
+ , HW_H_SYS_GPR99, HW_H_SYS_GPR100, HW_H_SYS_GPR101, HW_H_SYS_GPR102
+ , HW_H_SYS_GPR103, HW_H_SYS_GPR104, HW_H_SYS_GPR105, HW_H_SYS_GPR106
+ , HW_H_SYS_GPR107, HW_H_SYS_GPR108, HW_H_SYS_GPR109, HW_H_SYS_GPR110
+ , HW_H_SYS_GPR111, HW_H_SYS_GPR112, HW_H_SYS_GPR113, HW_H_SYS_GPR114
+ , HW_H_SYS_GPR115, HW_H_SYS_GPR116, HW_H_SYS_GPR117, HW_H_SYS_GPR118
+ , HW_H_SYS_GPR119, HW_H_SYS_GPR120, HW_H_SYS_GPR121, HW_H_SYS_GPR122
+ , HW_H_SYS_GPR123, HW_H_SYS_GPR124, HW_H_SYS_GPR125, HW_H_SYS_GPR126
+ , HW_H_SYS_GPR127, HW_H_SYS_GPR128, HW_H_SYS_GPR129, HW_H_SYS_GPR130
+ , HW_H_SYS_GPR131, HW_H_SYS_GPR132, HW_H_SYS_GPR133, HW_H_SYS_GPR134
+ , HW_H_SYS_GPR135, HW_H_SYS_GPR136, HW_H_SYS_GPR137, HW_H_SYS_GPR138
+ , HW_H_SYS_GPR139, HW_H_SYS_GPR140, HW_H_SYS_GPR141, HW_H_SYS_GPR142
+ , HW_H_SYS_GPR143, HW_H_SYS_GPR144, HW_H_SYS_GPR145, HW_H_SYS_GPR146
+ , HW_H_SYS_GPR147, HW_H_SYS_GPR148, HW_H_SYS_GPR149, HW_H_SYS_GPR150
+ , HW_H_SYS_GPR151, HW_H_SYS_GPR152, HW_H_SYS_GPR153, HW_H_SYS_GPR154
+ , HW_H_SYS_GPR155, HW_H_SYS_GPR156, HW_H_SYS_GPR157, HW_H_SYS_GPR158
+ , HW_H_SYS_GPR159, HW_H_SYS_GPR160, HW_H_SYS_GPR161, HW_H_SYS_GPR162
+ , HW_H_SYS_GPR163, HW_H_SYS_GPR164, HW_H_SYS_GPR165, HW_H_SYS_GPR166
+ , HW_H_SYS_GPR167, HW_H_SYS_GPR168, HW_H_SYS_GPR169, HW_H_SYS_GPR170
+ , HW_H_SYS_GPR171, HW_H_SYS_GPR172, HW_H_SYS_GPR173, HW_H_SYS_GPR174
+ , HW_H_SYS_GPR175, HW_H_SYS_GPR176, HW_H_SYS_GPR177, HW_H_SYS_GPR178
+ , HW_H_SYS_GPR179, HW_H_SYS_GPR180, HW_H_SYS_GPR181, HW_H_SYS_GPR182
+ , HW_H_SYS_GPR183, HW_H_SYS_GPR184, HW_H_SYS_GPR185, HW_H_SYS_GPR186
+ , HW_H_SYS_GPR187, HW_H_SYS_GPR188, HW_H_SYS_GPR189, HW_H_SYS_GPR190
+ , HW_H_SYS_GPR191, HW_H_SYS_GPR192, HW_H_SYS_GPR193, HW_H_SYS_GPR194
+ , HW_H_SYS_GPR195, HW_H_SYS_GPR196, HW_H_SYS_GPR197, HW_H_SYS_GPR198
+ , HW_H_SYS_GPR199, HW_H_SYS_GPR200, HW_H_SYS_GPR201, HW_H_SYS_GPR202
+ , HW_H_SYS_GPR203, HW_H_SYS_GPR204, HW_H_SYS_GPR205, HW_H_SYS_GPR206
+ , HW_H_SYS_GPR207, HW_H_SYS_GPR208, HW_H_SYS_GPR209, HW_H_SYS_GPR210
+ , HW_H_SYS_GPR211, HW_H_SYS_GPR212, HW_H_SYS_GPR213, HW_H_SYS_GPR214
+ , HW_H_SYS_GPR215, HW_H_SYS_GPR216, HW_H_SYS_GPR217, HW_H_SYS_GPR218
+ , HW_H_SYS_GPR219, HW_H_SYS_GPR220, HW_H_SYS_GPR221, HW_H_SYS_GPR222
+ , HW_H_SYS_GPR223, HW_H_SYS_GPR224, HW_H_SYS_GPR225, HW_H_SYS_GPR226
+ , HW_H_SYS_GPR227, HW_H_SYS_GPR228, HW_H_SYS_GPR229, HW_H_SYS_GPR230
+ , HW_H_SYS_GPR231, HW_H_SYS_GPR232, HW_H_SYS_GPR233, HW_H_SYS_GPR234
+ , HW_H_SYS_GPR235, HW_H_SYS_GPR236, HW_H_SYS_GPR237, HW_H_SYS_GPR238
+ , HW_H_SYS_GPR239, HW_H_SYS_GPR240, HW_H_SYS_GPR241, HW_H_SYS_GPR242
+ , HW_H_SYS_GPR243, HW_H_SYS_GPR244, HW_H_SYS_GPR245, HW_H_SYS_GPR246
+ , HW_H_SYS_GPR247, HW_H_SYS_GPR248, HW_H_SYS_GPR249, HW_H_SYS_GPR250
+ , HW_H_SYS_GPR251, HW_H_SYS_GPR252, HW_H_SYS_GPR253, HW_H_SYS_GPR254
+ , HW_H_SYS_GPR255, HW_H_SYS_GPR256, HW_H_SYS_GPR257, HW_H_SYS_GPR258
+ , HW_H_SYS_GPR259, HW_H_SYS_GPR260, HW_H_SYS_GPR261, HW_H_SYS_GPR262
+ , HW_H_SYS_GPR263, HW_H_SYS_GPR264, HW_H_SYS_GPR265, HW_H_SYS_GPR266
+ , HW_H_SYS_GPR267, HW_H_SYS_GPR268, HW_H_SYS_GPR269, HW_H_SYS_GPR270
+ , HW_H_SYS_GPR271, HW_H_SYS_GPR272, HW_H_SYS_GPR273, HW_H_SYS_GPR274
+ , HW_H_SYS_GPR275, HW_H_SYS_GPR276, HW_H_SYS_GPR277, HW_H_SYS_GPR278
+ , HW_H_SYS_GPR279, HW_H_SYS_GPR280, HW_H_SYS_GPR281, HW_H_SYS_GPR282
+ , HW_H_SYS_GPR283, HW_H_SYS_GPR284, HW_H_SYS_GPR285, HW_H_SYS_GPR286
+ , HW_H_SYS_GPR287, HW_H_SYS_GPR288, HW_H_SYS_GPR289, HW_H_SYS_GPR290
+ , HW_H_SYS_GPR291, HW_H_SYS_GPR292, HW_H_SYS_GPR293, HW_H_SYS_GPR294
+ , HW_H_SYS_GPR295, HW_H_SYS_GPR296, HW_H_SYS_GPR297, HW_H_SYS_GPR298
+ , HW_H_SYS_GPR299, HW_H_SYS_GPR300, HW_H_SYS_GPR301, HW_H_SYS_GPR302
+ , HW_H_SYS_GPR303, HW_H_SYS_GPR304, HW_H_SYS_GPR305, HW_H_SYS_GPR306
+ , HW_H_SYS_GPR307, HW_H_SYS_GPR308, HW_H_SYS_GPR309, HW_H_SYS_GPR310
+ , HW_H_SYS_GPR311, HW_H_SYS_GPR312, HW_H_SYS_GPR313, HW_H_SYS_GPR314
+ , HW_H_SYS_GPR315, HW_H_SYS_GPR316, HW_H_SYS_GPR317, HW_H_SYS_GPR318
+ , HW_H_SYS_GPR319, HW_H_SYS_GPR320, HW_H_SYS_GPR321, HW_H_SYS_GPR322
+ , HW_H_SYS_GPR323, HW_H_SYS_GPR324, HW_H_SYS_GPR325, HW_H_SYS_GPR326
+ , HW_H_SYS_GPR327, HW_H_SYS_GPR328, HW_H_SYS_GPR329, HW_H_SYS_GPR330
+ , HW_H_SYS_GPR331, HW_H_SYS_GPR332, HW_H_SYS_GPR333, HW_H_SYS_GPR334
+ , HW_H_SYS_GPR335, HW_H_SYS_GPR336, HW_H_SYS_GPR337, HW_H_SYS_GPR338
+ , HW_H_SYS_GPR339, HW_H_SYS_GPR340, HW_H_SYS_GPR341, HW_H_SYS_GPR342
+ , HW_H_SYS_GPR343, HW_H_SYS_GPR344, HW_H_SYS_GPR345, HW_H_SYS_GPR346
+ , HW_H_SYS_GPR347, HW_H_SYS_GPR348, HW_H_SYS_GPR349, HW_H_SYS_GPR350
+ , HW_H_SYS_GPR351, HW_H_SYS_GPR352, HW_H_SYS_GPR353, HW_H_SYS_GPR354
+ , HW_H_SYS_GPR355, HW_H_SYS_GPR356, HW_H_SYS_GPR357, HW_H_SYS_GPR358
+ , HW_H_SYS_GPR359, HW_H_SYS_GPR360, HW_H_SYS_GPR361, HW_H_SYS_GPR362
+ , HW_H_SYS_GPR363, HW_H_SYS_GPR364, HW_H_SYS_GPR365, HW_H_SYS_GPR366
+ , HW_H_SYS_GPR367, HW_H_SYS_GPR368, HW_H_SYS_GPR369, HW_H_SYS_GPR370
+ , HW_H_SYS_GPR371, HW_H_SYS_GPR372, HW_H_SYS_GPR373, HW_H_SYS_GPR374
+ , HW_H_SYS_GPR375, HW_H_SYS_GPR376, HW_H_SYS_GPR377, HW_H_SYS_GPR378
+ , HW_H_SYS_GPR379, HW_H_SYS_GPR380, HW_H_SYS_GPR381, HW_H_SYS_GPR382
+ , HW_H_SYS_GPR383, HW_H_SYS_GPR384, HW_H_SYS_GPR385, HW_H_SYS_GPR386
+ , HW_H_SYS_GPR387, HW_H_SYS_GPR388, HW_H_SYS_GPR389, HW_H_SYS_GPR390
+ , HW_H_SYS_GPR391, HW_H_SYS_GPR392, HW_H_SYS_GPR393, HW_H_SYS_GPR394
+ , HW_H_SYS_GPR395, HW_H_SYS_GPR396, HW_H_SYS_GPR397, HW_H_SYS_GPR398
+ , HW_H_SYS_GPR399, HW_H_SYS_GPR400, HW_H_SYS_GPR401, HW_H_SYS_GPR402
+ , HW_H_SYS_GPR403, HW_H_SYS_GPR404, HW_H_SYS_GPR405, HW_H_SYS_GPR406
+ , HW_H_SYS_GPR407, HW_H_SYS_GPR408, HW_H_SYS_GPR409, HW_H_SYS_GPR410
+ , HW_H_SYS_GPR411, HW_H_SYS_GPR412, HW_H_SYS_GPR413, HW_H_SYS_GPR414
+ , HW_H_SYS_GPR415, HW_H_SYS_GPR416, HW_H_SYS_GPR417, HW_H_SYS_GPR418
+ , HW_H_SYS_GPR419, HW_H_SYS_GPR420, HW_H_SYS_GPR421, HW_H_SYS_GPR422
+ , HW_H_SYS_GPR423, HW_H_SYS_GPR424, HW_H_SYS_GPR425, HW_H_SYS_GPR426
+ , HW_H_SYS_GPR427, HW_H_SYS_GPR428, HW_H_SYS_GPR429, HW_H_SYS_GPR430
+ , HW_H_SYS_GPR431, HW_H_SYS_GPR432, HW_H_SYS_GPR433, HW_H_SYS_GPR434
+ , HW_H_SYS_GPR435, HW_H_SYS_GPR436, HW_H_SYS_GPR437, HW_H_SYS_GPR438
+ , HW_H_SYS_GPR439, HW_H_SYS_GPR440, HW_H_SYS_GPR441, HW_H_SYS_GPR442
+ , HW_H_SYS_GPR443, HW_H_SYS_GPR444, HW_H_SYS_GPR445, HW_H_SYS_GPR446
+ , HW_H_SYS_GPR447, HW_H_SYS_GPR448, HW_H_SYS_GPR449, HW_H_SYS_GPR450
+ , HW_H_SYS_GPR451, HW_H_SYS_GPR452, HW_H_SYS_GPR453, HW_H_SYS_GPR454
+ , HW_H_SYS_GPR455, HW_H_SYS_GPR456, HW_H_SYS_GPR457, HW_H_SYS_GPR458
+ , HW_H_SYS_GPR459, HW_H_SYS_GPR460, HW_H_SYS_GPR461, HW_H_SYS_GPR462
+ , HW_H_SYS_GPR463, HW_H_SYS_GPR464, HW_H_SYS_GPR465, HW_H_SYS_GPR466
+ , HW_H_SYS_GPR467, HW_H_SYS_GPR468, HW_H_SYS_GPR469, HW_H_SYS_GPR470
+ , HW_H_SYS_GPR471, HW_H_SYS_GPR472, HW_H_SYS_GPR473, HW_H_SYS_GPR474
+ , HW_H_SYS_GPR475, HW_H_SYS_GPR476, HW_H_SYS_GPR477, HW_H_SYS_GPR478
+ , HW_H_SYS_GPR479, HW_H_SYS_GPR480, HW_H_SYS_GPR481, HW_H_SYS_GPR482
+ , HW_H_SYS_GPR483, HW_H_SYS_GPR484, HW_H_SYS_GPR485, HW_H_SYS_GPR486
+ , HW_H_SYS_GPR487, HW_H_SYS_GPR488, HW_H_SYS_GPR489, HW_H_SYS_GPR490
+ , HW_H_SYS_GPR491, HW_H_SYS_GPR492, HW_H_SYS_GPR493, HW_H_SYS_GPR494
+ , HW_H_SYS_GPR495, HW_H_SYS_GPR496, HW_H_SYS_GPR497, HW_H_SYS_GPR498
+ , HW_H_SYS_GPR499, HW_H_SYS_GPR500, HW_H_SYS_GPR501, HW_H_SYS_GPR502
+ , HW_H_SYS_GPR503, HW_H_SYS_GPR504, HW_H_SYS_GPR505, HW_H_SYS_GPR506
+ , HW_H_SYS_GPR507, HW_H_SYS_GPR508, HW_H_SYS_GPR509, HW_H_SYS_GPR510
+ , HW_H_SYS_GPR511, HW_H_MAC_MACLO, HW_H_MAC_MACHI, HW_H_TICK_TTMR
+ , HW_H_SYS_VR_REV, HW_H_SYS_VR_CFG, HW_H_SYS_VR_VER, HW_H_SYS_UPR_UP
+ , HW_H_SYS_UPR_DCP, HW_H_SYS_UPR_ICP, HW_H_SYS_UPR_DMP, HW_H_SYS_UPR_MP
+ , HW_H_SYS_UPR_IMP, HW_H_SYS_UPR_DUP, HW_H_SYS_UPR_PCUP, HW_H_SYS_UPR_PICP
+ , HW_H_SYS_UPR_PMP, HW_H_SYS_UPR_TTP, HW_H_SYS_UPR_CUP, HW_H_SYS_CPUCFGR_NSGR
+ , HW_H_SYS_CPUCFGR_CGF, HW_H_SYS_CPUCFGR_OB32S, HW_H_SYS_CPUCFGR_OB64S, HW_H_SYS_CPUCFGR_OF32S
+ , HW_H_SYS_CPUCFGR_OF64S, HW_H_SYS_CPUCFGR_OV64S, HW_H_SYS_CPUCFGR_ND, HW_H_SYS_SR_SM
+ , HW_H_SYS_SR_TEE, HW_H_SYS_SR_IEE, HW_H_SYS_SR_DCE, HW_H_SYS_SR_ICE
+ , HW_H_SYS_SR_DME, HW_H_SYS_SR_IME, HW_H_SYS_SR_LEE, HW_H_SYS_SR_CE
+ , HW_H_SYS_SR_F, HW_H_SYS_SR_CY, HW_H_SYS_SR_OV, HW_H_SYS_SR_OVE
+ , HW_H_SYS_SR_DSX, HW_H_SYS_SR_EPH, HW_H_SYS_SR_FO, HW_H_SYS_SR_SUMRA
+ , HW_H_SYS_SR_CID, HW_H_SYS_FPCSR_FPEE, HW_H_SYS_FPCSR_RM, HW_H_SYS_FPCSR_OVF
+ , HW_H_SYS_FPCSR_UNF, HW_H_SYS_FPCSR_SNF, HW_H_SYS_FPCSR_QNF, HW_H_SYS_FPCSR_ZF
+ , HW_H_SYS_FPCSR_IXF, HW_H_SYS_FPCSR_IVF, HW_H_SYS_FPCSR_INF, HW_H_SYS_FPCSR_DZF
+ , HW_H_SIMM16, HW_H_UIMM16, HW_H_UIMM6, HW_H_ATOMIC_RESERVE
+ , HW_H_ATOMIC_ADDRESS, HW_H_ROFF1, HW_MAX
} CGEN_HW_TYPE;
#define MAX_HW ((int) HW_MAX)
@@ -626,11 +632,12 @@ typedef enum cgen_operand_type {
, OR1K_OPERAND_DISP26, OR1K_OPERAND_DISP21, OR1K_OPERAND_SIMM16, OR1K_OPERAND_UIMM16
, OR1K_OPERAND_SIMM16_SPLIT, OR1K_OPERAND_UIMM16_SPLIT, OR1K_OPERAND_RDSF, OR1K_OPERAND_RASF
, OR1K_OPERAND_RBSF, OR1K_OPERAND_RDDF, OR1K_OPERAND_RADF, OR1K_OPERAND_RBDF
- , OR1K_OPERAND_MAX
+ , OR1K_OPERAND_RDD32F, OR1K_OPERAND_RDDI, OR1K_OPERAND_RAD32F, OR1K_OPERAND_RADI
+ , OR1K_OPERAND_RBD32F, OR1K_OPERAND_RBDI, OR1K_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
-#define MAX_OPERANDS 32
+#define MAX_OPERANDS 38
/* Maximum number of operands referenced by any insn. */
#define MAX_OPERAND_INSTANCES 10
@@ -678,9 +685,9 @@ extern const CGEN_ATTR_TABLE or1k_cgen_insn_attr_table[];
/* Hardware decls. */
+extern CGEN_KEYWORD or1k_cgen_opval_h_gpr;
extern CGEN_KEYWORD or1k_cgen_opval_h_fsr;
extern CGEN_KEYWORD or1k_cgen_opval_h_fdr;
-extern CGEN_KEYWORD or1k_cgen_opval_h_gpr;
extern const CGEN_HW_ENTRY or1k_cgen_hw_table[];
diff --git a/opcodes/or1k-dis.c b/opcodes/or1k-dis.c
index f14c56fec4..74bf38f26b 100644
--- a/opcodes/or1k-dis.c
+++ b/opcodes/or1k-dis.c
@@ -58,6 +58,27 @@ static int read_insn
\f
/* -- disassembler routines inserted here. */
+/* -- dis.c */
+
+static void
+print_regpair (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void * dis_info,
+ long value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = dis_info;
+ char reg1_index;
+ char reg2_index;
+
+ reg1_index = value & 0x1f;
+ reg2_index = reg1_index + ((value & (1 << 5)) ? 2 : 1);
+
+ (*info->fprintf_func) (info->stream, "r%d,r%d", reg1_index, reg2_index);
+}
+
+/* -- */
void or1k_cgen_print_operand
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
@@ -99,8 +120,14 @@ or1k_cgen_print_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RA :
print_keyword (cd, info, & or1k_cgen_opval_h_gpr, fields->f_r2, 0);
break;
+ case OR1K_OPERAND_RAD32F :
+ print_regpair (cd, info, fields->f_rad32, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
case OR1K_OPERAND_RADF :
- print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r1, 0);
+ print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r2, 0);
+ break;
+ case OR1K_OPERAND_RADI :
+ print_regpair (cd, info, fields->f_rad32, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
break;
case OR1K_OPERAND_RASF :
print_keyword (cd, info, & or1k_cgen_opval_h_fsr, fields->f_r2, 0);
@@ -108,8 +135,14 @@ or1k_cgen_print_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RB :
print_keyword (cd, info, & or1k_cgen_opval_h_gpr, fields->f_r3, 0);
break;
+ case OR1K_OPERAND_RBD32F :
+ print_regpair (cd, info, fields->f_rbd32, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
case OR1K_OPERAND_RBDF :
- print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r1, 0);
+ print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r3, 0);
+ break;
+ case OR1K_OPERAND_RBDI :
+ print_regpair (cd, info, fields->f_rbd32, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
break;
case OR1K_OPERAND_RBSF :
print_keyword (cd, info, & or1k_cgen_opval_h_fsr, fields->f_r3, 0);
@@ -117,9 +150,15 @@ or1k_cgen_print_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RD :
print_keyword (cd, info, & or1k_cgen_opval_h_gpr, fields->f_r1, 0);
break;
+ case OR1K_OPERAND_RDD32F :
+ print_regpair (cd, info, fields->f_rdd32, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
case OR1K_OPERAND_RDDF :
print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r1, 0);
break;
+ case OR1K_OPERAND_RDDI :
+ print_regpair (cd, info, fields->f_rdd32, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
case OR1K_OPERAND_RDSF :
print_keyword (cd, info, & or1k_cgen_opval_h_fsr, fields->f_r1, 0);
break;
diff --git a/opcodes/or1k-ibld.c b/opcodes/or1k-ibld.c
index 964ec33ee8..6271f5c6d1 100644
--- a/opcodes/or1k-ibld.c
+++ b/opcodes/or1k-ibld.c
@@ -590,8 +590,36 @@ or1k_cgen_insert_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RA :
errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
break;
+ case OR1K_OPERAND_RAD32F :
+ {
+{
+ FLD (f_r2) = ((FLD (f_rad32)) & (31));
+ FLD (f_raoff_9_1) = ((((SI) (FLD (f_rad32)) >> (5))) & (1));
+}
+ errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_raoff_9_1, 0, 0, 9, 1, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
case OR1K_OPERAND_RADF :
- errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
+ errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
+ break;
+ case OR1K_OPERAND_RADI :
+ {
+{
+ FLD (f_r2) = ((FLD (f_rad32)) & (31));
+ FLD (f_raoff_9_1) = ((((SI) (FLD (f_rad32)) >> (5))) & (1));
+}
+ errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_raoff_9_1, 0, 0, 9, 1, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
break;
case OR1K_OPERAND_RASF :
errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
@@ -599,8 +627,36 @@ or1k_cgen_insert_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RB :
errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
break;
+ case OR1K_OPERAND_RBD32F :
+ {
+{
+ FLD (f_r3) = ((FLD (f_rbd32)) & (31));
+ FLD (f_rboff_8_1) = ((((SI) (FLD (f_rbd32)) >> (5))) & (1));
+}
+ errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_rboff_8_1, 0, 0, 8, 1, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
case OR1K_OPERAND_RBDF :
- errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
+ errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
+ break;
+ case OR1K_OPERAND_RBDI :
+ {
+{
+ FLD (f_r3) = ((FLD (f_rbd32)) & (31));
+ FLD (f_rboff_8_1) = ((((SI) (FLD (f_rbd32)) >> (5))) & (1));
+}
+ errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_rboff_8_1, 0, 0, 8, 1, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
break;
case OR1K_OPERAND_RBSF :
errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
@@ -608,9 +664,37 @@ or1k_cgen_insert_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RD :
errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
break;
+ case OR1K_OPERAND_RDD32F :
+ {
+{
+ FLD (f_r1) = ((FLD (f_rdd32)) & (31));
+ FLD (f_rdoff_10_1) = ((((SI) (FLD (f_rdd32)) >> (5))) & (1));
+}
+ errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_rdoff_10_1, 0, 0, 10, 1, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
case OR1K_OPERAND_RDDF :
errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
break;
+ case OR1K_OPERAND_RDDI :
+ {
+{
+ FLD (f_r1) = ((FLD (f_rdd32)) & (31));
+ FLD (f_rdoff_10_1) = ((((SI) (FLD (f_rdd32)) >> (5))) & (1));
+}
+ errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_rdoff_10_1, 0, 0, 10, 1, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
case OR1K_OPERAND_RDSF :
errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
break;
@@ -714,8 +798,26 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RA :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
break;
+ case OR1K_OPERAND_RAD32F :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_raoff_9_1);
+ if (length <= 0) break;
+ FLD (f_rad32) = ((FLD (f_r2)) | (((FLD (f_raoff_9_1)) << (5))));
+ }
+ break;
case OR1K_OPERAND_RADF :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
+ break;
+ case OR1K_OPERAND_RADI :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_raoff_9_1);
+ if (length <= 0) break;
+ FLD (f_rad32) = ((FLD (f_r2)) | (((FLD (f_raoff_9_1)) << (5))));
+ }
break;
case OR1K_OPERAND_RASF :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
@@ -723,8 +825,26 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RB :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
break;
+ case OR1K_OPERAND_RBD32F :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_rboff_8_1);
+ if (length <= 0) break;
+ FLD (f_rbd32) = ((FLD (f_r3)) | (((FLD (f_rboff_8_1)) << (5))));
+ }
+ break;
case OR1K_OPERAND_RBDF :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
+ break;
+ case OR1K_OPERAND_RBDI :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_rboff_8_1);
+ if (length <= 0) break;
+ FLD (f_rbd32) = ((FLD (f_r3)) | (((FLD (f_rboff_8_1)) << (5))));
+ }
break;
case OR1K_OPERAND_RBSF :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
@@ -732,9 +852,27 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RD :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
break;
+ case OR1K_OPERAND_RDD32F :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_rdoff_10_1);
+ if (length <= 0) break;
+ FLD (f_rdd32) = ((FLD (f_r1)) | (((FLD (f_rdoff_10_1)) << (5))));
+ }
+ break;
case OR1K_OPERAND_RDDF :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
break;
+ case OR1K_OPERAND_RDDI :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_rdoff_10_1);
+ if (length <= 0) break;
+ FLD (f_rdd32) = ((FLD (f_r1)) | (((FLD (f_rdoff_10_1)) << (5))));
+ }
+ break;
case OR1K_OPERAND_RDSF :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
break;
@@ -813,8 +951,14 @@ or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RA :
value = fields->f_r2;
break;
+ case OR1K_OPERAND_RAD32F :
+ value = fields->f_rad32;
+ break;
case OR1K_OPERAND_RADF :
- value = fields->f_r1;
+ value = fields->f_r2;
+ break;
+ case OR1K_OPERAND_RADI :
+ value = fields->f_rad32;
break;
case OR1K_OPERAND_RASF :
value = fields->f_r2;
@@ -822,8 +966,14 @@ or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RB :
value = fields->f_r3;
break;
+ case OR1K_OPERAND_RBD32F :
+ value = fields->f_rbd32;
+ break;
case OR1K_OPERAND_RBDF :
- value = fields->f_r1;
+ value = fields->f_r3;
+ break;
+ case OR1K_OPERAND_RBDI :
+ value = fields->f_rbd32;
break;
case OR1K_OPERAND_RBSF :
value = fields->f_r3;
@@ -831,9 +981,15 @@ or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RD :
value = fields->f_r1;
break;
+ case OR1K_OPERAND_RDD32F :
+ value = fields->f_rdd32;
+ break;
case OR1K_OPERAND_RDDF :
value = fields->f_r1;
break;
+ case OR1K_OPERAND_RDDI :
+ value = fields->f_rdd32;
+ break;
case OR1K_OPERAND_RDSF :
value = fields->f_r1;
break;
@@ -882,8 +1038,14 @@ or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RA :
value = fields->f_r2;
break;
+ case OR1K_OPERAND_RAD32F :
+ value = fields->f_rad32;
+ break;
case OR1K_OPERAND_RADF :
- value = fields->f_r1;
+ value = fields->f_r2;
+ break;
+ case OR1K_OPERAND_RADI :
+ value = fields->f_rad32;
break;
case OR1K_OPERAND_RASF :
value = fields->f_r2;
@@ -891,8 +1053,14 @@ or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RB :
value = fields->f_r3;
break;
+ case OR1K_OPERAND_RBD32F :
+ value = fields->f_rbd32;
+ break;
case OR1K_OPERAND_RBDF :
- value = fields->f_r1;
+ value = fields->f_r3;
+ break;
+ case OR1K_OPERAND_RBDI :
+ value = fields->f_rbd32;
break;
case OR1K_OPERAND_RBSF :
value = fields->f_r3;
@@ -900,9 +1068,15 @@ or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RD :
value = fields->f_r1;
break;
+ case OR1K_OPERAND_RDD32F :
+ value = fields->f_rdd32;
+ break;
case OR1K_OPERAND_RDDF :
value = fields->f_r1;
break;
+ case OR1K_OPERAND_RDDI :
+ value = fields->f_rdd32;
+ break;
case OR1K_OPERAND_RDSF :
value = fields->f_r1;
break;
@@ -958,8 +1132,14 @@ or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RA :
fields->f_r2 = value;
break;
+ case OR1K_OPERAND_RAD32F :
+ fields->f_rad32 = value;
+ break;
case OR1K_OPERAND_RADF :
- fields->f_r1 = value;
+ fields->f_r2 = value;
+ break;
+ case OR1K_OPERAND_RADI :
+ fields->f_rad32 = value;
break;
case OR1K_OPERAND_RASF :
fields->f_r2 = value;
@@ -967,8 +1147,14 @@ or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RB :
fields->f_r3 = value;
break;
+ case OR1K_OPERAND_RBD32F :
+ fields->f_rbd32 = value;
+ break;
case OR1K_OPERAND_RBDF :
- fields->f_r1 = value;
+ fields->f_r3 = value;
+ break;
+ case OR1K_OPERAND_RBDI :
+ fields->f_rbd32 = value;
break;
case OR1K_OPERAND_RBSF :
fields->f_r3 = value;
@@ -976,9 +1162,15 @@ or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RD :
fields->f_r1 = value;
break;
+ case OR1K_OPERAND_RDD32F :
+ fields->f_rdd32 = value;
+ break;
case OR1K_OPERAND_RDDF :
fields->f_r1 = value;
break;
+ case OR1K_OPERAND_RDDI :
+ fields->f_rdd32 = value;
+ break;
case OR1K_OPERAND_RDSF :
fields->f_r1 = value;
break;
@@ -1024,8 +1216,14 @@ or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RA :
fields->f_r2 = value;
break;
+ case OR1K_OPERAND_RAD32F :
+ fields->f_rad32 = value;
+ break;
case OR1K_OPERAND_RADF :
- fields->f_r1 = value;
+ fields->f_r2 = value;
+ break;
+ case OR1K_OPERAND_RADI :
+ fields->f_rad32 = value;
break;
case OR1K_OPERAND_RASF :
fields->f_r2 = value;
@@ -1033,8 +1231,14 @@ or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RB :
fields->f_r3 = value;
break;
+ case OR1K_OPERAND_RBD32F :
+ fields->f_rbd32 = value;
+ break;
case OR1K_OPERAND_RBDF :
- fields->f_r1 = value;
+ fields->f_r3 = value;
+ break;
+ case OR1K_OPERAND_RBDI :
+ fields->f_rbd32 = value;
break;
case OR1K_OPERAND_RBSF :
fields->f_r3 = value;
@@ -1042,9 +1246,15 @@ or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RD :
fields->f_r1 = value;
break;
+ case OR1K_OPERAND_RDD32F :
+ fields->f_rdd32 = value;
+ break;
case OR1K_OPERAND_RDDF :
fields->f_r1 = value;
break;
+ case OR1K_OPERAND_RDDI :
+ fields->f_rdd32 = value;
+ break;
case OR1K_OPERAND_RDSF :
fields->f_r1 = value;
break;
diff --git a/opcodes/or1k-opc.c b/opcodes/or1k-opc.c
index 36aed256d6..86e421099a 100644
--- a/opcodes/or1k-opc.c
+++ b/opcodes/or1k-opc.c
@@ -32,6 +32,21 @@ This file is part of the GNU Binutils and/or GDB, the GNU debugger.
#include "libiberty.h"
/* -- opc.c */
+
+/* Special check to ensure that instruction exists for given machine. */
+
+int
+or1k_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
+{
+ int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
+
+ /* No mach attribute? Assume it's supported for all machs. */
+ if (machs == 0)
+ return 1;
+
+ return ((machs & cd->machs) != 0);
+}
+
/* -- */
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
@@ -149,31 +164,59 @@ static const CGEN_IFMT ifmt_lf_add_s ATTRIBUTE_UNUSED = {
};
static const CGEN_IFMT ifmt_lf_add_d ATTRIBUTE_UNUSED = {
- 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R1) }, { F (F_R1) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
+ 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lf_add_d32 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xfc0000ff, { { F (F_OPCODE) }, { F (F_RDD32) }, { F (F_RAD32) }, { F (F_RBD32) }, { F (F_OP_7_8) }, { 0 } }
};
static const CGEN_IFMT ifmt_lf_itof_s ATTRIBUTE_UNUSED = {
32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
};
+static const CGEN_IFMT ifmt_lf_itof_d ATTRIBUTE_UNUSED = {
+ 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lf_itof_d32 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xfc00f9ff, { { F (F_OPCODE) }, { F (F_R3) }, { F (F_RDD32) }, { F (F_RAD32) }, { F (F_RESV_8_1) }, { F (F_OP_7_8) }, { 0 } }
+};
+
static const CGEN_IFMT ifmt_lf_ftoi_s ATTRIBUTE_UNUSED = {
32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
};
static const CGEN_IFMT ifmt_lf_ftoi_d ATTRIBUTE_UNUSED = {
- 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R1) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
+ 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lf_ftoi_d32 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xfc00f9ff, { { F (F_OPCODE) }, { F (F_R3) }, { F (F_RDD32) }, { F (F_RAD32) }, { F (F_RESV_8_1) }, { F (F_OP_7_8) }, { 0 } }
};
-static const CGEN_IFMT ifmt_lf_eq_s ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_lf_sfeq_s ATTRIBUTE_UNUSED = {
32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
};
+static const CGEN_IFMT ifmt_lf_sfeq_d ATTRIBUTE_UNUSED = {
+ 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lf_sfeq_d32 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xffe004ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_RESV_10_1) }, { F (F_RAD32) }, { F (F_RBD32) }, { F (F_OP_7_8) }, { 0 } }
+};
+
static const CGEN_IFMT ifmt_lf_cust1_s ATTRIBUTE_UNUSED = {
32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
};
static const CGEN_IFMT ifmt_lf_cust1_d ATTRIBUTE_UNUSED = {
- 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_R1) }, { F (F_R1) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
+ 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lf_cust1_d32 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xffe004ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_RESV_10_1) }, { F (F_RAD32) }, { F (F_RBD32) }, { F (F_OP_7_8) }, { 0 } }
};
#undef F
@@ -791,6 +834,12 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } },
& ifmt_lf_add_d, { 0xc8000010 }
},
+/* lf.add.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RDD32F), ',', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_add_d32, { 0xc8000010 }
+ },
/* lf.sub.s $rDSF,$rASF,$rBSF */
{
{ 0, 0, 0, 0 },
@@ -803,6 +852,12 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } },
& ifmt_lf_add_d, { 0xc8000011 }
},
+/* lf.sub.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RDD32F), ',', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_add_d32, { 0xc8000011 }
+ },
/* lf.mul.s $rDSF,$rASF,$rBSF */
{
{ 0, 0, 0, 0 },
@@ -815,6 +870,12 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } },
& ifmt_lf_add_d, { 0xc8000012 }
},
+/* lf.mul.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RDD32F), ',', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_add_d32, { 0xc8000012 }
+ },
/* lf.div.s $rDSF,$rASF,$rBSF */
{
{ 0, 0, 0, 0 },
@@ -827,6 +888,12 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } },
& ifmt_lf_add_d, { 0xc8000013 }
},
+/* lf.div.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RDD32F), ',', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_add_d32, { 0xc8000013 }
+ },
/* lf.rem.s $rDSF,$rASF,$rBSF */
{
{ 0, 0, 0, 0 },
@@ -839,17 +906,29 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } },
& ifmt_lf_add_d, { 0xc8000016 }
},
+/* lf.rem.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RDD32F), ',', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_add_d32, { 0xc8000016 }
+ },
/* lf.itof.s $rDSF,$rA */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RDSF), ',', OP (RA), 0 } },
& ifmt_lf_itof_s, { 0xc8000004 }
},
-/* lf.itof.d $rDSF,$rA */
+/* lf.itof.d $rDDF,$rA */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RDSF), ',', OP (RA), 0 } },
- & ifmt_lf_itof_s, { 0xc8000014 }
+ { { MNEM, ' ', OP (RDDF), ',', OP (RA), 0 } },
+ & ifmt_lf_itof_d, { 0xc8000014 }
+ },
+/* lf.itof.d $rDD32F,$rADI */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RDD32F), ',', OP (RADI), 0 } },
+ & ifmt_lf_itof_d32, { 0xc8000014 }
},
/* lf.ftoi.s $rD,$rASF */
{
@@ -863,77 +942,245 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RD), ',', OP (RADF), 0 } },
& ifmt_lf_ftoi_d, { 0xc8000015 }
},
+/* lf.ftoi.d $rDDI,$rAD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RDDI), ',', OP (RAD32F), 0 } },
+ & ifmt_lf_ftoi_d32, { 0xc8000015 }
+ },
/* lf.sfeq.s $rASF,$rBSF */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
- & ifmt_lf_eq_s, { 0xc8000008 }
+ & ifmt_lf_sfeq_s, { 0xc8000008 }
},
-/* lf.sfeq.d $rASF,$rBSF */
+/* lf.sfeq.d $rADF,$rBDF */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
- & ifmt_lf_eq_s, { 0xc8000018 }
+ { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
+ & ifmt_lf_sfeq_d, { 0xc8000018 }
+ },
+/* lf.sfeq.d $rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_sfeq_d32, { 0xc8000018 }
},
/* lf.sfne.s $rASF,$rBSF */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
- & ifmt_lf_eq_s, { 0xc8000009 }
+ & ifmt_lf_sfeq_s, { 0xc8000009 }
},
-/* lf.sfne.d $rASF,$rBSF */
+/* lf.sfne.d $rADF,$rBDF */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
- & ifmt_lf_eq_s, { 0xc8000019 }
+ { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
+ & ifmt_lf_sfeq_d, { 0xc8000019 }
+ },
+/* lf.sfne.d $rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_sfeq_d32, { 0xc8000019 }
},
/* lf.sfge.s $rASF,$rBSF */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
- & ifmt_lf_eq_s, { 0xc800000b }
+ & ifmt_lf_sfeq_s, { 0xc800000b }
},
-/* lf.sfge.d $rASF,$rBSF */
+/* lf.sfge.d $rADF,$rBDF */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
- & ifmt_lf_eq_s, { 0xc800001b }
+ { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
+ & ifmt_lf_sfeq_d, { 0xc800001b }
+ },
+/* lf.sfge.d $rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_sfeq_d32, { 0xc800001b }
},
/* lf.sfgt.s $rASF,$rBSF */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
- & ifmt_lf_eq_s, { 0xc800000a }
+ & ifmt_lf_sfeq_s, { 0xc800000a }
},
-/* lf.sfgt.d $rASF,$rBSF */
+/* lf.sfgt.d $rADF,$rBDF */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
- & ifmt_lf_eq_s, { 0xc800001a }
+ { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
+ & ifmt_lf_sfeq_d, { 0xc800001a }
+ },
+/* lf.sfgt.d $rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_sfeq_d32, { 0xc800001a }
},
/* lf.sflt.s $rASF,$rBSF */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
- & ifmt_lf_eq_s, { 0xc800000c }
+ & ifmt_lf_sfeq_s, { 0xc800000c }
},
-/* lf.sflt.d $rASF,$rBSF */
+/* lf.sflt.d $rADF,$rBDF */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
- & ifmt_lf_eq_s, { 0xc800001c }
+ { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
+ & ifmt_lf_sfeq_d, { 0xc800001c }
+ },
+/* lf.sflt.d $rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_sfeq_d32, { 0xc800001c }
},
/* lf.sfle.s $rASF,$rBSF */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
- & ifmt_lf_eq_s, { 0xc800000d }
+ & ifmt_lf_sfeq_s, { 0xc800000d }
+ },
+/* lf.sfle.d $rADF,$rBDF */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
+ & ifmt_lf_sfeq_d, { 0xc800001d }
+ },
+/* lf.sfle.d $rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_sfeq_d32, { 0xc800001d }
+ },
+/* lf.sfueq.s $rASF,$rBSF */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
+ & ifmt_lf_sfeq_s, { 0xc8000028 }
+ },
+/* lf.sfueq.d $rADF,$rBDF */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
+ & ifmt_lf_sfeq_d, { 0xc8000038 }
+ },
+/* lf.sfueq.d $rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_sfeq_d32, { 0xc8000038 }
+ },
+/* lf.sfune.s $rASF,$rBSF */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
+ & ifmt_lf_sfeq_s, { 0xc8000029 }
+ },
+/* lf.sfune.d $rADF,$rBDF */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
+ & ifmt_lf_sfeq_d, { 0xc8000039 }
+ },
+/* lf.sfune.d $rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_sfeq_d32, { 0xc8000039 }
+ },
+/* lf.sfugt.s $rASF,$rBSF */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
+ & ifmt_lf_sfeq_s, { 0xc800002a }
+ },
+/* lf.sfugt.d $rADF,$rBDF */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
+ & ifmt_lf_sfeq_d, { 0xc800003a }
+ },
+/* lf.sfugt.d $rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_sfeq_d32, { 0xc800003a }
+ },
+/* lf.sfuge.s $rASF,$rBSF */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
+ & ifmt_lf_sfeq_s, { 0xc800002b }
+ },
+/* lf.sfuge.d $rADF,$rBDF */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
+ & ifmt_lf_sfeq_d, { 0xc800003b }
+ },
+/* lf.sfuge.d $rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_sfeq_d32, { 0xc800003b }
+ },
+/* lf.sfult.s $rASF,$rBSF */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
+ & ifmt_lf_sfeq_s, { 0xc800002c }
+ },
+/* lf.sfult.d $rADF,$rBDF */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
+ & ifmt_lf_sfeq_d, { 0xc800003c }
},
-/* lf.sfle.d $rASF,$rBSF */
+/* lf.sfult.d $rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_sfeq_d32, { 0xc800003c }
+ },
+/* lf.sfule.s $rASF,$rBSF */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
- & ifmt_lf_eq_s, { 0xc800001d }
+ & ifmt_lf_sfeq_s, { 0xc800002d }
+ },
+/* lf.sfule.d $rADF,$rBDF */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
+ & ifmt_lf_sfeq_d, { 0xc800003d }
+ },
+/* lf.sfule.d $rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_sfeq_d32, { 0xc800003d }
+ },
+/* lf.sfun.s $rASF,$rBSF */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
+ & ifmt_lf_sfeq_s, { 0xc800002e }
+ },
+/* lf.sfun.d $rADF,$rBDF */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
+ & ifmt_lf_sfeq_d, { 0xc800003e }
+ },
+/* lf.sfun.d $rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_sfeq_d32, { 0xc800003e }
},
/* lf.madd.s $rDSF,$rASF,$rBSF */
{
@@ -947,6 +1194,12 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } },
& ifmt_lf_add_d, { 0xc8000017 }
},
+/* lf.madd.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RDD32F), ',', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_add_d32, { 0xc8000017 }
+ },
/* lf.cust1.s $rASF,$rBSF */
{
{ 0, 0, 0, 0 },
@@ -959,6 +1212,12 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, 0 } },
& ifmt_lf_cust1_d, { 0xc80000e0 }
},
+/* lf.cust1.d */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_lf_cust1_d32, { 0xc80000e0 }
+ },
};
#undef A
diff --git a/opcodes/or1k-opc.h b/opcodes/or1k-opc.h
index 78ed425332..2ec4b4b323 100644
--- a/opcodes/or1k-opc.h
+++ b/opcodes/or1k-opc.h
@@ -37,6 +37,11 @@ extern "C" {
#undef CGEN_DIS_HASH
#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2)
+/* Check applicability of instructions against machines. */
+#define CGEN_VALIDATE_INSN_SUPPORTED
+
+extern int or1k_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
+
/* -- */
/* Enum declaration for or1k instruction types. */
typedef enum cgen_insn_type {
@@ -65,21 +70,30 @@ typedef enum cgen_insn_type {
, OR1K_INSN_L_MACU, OR1K_INSN_L_MSB, OR1K_INSN_L_MSBU, OR1K_INSN_L_CUST1
, OR1K_INSN_L_CUST2, OR1K_INSN_L_CUST3, OR1K_INSN_L_CUST4, OR1K_INSN_L_CUST5
, OR1K_INSN_L_CUST6, OR1K_INSN_L_CUST7, OR1K_INSN_L_CUST8, OR1K_INSN_LF_ADD_S
- , OR1K_INSN_LF_ADD_D, OR1K_INSN_LF_SUB_S, OR1K_INSN_LF_SUB_D, OR1K_INSN_LF_MUL_S
- , OR1K_INSN_LF_MUL_D, OR1K_INSN_LF_DIV_S, OR1K_INSN_LF_DIV_D, OR1K_INSN_LF_REM_S
- , OR1K_INSN_LF_REM_D, OR1K_INSN_LF_ITOF_S, OR1K_INSN_LF_ITOF_D, OR1K_INSN_LF_FTOI_S
- , OR1K_INSN_LF_FTOI_D, OR1K_INSN_LF_EQ_S, OR1K_INSN_LF_EQ_D, OR1K_INSN_LF_NE_S
- , OR1K_INSN_LF_NE_D, OR1K_INSN_LF_GE_S, OR1K_INSN_LF_GE_D, OR1K_INSN_LF_GT_S
- , OR1K_INSN_LF_GT_D, OR1K_INSN_LF_LT_S, OR1K_INSN_LF_LT_D, OR1K_INSN_LF_LE_S
- , OR1K_INSN_LF_LE_D, OR1K_INSN_LF_MADD_S, OR1K_INSN_LF_MADD_D, OR1K_INSN_LF_CUST1_S
- , OR1K_INSN_LF_CUST1_D
+ , OR1K_INSN_LF_ADD_D, OR1K_INSN_LF_ADD_D32, OR1K_INSN_LF_SUB_S, OR1K_INSN_LF_SUB_D
+ , OR1K_INSN_LF_SUB_D32, OR1K_INSN_LF_MUL_S, OR1K_INSN_LF_MUL_D, OR1K_INSN_LF_MUL_D32
+ , OR1K_INSN_LF_DIV_S, OR1K_INSN_LF_DIV_D, OR1K_INSN_LF_DIV_D32, OR1K_INSN_LF_REM_S
+ , OR1K_INSN_LF_REM_D, OR1K_INSN_LF_REM_D32, OR1K_INSN_LF_ITOF_S, OR1K_INSN_LF_ITOF_D
+ , OR1K_INSN_LF_ITOF_D32, OR1K_INSN_LF_FTOI_S, OR1K_INSN_LF_FTOI_D, OR1K_INSN_LF_FTOI_D32
+ , OR1K_INSN_LF_SFEQ_S, OR1K_INSN_LF_SFEQ_D, OR1K_INSN_LF_SFEQ_D32, OR1K_INSN_LF_SFNE_S
+ , OR1K_INSN_LF_SFNE_D, OR1K_INSN_LF_SFNE_D32, OR1K_INSN_LF_SFGE_S, OR1K_INSN_LF_SFGE_D
+ , OR1K_INSN_LF_SFGE_D32, OR1K_INSN_LF_SFGT_S, OR1K_INSN_LF_SFGT_D, OR1K_INSN_LF_SFGT_D32
+ , OR1K_INSN_LF_SFLT_S, OR1K_INSN_LF_SFLT_D, OR1K_INSN_LF_SFLT_D32, OR1K_INSN_LF_SFLE_S
+ , OR1K_INSN_LF_SFLE_D, OR1K_INSN_LF_SFLE_D32, OR1K_INSN_LF_SFUEQ_S, OR1K_INSN_LF_SFUEQ_D
+ , OR1K_INSN_LF_SFUEQ_D32, OR1K_INSN_LF_SFUNE_S, OR1K_INSN_LF_SFUNE_D, OR1K_INSN_LF_SFUNE_D32
+ , OR1K_INSN_LF_SFUGT_S, OR1K_INSN_LF_SFUGT_D, OR1K_INSN_LF_SFUGT_D32, OR1K_INSN_LF_SFUGE_S
+ , OR1K_INSN_LF_SFUGE_D, OR1K_INSN_LF_SFUGE_D32, OR1K_INSN_LF_SFULT_S, OR1K_INSN_LF_SFULT_D
+ , OR1K_INSN_LF_SFULT_D32, OR1K_INSN_LF_SFULE_S, OR1K_INSN_LF_SFULE_D, OR1K_INSN_LF_SFULE_D32
+ , OR1K_INSN_LF_SFUN_S, OR1K_INSN_LF_SFUN_D, OR1K_INSN_LF_SFUN_D32, OR1K_INSN_LF_MADD_S
+ , OR1K_INSN_LF_MADD_D, OR1K_INSN_LF_MADD_D32, OR1K_INSN_LF_CUST1_S, OR1K_INSN_LF_CUST1_D
+ , OR1K_INSN_LF_CUST1_D32
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
#define CGEN_INSN_INVALID OR1K_INSN_INVALID
/* Total number of insns in table. */
-#define MAX_INSNS ((int) OR1K_INSN_LF_CUST1_D + 1)
+#define MAX_INSNS ((int) OR1K_INSN_LF_CUST1_D32 + 1)
/* This struct records data prior to insertion or after extraction. */
struct cgen_fields
@@ -113,6 +127,7 @@ struct cgen_fields
long f_resv_10_7;
long f_resv_10_3;
long f_resv_10_1;
+ long f_resv_8_1;
long f_resv_7_4;
long f_resv_5_2;
long f_imm16_25_5;
@@ -124,6 +139,12 @@ struct cgen_fields
long f_uimm6;
long f_uimm16_split;
long f_simm16_split;
+ long f_rdoff_10_1;
+ long f_raoff_9_1;
+ long f_rboff_8_1;
+ long f_rdd32;
+ long f_rad32;
+ long f_rbd32;
};
#define CGEN_INIT_PARSE(od) \
diff --git a/opcodes/or1k-opinst.c b/opcodes/or1k-opinst.c
index 6b18dab986..84a0dfe9bc 100644
--- a/opcodes/or1k-opinst.c
+++ b/opcodes/or1k-opinst.c
@@ -461,6 +461,13 @@ static const CGEN_OPINST sfmt_lf_add_d_ops[] ATTRIBUTE_UNUSED = {
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
+static const CGEN_OPINST sfmt_lf_add_d32_ops[] ATTRIBUTE_UNUSED = {
+ { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 },
+ { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 },
+ { OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
static const CGEN_OPINST sfmt_lf_itof_s_ops[] ATTRIBUTE_UNUSED = {
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
{ INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 },
@@ -475,6 +482,13 @@ static const CGEN_OPINST sfmt_lf_itof_d_ops[] ATTRIBUTE_UNUSED = {
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
+static const CGEN_OPINST sfmt_lf_itof_d32_ops[] ATTRIBUTE_UNUSED = {
+ { INPUT, "rADI", HW_H_I64R, CGEN_MODE_DI, OP_ENT (RADI), 0, 0 },
+ { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 },
+ { OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
static const CGEN_OPINST sfmt_lf_ftoi_s_ops[] ATTRIBUTE_UNUSED = {
{ INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 },
{ INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 },
@@ -489,20 +503,34 @@ static const CGEN_OPINST sfmt_lf_ftoi_d_ops[] ATTRIBUTE_UNUSED = {
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
-static const CGEN_OPINST sfmt_lf_eq_s_ops[] ATTRIBUTE_UNUSED = {
+static const CGEN_OPINST sfmt_lf_ftoi_d32_ops[] ATTRIBUTE_UNUSED = {
+ { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 },
+ { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 },
+ { OUTPUT, "rDDI", HW_H_I64R, CGEN_MODE_DI, OP_ENT (RDDI), 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_lf_sfeq_s_ops[] ATTRIBUTE_UNUSED = {
{ INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 },
{ INPUT, "rBSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RBSF), 0, 0 },
{ OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
-static const CGEN_OPINST sfmt_lf_eq_d_ops[] ATTRIBUTE_UNUSED = {
+static const CGEN_OPINST sfmt_lf_sfeq_d_ops[] ATTRIBUTE_UNUSED = {
{ INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 },
{ INPUT, "rBDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RBDF), 0, 0 },
{ OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
+static const CGEN_OPINST sfmt_lf_sfeq_d32_ops[] ATTRIBUTE_UNUSED = {
+ { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 },
+ { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 },
+ { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
static const CGEN_OPINST sfmt_lf_madd_s_ops[] ATTRIBUTE_UNUSED = {
{ INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 },
{ INPUT, "rBSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RBSF), 0, 0 },
@@ -519,6 +547,14 @@ static const CGEN_OPINST sfmt_lf_madd_d_ops[] ATTRIBUTE_UNUSED = {
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
+static const CGEN_OPINST sfmt_lf_madd_d32_ops[] ATTRIBUTE_UNUSED = {
+ { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 },
+ { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 },
+ { INPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 },
+ { OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
#undef OP_ENT
#undef INPUT
#undef OUTPUT
@@ -629,32 +665,68 @@ static const CGEN_OPINST *or1k_cgen_opinst_table[MAX_INSNS] = {
& sfmt_l_msync_ops[0],
& sfmt_lf_add_s_ops[0],
& sfmt_lf_add_d_ops[0],
+ & sfmt_lf_add_d32_ops[0],
& sfmt_lf_add_s_ops[0],
& sfmt_lf_add_d_ops[0],
+ & sfmt_lf_add_d32_ops[0],
& sfmt_lf_add_s_ops[0],
& sfmt_lf_add_d_ops[0],
+ & sfmt_lf_add_d32_ops[0],
& sfmt_lf_add_s_ops[0],
& sfmt_lf_add_d_ops[0],
+ & sfmt_lf_add_d32_ops[0],
& sfmt_lf_add_s_ops[0],
& sfmt_lf_add_d_ops[0],
+ & sfmt_lf_add_d32_ops[0],
& sfmt_lf_itof_s_ops[0],
& sfmt_lf_itof_d_ops[0],
+ & sfmt_lf_itof_d32_ops[0],
& sfmt_lf_ftoi_s_ops[0],
& sfmt_lf_ftoi_d_ops[0],
- & sfmt_lf_eq_s_ops[0],
- & sfmt_lf_eq_d_ops[0],
- & sfmt_lf_eq_s_ops[0],
- & sfmt_lf_eq_d_ops[0],
- & sfmt_lf_eq_s_ops[0],
- & sfmt_lf_eq_d_ops[0],
- & sfmt_lf_eq_s_ops[0],
- & sfmt_lf_eq_d_ops[0],
- & sfmt_lf_eq_s_ops[0],
- & sfmt_lf_eq_d_ops[0],
- & sfmt_lf_eq_s_ops[0],
- & sfmt_lf_eq_d_ops[0],
+ & sfmt_lf_ftoi_d32_ops[0],
+ & sfmt_lf_sfeq_s_ops[0],
+ & sfmt_lf_sfeq_d_ops[0],
+ & sfmt_lf_sfeq_d32_ops[0],
+ & sfmt_lf_sfeq_s_ops[0],
+ & sfmt_lf_sfeq_d_ops[0],
+ & sfmt_lf_sfeq_d32_ops[0],
+ & sfmt_lf_sfeq_s_ops[0],
+ & sfmt_lf_sfeq_d_ops[0],
+ & sfmt_lf_sfeq_d32_ops[0],
+ & sfmt_lf_sfeq_s_ops[0],
+ & sfmt_lf_sfeq_d_ops[0],
+ & sfmt_lf_sfeq_d32_ops[0],
+ & sfmt_lf_sfeq_s_ops[0],
+ & sfmt_lf_sfeq_d_ops[0],
+ & sfmt_lf_sfeq_d32_ops[0],
+ & sfmt_lf_sfeq_s_ops[0],
+ & sfmt_lf_sfeq_d_ops[0],
+ & sfmt_lf_sfeq_d32_ops[0],
+ & sfmt_lf_sfeq_s_ops[0],
+ & sfmt_lf_sfeq_d_ops[0],
+ & sfmt_lf_sfeq_d32_ops[0],
+ & sfmt_lf_sfeq_s_ops[0],
+ & sfmt_lf_sfeq_d_ops[0],
+ & sfmt_lf_sfeq_d32_ops[0],
+ & sfmt_lf_sfeq_s_ops[0],
+ & sfmt_lf_sfeq_d_ops[0],
+ & sfmt_lf_sfeq_d32_ops[0],
+ & sfmt_lf_sfeq_s_ops[0],
+ & sfmt_lf_sfeq_d_ops[0],
+ & sfmt_lf_sfeq_d32_ops[0],
+ & sfmt_lf_sfeq_s_ops[0],
+ & sfmt_lf_sfeq_d_ops[0],
+ & sfmt_lf_sfeq_d32_ops[0],
+ & sfmt_lf_sfeq_s_ops[0],
+ & sfmt_lf_sfeq_d_ops[0],
+ & sfmt_lf_sfeq_d32_ops[0],
+ & sfmt_lf_sfeq_s_ops[0],
+ & sfmt_lf_sfeq_d_ops[0],
+ & sfmt_lf_sfeq_d32_ops[0],
& sfmt_lf_madd_s_ops[0],
& sfmt_lf_madd_d_ops[0],
+ & sfmt_lf_madd_d32_ops[0],
+ & sfmt_l_msync_ops[0],
& sfmt_l_msync_ops[0],
& sfmt_l_msync_ops[0],
};
--
2.21.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 09/11] sim/testsuite/or1k: Add test for 64-bit fpu operations
2019-06-08 21:32 [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Stafford Horne
` (4 preceding siblings ...)
2019-06-08 21:33 ` [PATCH v3 05/11] opcodes/or1k: Regenerate opcodes Stafford Horne
@ 2019-06-08 21:33 ` Stafford Horne
2019-06-08 21:33 ` [PATCH v3 08/11] sim/common: wire up new unordered comparisons Stafford Horne
` (4 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Stafford Horne @ 2019-06-08 21:33 UTC (permalink / raw)
To: GDB patches, GNU Binutils
Cc: Andrey Bacherov, Nick Clifton, Andrew Burgess, Richard Henderson,
Openrisc, Stafford Horne
This is a very basic test but it ensure the machine is wired up
correctly and that the assembler works.
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* fpu64a32.S: New file.
---
Changes from v2:
- use explicit register pairs.
sim/testsuite/sim/or1k/fpu64a32.S | 172 ++++++++++++++++++++++++++++++
1 file changed, 172 insertions(+)
create mode 100644 sim/testsuite/sim/or1k/fpu64a32.S
diff --git a/sim/testsuite/sim/or1k/fpu64a32.S b/sim/testsuite/sim/or1k/fpu64a32.S
new file mode 100644
index 0000000000..e263853580
--- /dev/null
+++ b/sim/testsuite/sim/or1k/fpu64a32.S
@@ -0,0 +1,172 @@
+/* Tests some basic fpu instructions.
+
+ Copyright (C) 2017-2019 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+# mach: or1k
+# output: report(0x400921f9);\n
+# output: report(0xf01b866e);\n
+# output: report(0x4005bf09);\n
+# output: report(0x95aaf790);\n
+# output: report(0x00000000);\n
+# output: report(0x00001234);\n
+# output: \n
+# output: report(0x40b23400);\n
+# output: report(0x00000000);\n
+# output: report(0x40b23400);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x40177081);\n
+# output: report(0xc2e33eff);\n
+# output: report(0x400921f9);\n
+# output: report(0xf01b866e);\n
+# output: \n
+# output: report(0x40211456);\n
+# output: report(0x587dfabf);\n
+# output: report(0x400921f9);\n
+# output: report(0xf01b866d);\n
+# output: \n
+# output: report(0x00000001);\n
+# output: \n
+# output: WARNING: ignoring fpu error caught in fast mode.\n
+# output: report(0x00000000);\n
+# output: \n
+# output: exit(0)\n
+
+#include "or1k-asm-test-helpers.h"
+
+ STANDARD_TEST_ENVIRONMENT
+
+ .section .exception_vectors
+
+ /* Floating point exception. */
+ .org 0xd00
+
+ /* The handling is a bit dubious at present. We just patch the
+ instruction with l.nop and restart. This will go wrong in branch
+ delay slots. But we don't have those in this test. */
+ l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE
+ PUSH r2
+ PUSH r3
+ /* Save the address of the instruction that caused the problem. */
+ MOVE_FROM_SPR r2, SPR_EPCR_BASE
+ LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */
+ l.sw -4(r2), r3
+ POP r3
+ POP r2
+ l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE
+ l.rfe
+
+ .section .data
+ .align 4
+ .type pi, @object
+ .size pi, 8
+anchor:
+pi:
+ .double 3.14159
+
+ .type e, @object
+ .size e, 8
+e:
+ .double 2.71828
+
+ .type large, @object
+ .size large, 8
+large:
+ .long 0
+ .long 0x1234
+
+ .section .text
+start_tests:
+ PUSH LINK_REGISTER_R9
+
+ /* Test lf.itof.d int to double conversion. Setting up:
+ * r11 pointer to data
+ * r12,r13 pi as double
+ * r14,r15 e as double
+ * r16,r17 a long long
+ */
+ l.ori r11, r0, ha(anchor)
+ l.addi r11, r11, lo(anchor)
+ l.lwz r12, 0(r11)
+ l.lwz r13, 4(r11)
+
+ l.lwz r14, 8(r11)
+ l.lwz r15, 12(r11)
+
+ l.lwz r16, 16(r11)
+ l.lwz r18, 20(r11)
+
+ /* Output to ensure we loaded it correctly. */
+ REPORT_REG_TO_CONSOLE r12
+ REPORT_REG_TO_CONSOLE r13
+
+ REPORT_REG_TO_CONSOLE r14
+ REPORT_REG_TO_CONSOLE r15
+
+ REPORT_REG_TO_CONSOLE r16
+ REPORT_REG_TO_CONSOLE r18
+ PRINT_NEWLINE_TO_CONSOLE
+
+ /* Convert the big long to a double. */
+ lf.itof.d r16,r18, r16,r18
+ REPORT_REG_TO_CONSOLE r16
+ REPORT_REG_TO_CONSOLE r18
+
+ /* Convert the double back to a long, it should match before. */
+ lf.ftoi.d r16,r18, r16,r18
+ lf.itof.d r16,r18, r16,r18
+
+ REPORT_REG_TO_CONSOLE r16
+ REPORT_REG_TO_CONSOLE r18
+
+ PRINT_NEWLINE_TO_CONSOLE
+
+ /* Add and subtract some double values. */
+ lf.add.d r12,r13, r12,r13, r14,r15
+ REPORT_REG_TO_CONSOLE r12
+ REPORT_REG_TO_CONSOLE r13
+
+ lf.sub.d r12,r13, r12,r13, r14,r15
+ REPORT_REG_TO_CONSOLE r12
+ REPORT_REG_TO_CONSOLE r13
+ PRINT_NEWLINE_TO_CONSOLE
+
+ /* Multiply and divide double values. */
+ lf.mul.d r12,r13, r12,r13, r14,r15
+ REPORT_REG_TO_CONSOLE r12
+ REPORT_REG_TO_CONSOLE r13
+
+ lf.div.d r12,r13, r12,r13, r14,r15
+ REPORT_REG_TO_CONSOLE r12
+ REPORT_REG_TO_CONSOLE r13
+ PRINT_NEWLINE_TO_CONSOLE
+
+ /* Test lf.sfge.s set flag if r6 >= r10. */
+ lf.sfge.d r12,r13, r14,r15
+ MOVE_FROM_SPR r2, SPR_SR
+ REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
+ PRINT_NEWLINE_TO_CONSOLE
+
+ /* Test raising an exception by dividing by 0. */
+ MOVE_FROM_SPR r2, SPR_FPCSR
+ l.ori r2, r2, 0x1
+ MOVE_TO_SPR SPR_FPCSR, r2
+div0: lf.div.d r2,r3, r12,r13, r0,r1
+ REPORT_EXCEPTION div0
+ PRINT_NEWLINE_TO_CONSOLE
+
+ POP LINK_REGISTER_R9
+ RETURN_TO_LINK_REGISTER_R9
--
2.21.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 08/11] sim/common: wire up new unordered comparisons
2019-06-08 21:32 [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Stafford Horne
` (5 preceding siblings ...)
2019-06-08 21:33 ` [PATCH v3 09/11] sim/testsuite/or1k: Add test for 64-bit fpu operations Stafford Horne
@ 2019-06-08 21:33 ` Stafford Horne
2019-06-08 21:33 ` [PATCH v3 07/11] sim/common: Wire in df/di conversion Stafford Horne
` (3 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Stafford Horne @ 2019-06-08 21:33 UTC (permalink / raw)
To: GDB patches, GNU Binutils
Cc: Andrey Bacherov, Nick Clifton, Andrew Burgess, Richard Henderson,
Openrisc, Stafford Horne
Define and wire up unordered floating point comparison operations for cgen
targets. This patch depends on my posted cgen patches[0].
[0] https://www.sourceware.org/ml/cgen/2019-q2/msg00013.html
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-accfp.c (unorderedsf, unordereddf): New functions.
(cgen_init_accurate_fpu): Wire up unorderedsf and unordereddf.
* cgen-fpu.h (cgen_fp_ops): Define fields unorderedsf and unordereddf.
---
Changes from v2:
- new patch
sim/common/cgen-accfp.c | 25 +++++++++++++++++++++++++
sim/common/cgen-fpu.h | 2 ++
2 files changed, 27 insertions(+)
diff --git a/sim/common/cgen-accfp.c b/sim/common/cgen-accfp.c
index 51f5a29fe2..b898de3935 100644
--- a/sim/common/cgen-accfp.c
+++ b/sim/common/cgen-accfp.c
@@ -303,6 +303,18 @@ gesf (CGEN_FPU* fpu, SF x, SF y)
return sim_fpu_is_ge (&op1, &op2);
}
+static int
+unorderedsf (CGEN_FPU* fpu, SF x, SF y)
+{
+ sim_fpu op1;
+ sim_fpu op2;
+
+ sim_fpu_32to (&op1, x);
+ sim_fpu_32to (&op2, y);
+ return sim_fpu_is_nan (&op1) || sim_fpu_is_nan (&op2);
+}
+
+
static DF
fextsfdf (CGEN_FPU* fpu, int how UNUSED, SF x)
{
@@ -703,6 +715,17 @@ gedf (CGEN_FPU* fpu, DF x, DF y)
sim_fpu_64to (&op2, y);
return sim_fpu_is_ge (&op1, &op2);
}
+
+static int
+unordereddf (CGEN_FPU* fpu, DF x, DF y)
+{
+ sim_fpu op1;
+ sim_fpu op2;
+
+ sim_fpu_64to (&op1, x);
+ sim_fpu_64to (&op2, y);
+ return sim_fpu_is_nan (&op1) || sim_fpu_is_nan (&op2);
+}
\f
/* Initialize FP_OPS to use accurate library. */
@@ -738,6 +761,7 @@ cgen_init_accurate_fpu (SIM_CPU* cpu, CGEN_FPU* fpu, CGEN_FPU_ERROR_FN* error)
o->lesf = lesf;
o->gtsf = gtsf;
o->gesf = gesf;
+ o->unorderedsf = unorderedsf;
o->adddf = adddf;
o->subdf = subdf;
@@ -757,6 +781,7 @@ cgen_init_accurate_fpu (SIM_CPU* cpu, CGEN_FPU* fpu, CGEN_FPU_ERROR_FN* error)
o->ledf = ledf;
o->gtdf = gtdf;
o->gedf = gedf;
+ o->unordereddf = unordereddf;
o->fextsfdf = fextsfdf;
o->ftruncdfsf = ftruncdfsf;
o->floatsisf = floatsisf;
diff --git a/sim/common/cgen-fpu.h b/sim/common/cgen-fpu.h
index 5f9b55d32e..cc5d3569e1 100644
--- a/sim/common/cgen-fpu.h
+++ b/sim/common/cgen-fpu.h
@@ -87,6 +87,7 @@ struct cgen_fp_ops {
int (*lesf) (CGEN_FPU*, SF, SF);
int (*gtsf) (CGEN_FPU*, SF, SF);
int (*gesf) (CGEN_FPU*, SF, SF);
+ int (*unorderedsf) (CGEN_FPU*, SF, SF);
/* basic DF ops */
@@ -112,6 +113,7 @@ struct cgen_fp_ops {
int (*ledf) (CGEN_FPU*, DF, DF);
int (*gtdf) (CGEN_FPU*, DF, DF);
int (*gedf) (CGEN_FPU*, DF, DF);
+ int (*unordereddf) (CGEN_FPU*, DF, DF);
/* SF/DF conversion ops */
--
2.21.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support
2019-06-08 21:32 [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Stafford Horne
` (8 preceding siblings ...)
2019-06-08 21:33 ` [PATCH v3 06/11] sim/or1k: Regenerate sim Stafford Horne
@ 2019-06-10 15:08 ` Nick Clifton
2019-06-10 20:51 ` Stafford Horne
2019-06-11 16:03 ` Nick Clifton
10 siblings, 1 reply; 15+ messages in thread
From: Nick Clifton @ 2019-06-10 15:08 UTC (permalink / raw)
To: Stafford Horne, GDB patches, GNU Binutils
Cc: Andrey Bacherov, Andrew Burgess, Richard Henderson, Openrisc
Hi Stafford,
> Its been a while since v2, but we have been busy changing direction a bit.
> Instead of just adding the orfpx64a32 extension support we have created a new
> architecture specification [0] and this series includes some of those changes.
I am just starting to look at this patch series, but I need to check one thing
first. The number suggests that there should be 11 patches, but I see only 9.
Are two missing, or is the numbering wrong ?
Cheers
Nick
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support
2019-06-10 15:08 ` [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Nick Clifton
@ 2019-06-10 20:51 ` Stafford Horne
0 siblings, 0 replies; 15+ messages in thread
From: Stafford Horne @ 2019-06-10 20:51 UTC (permalink / raw)
To: Nick Clifton
Cc: GDB patches, GNU Binutils, Andrey Bacherov, Andrew Burgess,
Richard Henderson, Openrisc
On Mon, Jun 10, 2019 at 04:07:48PM +0100, Nick Clifton wrote:
> Hi Stafford,
>
> > Its been a while since v2, but we have been busy changing direction a bit.
> > Instead of just adding the orfpx64a32 extension support we have created a new
> > architecture specification [0] and this series includes some of those changes.
>
> I am just starting to look at this patch series, but I need to check one thing
> first. The number suggests that there should be 11 patches, but I see only 9.
> Are two missing, or is the numbering wrong ?
Hello,
Thanks for having a look. Sorry, 2 were missing I just sent them.
-Stafford
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support
2019-06-08 21:32 [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Stafford Horne
` (9 preceding siblings ...)
2019-06-10 15:08 ` [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Nick Clifton
@ 2019-06-11 16:03 ` Nick Clifton
2019-06-12 13:12 ` Stafford Horne
10 siblings, 1 reply; 15+ messages in thread
From: Nick Clifton @ 2019-06-11 16:03 UTC (permalink / raw)
To: Stafford Horne, GDB patches, GNU Binutils
Cc: Andrey Bacherov, Andrew Burgess, Richard Henderson, Openrisc
Hi Stafford,
> Its been a while since v2, but we have been busy changing direction a bit.
> Instead of just adding the orfpx64a32 extension support we have created a new
> architecture specification [0] and this series includes some of those changes.
The binutils parts of the patch series are approved - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support
2019-06-11 16:03 ` Nick Clifton
@ 2019-06-12 13:12 ` Stafford Horne
2019-06-12 21:25 ` Stafford Horne
0 siblings, 1 reply; 15+ messages in thread
From: Stafford Horne @ 2019-06-12 13:12 UTC (permalink / raw)
To: Nick Clifton
Cc: GDB patches, GNU Binutils, Andrey Bacherov, Andrew Burgess,
Richard Henderson, Openrisc
On Tue, Jun 11, 2019 at 05:02:43PM +0100, Nick Clifton wrote:
> Hi Stafford,
>
> > Its been a while since v2, but we have been busy changing direction a bit.
> > Instead of just adding the orfpx64a32 extension support we have created a new
> > architecture specification [0] and this series includes some of those changes.
>
> The binutils parts of the patch series are approved - please apply.
Thanks for the review,
I will apply once I get the go ahead on the cgen patches.
-Stafford
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support
2019-06-12 13:12 ` Stafford Horne
@ 2019-06-12 21:25 ` Stafford Horne
0 siblings, 0 replies; 15+ messages in thread
From: Stafford Horne @ 2019-06-12 21:25 UTC (permalink / raw)
To: Nick Clifton
Cc: GDB patches, GNU Binutils, Andrey Bacherov, Andrew Burgess,
Richard Henderson, Openrisc
On Wed, Jun 12, 2019 at 10:12 PM Stafford Horne <shorne@gmail.com> wrote:
>
> On Tue, Jun 11, 2019 at 05:02:43PM +0100, Nick Clifton wrote:
> > Hi Stafford,
> >
> > > Its been a while since v2, but we have been busy changing direction a bit.
> > > Instead of just adding the orfpx64a32 extension support we have created a new
> > > architecture specification [0] and this series includes some of those changes.
> >
> > The binutils parts of the patch series are approved - please apply.
>
> Thanks for the review,
>
> I will apply once I get the go ahead on the cgen patches.
Note, the cgen changes were applied in cgen. The binutils portion has
been applied
now.
Thanks,
-Stafford
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2019-06-12 21:25 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-08 21:32 [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Stafford Horne
2019-06-08 21:32 ` [PATCH v3 02/11] cpu/or1k: Define unordered comparisons Stafford Horne
2019-06-08 21:32 ` [PATCH v3 04/11] cpu/or1k: Update fpu compare symbols to imply set flag Stafford Horne
2019-06-08 21:32 ` [PATCH v3 01/11] cpu/or1k: Add support for orfp64a32 spec Stafford Horne
2019-06-08 21:32 ` [PATCH v3 03/11] cpu/or1k: Document no branch delay slot architectures and l.adrp Stafford Horne
2019-06-08 21:33 ` [PATCH v3 05/11] opcodes/or1k: Regenerate opcodes Stafford Horne
2019-06-08 21:33 ` [PATCH v3 09/11] sim/testsuite/or1k: Add test for 64-bit fpu operations Stafford Horne
2019-06-08 21:33 ` [PATCH v3 08/11] sim/common: wire up new unordered comparisons Stafford Horne
2019-06-08 21:33 ` [PATCH v3 07/11] sim/common: Wire in df/di conversion Stafford Horne
2019-06-08 21:33 ` [PATCH v3 06/11] sim/or1k: Regenerate sim Stafford Horne
2019-06-10 15:08 ` [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Nick Clifton
2019-06-10 20:51 ` Stafford Horne
2019-06-11 16:03 ` Nick Clifton
2019-06-12 13:12 ` Stafford Horne
2019-06-12 21:25 ` Stafford Horne
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