From: Kito Cheng <kito.cheng@sifive.com>
To: binutils@sourceware.org, jimw@sifive.com
Cc: Kito Cheng <kito.cheng@sifive.com>
Subject: [PATCH v2 3/5] RISC-V: Fix wrong format for .insn
Date: Tue, 02 Jul 2019 09:58:00 -0000 [thread overview]
Message-ID: <20190702095801.32062-3-kito.cheng@sifive.com> (raw)
In-Reply-To: <20190702095801.32062-1-kito.cheng@sifive.com>
- LOAD should be I-Type and STORE should be S-Type.
gas/ChangeLog
* testsuite/gas/riscv/insn.s: Correct instruction type for load
and store.
opcodes/ChangeLog
* opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
format for sb type and correct s type.
---
gas/testsuite/gas/riscv/insn.s | 8 ++++----
opcodes/riscv-opc.c | 7 ++-----
2 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s
index 13e5417f7b..1b0915da4e 100644
--- a/gas/testsuite/gas/riscv/insn.s
+++ b/gas/testsuite/gas/riscv/insn.s
@@ -2,9 +2,9 @@ target:
.insn r 0x33, 0, 0, a0, a1, a2
.insn i 0x13, 0, a0, a1, 13
.insn i 0x67, 0, a0, 10(a1)
- .insn s 0x3, 0, a0, 4(a1)
+ .insn i 0x3, 0, a0, 4(a1)
.insn sb 0x63, 0, a0, a1, target
- .insn sb 0x23, 0, a0, 4(a1)
+ .insn s 0x23, 0, a0, 4(a1)
.insn u 0x37, a0, 0xfff
.insn uj 0x6f, a0, target
@@ -17,9 +17,9 @@ target:
.insn r OP, 0, 0, a0, a1, a2
.insn i OP_IMM, 0, a0, a1, 13
.insn i JALR, 0, a0, 10(a1)
- .insn s LOAD, 0, a0, 4(a1)
+ .insn i LOAD, 0, a0, 4(a1)
.insn sb BRANCH, 0, a0, a1, target
- .insn sb STORE, 0, a0, 4(a1)
+ .insn s STORE, 0, a0, 4(a1)
.insn u LUI, a0, 0xfff
.insn uj JAL, a0, target
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index bd652590b5..5b17279834 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -820,17 +820,14 @@ const struct riscv_opcode riscv_insn_types[] =
{"i", 0, {"I", 0}, "O4,F3,d,o(s)", 0, 0, match_opcode, 0 },
{"i", 0, {"I", 0}, "O4,F3,D,o(s)", 0, 0, match_opcode, 0 },
-{"s", 0, {"I", 0}, "O4,F3,d,o(s)", 0, 0, match_opcode, 0 },
-{"s", 0, {"I", 0}, "O4,F3,D,o(s)", 0, 0, match_opcode, 0 },
+{"s", 0, {"I", 0}, "O4,F3,t,q(s)", 0, 0, match_opcode, 0 },
+{"s", 0, {"I", 0}, "O4,F3,T,q(s)", 0, 0, match_opcode, 0 },
{"sb", 0, {"I", 0}, "O4,F3,s,t,p", 0, 0, match_opcode, 0 },
{"sb", 0, {"I", 0}, "O4,F3,S,t,p", 0, 0, match_opcode, 0 },
{"sb", 0, {"I", 0}, "O4,F3,s,T,p", 0, 0, match_opcode, 0 },
{"sb", 0, {"I", 0}, "O4,F3,S,T,p", 0, 0, match_opcode, 0 },
-{"sb", 0, {"I", 0}, "O4,F3,t,q(s)", 0, 0, match_opcode, 0 },
-{"sb", 0, {"I", 0}, "O4,F3,T,q(s)", 0, 0, match_opcode, 0 },
-
{"u", 0, {"I", 0}, "O4,d,u", 0, 0, match_opcode, 0 },
{"u", 0, {"I", 0}, "O4,D,u", 0, 0, match_opcode, 0 },
--
2.17.1
next prev parent reply other threads:[~2019-07-02 9:58 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-02 9:58 [PATCH v2 1/5] RISC-V: Fix doc " Kito Cheng
2019-07-02 9:58 ` [PATCH v2 5/5] RISC-V: Add r4 format for r type with 4 register operands Kito Cheng
2019-07-05 4:32 ` Jim Wilson
2019-07-02 9:58 ` [PATCH v2 4/5] RISC-V: sb/uj format named b/j in latest spec Kito Cheng
2019-07-05 4:31 ` Jim Wilson
2019-07-02 9:58 ` Kito Cheng [this message]
2019-07-05 4:30 ` [PATCH v2 3/5] RISC-V: Fix wrong format for .insn Jim Wilson
2019-07-02 9:58 ` [PATCH v2 2/5] RISC-V: Refine testcase Kito Cheng
2019-07-05 4:30 ` Jim Wilson
2019-07-05 4:29 ` [PATCH v2 1/5] RISC-V: Fix doc for .insn Jim Wilson
2019-07-05 5:46 ` Kito Cheng
2019-07-05 7:23 ` Jim Wilson
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