* [PATCH v5 0/5] x86: operand size handling improvements
@ 2020-02-11 10:23 Jan Beulich
2020-02-11 10:25 ` [PATCH v5 1/5] x86: also disallow non-byte/-word registers with byte/word suffix Jan Beulich
` (4 more replies)
0 siblings, 5 replies; 26+ messages in thread
From: Jan Beulich @ 2020-02-11 10:23 UTC (permalink / raw)
To: binutils; +Cc: H.J. Lu
The main goal continues to be better consistency in the handling of insn
operands, i.e. in particular less unexpected behavior when deducing how
things would behave from observations with one (set of) insn(s) or
operand(s) towards other constructs.
1: x86: also disallow non-byte/-word registers with byte/word suffix
2: x86: move certain MOVSX/MOVZX tests
3: x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZX
4: x86: correct VFPCLASSP{S,D} operand size handling
5: x86-64: Intel64 adjustments for insns dealing with far pointers
v5 is simply for re-basing over commits that have gone in since v4 was
sent.
Jan
^ permalink raw reply [flat|nested] 26+ messages in thread* [PATCH v5 1/5] x86: also disallow non-byte/-word registers with byte/word suffix 2020-02-11 10:23 [PATCH v5 0/5] x86: operand size handling improvements Jan Beulich @ 2020-02-11 10:25 ` Jan Beulich 2020-02-11 11:27 ` H.J. Lu 2020-02-11 10:25 ` [PATCH v5 3/5] x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZX Jan Beulich ` (3 subsequent siblings) 4 siblings, 1 reply; 26+ messages in thread From: Jan Beulich @ 2020-02-11 10:25 UTC (permalink / raw) To: binutils; +Cc: H.J. Lu Along the lines of be4c5e58bd ("x86: Always disallow double word suffix with word general register") also adjust check_{byte,word}_reg(), to make overall behavior consistent again in this regard. gas/ 2020-02-XX Jan Beulich <jbeulich@suse.com> PR gas/25438 * config/tc-i386.c (REGISTER_WARNINGS): Delete. (check_byte_reg): Skip only source operand of CRC32. Drop Non- 64-bit-only warning. (check_word_reg): Consistently error on mismatching register size and suffix. * testsuite/gas/i386/general.s: Replace dword GPR with word one for movw. Replace suffix / GPR for orb. * testsuite/gas/i386/inval.s: Add tests for movw with dword and byte GPRs as well as ones for inb/outb with a word accumulator. * testsuite/gas/i386/general.l, testsuite/gas/i386/intelbad.l, testsuite/gas/i386/inval.l: Adjust expectations. --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -44,10 +44,6 @@ #endif #endif -#ifndef REGISTER_WARNINGS -#define REGISTER_WARNINGS 1 -#endif - #ifndef INFER_ADDR_PREFIX #define INFER_ADDR_PREFIX 1 #endif @@ -6637,31 +6633,10 @@ check_byte_reg (void) && i.tm.operand_types[op].bitfield.word) continue; - /* crc32 doesn't generate this warning. */ - if (i.tm.base_opcode == 0xf20f38f0) + /* crc32 only wants its source operand checked here. */ + if (i.tm.base_opcode == 0xf20f38f0 && op) continue; - if ((i.types[op].bitfield.word - || i.types[op].bitfield.dword - || i.types[op].bitfield.qword) - && i.op[op].regs->reg_num < 4 - /* Prohibit these changes in 64bit mode, since the lowering - would be more complicated. */ - && flag_code != CODE_64BIT) - { -#if REGISTER_WARNINGS - if (!quiet_warnings) - as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), - register_prefix, - (i.op[op].regs + (i.types[op].bitfield.word - ? REGNAM_AL - REGNAM_AX - : REGNAM_AL - REGNAM_EAX))->reg_name, - register_prefix, - i.op[op].regs->reg_name, - i.suffix); -#endif - continue; - } /* Any other register is bad. */ if (i.types[op].bitfield.class == Reg || i.types[op].bitfield.class == RegMMX @@ -6817,29 +6792,17 @@ check_word_reg (void) i.suffix); return 0; } - /* Warn if the e or r prefix on a general reg is present. */ - else if ((!quiet_warnings || flag_code == CODE_64BIT) - && (i.types[op].bitfield.dword + /* Error if the e or r prefix on a general reg is present. */ + else if ((i.types[op].bitfield.dword || i.types[op].bitfield.qword) && (i.tm.operand_types[op].bitfield.class == Reg || i.tm.operand_types[op].bitfield.instance == Accum) && i.tm.operand_types[op].bitfield.word) { - /* Prohibit these changes in the 64bit mode, since the - lowering is more complicated. */ - if (flag_code == CODE_64BIT) - { - as_bad (_("incorrect register `%s%s' used with `%c' suffix"), - register_prefix, i.op[op].regs->reg_name, - i.suffix); - return 0; - } -#if REGISTER_WARNINGS - as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), - register_prefix, - (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, - register_prefix, i.op[op].regs->reg_name, i.suffix); -#endif + as_bad (_("incorrect register `%s%s' used with `%c' suffix"), + register_prefix, i.op[op].regs->reg_name, + i.suffix); + return 0; } return 1; } --- a/gas/testsuite/gas/i386/general.l +++ b/gas/testsuite/gas/i386/general.l @@ -9,12 +9,6 @@ .*:25: Warning:.* .*:27: Warning:.* .*:29: Warning:.* -.*:48: Warning:.* -.*:51: Warning:.* -.*:124: Warning:.* -.*:125: Warning:.* -.*:126: Warning:.* -.*:127: Warning:.* .*:128: Warning:.* .*:129: Warning:.* .*:130: Warning:.* @@ -90,12 +84,10 @@ 45 008d 661F popw %ds 46 008f 668CD8 mov %ds,%ax 47 0092 668CD8 movw %ds,%ax - 48 0095 668CD8 movw %ds,%eax -.*Warning:.* + 48 0095 668CDF movw %ds,%di 49 0098 8ED8 mov %ax,%ds 50 009a 8ED8 movw %ax,%ds - 51 009c 8ED8 movw %eax,%ds -.*Warning:.* + 51 009c 8EDF movw %di,%ds 52 53 # test various pushes 54 009e 6A0A pushl \$10 @@ -167,15 +159,11 @@ 120 012e 0F9303 setaeb \(%ebx\) 121 0131 0F93C0 setae %al 122 - 123 #these should give warnings - 124 0134 0C01 orb \$1,%ax -.*Warning:.* - 125 0136 0C01 orb \$1,%eax -.*Warning:.* - 126 0138 80CB01 orb \$1,%bx -.*Warning:.* - 127 013b 80CB01 orb \$1,%ebx -.*Warning:.* + 123 0134 0C01 orb \$1,%al + 124 0136 0D000100 00 orl \$0x100,%eax + 125 013b 80CB01 orb \$1,%bl + 126 + 127 #these should give warnings 128 013e D9C1 fldl %st\(1\) .*Warning:.* 129 0140 DDD2 fstl %st\(2\) --- a/gas/testsuite/gas/i386/general.s +++ b/gas/testsuite/gas/i386/general.s @@ -45,10 +45,10 @@ popw %ds mov %ds,%ax movw %ds,%ax - movw %ds,%eax + movw %ds,%di mov %ax,%ds movw %ax,%ds - movw %eax,%ds + movw %di,%ds # test various pushes pushl $10 @@ -120,11 +120,11 @@ setaeb (%ebx) setae %al + orb $1,%al + orl $0x100,%eax + orb $1,%bl + #these should give warnings - orb $1,%ax - orb $1,%eax - orb $1,%bx - orb $1,%ebx fldl %st(1) fstl %st(2) fstpl %st(3) --- a/gas/testsuite/gas/i386/intelbad.l +++ b/gas/testsuite/gas/i386/intelbad.l @@ -154,7 +154,7 @@ .*:172: Error: .* .*:174: Error: .* .*:175: Error: .* -.*:176: Warning: .* +.*:176: Error: .* .*:177: Error: .* .*:178: Error: .* .*:180: Error: .* --- a/gas/testsuite/gas/i386/inval.l +++ b/gas/testsuite/gas/i386/inval.l @@ -91,6 +91,12 @@ .*:104: Error: .* .*:105: Error: .* .*:106: Error: .* +.*:108: Error: .* +.*:109: Error: .* +.*:110: Error: .* +.*:112: Error: .* +.*:113: Error: .* +.*:114: Error: .* GAS LISTING .* @@ -203,3 +209,14 @@ GAS LISTING .* [ ]*[1-9][0-9]*[ ]+movl %ds, %ax [ ]*[1-9][0-9]*[ ]+movl %ax, %ds [ ]*[1-9][0-9]*[ ]+movl %ax, %bx +[ ]*[1-9][0-9]*[ ]+ +[ ]*[1-9][0-9]*[ ]+movw %ds, %eax +[ ]*[1-9][0-9]*[ ]+movw %eax, %ds +[ ]*[1-9][0-9]*[ ]+movw %eax, %ebx +[ ]*[1-9][0-9]*[ ]+ +[ ]*[1-9][0-9]*[ ]+inb %dx, %ax +[ ]*[1-9][0-9]*[ ]+outb %ax, %dx +[ ]*[1-9][0-9]*[ ]+movb %ax, %bx +\fGAS LISTING .* + + --- a/gas/testsuite/gas/i386/inval.s +++ b/gas/testsuite/gas/i386/inval.s @@ -104,3 +104,11 @@ movnti word ptr [eax], ax movl %ds, %ax movl %ax, %ds movl %ax, %bx + + movw %ds, %eax + movw %eax, %ds + movw %eax, %ebx + + inb %dx, %ax + outb %ax, %dx + movb %ax, %bx ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 1/5] x86: also disallow non-byte/-word registers with byte/word suffix 2020-02-11 10:25 ` [PATCH v5 1/5] x86: also disallow non-byte/-word registers with byte/word suffix Jan Beulich @ 2020-02-11 11:27 ` H.J. Lu 0 siblings, 0 replies; 26+ messages in thread From: H.J. Lu @ 2020-02-11 11:27 UTC (permalink / raw) To: Jan Beulich; +Cc: binutils On Tue, Feb 11, 2020 at 2:24 AM Jan Beulich <jbeulich@suse.com> wrote: > > Along the lines of be4c5e58bd ("x86: Always disallow double word suffix > with word general register") also adjust check_{byte,word}_reg(), to make > overall behavior consistent again in this regard. > > gas/ > 2020-02-XX Jan Beulich <jbeulich@suse.com> > > PR gas/25438 > * config/tc-i386.c (REGISTER_WARNINGS): Delete. > (check_byte_reg): Skip only source operand of CRC32. Drop Non- > 64-bit-only warning. > (check_word_reg): Consistently error on mismatching register > size and suffix. > * testsuite/gas/i386/general.s: Replace dword GPR with word one > for movw. Replace suffix / GPR for orb. > * testsuite/gas/i386/inval.s: Add tests for movw with dword and > byte GPRs as well as ones for inb/outb with a word accumulator. > * testsuite/gas/i386/general.l, testsuite/gas/i386/intelbad.l, > testsuite/gas/i386/inval.l: Adjust expectations. > OK. Thanks. -- H.J. ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v5 3/5] x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZX 2020-02-11 10:23 [PATCH v5 0/5] x86: operand size handling improvements Jan Beulich 2020-02-11 10:25 ` [PATCH v5 1/5] x86: also disallow non-byte/-word registers with byte/word suffix Jan Beulich @ 2020-02-11 10:25 ` Jan Beulich 2020-02-11 10:25 ` [PATCH v5 2/5] x86: move certain MOVSX/MOVZX tests Jan Beulich ` (2 subsequent siblings) 4 siblings, 0 replies; 26+ messages in thread From: Jan Beulich @ 2020-02-11 10:25 UTC (permalink / raw) To: binutils; +Cc: H.J. Lu For these to get treatment consistent with other operand size checking the special logic shouldn't live in md_assemble(), but process_suffix(). And there's more logic involved than simply zapping the suffix, in particular to enforce the general "suffix trumps register size" rule in AT&T mode. The cases where behavior is being corrected can be seen from the testcase adjustments (as mentioned in the commit introducing these tests some cases had wrong expectations at that point, but it seemed better to separate testcase introduction from actual code changes). Note however that MOVS[BW]* and MOVZ[BW]* still won't be fully consistent, due to the objection to fold MOVS* templates just like was done for MOVZ* in c07315e0c6 ("x86: allow suffix-less movzw and 64-bit movzb"). Note further that the assembler change points out (and this patch fixes) a wrong Intel syntax test introduced by bc31405ebb2c ("x86-64: Properly encode and decode movsxd"): When source code specifies a 16-bit destination register, disassembly expectations shouldn't have been to find a 32-bit one. gas/ 2020-02-XX Jan Beulich <jbeulich@suse.com> PR gas/25438 * config/tc-i386.c (md_assemble): Move movsx/movzx special casing ... (process_suffix): ... here. Consider just the first operand initially. (check_long_reg): Drop opcode 0x63 special case again. * testsuite/gas/i386/movx16.l, testsuite/gas/i386/movx32.l, testsuite/gas/i386/movx64.l, testsuite/gas/i386/noreg16.l, testsuite/gas/i386/noreg32.l, testsuite/gas/i386/noreg64.l, testsuite/gas/i386/x86-64-movsxd-intel.d, testsuite/gas/i386/x86-64-movsxd.d: Adjust expectations. opcodes/ 2020-02-XX Jan Beulich <jbeulich@suse.com> PR gas/25438 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as destination for Cpu64-only variant. (movsxd): Also allow Reg32 as destination. Drop Rex64. (movzx): Fold patterns. * i386-tbl.h: Re-generate. --- v5: Re-base. v4: Re-base. v3: Re-base. v2: Undo No_lSuf addition to MOVSXD template. Drop bogus / pointless !i.tm.opcode_modifier.rex64 part of conditional in md_assemble(). Re-base over changes earlier in the series. --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -4378,22 +4378,6 @@ md_assemble (char *line) : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); } - /* Zap movzx and movsx suffix. The suffix has been set from - "word ptr" or "byte ptr" on the source operand in Intel syntax - or extracted from mnemonic in AT&T syntax. But we'll use - the destination register to choose the suffix for encoding. */ - if ((i.tm.base_opcode & ~9) == 0x0fb6) - { - /* In Intel syntax, there must be a suffix. In AT&T syntax, if - there is no suffix, the default will be byte extension. */ - if (i.reg_operands != 2 - && !i.suffix - && intel_syntax) - as_bad (_("ambiguous operand size for `%s'"), i.tm.name); - - i.suffix = 0; - } - if (i.tm.opcode_modifier.fwait) if (!add_prefix (FWAIT_OPCODE)) return; @@ -6311,6 +6295,15 @@ process_suffix (void) else if (i.reg_operands && (i.operands > 1 || i.types[0].bitfield.class == Reg)) { + unsigned int numop = i.operands; + + /* movsx/movzx want only their source operand considered here, for the + ambiguity checking below. The suffix will be replaced afterwards + to represent the destination (register). */ + if (((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w) + || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64)) + --i.operands; + /* If there's no instruction mnemonic suffix we try to invent one based on GPR operands. */ if (!i.suffix) @@ -6339,6 +6332,13 @@ process_suffix (void) continue; break; } + + /* As an exception, movsx/movzx with a word register destination + silently default to a byte source in AT&T mode, as their word + memory source case isn't really useful. */ + if ((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w + && !i.suffix && !intel_syntax && i.types[1].bitfield.word) + i.suffix = BYTE_MNEM_SUFFIX; } else if (i.suffix == BYTE_MNEM_SUFFIX) { @@ -6385,6 +6385,9 @@ process_suffix (void) ; else abort (); + + /* Undo the movsx/movzx change done above. */ + i.operands = numop; } else if (i.tm.opcode_modifier.defaultsize && !i.suffix) { @@ -6484,6 +6487,10 @@ process_suffix (void) if (i.tm.opcode_modifier.floatmf) i.suffix = SHORT_MNEM_SUFFIX; + else if ((i.tm.base_opcode | 8) == 0xfbe + || (i.tm.base_opcode == 0x63 + && i.tm.cpu_flags.bitfield.cpu64)) + /* handled below */; else if (flag_code == CODE_16BIT) i.suffix = WORD_MNEM_SUFFIX; else if (!i.tm.opcode_modifier.no_lsuf) @@ -6493,6 +6500,32 @@ process_suffix (void) } } + if ((i.tm.base_opcode | 8) == 0xfbe + || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64)) + { + /* In Intel syntax, movsx/movzx must have a "suffix" (checked above). + In AT&T syntax, if there is no suffix (warned about above), the default + will be byte extension. */ + if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX) + i.tm.base_opcode |= 1; + + /* For further processing, the suffix should represent the destination + (register). This is already the case when one was used with + mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was + no suffix to begin with. */ + if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix) + { + if (i.types[1].bitfield.word) + i.suffix = WORD_MNEM_SUFFIX; + else if (i.types[1].bitfield.qword) + i.suffix = QWORD_MNEM_SUFFIX; + else + i.suffix = LONG_MNEM_SUFFIX; + + i.tm.opcode_modifier.w = 0; + } + } + if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3) i.short_form = (i.tm.operand_types[0].bitfield.class == Reg) != (i.tm.operand_types[1].bitfield.class == Reg); @@ -6699,9 +6732,7 @@ check_long_reg (void) && i.tm.operand_types[op].bitfield.dword) { if (intel_syntax - && (i.tm.opcode_modifier.toqword - /* Also convert to QWORD for MOVSXD. */ - || i.tm.base_opcode == 0x63) + && i.tm.opcode_modifier.toqword && i.types[0].bitfield.class != RegSIMD) { /* Convert to QWORD. We want REX byte. */ --- a/gas/testsuite/gas/i386/movx16.l +++ b/gas/testsuite/gas/i386/movx16.l @@ -6,7 +6,7 @@ [ ]*[1-9][0-9]*[ ]+movsx %eax, %cl [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsx %al, %cx -[ ]*[1-9][0-9]*[ ]+movsx %ax, %cx +[ ]*[1-9][0-9]* \?\?\?\? 0FBFC8[ ]+movsx %ax, %cx [ ]*[1-9][0-9]*[ ]+movsx %eax, %cx [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsx %al, %ecx @@ -30,7 +30,7 @@ [ ]*[1-9][0-9]*[ ]+movsxw %eax, %cl [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]*[ ]+movsxw %al, %cx -[ ]*[1-9][0-9]*[ ]+movsxw %ax, %cx +[ ]*[1-9][0-9]* \?\?\?\? 0FBFC8[ ]+movsxw %ax, %cx [ ]*[1-9][0-9]*[ ]+movsxw %eax, %cx [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]*[ ]+movsxw %al, %ecx @@ -103,7 +103,7 @@ [ ]*[1-9][0-9]*[ ]+movzx %eax, %cl [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzx %al, %cx -[ ]*[1-9][0-9]*[ ]+movzx %ax, %cx +[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzx %ax, %cx [ ]*[1-9][0-9]*[ ]+movzx %eax, %cx [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzx %al, %ecx @@ -127,7 +127,7 @@ [ ]*[1-9][0-9]*[ ]+movzxw %eax, %cl [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]*[ ]+movzxw %al, %cx -[ ]*[1-9][0-9]*[ ]+movzxw %ax, %cx +[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzxw %ax, %cx [ ]*[1-9][0-9]*[ ]+movzxw %eax, %cx [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]*[ ]+movzxw %al, %ecx @@ -154,7 +154,7 @@ [ ]*[1-9][0-9]*[ ]+movzbw %ax, %cx [ ]*[1-9][0-9]*[ ]+movzbw %eax, %cx [ ]*[1-9][0-9]*[ ]* -[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbw %al, %ecx +[ ]*[1-9][0-9]*[ ]+movzbw %al, %ecx [ ]*[1-9][0-9]*[ ]+movzbw %ax, %ecx [ ]*[1-9][0-9]*[ ]+movzbw %eax, %ecx [ ]*[1-9][0-9]*[ ]* @@ -162,7 +162,7 @@ [ ]*[1-9][0-9]*[ ]+movzbl %ax, %cl [ ]*[1-9][0-9]*[ ]+movzbl %eax, %cl [ ]*[1-9][0-9]*[ ]* -[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbl %al, %cx +[ ]*[1-9][0-9]*[ ]+movzbl %al, %cx [ ]*[1-9][0-9]*[ ]+movzbl %ax, %cx [ ]*[1-9][0-9]*[ ]+movzbl %eax, %cx [ ]*[1-9][0-9]*[ ]* --- a/gas/testsuite/gas/i386/movx32.l +++ b/gas/testsuite/gas/i386/movx32.l @@ -6,7 +6,7 @@ [ ]*[1-9][0-9]*[ ]+movsx %eax, %cl [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsx %al, %cx -[ ]*[1-9][0-9]*[ ]+movsx %ax, %cx +[ ]*[1-9][0-9]* \?\?\?\? 660FBFC8[ ]+movsx %ax, %cx [ ]*[1-9][0-9]*[ ]+movsx %eax, %cx [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsx %al, %ecx @@ -30,7 +30,7 @@ [ ]*[1-9][0-9]*[ ]+movsxw %eax, %cl [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]*[ ]+movsxw %al, %cx -[ ]*[1-9][0-9]*[ ]+movsxw %ax, %cx +[ ]*[1-9][0-9]* \?\?\?\? 660FBFC8[ ]+movsxw %ax, %cx [ ]*[1-9][0-9]*[ ]+movsxw %eax, %cx [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]*[ ]+movsxw %al, %ecx @@ -103,7 +103,7 @@ [ ]*[1-9][0-9]*[ ]+movzx %eax, %cl [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzx %al, %cx -[ ]*[1-9][0-9]*[ ]+movzx %ax, %cx +[ ]*[1-9][0-9]* \?\?\?\? 660FB7C8[ ]+movzx %ax, %cx [ ]*[1-9][0-9]*[ ]+movzx %eax, %cx [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzx %al, %ecx @@ -127,7 +127,7 @@ [ ]*[1-9][0-9]*[ ]+movzxw %eax, %cl [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]*[ ]+movzxw %al, %cx -[ ]*[1-9][0-9]*[ ]+movzxw %ax, %cx +[ ]*[1-9][0-9]* \?\?\?\? 660FB7C8[ ]+movzxw %ax, %cx [ ]*[1-9][0-9]*[ ]+movzxw %eax, %cx [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]*[ ]+movzxw %al, %ecx @@ -154,7 +154,7 @@ [ ]*[1-9][0-9]*[ ]+movzbw %ax, %cx [ ]*[1-9][0-9]*[ ]+movzbw %eax, %cx [ ]*[1-9][0-9]*[ ]* -[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbw %al, %ecx +[ ]*[1-9][0-9]*[ ]+movzbw %al, %ecx [ ]*[1-9][0-9]*[ ]+movzbw %ax, %ecx [ ]*[1-9][0-9]*[ ]+movzbw %eax, %ecx [ ]*[1-9][0-9]*[ ]* @@ -162,7 +162,7 @@ [ ]*[1-9][0-9]*[ ]+movzbl %ax, %cl [ ]*[1-9][0-9]*[ ]+movzbl %eax, %cl [ ]*[1-9][0-9]*[ ]* -[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbl %al, %cx +[ ]*[1-9][0-9]*[ ]+movzbl %al, %cx [ ]*[1-9][0-9]*[ ]+movzbl %ax, %cx [ ]*[1-9][0-9]*[ ]+movzbl %eax, %cx [ ]*[1-9][0-9]*[ ]* --- a/gas/testsuite/gas/i386/movx64.l +++ b/gas/testsuite/gas/i386/movx64.l @@ -7,13 +7,13 @@ [ ]*[1-9][0-9]*[ ]+movsx %rax, %cl [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsx %al, %cx -[ ]*[1-9][0-9]*[ ]+movsx %ax, %cx +[ ]*[1-9][0-9]* \?\?\?\? 660FBFC8[ ]+movsx %ax, %cx [ ]*[1-9][0-9]*[ ]+movsx %eax, %cx [ ]*[1-9][0-9]*[ ]+movsx %rax, %cx [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsx %al, %ecx [ ]*[1-9][0-9]* \?\?\?\? 0FBFC8[ ]+movsx %ax, %ecx -[ ]*[1-9][0-9]*[ ]+movsx %eax, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 63C8[ ]+movsx %eax, %ecx [ ]*[1-9][0-9]*[ ]+movsx %rax, %ecx [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]* \?\?\?\? 480FBEC8[ ]+movsx %al, %rcx @@ -47,7 +47,7 @@ [ ]*[1-9][0-9]*[ ]+movsxw %rax, %cl [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]*[ ]+movsxw %al, %cx -[ ]*[1-9][0-9]*[ ]+movsxw %ax, %cx +[ ]*[1-9][0-9]* \?\?\?\? 660FBFC8[ ]+movsxw %ax, %cx [ ]*[1-9][0-9]*[ ]+movsxw %eax, %cx [ ]*[1-9][0-9]*[ ]+movsxw %rax, %cx [ ]*[1-9][0-9]*[ ]* @@ -73,7 +73,7 @@ [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]*[ ]+movsxl %al, %ecx [ ]*[1-9][0-9]*[ ]+movsxl %ax, %ecx -[ ]*[1-9][0-9]*[ ]+movsxl %eax, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 63C8[ ]+movsxl %eax, %ecx [ ]*[1-9][0-9]*[ ]+movsxl %rax, %ecx [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]*[ ]+movsxl %al, %rcx @@ -248,7 +248,7 @@ [ ]*[1-9][0-9]*[ ]+movzx %rax, %cl [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzx %al, %cx -[ ]*[1-9][0-9]*[ ]+movzx %ax, %cx +[ ]*[1-9][0-9]* \?\?\?\? 660FB7C8[ ]+movzx %ax, %cx [ ]*[1-9][0-9]*[ ]+movzx %eax, %cx [ ]*[1-9][0-9]*[ ]+movzx %rax, %cx [ ]*[1-9][0-9]*[ ]* @@ -288,7 +288,7 @@ [ ]*[1-9][0-9]*[ ]+movzxw %rax, %cl [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]*[ ]+movzxw %al, %cx -[ ]*[1-9][0-9]*[ ]+movzxw %ax, %cx +[ ]*[1-9][0-9]* \?\?\?\? 660FB7C8[ ]+movzxw %ax, %cx [ ]*[1-9][0-9]*[ ]+movzxw %eax, %cx [ ]*[1-9][0-9]*[ ]+movzxw %rax, %cx [ ]*[1-9][0-9]*[ ]* @@ -372,12 +372,12 @@ [ ]*[1-9][0-9]*[ ]+movzbw %eax, %cx [ ]*[1-9][0-9]*[ ]+movzbw %rax, %cx [ ]*[1-9][0-9]*[ ]* -[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbw %al, %ecx +[ ]*[1-9][0-9]*[ ]+movzbw %al, %ecx [ ]*[1-9][0-9]*[ ]+movzbw %ax, %ecx [ ]*[1-9][0-9]*[ ]+movzbw %eax, %ecx [ ]*[1-9][0-9]*[ ]+movzbw %rax, %ecx [ ]*[1-9][0-9]*[ ]* -[ ]*[1-9][0-9]* \?\?\?\? 480FB6C8[ ]+movzbw %al, %rcx +[ ]*[1-9][0-9]*[ ]+movzbw %al, %rcx [ ]*[1-9][0-9]*[ ]+movzbw %ax, %rcx [ ]*[1-9][0-9]*[ ]+movzbw %eax, %rcx [ ]*[1-9][0-9]*[ ]+movzbw %rax, %rcx @@ -387,7 +387,7 @@ [ ]*[1-9][0-9]*[ ]+movzbl %eax, %cl [ ]*[1-9][0-9]*[ ]+movzbl %rax, %cl [ ]*[1-9][0-9]*[ ]* -[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbl %al, %cx +[ ]*[1-9][0-9]*[ ]+movzbl %al, %cx [ ]*[1-9][0-9]*[ ]+movzbl %ax, %cx [ ]*[1-9][0-9]*[ ]+movzbl %eax, %cx [ ]*[1-9][0-9]*[ ]+movzbl %rax, %cx @@ -397,7 +397,7 @@ [ ]*[1-9][0-9]*[ ]+movzbl %eax, %ecx [ ]*[1-9][0-9]*[ ]+movzbl %rax, %ecx [ ]*[1-9][0-9]*[ ]* -[ ]*[1-9][0-9]* \?\?\?\? 480FB6C8[ ]+movzbl %al, %rcx +[ ]*[1-9][0-9]*[ ]+movzbl %al, %rcx [ ]*[1-9][0-9]*[ ]+movzbl %ax, %rcx [ ]*[1-9][0-9]*[ ]+movzbl %eax, %rcx [ ]*[1-9][0-9]*[ ]+movzbl %rax, %rcx @@ -407,12 +407,12 @@ [ ]*[1-9][0-9]*[ ]+movzbq %eax, %cl [ ]*[1-9][0-9]*[ ]+movzbq %rax, %cl [ ]*[1-9][0-9]*[ ]* -[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbq %al, %cx +[ ]*[1-9][0-9]*[ ]+movzbq %al, %cx [ ]*[1-9][0-9]*[ ]+movzbq %ax, %cx [ ]*[1-9][0-9]*[ ]+movzbq %eax, %cx [ ]*[1-9][0-9]*[ ]+movzbq %rax, %cx [ ]*[1-9][0-9]*[ ]* -[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbq %al, %ecx +[ ]*[1-9][0-9]*[ ]+movzbq %al, %ecx [ ]*[1-9][0-9]*[ ]+movzbq %ax, %ecx [ ]*[1-9][0-9]*[ ]+movzbq %eax, %ecx [ ]*[1-9][0-9]*[ ]+movzbq %rax, %ecx @@ -458,7 +458,7 @@ [ ]*[1-9][0-9]*[ ]+movzwl %rax, %ecx [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]*[ ]+movzwl %al, %rcx -[ ]*[1-9][0-9]* \?\?\?\? 480FB7C8[ ]+movzwl %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movzwl %ax, %rcx [ ]*[1-9][0-9]*[ ]+movzwl %eax, %rcx [ ]*[1-9][0-9]*[ ]+movzwl %rax, %rcx [ ]*[1-9][0-9]*[ ]* @@ -473,7 +473,7 @@ [ ]*[1-9][0-9]*[ ]+movzwq %rax, %cx [ ]*[1-9][0-9]*[ ]* [ ]*[1-9][0-9]*[ ]+movzwq %al, %ecx -[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzwq %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzwq %ax, %ecx [ ]*[1-9][0-9]*[ ]+movzwq %eax, %ecx [ ]*[1-9][0-9]*[ ]+movzwq %rax, %ecx [ ]*[1-9][0-9]*[ ]* --- a/gas/testsuite/gas/i386/noreg16.l +++ b/gas/testsuite/gas/i386/noreg16.l @@ -56,6 +56,8 @@ .*:[1-9][0-9]*: Warning: .* `mov' .*:[1-9][0-9]*: Warning: .* `movs' .*:[1-9][0-9]*: Warning: .* `movs' +.*:[1-9][0-9]*: Warning: .* `movsx' +.*:[1-9][0-9]*: Warning: .* `movzx' .*:[1-9][0-9]*: Warning: .* `mul' .*:[1-9][0-9]*: Warning: .* `neg' .*:[1-9][0-9]*: Warning: .* `nop' --- a/gas/testsuite/gas/i386/noreg32.l +++ b/gas/testsuite/gas/i386/noreg32.l @@ -61,6 +61,8 @@ .*:[1-9][0-9]*: Warning: .* `mov' .*:[1-9][0-9]*: Warning: .* `movs' .*:[1-9][0-9]*: Warning: .* `movs' +.*:[1-9][0-9]*: Warning: .* `movsx' +.*:[1-9][0-9]*: Warning: .* `movzx' .*:[1-9][0-9]*: Warning: .* `mul' .*:[1-9][0-9]*: Warning: .* `neg' .*:[1-9][0-9]*: Warning: .* `nop' --- a/gas/testsuite/gas/i386/noreg64.l +++ b/gas/testsuite/gas/i386/noreg64.l @@ -67,6 +67,10 @@ .*:[1-9][0-9]*: Warning: .* `mov' .*:[1-9][0-9]*: Warning: .* `movs' .*:[1-9][0-9]*: Warning: .* `movs' +.*:[1-9][0-9]*: Warning: .* `movsx' +.*:[1-9][0-9]*: Warning: .* `movsx' +.*:[1-9][0-9]*: Warning: .* `movzx' +.*:[1-9][0-9]*: Warning: .* `movzx' .*:[1-9][0-9]*: Warning: .* `mul' .*:[1-9][0-9]*: Warning: .* `neg' .*:[1-9][0-9]*: Warning: .* `nop' --- a/gas/testsuite/gas/i386/x86-64-movsxd-intel.d +++ b/gas/testsuite/gas/i386/x86-64-movsxd-intel.d @@ -21,6 +21,6 @@ Disassembly of section .text: +[a-f0-9]+: 63 08 movsxd ecx,DWORD PTR \[rax\] +[a-f0-9]+: 63 08 movsxd ecx,DWORD PTR \[rax\] +[a-f0-9]+: 66 63 c8 movsxd cx,eax - +[a-f0-9]+: 63 08 movsxd ecx,DWORD PTR \[rax\] + +[a-f0-9]+: 66 63 08 movsxd cx,DWORD PTR \[rax\] +[a-f0-9]+: 66 63 08 movsxd cx,DWORD PTR \[rax\] #pass --- a/gas/testsuite/gas/i386/x86-64-movsxd.d +++ b/gas/testsuite/gas/i386/x86-64-movsxd.d @@ -20,6 +20,6 @@ Disassembly of section .text: +[a-f0-9]+: 63 08 movsxd \(%rax\),%ecx +[a-f0-9]+: 63 08 movsxd \(%rax\),%ecx +[a-f0-9]+: 66 63 c8 movsxd %eax,%cx - +[a-f0-9]+: 63 08 movsxd \(%rax\),%ecx + +[a-f0-9]+: 66 63 08 movsxd \(%rax\),%cx +[a-f0-9]+: 66 63 08 movsxd \(%rax\),%cx #pass --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -132,13 +132,9 @@ movswl, 2, 0xfbf, None, 2, Cpu386, Modrm movsbq, 2, 0xfbe, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg8|Byte|Unspecified|BaseIndex, Reg64 } movswq, 2, 0xfbf, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg16|Word|Unspecified|BaseIndex, Reg64 } movslq, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg32|Dword|Unspecified|BaseIndex, Reg64 } -// Intel Syntax next 3 insns -movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 } -movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|ATTSyntax, { Reg32|Unspecified|BaseIndex, Reg64 } -movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg8|Byte|BaseIndex, Reg16|Reg32|Reg64 } -movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex, Reg32|Reg64 } -movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|IntelSyntax, { Reg32|Dword|BaseIndex, Reg64 } +// Intel Syntax next 2 insns +movsx, 2, 0xfbe, None, 2, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 } movsxd, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 } movsxd, 2, 0x63, None, 1, Cpu64, Amd64|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg16 } movsxd, 2, 0x63, None, 1, Cpu64, Intel64|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Unspecified|BaseIndex, Reg16 } @@ -146,12 +142,9 @@ movsxd, 2, 0x63, None, 1, Cpu64, Intel64 // Move with zero extend. movzb, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } movzw, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32|Reg64 } -// Intel Syntax next 2 insns (the 64-bit variants are not particulary +// Intel Syntax next insn (the 64-bit variant is not particulary // useful since the zero extend 32->64 is implicit, but we can encode them). -movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 } -movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg8|Byte|BaseIndex, Reg16|Reg32|Reg64 } -movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex, Reg32|Reg64 } +movzx, 2, 0xfb6, None, 2, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // Push instructions. push, 1, 0x50, None, 1, CpuNo64, No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 } ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v5 2/5] x86: move certain MOVSX/MOVZX tests 2020-02-11 10:23 [PATCH v5 0/5] x86: operand size handling improvements Jan Beulich 2020-02-11 10:25 ` [PATCH v5 1/5] x86: also disallow non-byte/-word registers with byte/word suffix Jan Beulich 2020-02-11 10:25 ` [PATCH v5 3/5] x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZX Jan Beulich @ 2020-02-11 10:25 ` Jan Beulich 2020-02-11 11:43 ` H.J. Lu 2020-02-11 10:26 ` [PATCH v5 4/5] x86: correct VFPCLASSP{S,D} operand size handling Jan Beulich 2020-02-11 10:27 ` [PATCH v5 5/5] x86-64: Intel64 adjustments for insns dealing with far pointers Jan Beulich 4 siblings, 1 reply; 26+ messages in thread From: Jan Beulich @ 2020-02-11 10:25 UTC (permalink / raw) To: binutils; +Cc: H.J. Lu Some encodings are about to gain a warning - move them from test cases not expecting any diagnostics to the new, dedicated ones, to allow better focus on the actual changes in the subsequent patch. The new tests added have some wrong expectations right now, which will be corrected by the next patch. The test is being added here to make more visible which cases actually were wrong (and hence get changed), besides demonstrating that in the vast majority of cases the subsequent change doesn't alter generated code. gas/ 2020-02-XX Jan Beulich <jbeulich@suse.com> * testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s, testsuite/gas/i386/ilp32/x86-64.s: Move ambiguous operand size tests ... * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s, testsuite/gas/i386/noreg64.s, testsuite/gas/i386/x86_64.s: ... here. * testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d, testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d, testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg64.d, testsuite/gas/i386/x86_64-intel.d, testsuite/gas/i386/x86_64.d: Adjust expectations. * testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l, testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l, testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New. * testsuite/gas/i386/i386.exp: Run new tests. --- v5: Re-base. v4: Make tests also work on COFF/PE targets. Re-base. v3: Re-base. v2: Add new MOVSXD cases to x86_64.s testcase. Re-base over NOP addition to testcases modified here. --- a/gas/testsuite/gas/i386/i386-intel.d +++ b/gas/testsuite/gas/i386/i386-intel.d @@ -14,7 +14,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f be f0 movsx si,al [ ]*[a-f0-9]+: 0f be f0 movsx esi,al [ ]*[a-f0-9]+: 0f bf f0 movsx esi,ax -[ ]*[a-f0-9]+: 0f be 10 movsx edx,BYTE PTR \[eax\] [ ]*[a-f0-9]+: 66 0f be 10 movsx dx,BYTE PTR \[eax\] [ ]*[a-f0-9]+: 66 0f be 10 movsx dx,BYTE PTR \[eax\] [ ]*[a-f0-9]+: 0f be 10 movsx edx,BYTE PTR \[eax\] @@ -25,7 +24,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f b6 f0 movzx si,al [ ]*[a-f0-9]+: 0f b6 f0 movzx esi,al [ ]*[a-f0-9]+: 0f b7 f0 movzx esi,ax -[ ]*[a-f0-9]+: 0f b6 10 movzx edx,BYTE PTR \[eax\] [ ]*[a-f0-9]+: 66 0f b6 10 movzx dx,BYTE PTR \[eax\] [ ]*[a-f0-9]+: 66 0f b6 10 movzx dx,BYTE PTR \[eax\] [ ]*[a-f0-9]+: 0f b6 10 movzx edx,BYTE PTR \[eax\] --- a/gas/testsuite/gas/i386/i386.d +++ b/gas/testsuite/gas/i386/i386.d @@ -13,7 +13,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi [ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi -[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx [ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx @@ -24,7 +23,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si [ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi [ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi -[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -132,6 +132,8 @@ if [expr ([istarget "i*86-*-*"] || [ist run_list_test "noreg16" run_dump_test "noreg32" run_list_test "noreg32" + run_list_test "movx16" "-I${srcdir}/$subdir -al" + run_list_test "movx32" "-al" run_dump_test "addr16" run_dump_test "addr32" run_dump_test "code16" @@ -734,6 +736,7 @@ if [expr ([istarget "i*86-*-*"] || [ista run_list_test "x86-64-sysenter-amd" "-mamd64" run_dump_test "noreg64" run_list_test "noreg64" + run_list_test "movx64" "-al" run_list_test "cvtsi2sX" run_dump_test "x86-64-sse4_1" run_dump_test "x86-64-sse4_1-intel" --- a/gas/testsuite/gas/i386/i386.s +++ b/gas/testsuite/gas/i386/i386.s @@ -9,7 +9,6 @@ movsx %al, %si movsx %al, %esi movsx %ax, %esi - movsx (%eax), %edx movsx (%eax), %dx movsxb (%eax), %dx movsxb (%eax), %edx @@ -21,7 +20,6 @@ movzx %al, %si movzx %al, %esi movzx %ax, %esi - movzx (%eax), %edx movzx (%eax), %dx movzxb (%eax), %dx movzxb (%eax), %edx --- a/gas/testsuite/gas/i386/iamcu-1.d +++ b/gas/testsuite/gas/i386/iamcu-1.d @@ -10,7 +10,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi [ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi -[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx [ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx @@ -21,7 +20,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si [ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi [ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi -[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx --- a/gas/testsuite/gas/i386/iamcu-1.s +++ b/gas/testsuite/gas/i386/iamcu-1.s @@ -4,7 +4,6 @@ movsx %al, %si movsx %al, %esi movsx %ax, %esi - movsx (%eax), %edx movsx (%eax), %dx movsxb (%eax), %dx movsxb (%eax), %edx @@ -16,7 +15,6 @@ movzx %al, %si movzx %al, %esi movzx %ax, %esi - movzx (%eax), %edx movzx (%eax), %dx movzxb (%eax), %dx movzxb (%eax), %edx --- a/gas/testsuite/gas/i386/ilp32/x86-64.d +++ b/gas/testsuite/gas/i386/ilp32/x86-64.d @@ -162,8 +162,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi [ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi [ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi -[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx -[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx @@ -175,8 +173,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi [ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi [ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi -[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx -[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx @@ -220,8 +216,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 9b df e0 fstsw %ax [ ]*[a-f0-9]+: 9b df e0 fstsw %ax [ ]*[a-f0-9]+: 66 0f be 00 movsbw \(%rax\),%ax -[ ]*[a-f0-9]+: 0f be 00 movsbl \(%rax\),%eax -[ ]*[a-f0-9]+: 48 0f be 00 movsbq \(%rax\),%rax [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx @@ -230,8 +224,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 63 10 movslq \(%rax\),%rdx [ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax [ ]*[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax -[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax -[ ]*[a-f0-9]+: 48 0f b6 00 movzbq \(%rax\),%rax [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx --- a/gas/testsuite/gas/i386/ilp32/x86-64.s +++ b/gas/testsuite/gas/i386/ilp32/x86-64.s @@ -194,8 +194,6 @@ cmpxchg16b oword ptr [rax] movsx %ax, %esi movsx %ax, %rsi movsx %eax, %rsi - movsx (%rax), %edx - movsx (%rax), %rdx movsx (%rax), %dx movsbl (%rax), %edx movsbq (%rax), %rdx @@ -208,8 +206,6 @@ cmpxchg16b oword ptr [rax] movzx %al, %rsi movzx %ax, %esi movzx %ax, %rsi - movzx (%rax), %edx - movzx (%rax), %rdx movzx (%rax), %dx movzb (%rax), %edx movzb (%rax), %rdx @@ -263,8 +259,6 @@ cmpxchg16b oword ptr [rax] .att_syntax movsx (%rax),%ax -movsx (%rax),%eax -movsx (%rax),%rax movsxb (%rax), %dx movsxb (%rax), %edx movsxb (%rax), %rdx @@ -273,8 +267,6 @@ movsxw (%rax), %rdx movsxl (%rax), %rdx movsxd (%rax),%rax movzx (%rax),%ax -movzx (%rax),%eax -movzx (%rax),%rax movzxb (%rax), %dx movzxb (%rax), %edx movzxb (%rax), %rdx --- a/gas/testsuite/gas/i386/k1om.d +++ b/gas/testsuite/gas/i386/k1om.d @@ -175,8 +175,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi [ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi [ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi -[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx -[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx @@ -188,8 +186,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi [ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi [ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi -[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx -[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx @@ -233,8 +229,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 9b df e0 fstsw %ax [ ]*[a-f0-9]+: 9b df e0 fstsw %ax [ ]*[a-f0-9]+: 66 0f be 00 movsbw \(%rax\),%ax -[ ]*[a-f0-9]+: 0f be 00 movsbl \(%rax\),%eax -[ ]*[a-f0-9]+: 48 0f be 00 movsbq \(%rax\),%rax [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx @@ -243,8 +237,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 63 10 movslq \(%rax\),%rdx [ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax [ ]*[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax -[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax -[ ]*[a-f0-9]+: 48 0f b6 00 movzbq \(%rax\),%rax [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx --- a/gas/testsuite/gas/i386/l1om.d +++ b/gas/testsuite/gas/i386/l1om.d @@ -175,8 +175,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi [ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi [ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi -[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx -[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx @@ -188,8 +186,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi [ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi [ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi -[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx -[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx @@ -233,8 +229,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 9b df e0 fstsw %ax [ ]*[a-f0-9]+: 9b df e0 fstsw %ax [ ]*[a-f0-9]+: 66 0f be 00 movsbw \(%rax\),%ax -[ ]*[a-f0-9]+: 0f be 00 movsbl \(%rax\),%eax -[ ]*[a-f0-9]+: 48 0f be 00 movsbq \(%rax\),%rax [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx @@ -243,8 +237,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 63 10 movslq \(%rax\),%rdx [ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax [ ]*[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax -[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax -[ ]*[a-f0-9]+: 48 0f b6 00 movzbq \(%rax\),%rax [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx --- /dev/null +++ b/gas/testsuite/gas/i386/movx16.l @@ -0,0 +1,197 @@ +.*: Assembler messages: +#... +[ ]*[1-9][0-9]*[ ]+movsx: +[ ]*[1-9][0-9]*[ ]+movsx %al, %cl +[ ]*[1-9][0-9]*[ ]+movsx %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsx %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsx %al, %cx +[ ]*[1-9][0-9]*[ ]+movsx %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsx %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsx %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 660FBFC8[ ]+movsx %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsx %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxb %al, %cl +[ ]*[1-9][0-9]*[ ]+movsxb %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsxb %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsxb %al, %cx +[ ]*[1-9][0-9]*[ ]+movsxb %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsxb %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsxb %al, %ecx +[ ]*[1-9][0-9]*[ ]+movsxb %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsxb %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxw %al, %cl +[ ]*[1-9][0-9]*[ ]+movsxw %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsxw %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxw %al, %cx +[ ]*[1-9][0-9]*[ ]+movsxw %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsxw %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxw %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 660FBFC8[ ]+movsxw %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsxw %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsb %al, %cl +[ ]*[1-9][0-9]*[ ]+movsb %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsb %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsb %al, %cx +[ ]*[1-9][0-9]*[ ]+movsb %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsb %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsb %al, %ecx +[ ]*[1-9][0-9]*[ ]+movsb %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsb %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsbw %al, %cl +[ ]*[1-9][0-9]*[ ]+movsbw %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsbw %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsbw %al, %cx +[ ]*[1-9][0-9]*[ ]+movsbw %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsbw %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsbw %al, %ecx +[ ]*[1-9][0-9]*[ ]+movsbw %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsbw %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsbl %al, %cl +[ ]*[1-9][0-9]*[ ]+movsbl %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsbl %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsbl %al, %cx +[ ]*[1-9][0-9]*[ ]+movsbl %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsbl %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsbl %al, %ecx +[ ]*[1-9][0-9]*[ ]+movsbl %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsbl %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsw %al, %cl +[ ]*[1-9][0-9]*[ ]+movsw %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsw %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsw %al, %cx +[ ]*[1-9][0-9]*[ ]+movsw %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsw %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsw %al, %ecx +[ ]*[1-9][0-9]*[ ]+movsw %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsw %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movswl %al, %cl +[ ]*[1-9][0-9]*[ ]+movswl %ax, %cl +[ ]*[1-9][0-9]*[ ]+movswl %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movswl %al, %cx +[ ]*[1-9][0-9]*[ ]+movswl %ax, %cx +[ ]*[1-9][0-9]*[ ]+movswl %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movswl %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 660FBFC8[ ]+movswl %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movswl %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzx: +[ ]*[1-9][0-9]*[ ]+movzx %al, %cl +[ ]*[1-9][0-9]*[ ]+movzx %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzx %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzx %al, %cx +[ ]*[1-9][0-9]*[ ]+movzx %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzx %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzx %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 660FB7C8[ ]+movzx %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzx %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxb %al, %cl +[ ]*[1-9][0-9]*[ ]+movzxb %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzxb %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzxb %al, %cx +[ ]*[1-9][0-9]*[ ]+movzxb %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzxb %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzxb %al, %ecx +[ ]*[1-9][0-9]*[ ]+movzxb %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzxb %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxw %al, %cl +[ ]*[1-9][0-9]*[ ]+movzxw %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzxw %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxw %al, %cx +[ ]*[1-9][0-9]*[ ]+movzxw %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzxw %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxw %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 660FB7C8[ ]+movzxw %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzxw %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzb %al, %cl +[ ]*[1-9][0-9]*[ ]+movzb %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzb %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzb %al, %cx +[ ]*[1-9][0-9]*[ ]+movzb %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzb %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzb %al, %ecx +[ ]*[1-9][0-9]*[ ]+movzb %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzb %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzbw %al, %cl +[ ]*[1-9][0-9]*[ ]+movzbw %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzbw %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbw %al, %cx +[ ]*[1-9][0-9]*[ ]+movzbw %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzbw %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbw %al, %ecx +[ ]*[1-9][0-9]*[ ]+movzbw %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzbw %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzbl %al, %cl +[ ]*[1-9][0-9]*[ ]+movzbl %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzbl %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbl %al, %cx +[ ]*[1-9][0-9]*[ ]+movzbl %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzbl %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbl %al, %ecx +[ ]*[1-9][0-9]*[ ]+movzbl %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzbl %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzw %al, %cl +[ ]*[1-9][0-9]*[ ]+movzw %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzw %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzw %al, %cx +[ ]*[1-9][0-9]*[ ]+movzw %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzw %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzw %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 660FB7C8[ ]+movzw %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzw %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzwl %al, %cl +[ ]*[1-9][0-9]*[ ]+movzwl %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzwl %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzwl %al, %cx +[ ]*[1-9][0-9]*[ ]+movzwl %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzwl %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzwl %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 660FB7C8[ ]+movzwl %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzwl %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +#pass --- /dev/null +++ b/gas/testsuite/gas/i386/movx16.s @@ -0,0 +1,2 @@ + .code16 + .include "movx32.s" --- /dev/null +++ b/gas/testsuite/gas/i386/movx32.l @@ -0,0 +1,197 @@ +.*: Assembler messages: +#... +[ ]*[1-9][0-9]*[ ]+movsx: +[ ]*[1-9][0-9]*[ ]+movsx %al, %cl +[ ]*[1-9][0-9]*[ ]+movsx %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsx %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsx %al, %cx +[ ]*[1-9][0-9]*[ ]+movsx %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsx %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsx %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 0FBFC8[ ]+movsx %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsx %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxb %al, %cl +[ ]*[1-9][0-9]*[ ]+movsxb %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsxb %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsxb %al, %cx +[ ]*[1-9][0-9]*[ ]+movsxb %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsxb %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsxb %al, %ecx +[ ]*[1-9][0-9]*[ ]+movsxb %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsxb %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxw %al, %cl +[ ]*[1-9][0-9]*[ ]+movsxw %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsxw %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxw %al, %cx +[ ]*[1-9][0-9]*[ ]+movsxw %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsxw %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxw %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 0FBFC8[ ]+movsxw %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsxw %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsb %al, %cl +[ ]*[1-9][0-9]*[ ]+movsb %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsb %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsb %al, %cx +[ ]*[1-9][0-9]*[ ]+movsb %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsb %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsb %al, %ecx +[ ]*[1-9][0-9]*[ ]+movsb %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsb %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsbw %al, %cl +[ ]*[1-9][0-9]*[ ]+movsbw %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsbw %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsbw %al, %cx +[ ]*[1-9][0-9]*[ ]+movsbw %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsbw %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsbw %al, %ecx +[ ]*[1-9][0-9]*[ ]+movsbw %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsbw %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsbl %al, %cl +[ ]*[1-9][0-9]*[ ]+movsbl %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsbl %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsbl %al, %cx +[ ]*[1-9][0-9]*[ ]+movsbl %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsbl %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsbl %al, %ecx +[ ]*[1-9][0-9]*[ ]+movsbl %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsbl %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsw %al, %cl +[ ]*[1-9][0-9]*[ ]+movsw %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsw %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsw %al, %cx +[ ]*[1-9][0-9]*[ ]+movsw %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsw %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsw %al, %ecx +[ ]*[1-9][0-9]*[ ]+movsw %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsw %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movswl %al, %cl +[ ]*[1-9][0-9]*[ ]+movswl %ax, %cl +[ ]*[1-9][0-9]*[ ]+movswl %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movswl %al, %cx +[ ]*[1-9][0-9]*[ ]+movswl %ax, %cx +[ ]*[1-9][0-9]*[ ]+movswl %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movswl %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 0FBFC8[ ]+movswl %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movswl %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzx: +[ ]*[1-9][0-9]*[ ]+movzx %al, %cl +[ ]*[1-9][0-9]*[ ]+movzx %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzx %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzx %al, %cx +[ ]*[1-9][0-9]*[ ]+movzx %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzx %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzx %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzx %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzx %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxb %al, %cl +[ ]*[1-9][0-9]*[ ]+movzxb %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzxb %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzxb %al, %cx +[ ]*[1-9][0-9]*[ ]+movzxb %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzxb %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzxb %al, %ecx +[ ]*[1-9][0-9]*[ ]+movzxb %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzxb %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxw %al, %cl +[ ]*[1-9][0-9]*[ ]+movzxw %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzxw %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxw %al, %cx +[ ]*[1-9][0-9]*[ ]+movzxw %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzxw %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxw %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzxw %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzxw %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzb %al, %cl +[ ]*[1-9][0-9]*[ ]+movzb %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzb %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzb %al, %cx +[ ]*[1-9][0-9]*[ ]+movzb %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzb %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzb %al, %ecx +[ ]*[1-9][0-9]*[ ]+movzb %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzb %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzbw %al, %cl +[ ]*[1-9][0-9]*[ ]+movzbw %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzbw %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbw %al, %cx +[ ]*[1-9][0-9]*[ ]+movzbw %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzbw %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbw %al, %ecx +[ ]*[1-9][0-9]*[ ]+movzbw %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzbw %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzbl %al, %cl +[ ]*[1-9][0-9]*[ ]+movzbl %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzbl %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbl %al, %cx +[ ]*[1-9][0-9]*[ ]+movzbl %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzbl %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbl %al, %ecx +[ ]*[1-9][0-9]*[ ]+movzbl %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzbl %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzw %al, %cl +[ ]*[1-9][0-9]*[ ]+movzw %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzw %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzw %al, %cx +[ ]*[1-9][0-9]*[ ]+movzw %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzw %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzw %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzw %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzw %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzwl %al, %cl +[ ]*[1-9][0-9]*[ ]+movzwl %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzwl %eax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzwl %al, %cx +[ ]*[1-9][0-9]*[ ]+movzwl %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzwl %eax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzwl %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzwl %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzwl %eax, %ecx +[ ]*[1-9][0-9]*[ ]* +#pass --- /dev/null +++ b/gas/testsuite/gas/i386/movx32.s @@ -0,0 +1,197 @@ + .text + .psize 0 +movsx: + movsx %al, %cl + movsx %ax, %cl + movsx %eax, %cl + + movsx %al, %cx + movsx %ax, %cx + movsx %eax, %cx + + movsx %al, %ecx + movsx %ax, %ecx + movsx %eax, %ecx + + movsxb %al, %cl + movsxb %ax, %cl + movsxb %eax, %cl + + movsxb %al, %cx + movsxb %ax, %cx + movsxb %eax, %cx + + movsxb %al, %ecx + movsxb %ax, %ecx + movsxb %eax, %ecx + + movsxw %al, %cl + movsxw %ax, %cl + movsxw %eax, %cl + + movsxw %al, %cx + movsxw %ax, %cx + movsxw %eax, %cx + + movsxw %al, %ecx + movsxw %ax, %ecx + movsxw %eax, %ecx + + movsb %al, %cl + movsb %ax, %cl + movsb %eax, %cl + + movsb %al, %cx + movsb %ax, %cx + movsb %eax, %cx + + movsb %al, %ecx + movsb %ax, %ecx + movsb %eax, %ecx + + movsbw %al, %cl + movsbw %ax, %cl + movsbw %eax, %cl + + movsbw %al, %cx + movsbw %ax, %cx + movsbw %eax, %cx + + movsbw %al, %ecx + movsbw %ax, %ecx + movsbw %eax, %ecx + + movsbl %al, %cl + movsbl %ax, %cl + movsbl %eax, %cl + + movsbl %al, %cx + movsbl %ax, %cx + movsbl %eax, %cx + + movsbl %al, %ecx + movsbl %ax, %ecx + movsbl %eax, %ecx + + movsw %al, %cl + movsw %ax, %cl + movsw %eax, %cl + + movsw %al, %cx + movsw %ax, %cx + movsw %eax, %cx + + movsw %al, %ecx + movsw %ax, %ecx + movsw %eax, %ecx + + movswl %al, %cl + movswl %ax, %cl + movswl %eax, %cl + + movswl %al, %cx + movswl %ax, %cx + movswl %eax, %cx + + movswl %al, %ecx + movswl %ax, %ecx + movswl %eax, %ecx + +movzx: + movzx %al, %cl + movzx %ax, %cl + movzx %eax, %cl + + movzx %al, %cx + movzx %ax, %cx + movzx %eax, %cx + + movzx %al, %ecx + movzx %ax, %ecx + movzx %eax, %ecx + + movzxb %al, %cl + movzxb %ax, %cl + movzxb %eax, %cl + + movzxb %al, %cx + movzxb %ax, %cx + movzxb %eax, %cx + + movzxb %al, %ecx + movzxb %ax, %ecx + movzxb %eax, %ecx + + movzxw %al, %cl + movzxw %ax, %cl + movzxw %eax, %cl + + movzxw %al, %cx + movzxw %ax, %cx + movzxw %eax, %cx + + movzxw %al, %ecx + movzxw %ax, %ecx + movzxw %eax, %ecx + + movzb %al, %cl + movzb %ax, %cl + movzb %eax, %cl + + movzb %al, %cx + movzb %ax, %cx + movzb %eax, %cx + + movzb %al, %ecx + movzb %ax, %ecx + movzb %eax, %ecx + + movzbw %al, %cl + movzbw %ax, %cl + movzbw %eax, %cl + + movzbw %al, %cx + movzbw %ax, %cx + movzbw %eax, %cx + + movzbw %al, %ecx + movzbw %ax, %ecx + movzbw %eax, %ecx + + movzbl %al, %cl + movzbl %ax, %cl + movzbl %eax, %cl + + movzbl %al, %cx + movzbl %ax, %cx + movzbl %eax, %cx + + movzbl %al, %ecx + movzbl %ax, %ecx + movzbl %eax, %ecx + + movzw %al, %cl + movzw %ax, %cl + movzw %eax, %cl + + movzw %al, %cx + movzw %ax, %cx + movzw %eax, %cx + + movzw %al, %ecx + movzw %ax, %ecx + movzw %eax, %ecx + + movzwl %al, %cl + movzwl %ax, %cl + movzwl %eax, %cl + + movzwl %al, %cx + movzwl %ax, %cx + movzwl %eax, %cx + + movzwl %al, %ecx + movzwl %ax, %ecx + movzwl %eax, %ecx + + .p2align 4 --- /dev/null +++ b/gas/testsuite/gas/i386/movx64.l @@ -0,0 +1,485 @@ +.*: Assembler messages: +#... +[ ]*[1-9][0-9]*[ ]+movsx: +[ ]*[1-9][0-9]*[ ]+movsx %al, %cl +[ ]*[1-9][0-9]*[ ]+movsx %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsx %eax, %cl +[ ]*[1-9][0-9]*[ ]+movsx %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsx %al, %cx +[ ]*[1-9][0-9]*[ ]+movsx %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsx %eax, %cx +[ ]*[1-9][0-9]*[ ]+movsx %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsx %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 0FBFC8[ ]+movsx %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsx %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movsx %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 480FBEC8[ ]+movsx %al, %rcx +[ ]*[1-9][0-9]* \?\?\?\? 480FBFC8[ ]+movsx %ax, %rcx +[ ]*[1-9][0-9]* \?\?\?\? 4863C8[ ]+movsx %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movsx %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxb %al, %cl +[ ]*[1-9][0-9]*[ ]+movsxb %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsxb %eax, %cl +[ ]*[1-9][0-9]*[ ]+movsxb %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsxb %al, %cx +[ ]*[1-9][0-9]*[ ]+movsxb %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsxb %eax, %cx +[ ]*[1-9][0-9]*[ ]+movsxb %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsxb %al, %ecx +[ ]*[1-9][0-9]*[ ]+movsxb %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsxb %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movsxb %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 480FBEC8[ ]+movsxb %al, %rcx +[ ]*[1-9][0-9]*[ ]+movsxb %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movsxb %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movsxb %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxw %al, %cl +[ ]*[1-9][0-9]*[ ]+movsxw %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsxw %eax, %cl +[ ]*[1-9][0-9]*[ ]+movsxw %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxw %al, %cx +[ ]*[1-9][0-9]*[ ]+movsxw %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsxw %eax, %cx +[ ]*[1-9][0-9]*[ ]+movsxw %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxw %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 0FBFC8[ ]+movsxw %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsxw %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movsxw %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxw %al, %rcx +[ ]*[1-9][0-9]* \?\?\?\? 480FBFC8[ ]+movsxw %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movsxw %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movsxw %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxl %al, %cl +[ ]*[1-9][0-9]*[ ]+movsxl %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsxl %eax, %cl +[ ]*[1-9][0-9]*[ ]+movsxl %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxl %al, %cx +[ ]*[1-9][0-9]*[ ]+movsxl %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsxl %eax, %cx +[ ]*[1-9][0-9]*[ ]+movsxl %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxl %al, %ecx +[ ]*[1-9][0-9]*[ ]+movsxl %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsxl %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movsxl %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxl %al, %rcx +[ ]*[1-9][0-9]*[ ]+movsxl %ax, %rcx +[ ]*[1-9][0-9]* \?\?\?\? 4863C8[ ]+movsxl %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movsxl %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxd %al, %cl +[ ]*[1-9][0-9]*[ ]+movsxd %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsxd %eax, %cl +[ ]*[1-9][0-9]*[ ]+movsxd %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxd %al, %cx +[ ]*[1-9][0-9]*[ ]+movsxd %ax, %cx +[ ]*[1-9][0-9]* \?\?\?\? 6663C8[ ]+movsxd %eax, %cx +[ ]*[1-9][0-9]*[ ]+movsxd %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxd %al, %ecx +[ ]*[1-9][0-9]*[ ]+movsxd %ax, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 63C8[ ]+movsxd %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movsxd %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsxd %al, %rcx +[ ]*[1-9][0-9]*[ ]+movsxd %ax, %rcx +[ ]*[1-9][0-9]* \?\?\?\? 4863C8[ ]+movsxd %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movsxd %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsb %al, %cl +[ ]*[1-9][0-9]*[ ]+movsb %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsb %eax, %cl +[ ]*[1-9][0-9]*[ ]+movsb %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsb %al, %cx +[ ]*[1-9][0-9]*[ ]+movsb %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsb %eax, %cx +[ ]*[1-9][0-9]*[ ]+movsb %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsb %al, %ecx +[ ]*[1-9][0-9]*[ ]+movsb %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsb %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movsb %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsb %al, %rcx +[ ]*[1-9][0-9]*[ ]+movsb %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movsb %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movsb %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsbw %al, %cl +[ ]*[1-9][0-9]*[ ]+movsbw %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsbw %eax, %cl +[ ]*[1-9][0-9]*[ ]+movsbw %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsbw %al, %cx +[ ]*[1-9][0-9]*[ ]+movsbw %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsbw %eax, %cx +[ ]*[1-9][0-9]*[ ]+movsbw %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsbw %al, %ecx +[ ]*[1-9][0-9]*[ ]+movsbw %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsbw %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movsbw %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsbw %al, %rcx +[ ]*[1-9][0-9]*[ ]+movsbw %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movsbw %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movsbw %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsbl %al, %cl +[ ]*[1-9][0-9]*[ ]+movsbl %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsbl %eax, %cl +[ ]*[1-9][0-9]*[ ]+movsbl %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsbl %al, %cx +[ ]*[1-9][0-9]*[ ]+movsbl %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsbl %eax, %cx +[ ]*[1-9][0-9]*[ ]+movsbl %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsbl %al, %ecx +[ ]*[1-9][0-9]*[ ]+movsbl %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsbl %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movsbl %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsbl %al, %rcx +[ ]*[1-9][0-9]*[ ]+movsbl %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movsbl %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movsbl %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsbq %al, %cl +[ ]*[1-9][0-9]*[ ]+movsbq %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsbq %eax, %cl +[ ]*[1-9][0-9]*[ ]+movsbq %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsbq %al, %cx +[ ]*[1-9][0-9]*[ ]+movsbq %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsbq %eax, %cx +[ ]*[1-9][0-9]*[ ]+movsbq %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsbq %al, %ecx +[ ]*[1-9][0-9]*[ ]+movsbq %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsbq %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movsbq %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 480FBEC8[ ]+movsbq %al, %rcx +[ ]*[1-9][0-9]*[ ]+movsbq %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movsbq %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movsbq %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsw %al, %cl +[ ]*[1-9][0-9]*[ ]+movsw %ax, %cl +[ ]*[1-9][0-9]*[ ]+movsw %eax, %cl +[ ]*[1-9][0-9]*[ ]+movsw %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsw %al, %cx +[ ]*[1-9][0-9]*[ ]+movsw %ax, %cx +[ ]*[1-9][0-9]*[ ]+movsw %eax, %cx +[ ]*[1-9][0-9]*[ ]+movsw %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsw %al, %ecx +[ ]*[1-9][0-9]*[ ]+movsw %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movsw %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movsw %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movsw %al, %rcx +[ ]*[1-9][0-9]*[ ]+movsw %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movsw %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movsw %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movswl %al, %cl +[ ]*[1-9][0-9]*[ ]+movswl %ax, %cl +[ ]*[1-9][0-9]*[ ]+movswl %eax, %cl +[ ]*[1-9][0-9]*[ ]+movswl %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movswl %al, %cx +[ ]*[1-9][0-9]*[ ]+movswl %ax, %cx +[ ]*[1-9][0-9]*[ ]+movswl %eax, %cx +[ ]*[1-9][0-9]*[ ]+movswl %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movswl %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 0FBFC8[ ]+movswl %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movswl %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movswl %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movswl %al, %rcx +[ ]*[1-9][0-9]*[ ]+movswl %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movswl %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movswl %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movswq %al, %cl +[ ]*[1-9][0-9]*[ ]+movswq %ax, %cl +[ ]*[1-9][0-9]*[ ]+movswq %eax, %cl +[ ]*[1-9][0-9]*[ ]+movswq %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movswq %al, %cx +[ ]*[1-9][0-9]*[ ]+movswq %ax, %cx +[ ]*[1-9][0-9]*[ ]+movswq %eax, %cx +[ ]*[1-9][0-9]*[ ]+movswq %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movswq %al, %ecx +[ ]*[1-9][0-9]*[ ]+movswq %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movswq %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movswq %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movswq %al, %rcx +[ ]*[1-9][0-9]* \?\?\?\? 480FBFC8[ ]+movswq %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movswq %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movswq %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzx: +[ ]*[1-9][0-9]*[ ]+movzx %al, %cl +[ ]*[1-9][0-9]*[ ]+movzx %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzx %eax, %cl +[ ]*[1-9][0-9]*[ ]+movzx %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzx %al, %cx +[ ]*[1-9][0-9]*[ ]+movzx %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzx %eax, %cx +[ ]*[1-9][0-9]*[ ]+movzx %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzx %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzx %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzx %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movzx %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 480FB6C8[ ]+movzx %al, %rcx +[ ]*[1-9][0-9]* \?\?\?\? 480FB7C8[ ]+movzx %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movzx %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movzx %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxb %al, %cl +[ ]*[1-9][0-9]*[ ]+movzxb %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzxb %eax, %cl +[ ]*[1-9][0-9]*[ ]+movzxb %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzxb %al, %cx +[ ]*[1-9][0-9]*[ ]+movzxb %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzxb %eax, %cx +[ ]*[1-9][0-9]*[ ]+movzxb %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzxb %al, %ecx +[ ]*[1-9][0-9]*[ ]+movzxb %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzxb %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movzxb %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 480FB6C8[ ]+movzxb %al, %rcx +[ ]*[1-9][0-9]*[ ]+movzxb %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movzxb %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movzxb %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxw %al, %cl +[ ]*[1-9][0-9]*[ ]+movzxw %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzxw %eax, %cl +[ ]*[1-9][0-9]*[ ]+movzxw %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxw %al, %cx +[ ]*[1-9][0-9]*[ ]+movzxw %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzxw %eax, %cx +[ ]*[1-9][0-9]*[ ]+movzxw %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxw %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzxw %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzxw %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movzxw %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxw %al, %rcx +[ ]*[1-9][0-9]* \?\?\?\? 480FB7C8[ ]+movzxw %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movzxw %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movzxw %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxl %al, %cl +[ ]*[1-9][0-9]*[ ]+movzxl %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzxl %eax, %cl +[ ]*[1-9][0-9]*[ ]+movzxl %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxl %al, %cx +[ ]*[1-9][0-9]*[ ]+movzxl %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzxl %eax, %cx +[ ]*[1-9][0-9]*[ ]+movzxl %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxl %al, %ecx +[ ]*[1-9][0-9]*[ ]+movzxl %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzxl %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movzxl %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxl %al, %rcx +[ ]*[1-9][0-9]*[ ]+movzxl %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movzxl %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movzxl %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxd %al, %cl +[ ]*[1-9][0-9]*[ ]+movzxd %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzxd %eax, %cl +[ ]*[1-9][0-9]*[ ]+movzxd %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxd %al, %cx +[ ]*[1-9][0-9]*[ ]+movzxd %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzxd %eax, %cx +[ ]*[1-9][0-9]*[ ]+movzxd %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxd %al, %ecx +[ ]*[1-9][0-9]*[ ]+movzxd %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzxd %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movzxd %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzxd %al, %rcx +[ ]*[1-9][0-9]*[ ]+movzxd %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movzxd %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movzxd %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzb %al, %cl +[ ]*[1-9][0-9]*[ ]+movzb %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzb %eax, %cl +[ ]*[1-9][0-9]*[ ]+movzb %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzb %al, %cx +[ ]*[1-9][0-9]*[ ]+movzb %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzb %eax, %cx +[ ]*[1-9][0-9]*[ ]+movzb %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzb %al, %ecx +[ ]*[1-9][0-9]*[ ]+movzb %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzb %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movzb %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 480FB6C8[ ]+movzb %al, %rcx +[ ]*[1-9][0-9]*[ ]+movzb %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movzb %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movzb %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzbw %al, %cl +[ ]*[1-9][0-9]*[ ]+movzbw %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzbw %eax, %cl +[ ]*[1-9][0-9]*[ ]+movzbw %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbw %al, %cx +[ ]*[1-9][0-9]*[ ]+movzbw %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzbw %eax, %cx +[ ]*[1-9][0-9]*[ ]+movzbw %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbw %al, %ecx +[ ]*[1-9][0-9]*[ ]+movzbw %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzbw %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movzbw %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 480FB6C8[ ]+movzbw %al, %rcx +[ ]*[1-9][0-9]*[ ]+movzbw %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movzbw %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movzbw %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzbl %al, %cl +[ ]*[1-9][0-9]*[ ]+movzbl %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzbl %eax, %cl +[ ]*[1-9][0-9]*[ ]+movzbl %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbl %al, %cx +[ ]*[1-9][0-9]*[ ]+movzbl %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzbl %eax, %cx +[ ]*[1-9][0-9]*[ ]+movzbl %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbl %al, %ecx +[ ]*[1-9][0-9]*[ ]+movzbl %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzbl %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movzbl %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 480FB6C8[ ]+movzbl %al, %rcx +[ ]*[1-9][0-9]*[ ]+movzbl %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movzbl %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movzbl %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzbq %al, %cl +[ ]*[1-9][0-9]*[ ]+movzbq %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzbq %eax, %cl +[ ]*[1-9][0-9]*[ ]+movzbq %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbq %al, %cx +[ ]*[1-9][0-9]*[ ]+movzbq %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzbq %eax, %cx +[ ]*[1-9][0-9]*[ ]+movzbq %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbq %al, %ecx +[ ]*[1-9][0-9]*[ ]+movzbq %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzbq %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movzbq %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]* \?\?\?\? 480FB6C8[ ]+movzbq %al, %rcx +[ ]*[1-9][0-9]*[ ]+movzbq %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movzbq %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movzbq %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzw %al, %cl +[ ]*[1-9][0-9]*[ ]+movzw %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzw %eax, %cl +[ ]*[1-9][0-9]*[ ]+movzw %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzw %al, %cx +[ ]*[1-9][0-9]*[ ]+movzw %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzw %eax, %cx +[ ]*[1-9][0-9]*[ ]+movzw %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzw %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzw %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzw %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movzw %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzw %al, %rcx +[ ]*[1-9][0-9]* \?\?\?\? 480FB7C8[ ]+movzw %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movzw %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movzw %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzwl %al, %cl +[ ]*[1-9][0-9]*[ ]+movzwl %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzwl %eax, %cl +[ ]*[1-9][0-9]*[ ]+movzwl %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzwl %al, %cx +[ ]*[1-9][0-9]*[ ]+movzwl %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzwl %eax, %cx +[ ]*[1-9][0-9]*[ ]+movzwl %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzwl %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzwl %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzwl %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movzwl %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzwl %al, %rcx +[ ]*[1-9][0-9]* \?\?\?\? 480FB7C8[ ]+movzwl %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movzwl %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movzwl %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzwq %al, %cl +[ ]*[1-9][0-9]*[ ]+movzwq %ax, %cl +[ ]*[1-9][0-9]*[ ]+movzwq %eax, %cl +[ ]*[1-9][0-9]*[ ]+movzwq %rax, %cl +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzwq %al, %cx +[ ]*[1-9][0-9]*[ ]+movzwq %ax, %cx +[ ]*[1-9][0-9]*[ ]+movzwq %eax, %cx +[ ]*[1-9][0-9]*[ ]+movzwq %rax, %cx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzwq %al, %ecx +[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzwq %ax, %ecx +[ ]*[1-9][0-9]*[ ]+movzwq %eax, %ecx +[ ]*[1-9][0-9]*[ ]+movzwq %rax, %ecx +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]+movzwq %al, %rcx +[ ]*[1-9][0-9]* \?\?\?\? 480FB7C8[ ]+movzwq %ax, %rcx +[ ]*[1-9][0-9]*[ ]+movzwq %eax, %rcx +[ ]*[1-9][0-9]*[ ]+movzwq %rax, %rcx +[ ]*[1-9][0-9]*[ ]* +#pass --- /dev/null +++ b/gas/testsuite/gas/i386/movx64.s @@ -0,0 +1,485 @@ + .text + .psize 0 +movsx: + movsx %al, %cl + movsx %ax, %cl + movsx %eax, %cl + movsx %rax, %cl + + movsx %al, %cx + movsx %ax, %cx + movsx %eax, %cx + movsx %rax, %cx + + movsx %al, %ecx + movsx %ax, %ecx + movsx %eax, %ecx + movsx %rax, %ecx + + movsx %al, %rcx + movsx %ax, %rcx + movsx %eax, %rcx + movsx %rax, %rcx + + movsxb %al, %cl + movsxb %ax, %cl + movsxb %eax, %cl + movsxb %rax, %cl + + movsxb %al, %cx + movsxb %ax, %cx + movsxb %eax, %cx + movsxb %rax, %cx + + movsxb %al, %ecx + movsxb %ax, %ecx + movsxb %eax, %ecx + movsxb %rax, %ecx + + movsxb %al, %rcx + movsxb %ax, %rcx + movsxb %eax, %rcx + movsxb %rax, %rcx + + movsxw %al, %cl + movsxw %ax, %cl + movsxw %eax, %cl + movsxw %rax, %cl + + movsxw %al, %cx + movsxw %ax, %cx + movsxw %eax, %cx + movsxw %rax, %cx + + movsxw %al, %ecx + movsxw %ax, %ecx + movsxw %eax, %ecx + movsxw %rax, %ecx + + movsxw %al, %rcx + movsxw %ax, %rcx + movsxw %eax, %rcx + movsxw %rax, %rcx + + movsxl %al, %cl + movsxl %ax, %cl + movsxl %eax, %cl + movsxl %rax, %cl + + movsxl %al, %cx + movsxl %ax, %cx + movsxl %eax, %cx + movsxl %rax, %cx + + movsxl %al, %ecx + movsxl %ax, %ecx + movsxl %eax, %ecx + movsxl %rax, %ecx + + movsxl %al, %rcx + movsxl %ax, %rcx + movsxl %eax, %rcx + movsxl %rax, %rcx + + movsxd %al, %cl + movsxd %ax, %cl + movsxd %eax, %cl + movsxd %rax, %cl + + movsxd %al, %cx + movsxd %ax, %cx + movsxd %eax, %cx + movsxd %rax, %cx + + movsxd %al, %ecx + movsxd %ax, %ecx + movsxd %eax, %ecx + movsxd %rax, %ecx + + movsxd %al, %rcx + movsxd %ax, %rcx + movsxd %eax, %rcx + movsxd %rax, %rcx + + movsb %al, %cl + movsb %ax, %cl + movsb %eax, %cl + movsb %rax, %cl + + movsb %al, %cx + movsb %ax, %cx + movsb %eax, %cx + movsb %rax, %cx + + movsb %al, %ecx + movsb %ax, %ecx + movsb %eax, %ecx + movsb %rax, %ecx + + movsb %al, %rcx + movsb %ax, %rcx + movsb %eax, %rcx + movsb %rax, %rcx + + movsbw %al, %cl + movsbw %ax, %cl + movsbw %eax, %cl + movsbw %rax, %cl + + movsbw %al, %cx + movsbw %ax, %cx + movsbw %eax, %cx + movsbw %rax, %cx + + movsbw %al, %ecx + movsbw %ax, %ecx + movsbw %eax, %ecx + movsbw %rax, %ecx + + movsbw %al, %rcx + movsbw %ax, %rcx + movsbw %eax, %rcx + movsbw %rax, %rcx + + movsbl %al, %cl + movsbl %ax, %cl + movsbl %eax, %cl + movsbl %rax, %cl + + movsbl %al, %cx + movsbl %ax, %cx + movsbl %eax, %cx + movsbl %rax, %cx + + movsbl %al, %ecx + movsbl %ax, %ecx + movsbl %eax, %ecx + movsbl %rax, %ecx + + movsbl %al, %rcx + movsbl %ax, %rcx + movsbl %eax, %rcx + movsbl %rax, %rcx + + movsbq %al, %cl + movsbq %ax, %cl + movsbq %eax, %cl + movsbq %rax, %cl + + movsbq %al, %cx + movsbq %ax, %cx + movsbq %eax, %cx + movsbq %rax, %cx + + movsbq %al, %ecx + movsbq %ax, %ecx + movsbq %eax, %ecx + movsbq %rax, %ecx + + movsbq %al, %rcx + movsbq %ax, %rcx + movsbq %eax, %rcx + movsbq %rax, %rcx + + movsw %al, %cl + movsw %ax, %cl + movsw %eax, %cl + movsw %rax, %cl + + movsw %al, %cx + movsw %ax, %cx + movsw %eax, %cx + movsw %rax, %cx + + movsw %al, %ecx + movsw %ax, %ecx + movsw %eax, %ecx + movsw %rax, %ecx + + movsw %al, %rcx + movsw %ax, %rcx + movsw %eax, %rcx + movsw %rax, %rcx + + movswl %al, %cl + movswl %ax, %cl + movswl %eax, %cl + movswl %rax, %cl + + movswl %al, %cx + movswl %ax, %cx + movswl %eax, %cx + movswl %rax, %cx + + movswl %al, %ecx + movswl %ax, %ecx + movswl %eax, %ecx + movswl %rax, %ecx + + movswl %al, %rcx + movswl %ax, %rcx + movswl %eax, %rcx + movswl %rax, %rcx + + movswq %al, %cl + movswq %ax, %cl + movswq %eax, %cl + movswq %rax, %cl + + movswq %al, %cx + movswq %ax, %cx + movswq %eax, %cx + movswq %rax, %cx + + movswq %al, %ecx + movswq %ax, %ecx + movswq %eax, %ecx + movswq %rax, %ecx + + movswq %al, %rcx + movswq %ax, %rcx + movswq %eax, %rcx + movswq %rax, %rcx + +movzx: + movzx %al, %cl + movzx %ax, %cl + movzx %eax, %cl + movzx %rax, %cl + + movzx %al, %cx + movzx %ax, %cx + movzx %eax, %cx + movzx %rax, %cx + + movzx %al, %ecx + movzx %ax, %ecx + movzx %eax, %ecx + movzx %rax, %ecx + + movzx %al, %rcx + movzx %ax, %rcx + movzx %eax, %rcx + movzx %rax, %rcx + + movzxb %al, %cl + movzxb %ax, %cl + movzxb %eax, %cl + movzxb %rax, %cl + + movzxb %al, %cx + movzxb %ax, %cx + movzxb %eax, %cx + movzxb %rax, %cx + + movzxb %al, %ecx + movzxb %ax, %ecx + movzxb %eax, %ecx + movzxb %rax, %ecx + + movzxb %al, %rcx + movzxb %ax, %rcx + movzxb %eax, %rcx + movzxb %rax, %rcx + + movzxw %al, %cl + movzxw %ax, %cl + movzxw %eax, %cl + movzxw %rax, %cl + + movzxw %al, %cx + movzxw %ax, %cx + movzxw %eax, %cx + movzxw %rax, %cx + + movzxw %al, %ecx + movzxw %ax, %ecx + movzxw %eax, %ecx + movzxw %rax, %ecx + + movzxw %al, %rcx + movzxw %ax, %rcx + movzxw %eax, %rcx + movzxw %rax, %rcx + + movzxl %al, %cl + movzxl %ax, %cl + movzxl %eax, %cl + movzxl %rax, %cl + + movzxl %al, %cx + movzxl %ax, %cx + movzxl %eax, %cx + movzxl %rax, %cx + + movzxl %al, %ecx + movzxl %ax, %ecx + movzxl %eax, %ecx + movzxl %rax, %ecx + + movzxl %al, %rcx + movzxl %ax, %rcx + movzxl %eax, %rcx + movzxl %rax, %rcx + + movzxd %al, %cl + movzxd %ax, %cl + movzxd %eax, %cl + movzxd %rax, %cl + + movzxd %al, %cx + movzxd %ax, %cx + movzxd %eax, %cx + movzxd %rax, %cx + + movzxd %al, %ecx + movzxd %ax, %ecx + movzxd %eax, %ecx + movzxd %rax, %ecx + + movzxd %al, %rcx + movzxd %ax, %rcx + movzxd %eax, %rcx + movzxd %rax, %rcx + + movzb %al, %cl + movzb %ax, %cl + movzb %eax, %cl + movzb %rax, %cl + + movzb %al, %cx + movzb %ax, %cx + movzb %eax, %cx + movzb %rax, %cx + + movzb %al, %ecx + movzb %ax, %ecx + movzb %eax, %ecx + movzb %rax, %ecx + + movzb %al, %rcx + movzb %ax, %rcx + movzb %eax, %rcx + movzb %rax, %rcx + + movzbw %al, %cl + movzbw %ax, %cl + movzbw %eax, %cl + movzbw %rax, %cl + + movzbw %al, %cx + movzbw %ax, %cx + movzbw %eax, %cx + movzbw %rax, %cx + + movzbw %al, %ecx + movzbw %ax, %ecx + movzbw %eax, %ecx + movzbw %rax, %ecx + + movzbw %al, %rcx + movzbw %ax, %rcx + movzbw %eax, %rcx + movzbw %rax, %rcx + + movzbl %al, %cl + movzbl %ax, %cl + movzbl %eax, %cl + movzbl %rax, %cl + + movzbl %al, %cx + movzbl %ax, %cx + movzbl %eax, %cx + movzbl %rax, %cx + + movzbl %al, %ecx + movzbl %ax, %ecx + movzbl %eax, %ecx + movzbl %rax, %ecx + + movzbl %al, %rcx + movzbl %ax, %rcx + movzbl %eax, %rcx + movzbl %rax, %rcx + + movzbq %al, %cl + movzbq %ax, %cl + movzbq %eax, %cl + movzbq %rax, %cl + + movzbq %al, %cx + movzbq %ax, %cx + movzbq %eax, %cx + movzbq %rax, %cx + + movzbq %al, %ecx + movzbq %ax, %ecx + movzbq %eax, %ecx + movzbq %rax, %ecx + + movzbq %al, %rcx + movzbq %ax, %rcx + movzbq %eax, %rcx + movzbq %rax, %rcx + + movzw %al, %cl + movzw %ax, %cl + movzw %eax, %cl + movzw %rax, %cl + + movzw %al, %cx + movzw %ax, %cx + movzw %eax, %cx + movzw %rax, %cx + + movzw %al, %ecx + movzw %ax, %ecx + movzw %eax, %ecx + movzw %rax, %ecx + + movzw %al, %rcx + movzw %ax, %rcx + movzw %eax, %rcx + movzw %rax, %rcx + + movzwl %al, %cl + movzwl %ax, %cl + movzwl %eax, %cl + movzwl %rax, %cl + + movzwl %al, %cx + movzwl %ax, %cx + movzwl %eax, %cx + movzwl %rax, %cx + + movzwl %al, %ecx + movzwl %ax, %ecx + movzwl %eax, %ecx + movzwl %rax, %ecx + + movzwl %al, %rcx + movzwl %ax, %rcx + movzwl %eax, %rcx + movzwl %rax, %rcx + + movzwq %al, %cl + movzwq %ax, %cl + movzwq %eax, %cl + movzwq %rax, %cl + + movzwq %al, %cx + movzwq %ax, %cx + movzwq %eax, %cx + movzwq %rax, %cx + + movzwq %al, %ecx + movzwq %ax, %ecx + movzwq %eax, %ecx + movzwq %rax, %ecx + + movzwq %al, %rcx + movzwq %ax, %rcx + movzwq %eax, %rcx + movzwq %rax, %rcx + + .p2align 4 --- a/gas/testsuite/gas/i386/noreg16.d +++ b/gas/testsuite/gas/i386/noreg16.d @@ -75,6 +75,10 @@ Disassembly of section .text: *[a-f0-9]+: 8e 07 mov \(%bx\),%es *[a-f0-9]+: a5 movsw %ds:\(%si\),%es:\(%di\) *[a-f0-9]+: 67 a5 movsw %ds:\(%esi\),%es:\(%edi\) + *[a-f0-9]+: 0f be 07 movsbw \(%bx\),%ax + *[a-f0-9]+: 66 0f be 07 movsbl \(%bx\),%eax + *[a-f0-9]+: 0f b6 07 movzbw \(%bx\),%ax + *[a-f0-9]+: 66 0f b6 07 movzbl \(%bx\),%eax *[a-f0-9]+: f7 27 mulw \(%bx\) *[a-f0-9]+: f7 1f negw \(%bx\) *[a-f0-9]+: 0f 1f 07 nopw \(%bx\) --- a/gas/testsuite/gas/i386/noreg16.s +++ b/gas/testsuite/gas/i386/noreg16.s @@ -69,6 +69,10 @@ noreg: mov (%bx), %es movs movs (%esi), %es:(%edi) + movsx (%bx), %ax + movsx (%bx), %eax + movzx (%bx), %ax + movzx (%bx), %eax mul (%bx) neg (%bx) nop (%bx) --- a/gas/testsuite/gas/i386/noreg32.d +++ b/gas/testsuite/gas/i386/noreg32.d @@ -80,6 +80,10 @@ Disassembly of section .text: *[a-f0-9]+: 8e 00 mov \(%eax\),%es *[a-f0-9]+: a5 movsl %ds:\(%esi\),%es:\(%edi\) *[a-f0-9]+: a5 movsl %ds:\(%esi\),%es:\(%edi\) + *[a-f0-9]+: 66 0f be 00 movsbw \(%eax\),%ax + *[a-f0-9]+: 0f be 00 movsbl \(%eax\),%eax + *[a-f0-9]+: 66 0f b6 00 movzbw \(%eax\),%ax + *[a-f0-9]+: 0f b6 00 movzbl \(%eax\),%eax *[a-f0-9]+: f7 20 mull \(%eax\) *[a-f0-9]+: f7 18 negl \(%eax\) *[a-f0-9]+: 0f 1f 00 nopl \(%eax\) --- a/gas/testsuite/gas/i386/noreg32.s +++ b/gas/testsuite/gas/i386/noreg32.s @@ -73,6 +73,10 @@ noreg: mov (%eax), %es movs movs (%esi), %es:(%edi) + movsx (%eax), %ax + movsx (%eax), %eax + movzx (%eax), %ax + movzx (%eax), %eax mul (%eax) neg (%eax) nop (%eax) --- a/gas/testsuite/gas/i386/noreg64.d +++ b/gas/testsuite/gas/i386/noreg64.d @@ -84,6 +84,12 @@ Disassembly of section .text: *[a-f0-9]+: 8e 00 mov \(%rax\),%es *[a-f0-9]+: a5 movsl %ds:\(%rsi\),%es:\(%rdi\) *[a-f0-9]+: a5 movsl %ds:\(%rsi\),%es:\(%rdi\) + *[a-f0-9]+: 66 0f be 00 movsbw \(%rax\),%ax + *[a-f0-9]+: 0f be 00 movsbl \(%rax\),%eax + *[a-f0-9]+: 48 0f be 00 movsbq \(%rax\),%rax + *[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax + *[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax + *[a-f0-9]+: 48 0f b6 00 movzbq \(%rax\),%rax *[a-f0-9]+: f7 20 mull \(%rax\) *[a-f0-9]+: f7 18 negl \(%rax\) *[a-f0-9]+: 0f 1f 00 nopl \(%rax\) --- a/gas/testsuite/gas/i386/noreg64.s +++ b/gas/testsuite/gas/i386/noreg64.s @@ -77,6 +77,12 @@ noreg: mov (%rax), %es movs movs (%rsi), %es:(%rdi) + movsx (%rax), %ax + movsx (%rax), %eax + movsx (%rax), %rax + movzx (%rax), %ax + movzx (%rax), %eax + movzx (%rax), %rax mul (%rax) neg (%rax) nop (%rax) --- a/gas/testsuite/gas/i386/x86_64-intel.d +++ b/gas/testsuite/gas/i386/x86_64-intel.d @@ -173,8 +173,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f bf f0 movsx esi,ax [ ]*[a-f0-9]+: 48 0f bf f0 movsx rsi,ax [ ]*[a-f0-9]+: 48 63 f0 movsxd rsi,eax -[ ]*[a-f0-9]+: 0f be 10 movsx edx,BYTE PTR \[rax\] -[ ]*[a-f0-9]+: 48 0f be 10 movsx rdx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 66 0f be 10 movsx dx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 0f be 10 movsx edx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 48 0f be 10 movsx rdx,BYTE PTR \[rax\] @@ -186,8 +184,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f b6 f0 movzx rsi,al [ ]*[a-f0-9]+: 0f b7 f0 movzx esi,ax [ ]*[a-f0-9]+: 48 0f b7 f0 movzx rsi,ax -[ ]*[a-f0-9]+: 0f b6 10 movzx edx,BYTE PTR \[rax\] -[ ]*[a-f0-9]+: 48 0f b6 10 movzx rdx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 66 0f b6 10 movzx dx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 0f b6 10 movzx edx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 48 0f b6 10 movzx rdx,BYTE PTR \[rax\] @@ -231,8 +227,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 9b df e0 fstsw ax [ ]*[a-f0-9]+: 9b df e0 fstsw ax [ ]*[a-f0-9]+: 66 0f be 00 movsx ax,BYTE PTR \[rax\] -[ ]*[a-f0-9]+: 0f be 00 movsx eax,BYTE PTR \[rax\] -[ ]*[a-f0-9]+: 48 0f be 00 movsx rax,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 66 0f be 10 movsx dx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 0f be 10 movsx edx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 48 0f be 10 movsx rdx,BYTE PTR \[rax\] @@ -241,8 +235,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 63 10 movsxd rdx,DWORD PTR \[rax\] [ ]*[a-f0-9]+: 48 63 00 movsxd rax,DWORD PTR \[rax\] [ ]*[a-f0-9]+: 66 0f b6 00 movzx ax,BYTE PTR \[rax\] -[ ]*[a-f0-9]+: 0f b6 00 movzx eax,BYTE PTR \[rax\] -[ ]*[a-f0-9]+: 48 0f b6 00 movzx rax,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 66 0f b6 10 movzx dx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 0f b6 10 movzx edx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 48 0f b6 10 movzx rdx,BYTE PTR \[rax\] --- a/gas/testsuite/gas/i386/x86_64.d +++ b/gas/testsuite/gas/i386/x86_64.d @@ -173,8 +173,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi [ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi [ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi -[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx -[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx @@ -186,8 +184,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi [ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi [ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi -[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx -[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx @@ -231,8 +227,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 9b df e0 fstsw %ax [ ]*[a-f0-9]+: 9b df e0 fstsw %ax [ ]*[a-f0-9]+: 66 0f be 00 movsbw \(%rax\),%ax -[ ]*[a-f0-9]+: 0f be 00 movsbl \(%rax\),%eax -[ ]*[a-f0-9]+: 48 0f be 00 movsbq \(%rax\),%rax [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx @@ -241,8 +235,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 63 10 movslq \(%rax\),%rdx [ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax [ ]*[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax -[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax -[ ]*[a-f0-9]+: 48 0f b6 00 movzbq \(%rax\),%rax [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx --- a/gas/testsuite/gas/i386/x86_64.s +++ b/gas/testsuite/gas/i386/x86_64.s @@ -208,8 +208,6 @@ cmpxchg16b oword ptr [rax] movsx %ax, %esi movsx %ax, %rsi movsx %eax, %rsi - movsx (%rax), %edx - movsx (%rax), %rdx movsx (%rax), %dx movsbl (%rax), %edx movsbq (%rax), %rdx @@ -222,8 +220,6 @@ cmpxchg16b oword ptr [rax] movzx %al, %rsi movzx %ax, %esi movzx %ax, %rsi - movzx (%rax), %edx - movzx (%rax), %rdx movzx (%rax), %dx movzb (%rax), %edx movzb (%rax), %rdx @@ -277,8 +273,6 @@ cmpxchg16b oword ptr [rax] .att_syntax movsx (%rax),%ax -movsx (%rax),%eax -movsx (%rax),%rax movsxb (%rax), %dx movsxb (%rax), %edx movsxb (%rax), %rdx @@ -287,8 +281,6 @@ movsxw (%rax), %rdx movsxl (%rax), %rdx movsxd (%rax),%rax movzx (%rax),%ax -movzx (%rax),%eax -movzx (%rax),%rax movzxb (%rax), %dx movzxb (%rax), %edx movzxb (%rax), %rdx ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 2/5] x86: move certain MOVSX/MOVZX tests 2020-02-11 10:25 ` [PATCH v5 2/5] x86: move certain MOVSX/MOVZX tests Jan Beulich @ 2020-02-11 11:43 ` H.J. Lu 2020-02-11 11:55 ` Jan Beulich 0 siblings, 1 reply; 26+ messages in thread From: H.J. Lu @ 2020-02-11 11:43 UTC (permalink / raw) To: Jan Beulich; +Cc: binutils On Tue, Feb 11, 2020 at 2:25 AM Jan Beulich <jbeulich@suse.com> wrote: > > Some encodings are about to gain a warning - move them from test cases > not expecting any diagnostics to the new, dedicated ones, to allow > better focus on the actual changes in the subsequent patch. > > The new tests added have some wrong expectations right now, which will > be corrected by the next patch. The test is being added here to make > more visible which cases actually were wrong (and hence get changed), > besides demonstrating that in the vast majority of cases the subsequent > change doesn't alter generated code. > > gas/ > 2020-02-XX Jan Beulich <jbeulich@suse.com> > > * testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s, > testsuite/gas/i386/ilp32/x86-64.s: Move ambiguous operand size > tests ... > * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s, > testsuite/gas/i386/noreg64.s, testsuite/gas/i386/x86_64.s: ... > here. > * testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d > testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d, > testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d, > testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d, > testsuite/gas/i386/noreg64.d, testsuite/gas/i386/x86_64-intel.d, > testsuite/gas/i386/x86_64.d: Adjust expectations. > * testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l, > testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l, > testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New. > * testsuite/gas/i386/i386.exp: Run new tests. Please make a separate patch to address MOVSX/MOVZX. MOVSX and MOVZX should take no suffixes. AT&T syntax is supported if there is no ambiguity. AT&T syntax also supports movsXY and movzXY. We should also improve MOVSX/MOVZX documentation. -- H.J. ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 2/5] x86: move certain MOVSX/MOVZX tests 2020-02-11 11:43 ` H.J. Lu @ 2020-02-11 11:55 ` Jan Beulich 2020-02-11 12:20 ` H.J. Lu 0 siblings, 1 reply; 26+ messages in thread From: Jan Beulich @ 2020-02-11 11:55 UTC (permalink / raw) To: H.J. Lu; +Cc: binutils On 11.02.2020 12:42, H.J. Lu wrote: > On Tue, Feb 11, 2020 at 2:25 AM Jan Beulich <jbeulich@suse.com> wrote: >> >> Some encodings are about to gain a warning - move them from test cases >> not expecting any diagnostics to the new, dedicated ones, to allow >> better focus on the actual changes in the subsequent patch. >> >> The new tests added have some wrong expectations right now, which will >> be corrected by the next patch. The test is being added here to make >> more visible which cases actually were wrong (and hence get changed), >> besides demonstrating that in the vast majority of cases the subsequent >> change doesn't alter generated code. >> >> gas/ >> 2020-02-XX Jan Beulich <jbeulich@suse.com> >> >> * testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s, >> testsuite/gas/i386/ilp32/x86-64.s: Move ambiguous operand size >> tests ... >> * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s, >> testsuite/gas/i386/noreg64.s, testsuite/gas/i386/x86_64.s: ... >> here. >> * testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d >> testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d, >> testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d, >> testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d, >> testsuite/gas/i386/noreg64.d, testsuite/gas/i386/x86_64-intel.d, >> testsuite/gas/i386/x86_64.d: Adjust expectations. >> * testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l, >> testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l, >> testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New. >> * testsuite/gas/i386/i386.exp: Run new tests. > > Please make a separate patch to address MOVSX/MOVZX. I don't understand what you mean here. This patch simply documents the status quo, to make it (much) easier to see what the next patch actually adjusts. It doesn't "address" anything. If, for the purpose of committing, you'd like to see both patches folded - fine by me. But only then, not any earlier. > MOVSX and MOVZX > should take no suffixes. AT&T syntax is supported if there is no > ambiguity. AT&T > syntax also supports movsXY and movzXY. Please could you clarify what specifically you'd like to see changed, at the very least by pointing out one case each where you think I'm moving in the wrong direction (presumably in the next patch really)? I'm afraid your response isn't such that I can derive from it what exactly you want. > We should also improve MOVSX/MOVZX documentation. Probably, but not here and now. Jan ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 2/5] x86: move certain MOVSX/MOVZX tests 2020-02-11 11:55 ` Jan Beulich @ 2020-02-11 12:20 ` H.J. Lu 2020-02-11 12:58 ` Jan Beulich 0 siblings, 1 reply; 26+ messages in thread From: H.J. Lu @ 2020-02-11 12:20 UTC (permalink / raw) To: Jan Beulich; +Cc: binutils On Tue, Feb 11, 2020 at 3:55 AM Jan Beulich <jbeulich@suse.com> wrote: > > On 11.02.2020 12:42, H.J. Lu wrote: > > On Tue, Feb 11, 2020 at 2:25 AM Jan Beulich <jbeulich@suse.com> wrote: > >> > >> Some encodings are about to gain a warning - move them from test cases > >> not expecting any diagnostics to the new, dedicated ones, to allow > >> better focus on the actual changes in the subsequent patch. > >> > >> The new tests added have some wrong expectations right now, which will > >> be corrected by the next patch. The test is being added here to make > >> more visible which cases actually were wrong (and hence get changed), > >> besides demonstrating that in the vast majority of cases the subsequent > >> change doesn't alter generated code. > >> > >> gas/ > >> 2020-02-XX Jan Beulich <jbeulich@suse.com> > >> > >> * testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s, > >> testsuite/gas/i386/ilp32/x86-64.s: Move ambiguous operand size > >> tests ... > >> * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s, > >> testsuite/gas/i386/noreg64.s, testsuite/gas/i386/x86_64.s: ... > >> here. > >> * testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d > >> testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d, > >> testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d, > >> testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d, > >> testsuite/gas/i386/noreg64.d, testsuite/gas/i386/x86_64-intel.d, > >> testsuite/gas/i386/x86_64.d: Adjust expectations. > >> * testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l, > >> testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l, > >> testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New. > >> * testsuite/gas/i386/i386.exp: Run new tests. > > > > Please make a separate patch to address MOVSX/MOVZX. > > I don't understand what you mean here. This patch simply documents the > status quo, to make it (much) easier to see what the next patch > actually adjusts. It doesn't "address" anything. If, for the purpose > of committing, you'd like to see both patches folded - fine by me. But > only then, not any earlier. > > > MOVSX and MOVZX > > should take no suffixes. AT&T syntax is supported if there is no > > ambiguity. AT&T > > syntax also supports movsXY and movzXY. > > Please could you clarify what specifically you'd like to see changed, > at the very least by pointing out one case each where you think I'm > moving in the wrong direction (presumably in the next patch really)? > I'm afraid your response isn't such that I can derive from it what > exactly you want. We support movsx %ax, %ecx movzx %ax, %ecx movswl %ax, %ecx movzwl %ax, %ecx We disallow movsxw %ax, %ecx movzxw %ax, %ecx > > We should also improve MOVSX/MOVZX documentation. > > Probably, but not here and now. > > Jan -- H.J. ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 2/5] x86: move certain MOVSX/MOVZX tests 2020-02-11 12:20 ` H.J. Lu @ 2020-02-11 12:58 ` Jan Beulich 2020-02-11 13:02 ` H.J. Lu 0 siblings, 1 reply; 26+ messages in thread From: Jan Beulich @ 2020-02-11 12:58 UTC (permalink / raw) To: H.J. Lu; +Cc: binutils On 11.02.2020 13:19, H.J. Lu wrote: > On Tue, Feb 11, 2020 at 3:55 AM Jan Beulich <jbeulich@suse.com> wrote: >> >> On 11.02.2020 12:42, H.J. Lu wrote: >>> On Tue, Feb 11, 2020 at 2:25 AM Jan Beulich <jbeulich@suse.com> wrote: >>>> >>>> Some encodings are about to gain a warning - move them from test cases >>>> not expecting any diagnostics to the new, dedicated ones, to allow >>>> better focus on the actual changes in the subsequent patch. >>>> >>>> The new tests added have some wrong expectations right now, which will >>>> be corrected by the next patch. The test is being added here to make >>>> more visible which cases actually were wrong (and hence get changed), >>>> besides demonstrating that in the vast majority of cases the subsequent >>>> change doesn't alter generated code. >>>> >>>> gas/ >>>> 2020-02-XX Jan Beulich <jbeulich@suse.com> >>>> >>>> * testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s, >>>> testsuite/gas/i386/ilp32/x86-64.s: Move ambiguous operand size >>>> tests ... >>>> * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s, >>>> testsuite/gas/i386/noreg64.s, testsuite/gas/i386/x86_64.s: ... >>>> here. >>>> * testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d >>>> testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d, >>>> testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d, >>>> testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d, >>>> testsuite/gas/i386/noreg64.d, testsuite/gas/i386/x86_64-intel.d, >>>> testsuite/gas/i386/x86_64.d: Adjust expectations. >>>> * testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l, >>>> testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l, >>>> testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New. >>>> * testsuite/gas/i386/i386.exp: Run new tests. >>> >>> Please make a separate patch to address MOVSX/MOVZX. >> >> I don't understand what you mean here. This patch simply documents the >> status quo, to make it (much) easier to see what the next patch >> actually adjusts. It doesn't "address" anything. If, for the purpose >> of committing, you'd like to see both patches folded - fine by me. But >> only then, not any earlier. >> >>> MOVSX and MOVZX >>> should take no suffixes. AT&T syntax is supported if there is no >>> ambiguity. AT&T >>> syntax also supports movsXY and movzXY. >> >> Please could you clarify what specifically you'd like to see changed, >> at the very least by pointing out one case each where you think I'm >> moving in the wrong direction (presumably in the next patch really)? >> I'm afraid your response isn't such that I can derive from it what >> exactly you want. > > We support > > movsx %ax, %ecx > movzx %ax, %ecx > movswl %ax, %ecx > movzwl %ax, %ecx > > We disallow > > movsxw %ax, %ecx > movzxw %ax, %ecx We don't (as this patch demonstrates, along with pre-existing tests, unless you mean once again to have an inconsistency between insns with all register operands and similar ones with e memory source), and if you want it to be this way, then please do so yourself, but please also only on top of my changes, so I won't need to re-base _yet_ another time. Just to repeat my request from an earlier version: Please take the time to check what this patch does (documenting _just_ current behavior), and what the next patch changes behavior-wise. And please comment on that following patch in case you think it makes a change that it shouldn't make, i.e. in particular one which isn't in line with other similar behavior. Jan ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 2/5] x86: move certain MOVSX/MOVZX tests 2020-02-11 12:58 ` Jan Beulich @ 2020-02-11 13:02 ` H.J. Lu 2020-02-11 13:04 ` Jan Beulich 0 siblings, 1 reply; 26+ messages in thread From: H.J. Lu @ 2020-02-11 13:02 UTC (permalink / raw) To: Jan Beulich; +Cc: binutils On Tue, Feb 11, 2020 at 4:58 AM Jan Beulich <jbeulich@suse.com> wrote: > > On 11.02.2020 13:19, H.J. Lu wrote: > > On Tue, Feb 11, 2020 at 3:55 AM Jan Beulich <jbeulich@suse.com> wrote: > >> > >> On 11.02.2020 12:42, H.J. Lu wrote: > >>> On Tue, Feb 11, 2020 at 2:25 AM Jan Beulich <jbeulich@suse.com> wrote: > >>>> > >>>> Some encodings are about to gain a warning - move them from test cases > >>>> not expecting any diagnostics to the new, dedicated ones, to allow > >>>> better focus on the actual changes in the subsequent patch. > >>>> > >>>> The new tests added have some wrong expectations right now, which will > >>>> be corrected by the next patch. The test is being added here to make > >>>> more visible which cases actually were wrong (and hence get changed), > >>>> besides demonstrating that in the vast majority of cases the subsequent > >>>> change doesn't alter generated code. > >>>> > >>>> gas/ > >>>> 2020-02-XX Jan Beulich <jbeulich@suse.com> > >>>> > >>>> * testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s, > >>>> testsuite/gas/i386/ilp32/x86-64.s: Move ambiguous operand size > >>>> tests ... > >>>> * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s, > >>>> testsuite/gas/i386/noreg64.s, testsuite/gas/i386/x86_64.s: ... > >>>> here. > >>>> * testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d > >>>> testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d, > >>>> testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d, > >>>> testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d, > >>>> testsuite/gas/i386/noreg64.d, testsuite/gas/i386/x86_64-intel.d, > >>>> testsuite/gas/i386/x86_64.d: Adjust expectations. > >>>> * testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l, > >>>> testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l, > >>>> testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New. > >>>> * testsuite/gas/i386/i386.exp: Run new tests. > >>> > >>> Please make a separate patch to address MOVSX/MOVZX. > >> > >> I don't understand what you mean here. This patch simply documents the > >> status quo, to make it (much) easier to see what the next patch > >> actually adjusts. It doesn't "address" anything. If, for the purpose > >> of committing, you'd like to see both patches folded - fine by me. But > >> only then, not any earlier. > >> > >>> MOVSX and MOVZX > >>> should take no suffixes. AT&T syntax is supported if there is no > >>> ambiguity. AT&T > >>> syntax also supports movsXY and movzXY. > >> > >> Please could you clarify what specifically you'd like to see changed, > >> at the very least by pointing out one case each where you think I'm > >> moving in the wrong direction (presumably in the next patch really)? > >> I'm afraid your response isn't such that I can derive from it what > >> exactly you want. > > > > We support > > > > movsx %ax, %ecx > > movzx %ax, %ecx > > movswl %ax, %ecx > > movzwl %ax, %ecx > > > > We disallow > > > > movsxw %ax, %ecx > > movzxw %ax, %ecx > > We don't (as this patch demonstrates, along with pre-existing tests, > unless you mean once again to have an inconsistency between insns > with all register operands and similar ones with e memory source), > and if you want it to be this way, then please do so yourself, but I will do it. > please also only on top of my changes, so I won't need to re-base Which changes of yours are you referring to? > _yet_ another time. > > Just to repeat my request from an earlier version: Please take the > time to check what this patch does (documenting _just_ current > behavior), and what the next patch changes behavior-wise. And > please comment on that following patch in case you think it makes > a change that it shouldn't make, i.e. in particular one which > isn't in line with other similar behavior. > > Jan -- H.J. ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 2/5] x86: move certain MOVSX/MOVZX tests 2020-02-11 13:02 ` H.J. Lu @ 2020-02-11 13:04 ` Jan Beulich 2020-02-11 13:07 ` H.J. Lu 0 siblings, 1 reply; 26+ messages in thread From: Jan Beulich @ 2020-02-11 13:04 UTC (permalink / raw) To: H.J. Lu; +Cc: binutils On 11.02.2020 14:01, H.J. Lu wrote: > On Tue, Feb 11, 2020 at 4:58 AM Jan Beulich <jbeulich@suse.com> wrote: >> >> On 11.02.2020 13:19, H.J. Lu wrote: >>> On Tue, Feb 11, 2020 at 3:55 AM Jan Beulich <jbeulich@suse.com> wrote: >>>> >>>> On 11.02.2020 12:42, H.J. Lu wrote: >>>>> On Tue, Feb 11, 2020 at 2:25 AM Jan Beulich <jbeulich@suse.com> wrote: >>>>>> >>>>>> Some encodings are about to gain a warning - move them from test cases >>>>>> not expecting any diagnostics to the new, dedicated ones, to allow >>>>>> better focus on the actual changes in the subsequent patch. >>>>>> >>>>>> The new tests added have some wrong expectations right now, which will >>>>>> be corrected by the next patch. The test is being added here to make >>>>>> more visible which cases actually were wrong (and hence get changed), >>>>>> besides demonstrating that in the vast majority of cases the subsequent >>>>>> change doesn't alter generated code. >>>>>> >>>>>> gas/ >>>>>> 2020-02-XX Jan Beulich <jbeulich@suse.com> >>>>>> >>>>>> * testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s, >>>>>> testsuite/gas/i386/ilp32/x86-64.s: Move ambiguous operand size >>>>>> tests ... >>>>>> * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s, >>>>>> testsuite/gas/i386/noreg64.s, testsuite/gas/i386/x86_64.s: ... >>>>>> here. >>>>>> * testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d >>>>>> testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d, >>>>>> testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d, >>>>>> testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d, >>>>>> testsuite/gas/i386/noreg64.d, testsuite/gas/i386/x86_64-intel.d, >>>>>> testsuite/gas/i386/x86_64.d: Adjust expectations. >>>>>> * testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l, >>>>>> testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l, >>>>>> testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New. >>>>>> * testsuite/gas/i386/i386.exp: Run new tests. >>>>> >>>>> Please make a separate patch to address MOVSX/MOVZX. >>>> >>>> I don't understand what you mean here. This patch simply documents the >>>> status quo, to make it (much) easier to see what the next patch >>>> actually adjusts. It doesn't "address" anything. If, for the purpose >>>> of committing, you'd like to see both patches folded - fine by me. But >>>> only then, not any earlier. >>>> >>>>> MOVSX and MOVZX >>>>> should take no suffixes. AT&T syntax is supported if there is no >>>>> ambiguity. AT&T >>>>> syntax also supports movsXY and movzXY. >>>> >>>> Please could you clarify what specifically you'd like to see changed, >>>> at the very least by pointing out one case each where you think I'm >>>> moving in the wrong direction (presumably in the next patch really)? >>>> I'm afraid your response isn't such that I can derive from it what >>>> exactly you want. >>> >>> We support >>> >>> movsx %ax, %ecx >>> movzx %ax, %ecx >>> movswl %ax, %ecx >>> movzwl %ax, %ecx >>> >>> We disallow >>> >>> movsxw %ax, %ecx >>> movzxw %ax, %ecx >> >> We don't (as this patch demonstrates, along with pre-existing tests, >> unless you mean once again to have an inconsistency between insns >> with all register operands and similar ones with e memory source), >> and if you want it to be this way, then please do so yourself, but > > I will do it. > >> please also only on top of my changes, so I won't need to re-base > > Which changes of yours are you referring to? This patch and the subsequent one. Jan >> _yet_ another time. >> >> Just to repeat my request from an earlier version: Please take the >> time to check what this patch does (documenting _just_ current >> behavior), and what the next patch changes behavior-wise. And >> please comment on that following patch in case you think it makes >> a change that it shouldn't make, i.e. in particular one which >> isn't in line with other similar behavior. >> >> Jan > > > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 2/5] x86: move certain MOVSX/MOVZX tests 2020-02-11 13:04 ` Jan Beulich @ 2020-02-11 13:07 ` H.J. Lu 2020-02-11 16:45 ` Jan Beulich 0 siblings, 1 reply; 26+ messages in thread From: H.J. Lu @ 2020-02-11 13:07 UTC (permalink / raw) To: Jan Beulich; +Cc: binutils On Tue, Feb 11, 2020 at 5:04 AM Jan Beulich <jbeulich@suse.com> wrote: > > On 11.02.2020 14:01, H.J. Lu wrote: > > On Tue, Feb 11, 2020 at 4:58 AM Jan Beulich <jbeulich@suse.com> wrote: > >> > >> On 11.02.2020 13:19, H.J. Lu wrote: > >>> On Tue, Feb 11, 2020 at 3:55 AM Jan Beulich <jbeulich@suse.com> wrote: > >>>> > >>>> On 11.02.2020 12:42, H.J. Lu wrote: > >>>>> On Tue, Feb 11, 2020 at 2:25 AM Jan Beulich <jbeulich@suse.com> wrote: > >>>>>> > >>>>>> Some encodings are about to gain a warning - move them from test cases > >>>>>> not expecting any diagnostics to the new, dedicated ones, to allow > >>>>>> better focus on the actual changes in the subsequent patch. > >>>>>> > >>>>>> The new tests added have some wrong expectations right now, which will > >>>>>> be corrected by the next patch. The test is being added here to make > >>>>>> more visible which cases actually were wrong (and hence get changed), > >>>>>> besides demonstrating that in the vast majority of cases the subsequent > >>>>>> change doesn't alter generated code. > >>>>>> > >>>>>> gas/ > >>>>>> 2020-02-XX Jan Beulich <jbeulich@suse.com> > >>>>>> > >>>>>> * testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s, > >>>>>> testsuite/gas/i386/ilp32/x86-64.s: Move ambiguous operand size > >>>>>> tests ... > >>>>>> * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s, > >>>>>> testsuite/gas/i386/noreg64.s, testsuite/gas/i386/x86_64.s: ... > >>>>>> here. > >>>>>> * testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d > >>>>>> testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d, > >>>>>> testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d, > >>>>>> testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d, > >>>>>> testsuite/gas/i386/noreg64.d, testsuite/gas/i386/x86_64-intel.d, > >>>>>> testsuite/gas/i386/x86_64.d: Adjust expectations. > >>>>>> * testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l, > >>>>>> testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l, > >>>>>> testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New. > >>>>>> * testsuite/gas/i386/i386.exp: Run new tests. > >>>>> > >>>>> Please make a separate patch to address MOVSX/MOVZX. > >>>> > >>>> I don't understand what you mean here. This patch simply documents the > >>>> status quo, to make it (much) easier to see what the next patch > >>>> actually adjusts. It doesn't "address" anything. If, for the purpose > >>>> of committing, you'd like to see both patches folded - fine by me. But > >>>> only then, not any earlier. > >>>> > >>>>> MOVSX and MOVZX > >>>>> should take no suffixes. AT&T syntax is supported if there is no > >>>>> ambiguity. AT&T > >>>>> syntax also supports movsXY and movzXY. > >>>> > >>>> Please could you clarify what specifically you'd like to see changed, > >>>> at the very least by pointing out one case each where you think I'm > >>>> moving in the wrong direction (presumably in the next patch really)? > >>>> I'm afraid your response isn't such that I can derive from it what > >>>> exactly you want. > >>> > >>> We support > >>> > >>> movsx %ax, %ecx > >>> movzx %ax, %ecx > >>> movswl %ax, %ecx > >>> movzwl %ax, %ecx > >>> > >>> We disallow > >>> > >>> movsxw %ax, %ecx > >>> movzxw %ax, %ecx > >> > >> We don't (as this patch demonstrates, along with pre-existing tests, > >> unless you mean once again to have an inconsistency between insns > >> with all register operands and similar ones with e memory source), > >> and if you want it to be this way, then please do so yourself, but > > > > I will do it. > > > >> please also only on top of my changes, so I won't need to re-base > > > > Which changes of yours are you referring to? > > This patch and the subsequent one. > Both changes won't be necessary after my changes. -- H.J. ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 2/5] x86: move certain MOVSX/MOVZX tests 2020-02-11 13:07 ` H.J. Lu @ 2020-02-11 16:45 ` Jan Beulich 2020-02-11 17:04 ` H.J. Lu 0 siblings, 1 reply; 26+ messages in thread From: Jan Beulich @ 2020-02-11 16:45 UTC (permalink / raw) To: H.J. Lu; +Cc: binutils On 11.02.2020 14:07, H.J. Lu wrote: > On Tue, Feb 11, 2020 at 5:04 AM Jan Beulich <jbeulich@suse.com> wrote: >> >> On 11.02.2020 14:01, H.J. Lu wrote: >>> On Tue, Feb 11, 2020 at 4:58 AM Jan Beulich <jbeulich@suse.com> wrote: >>>> >>>> On 11.02.2020 13:19, H.J. Lu wrote: >>>>> On Tue, Feb 11, 2020 at 3:55 AM Jan Beulich <jbeulich@suse.com> wrote: >>>>>> >>>>>> On 11.02.2020 12:42, H.J. Lu wrote: >>>>>>> On Tue, Feb 11, 2020 at 2:25 AM Jan Beulich <jbeulich@suse.com> wrote: >>>>>>>> >>>>>>>> Some encodings are about to gain a warning - move them from test cases >>>>>>>> not expecting any diagnostics to the new, dedicated ones, to allow >>>>>>>> better focus on the actual changes in the subsequent patch. >>>>>>>> >>>>>>>> The new tests added have some wrong expectations right now, which will >>>>>>>> be corrected by the next patch. The test is being added here to make >>>>>>>> more visible which cases actually were wrong (and hence get changed), >>>>>>>> besides demonstrating that in the vast majority of cases the subsequent >>>>>>>> change doesn't alter generated code. >>>>>>>> >>>>>>>> gas/ >>>>>>>> 2020-02-XX Jan Beulich <jbeulich@suse.com> >>>>>>>> >>>>>>>> * testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s, >>>>>>>> testsuite/gas/i386/ilp32/x86-64.s: Move ambiguous operand size >>>>>>>> tests ... >>>>>>>> * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s, >>>>>>>> testsuite/gas/i386/noreg64.s, testsuite/gas/i386/x86_64.s: ... >>>>>>>> here. >>>>>>>> * testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d >>>>>>>> testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d, >>>>>>>> testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d, >>>>>>>> testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d, >>>>>>>> testsuite/gas/i386/noreg64.d, testsuite/gas/i386/x86_64-intel.d, >>>>>>>> testsuite/gas/i386/x86_64.d: Adjust expectations. >>>>>>>> * testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l, >>>>>>>> testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l, >>>>>>>> testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New. >>>>>>>> * testsuite/gas/i386/i386.exp: Run new tests. >>>>>>> >>>>>>> Please make a separate patch to address MOVSX/MOVZX. >>>>>> >>>>>> I don't understand what you mean here. This patch simply documents the >>>>>> status quo, to make it (much) easier to see what the next patch >>>>>> actually adjusts. It doesn't "address" anything. If, for the purpose >>>>>> of committing, you'd like to see both patches folded - fine by me. But >>>>>> only then, not any earlier. >>>>>> >>>>>>> MOVSX and MOVZX >>>>>>> should take no suffixes. AT&T syntax is supported if there is no >>>>>>> ambiguity. AT&T >>>>>>> syntax also supports movsXY and movzXY. >>>>>> >>>>>> Please could you clarify what specifically you'd like to see changed, >>>>>> at the very least by pointing out one case each where you think I'm >>>>>> moving in the wrong direction (presumably in the next patch really)? >>>>>> I'm afraid your response isn't such that I can derive from it what >>>>>> exactly you want. >>>>> >>>>> We support >>>>> >>>>> movsx %ax, %ecx >>>>> movzx %ax, %ecx >>>>> movswl %ax, %ecx >>>>> movzwl %ax, %ecx >>>>> >>>>> We disallow >>>>> >>>>> movsxw %ax, %ecx >>>>> movzxw %ax, %ecx >>>> >>>> We don't (as this patch demonstrates, along with pre-existing tests, >>>> unless you mean once again to have an inconsistency between insns >>>> with all register operands and similar ones with e memory source), >>>> and if you want it to be this way, then please do so yourself, but >>> >>> I will do it. >>> >>>> please also only on top of my changes, so I won't need to re-base >>> >>> Which changes of yours are you referring to? >> >> This patch and the subsequent one. >> > > Both changes won't be necessary after my changes. I'm confused. What you want to deal with is - afaict - orthogonal to what the next patch in the series here does. Jan ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 2/5] x86: move certain MOVSX/MOVZX tests 2020-02-11 16:45 ` Jan Beulich @ 2020-02-11 17:04 ` H.J. Lu 2020-02-11 20:12 ` [PATCH] x86: Remove movsx/movzx with memory operand from AT&T syntax H.J. Lu 0 siblings, 1 reply; 26+ messages in thread From: H.J. Lu @ 2020-02-11 17:04 UTC (permalink / raw) To: Jan Beulich; +Cc: binutils On Tue, Feb 11, 2020 at 8:45 AM Jan Beulich <jbeulich@suse.com> wrote: > > On 11.02.2020 14:07, H.J. Lu wrote: > > On Tue, Feb 11, 2020 at 5:04 AM Jan Beulich <jbeulich@suse.com> wrote: > >> > >> On 11.02.2020 14:01, H.J. Lu wrote: > >>> On Tue, Feb 11, 2020 at 4:58 AM Jan Beulich <jbeulich@suse.com> wrote: > >>>> > >>>> On 11.02.2020 13:19, H.J. Lu wrote: > >>>>> On Tue, Feb 11, 2020 at 3:55 AM Jan Beulich <jbeulich@suse.com> wrote: > >>>>>> > >>>>>> On 11.02.2020 12:42, H.J. Lu wrote: > >>>>>>> On Tue, Feb 11, 2020 at 2:25 AM Jan Beulich <jbeulich@suse.com> wrote: > >>>>>>>> > >>>>>>>> Some encodings are about to gain a warning - move them from test cases > >>>>>>>> not expecting any diagnostics to the new, dedicated ones, to allow > >>>>>>>> better focus on the actual changes in the subsequent patch. > >>>>>>>> > >>>>>>>> The new tests added have some wrong expectations right now, which will > >>>>>>>> be corrected by the next patch. The test is being added here to make > >>>>>>>> more visible which cases actually were wrong (and hence get changed), > >>>>>>>> besides demonstrating that in the vast majority of cases the subsequent > >>>>>>>> change doesn't alter generated code. > >>>>>>>> > >>>>>>>> gas/ > >>>>>>>> 2020-02-XX Jan Beulich <jbeulich@suse.com> > >>>>>>>> > >>>>>>>> * testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s, > >>>>>>>> testsuite/gas/i386/ilp32/x86-64.s: Move ambiguous operand size > >>>>>>>> tests ... > >>>>>>>> * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s, > >>>>>>>> testsuite/gas/i386/noreg64.s, testsuite/gas/i386/x86_64.s: ... > >>>>>>>> here. > >>>>>>>> * testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d > >>>>>>>> testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d, > >>>>>>>> testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d, > >>>>>>>> testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d, > >>>>>>>> testsuite/gas/i386/noreg64.d, testsuite/gas/i386/x86_64-intel.d, > >>>>>>>> testsuite/gas/i386/x86_64.d: Adjust expectations. > >>>>>>>> * testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l, > >>>>>>>> testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l, > >>>>>>>> testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New. > >>>>>>>> * testsuite/gas/i386/i386.exp: Run new tests. > >>>>>>> > >>>>>>> Please make a separate patch to address MOVSX/MOVZX. > >>>>>> > >>>>>> I don't understand what you mean here. This patch simply documents the > >>>>>> status quo, to make it (much) easier to see what the next patch > >>>>>> actually adjusts. It doesn't "address" anything. If, for the purpose > >>>>>> of committing, you'd like to see both patches folded - fine by me. But > >>>>>> only then, not any earlier. > >>>>>> > >>>>>>> MOVSX and MOVZX > >>>>>>> should take no suffixes. AT&T syntax is supported if there is no > >>>>>>> ambiguity. AT&T > >>>>>>> syntax also supports movsXY and movzXY. > >>>>>> > >>>>>> Please could you clarify what specifically you'd like to see changed, > >>>>>> at the very least by pointing out one case each where you think I'm > >>>>>> moving in the wrong direction (presumably in the next patch really)? > >>>>>> I'm afraid your response isn't such that I can derive from it what > >>>>>> exactly you want. > >>>>> > >>>>> We support > >>>>> > >>>>> movsx %ax, %ecx > >>>>> movzx %ax, %ecx > >>>>> movswl %ax, %ecx > >>>>> movzwl %ax, %ecx > >>>>> > >>>>> We disallow > >>>>> > >>>>> movsxw %ax, %ecx > >>>>> movzxw %ax, %ecx > >>>> > >>>> We don't (as this patch demonstrates, along with pre-existing tests, > >>>> unless you mean once again to have an inconsistency between insns > >>>> with all register operands and similar ones with e memory source), > >>>> and if you want it to be this way, then please do so yourself, but > >>> > >>> I will do it. > >>> > >>>> please also only on top of my changes, so I won't need to re-base > >>> > >>> Which changes of yours are you referring to? > >> > >> This patch and the subsequent one. > >> > > > > Both changes won't be necessary after my changes. > > I'm confused. What you want to deal with is - afaict - orthogonal to > what the next patch in the series here does. > You will see what I mean when I post my patch for review. -- H.J. ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH] x86: Remove movsx/movzx with memory operand from AT&T syntax 2020-02-11 17:04 ` H.J. Lu @ 2020-02-11 20:12 ` H.J. Lu 2020-02-11 23:34 ` H.J. Lu 0 siblings, 1 reply; 26+ messages in thread From: H.J. Lu @ 2020-02-11 20:12 UTC (permalink / raw) To: Jan Beulich; +Cc: binutils [-- Attachment #1: Type: text/plain, Size: 5092 bytes --] On Tue, Feb 11, 2020 at 9:04 AM H.J. Lu <hjl.tools@gmail.com> wrote: > > On Tue, Feb 11, 2020 at 8:45 AM Jan Beulich <jbeulich@suse.com> wrote: > > > > On 11.02.2020 14:07, H.J. Lu wrote: > > > On Tue, Feb 11, 2020 at 5:04 AM Jan Beulich <jbeulich@suse.com> wrote: > > >> > > >> On 11.02.2020 14:01, H.J. Lu wrote: > > >>> On Tue, Feb 11, 2020 at 4:58 AM Jan Beulich <jbeulich@suse.com> wrote: > > >>>> > > >>>> On 11.02.2020 13:19, H.J. Lu wrote: > > >>>>> On Tue, Feb 11, 2020 at 3:55 AM Jan Beulich <jbeulich@suse.com> wrote: > > >>>>>> > > >>>>>> On 11.02.2020 12:42, H.J. Lu wrote: > > >>>>>>> On Tue, Feb 11, 2020 at 2:25 AM Jan Beulich <jbeulich@suse.com> wrote: > > >>>>>>>> > > >>>>>>>> Some encodings are about to gain a warning - move them from test cases > > >>>>>>>> not expecting any diagnostics to the new, dedicated ones, to allow > > >>>>>>>> better focus on the actual changes in the subsequent patch. > > >>>>>>>> > > >>>>>>>> The new tests added have some wrong expectations right now, which will > > >>>>>>>> be corrected by the next patch. The test is being added here to make > > >>>>>>>> more visible which cases actually were wrong (and hence get changed), > > >>>>>>>> besides demonstrating that in the vast majority of cases the subsequent > > >>>>>>>> change doesn't alter generated code. > > >>>>>>>> > > >>>>>>>> gas/ > > >>>>>>>> 2020-02-XX Jan Beulich <jbeulich@suse.com> > > >>>>>>>> > > >>>>>>>> * testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s, > > >>>>>>>> testsuite/gas/i386/ilp32/x86-64.s: Move ambiguous operand size > > >>>>>>>> tests ... > > >>>>>>>> * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s, > > >>>>>>>> testsuite/gas/i386/noreg64.s, testsuite/gas/i386/x86_64.s: ... > > >>>>>>>> here. > > >>>>>>>> * testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d > > >>>>>>>> testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d, > > >>>>>>>> testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d, > > >>>>>>>> testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d, > > >>>>>>>> testsuite/gas/i386/noreg64.d, testsuite/gas/i386/x86_64-intel.d, > > >>>>>>>> testsuite/gas/i386/x86_64.d: Adjust expectations. > > >>>>>>>> * testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l, > > >>>>>>>> testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l, > > >>>>>>>> testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New. > > >>>>>>>> * testsuite/gas/i386/i386.exp: Run new tests. > > >>>>>>> > > >>>>>>> Please make a separate patch to address MOVSX/MOVZX. > > >>>>>> > > >>>>>> I don't understand what you mean here. This patch simply documents the > > >>>>>> status quo, to make it (much) easier to see what the next patch > > >>>>>> actually adjusts. It doesn't "address" anything. If, for the purpose > > >>>>>> of committing, you'd like to see both patches folded - fine by me. But > > >>>>>> only then, not any earlier. > > >>>>>> > > >>>>>>> MOVSX and MOVZX > > >>>>>>> should take no suffixes. AT&T syntax is supported if there is no > > >>>>>>> ambiguity. AT&T > > >>>>>>> syntax also supports movsXY and movzXY. > > >>>>>> > > >>>>>> Please could you clarify what specifically you'd like to see changed, > > >>>>>> at the very least by pointing out one case each where you think I'm > > >>>>>> moving in the wrong direction (presumably in the next patch really)? > > >>>>>> I'm afraid your response isn't such that I can derive from it what > > >>>>>> exactly you want. > > >>>>> > > >>>>> We support > > >>>>> > > >>>>> movsx %ax, %ecx > > >>>>> movzx %ax, %ecx > > >>>>> movswl %ax, %ecx > > >>>>> movzwl %ax, %ecx > > >>>>> > > >>>>> We disallow > > >>>>> > > >>>>> movsxw %ax, %ecx > > >>>>> movzxw %ax, %ecx > > >>>> > > >>>> We don't (as this patch demonstrates, along with pre-existing tests, > > >>>> unless you mean once again to have an inconsistency between insns > > >>>> with all register operands and similar ones with e memory source), > > >>>> and if you want it to be this way, then please do so yourself, but > > >>> > > >>> I will do it. > > >>> > > >>>> please also only on top of my changes, so I won't need to re-base > > >>> > > >>> Which changes of yours are you referring to? > > >> > > >> This patch and the subsequent one. > > >> > > > > > > Both changes won't be necessary after my changes. > > > > I'm confused. What you want to deal with is - afaict - orthogonal to > > what the next patch in the series here does. > > > > You will see what I mean when I post my patch for review. > AT&T syntax requires suffix to specify memory operand size. Since movsx and movzx can have different memory operand sizes with the same destination register, this patch removes movsx and movzx with memory operand from AT&T syntax. Since AT&T syntax uses different mnemonics for movsx and movzx, this change should have little impact on assembly sources. Tested with Linux kernel 5.5.3 for x86-64 and glibc 2.31 for i686 and x86-64. -- H.J. [-- Attachment #2: 0001-x86-Remove-movsx-movzx-with-memory-operand-from-AT-T.patch --] [-- Type: application/x-patch, Size: 42162 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH] x86: Remove movsx/movzx with memory operand from AT&T syntax 2020-02-11 20:12 ` [PATCH] x86: Remove movsx/movzx with memory operand from AT&T syntax H.J. Lu @ 2020-02-11 23:34 ` H.J. Lu 2020-02-11 23:52 ` H.J. Lu 0 siblings, 1 reply; 26+ messages in thread From: H.J. Lu @ 2020-02-11 23:34 UTC (permalink / raw) To: Jan Beulich; +Cc: binutils [-- Attachment #1: Type: text/plain, Size: 5464 bytes --] On Tue, Feb 11, 2020 at 12:11 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > On Tue, Feb 11, 2020 at 9:04 AM H.J. Lu <hjl.tools@gmail.com> wrote: > > > > On Tue, Feb 11, 2020 at 8:45 AM Jan Beulich <jbeulich@suse.com> wrote: > > > > > > On 11.02.2020 14:07, H.J. Lu wrote: > > > > On Tue, Feb 11, 2020 at 5:04 AM Jan Beulich <jbeulich@suse.com> wrote: > > > >> > > > >> On 11.02.2020 14:01, H.J. Lu wrote: > > > >>> On Tue, Feb 11, 2020 at 4:58 AM Jan Beulich <jbeulich@suse.com> wrote: > > > >>>> > > > >>>> On 11.02.2020 13:19, H.J. Lu wrote: > > > >>>>> On Tue, Feb 11, 2020 at 3:55 AM Jan Beulich <jbeulich@suse.com> wrote: > > > >>>>>> > > > >>>>>> On 11.02.2020 12:42, H.J. Lu wrote: > > > >>>>>>> On Tue, Feb 11, 2020 at 2:25 AM Jan Beulich <jbeulich@suse.com> wrote: > > > >>>>>>>> > > > >>>>>>>> Some encodings are about to gain a warning - move them from test cases > > > >>>>>>>> not expecting any diagnostics to the new, dedicated ones, to allow > > > >>>>>>>> better focus on the actual changes in the subsequent patch. > > > >>>>>>>> > > > >>>>>>>> The new tests added have some wrong expectations right now, which will > > > >>>>>>>> be corrected by the next patch. The test is being added here to make > > > >>>>>>>> more visible which cases actually were wrong (and hence get changed), > > > >>>>>>>> besides demonstrating that in the vast majority of cases the subsequent > > > >>>>>>>> change doesn't alter generated code. > > > >>>>>>>> > > > >>>>>>>> gas/ > > > >>>>>>>> 2020-02-XX Jan Beulich <jbeulich@suse.com> > > > >>>>>>>> > > > >>>>>>>> * testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s, > > > >>>>>>>> testsuite/gas/i386/ilp32/x86-64.s: Move ambiguous operand size > > > >>>>>>>> tests ... > > > >>>>>>>> * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s, > > > >>>>>>>> testsuite/gas/i386/noreg64.s, testsuite/gas/i386/x86_64.s: ... > > > >>>>>>>> here. > > > >>>>>>>> * testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d > > > >>>>>>>> testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d, > > > >>>>>>>> testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d, > > > >>>>>>>> testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d, > > > >>>>>>>> testsuite/gas/i386/noreg64.d, testsuite/gas/i386/x86_64-intel.d, > > > >>>>>>>> testsuite/gas/i386/x86_64.d: Adjust expectations. > > > >>>>>>>> * testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l, > > > >>>>>>>> testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l, > > > >>>>>>>> testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New. > > > >>>>>>>> * testsuite/gas/i386/i386.exp: Run new tests. > > > >>>>>>> > > > >>>>>>> Please make a separate patch to address MOVSX/MOVZX. > > > >>>>>> > > > >>>>>> I don't understand what you mean here. This patch simply documents the > > > >>>>>> status quo, to make it (much) easier to see what the next patch > > > >>>>>> actually adjusts. It doesn't "address" anything. If, for the purpose > > > >>>>>> of committing, you'd like to see both patches folded - fine by me. But > > > >>>>>> only then, not any earlier. > > > >>>>>> > > > >>>>>>> MOVSX and MOVZX > > > >>>>>>> should take no suffixes. AT&T syntax is supported if there is no > > > >>>>>>> ambiguity. AT&T > > > >>>>>>> syntax also supports movsXY and movzXY. > > > >>>>>> > > > >>>>>> Please could you clarify what specifically you'd like to see changed, > > > >>>>>> at the very least by pointing out one case each where you think I'm > > > >>>>>> moving in the wrong direction (presumably in the next patch really)? > > > >>>>>> I'm afraid your response isn't such that I can derive from it what > > > >>>>>> exactly you want. > > > >>>>> > > > >>>>> We support > > > >>>>> > > > >>>>> movsx %ax, %ecx > > > >>>>> movzx %ax, %ecx > > > >>>>> movswl %ax, %ecx > > > >>>>> movzwl %ax, %ecx > > > >>>>> > > > >>>>> We disallow > > > >>>>> > > > >>>>> movsxw %ax, %ecx > > > >>>>> movzxw %ax, %ecx > > > >>>> > > > >>>> We don't (as this patch demonstrates, along with pre-existing tests, > > > >>>> unless you mean once again to have an inconsistency between insns > > > >>>> with all register operands and similar ones with e memory source), > > > >>>> and if you want it to be this way, then please do so yourself, but > > > >>> > > > >>> I will do it. > > > >>> > > > >>>> please also only on top of my changes, so I won't need to re-base > > > >>> > > > >>> Which changes of yours are you referring to? > > > >> > > > >> This patch and the subsequent one. > > > >> > > > > > > > > Both changes won't be necessary after my changes. > > > > > > I'm confused. What you want to deal with is - afaict - orthogonal to > > > what the next patch in the series here does. > > > > > > > You will see what I mean when I post my patch for review. > > > > AT&T syntax requires suffix to specify memory operand size. Since > movsx and movzx can have different memory operand sizes with the same > destination register, this patch removes movsx and movzx with memory > operand from AT&T syntax. Since AT&T syntax uses different mnemonics > for movsx and movzx, this change should have little impact on assembly > sources. Tested with Linux kernel 5.5.3 for x86-64 and glibc 2.31 for > i686 and x86-64. > Updated patch to add more testcases and allow register operand with mov[sz]x[bwl]. -- H.J. [-- Attachment #2: 0001-x86-Remove-movsx-movzx-with-memory-operand-from-AT-T.patch --] [-- Type: text/x-patch, Size: 50789 bytes --] From c92f793b90ded44dda15703d7b1581bd5731d931 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" <hjl.tools@gmail.com> Date: Tue, 11 Feb 2020 05:39:53 -0800 Subject: [PATCH] x86: Remove movsx/movzx with memory operand from AT&T syntax AT&T syntax requires suffix to specify memory operand size. Since movsx and movzx can have different memory operand sizes with the same destination register, this patch removes movsx and movzx with memory operand from AT&T syntax. Since AT&T syntax uses different mnemonics for movsx and movzx, this change should have little impact on assembly sources. Tested with Linux kernel 5.5.3 for x86-64 and glibc 2.31 for i686 and x86-64. gas/ PR gas/25438 * doc/c-i386.texi: Document movsx, movsxd and movzx for AT&T syntax. * testsuite/gas/i386/i386-intel.d: Updated. * testsuite/gas/i386/i386.d: Likewise. * testsuite/gas/i386/iamcu-1.d: Likewise. * testsuite/gas/i386/ilp32/x86-64.d: Likewise. * testsuite/gas/i386/k1om.d: Likewise. * testsuite/gas/i386/l1om.d: Likewise. * testsuite/gas/i386/x86_64-intel.d: Likewise. * testsuite/gas/i386/x86_64.d: Likewise. * testsuite/gas/i386/i386.exp: Run movszx-inval and x86-64-movszx-inval. * testsuite/gas/i386/i386.s: Remove movsx/movzx tests with memory operand in AT&T syntax. * testsuite/gas/i386/iamcu-1.s: Likewise. * testsuite/gas/i386/x86_64.s: Likewise. * testsuite/gas/i386/ilp32/x86-64.s: Likewise. * testsuite/gas/i386/movszx-inval.l: New file. * testsuite/gas/i386/movszx-inval.s: Likewise. * testsuite/gas/i386/x86-64-movszx-inval.l: Likewise. * testsuite/gas/i386/x86-64-movszx-inval.s: Likewise. opcodes/ PR gas/25438 * i386-opc.tbl: Remove movsx and movzx with memory operand from AT&T syntax. Don't allow suffix with movsx and movzx. Add movsxb, movsxw, movsxl, movzxb and movzxw for AT&T syntax. * i386-tbl.h: Regenerated. --- gas/doc/c-i386.texi | 43 +++++++ gas/testsuite/gas/i386/i386-intel.d | 10 +- gas/testsuite/gas/i386/i386.d | 10 +- gas/testsuite/gas/i386/i386.exp | 2 + gas/testsuite/gas/i386/i386.s | 10 +- gas/testsuite/gas/i386/iamcu-1.d | 10 +- gas/testsuite/gas/i386/iamcu-1.s | 10 +- gas/testsuite/gas/i386/ilp32/x86-64.d | 23 ++-- gas/testsuite/gas/i386/ilp32/x86-64.s | 23 ++-- gas/testsuite/gas/i386/k1om.d | 23 ++-- gas/testsuite/gas/i386/l1om.d | 23 ++-- gas/testsuite/gas/i386/movszx-inval.l | 29 +++++ gas/testsuite/gas/i386/movszx-inval.s | 15 +++ gas/testsuite/gas/i386/x86-64-movszx-inval.l | 41 +++++++ gas/testsuite/gas/i386/x86-64-movszx-inval.s | 21 ++++ gas/testsuite/gas/i386/x86_64-intel.d | 23 ++-- gas/testsuite/gas/i386/x86_64.d | 23 ++-- gas/testsuite/gas/i386/x86_64.s | 23 ++-- opcodes/i386-opc.tbl | 25 +++-- opcodes/i386-tbl.h | 112 +++++++++++++++---- 20 files changed, 364 insertions(+), 135 deletions(-) create mode 100644 gas/testsuite/gas/i386/movszx-inval.l create mode 100644 gas/testsuite/gas/i386/movszx-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-movszx-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-movszx-inval.s diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index f0189ccb44..dd96dd1e57 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -835,6 +835,49 @@ are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these instructions. +@cindex extension instructions, i386 +@cindex i386 extension instructions +@cindex extension instructions, x86-64 +@cindex x86-64 extension instructions +The Intel-syntax extension instructions + +@itemize @bullet +@item +@samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg16}. + +@samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg32}. + +@samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg64} +(x86-64 only). + +@samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg32} + +@samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg64} +(x86-64 only). + +@samp{movsxd} --- sign-extend @samp{reg32/mem32} to @samp{reg64} +(x86-64 only). + +@samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg16}. + +@samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg32}. + +@samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg64} +(x86-64 only). + +@samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg32} + +@samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg64} +(x86-64 only). +@end itemize + +@noindent +are called @samp{movsbw/movsxb}, @samp{movsbl/movsxb}, +@samp{movsbq/movsb}, @samp{movswl/movsxw}, @samp{movswq/movsxw}, +@samp{movslq/movsxl}, @samp{movzbw/movzxb}, @samp{movzbl/movzxb}, +@samp{movzbq/movzxb}, @samp{movzwl/movzxw} and @samp{movzwq/movzxw} +in AT&T syntax. + @cindex jump instructions, i386 @cindex call instructions, i386 @cindex jump instructions, x86-64 diff --git a/gas/testsuite/gas/i386/i386-intel.d b/gas/testsuite/gas/i386/i386-intel.d index 1913e8da19..580f858ec7 100644 --- a/gas/testsuite/gas/i386/i386-intel.d +++ b/gas/testsuite/gas/i386/i386-intel.d @@ -14,8 +14,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f be f0 movsx si,al [ ]*[a-f0-9]+: 0f be f0 movsx esi,al [ ]*[a-f0-9]+: 0f bf f0 movsx esi,ax -[ ]*[a-f0-9]+: 0f be 10 movsx edx,BYTE PTR \[eax\] -[ ]*[a-f0-9]+: 66 0f be 10 movsx dx,BYTE PTR \[eax\] +[ ]*[a-f0-9]+: 66 0f be f0 movsx si,al +[ ]*[a-f0-9]+: 0f be f0 movsx esi,al +[ ]*[a-f0-9]+: 0f bf f0 movsx esi,ax [ ]*[a-f0-9]+: 66 0f be 10 movsx dx,BYTE PTR \[eax\] [ ]*[a-f0-9]+: 0f be 10 movsx edx,BYTE PTR \[eax\] [ ]*[a-f0-9]+: 0f bf 10 movsx edx,WORD PTR \[eax\] @@ -25,8 +26,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f b6 f0 movzx si,al [ ]*[a-f0-9]+: 0f b6 f0 movzx esi,al [ ]*[a-f0-9]+: 0f b7 f0 movzx esi,ax -[ ]*[a-f0-9]+: 0f b6 10 movzx edx,BYTE PTR \[eax\] -[ ]*[a-f0-9]+: 66 0f b6 10 movzx dx,BYTE PTR \[eax\] +[ ]*[a-f0-9]+: 66 0f b6 f0 movzx si,al +[ ]*[a-f0-9]+: 0f b6 f0 movzx esi,al +[ ]*[a-f0-9]+: 0f b7 f0 movzx esi,ax [ ]*[a-f0-9]+: 66 0f b6 10 movzx dx,BYTE PTR \[eax\] [ ]*[a-f0-9]+: 0f b6 10 movzx edx,BYTE PTR \[eax\] [ ]*[a-f0-9]+: 0f b7 10 movzx edx,WORD PTR \[eax\] diff --git a/gas/testsuite/gas/i386/i386.d b/gas/testsuite/gas/i386/i386.d index 1c6c4cc3fd..b94e248373 100644 --- a/gas/testsuite/gas/i386/i386.d +++ b/gas/testsuite/gas/i386/i386.d @@ -13,8 +13,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi [ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi -[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx -[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx +[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi +[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx [ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx [ ]*[a-f0-9]+: 0f bf 10 movswl \(%eax\),%edx @@ -24,8 +25,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si [ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi [ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi -[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx -[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx +[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si +[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi +[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx [ ]*[a-f0-9]+: 0f b7 10 movzwl \(%eax\),%edx diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index c4280417c5..40154f39c9 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -491,6 +491,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_list_test "inval-pseudo" "-al" run_dump_test "nop-1" run_dump_test "nop-2" + run_list_test "movszx-inval" "-al" run_dump_test "optimize-1" run_dump_test "optimize-1a" run_dump_test "optimize-2" @@ -1052,6 +1053,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_dump_test "x86-64-movd-intel" run_dump_test "x86-64-nop-1" run_dump_test "x86-64-nop-2" + run_list_test "x86-64-movszx-inval" "-al" run_dump_test "x86-64-movsxd" run_dump_test "x86-64-movsxd-intel" run_list_test "x86-64-movsxd-inval" "-al" diff --git a/gas/testsuite/gas/i386/i386.s b/gas/testsuite/gas/i386/i386.s index 7da361f5f8..590cf820a4 100644 --- a/gas/testsuite/gas/i386/i386.s +++ b/gas/testsuite/gas/i386/i386.s @@ -9,8 +9,9 @@ movsx %al, %si movsx %al, %esi movsx %ax, %esi - movsx (%eax), %edx - movsx (%eax), %dx + movsxb %al, %si + movsxb %al, %esi + movsxw %ax, %esi movsxb (%eax), %dx movsxb (%eax), %edx movsxw (%eax), %edx @@ -21,8 +22,9 @@ movzx %al, %si movzx %al, %esi movzx %ax, %esi - movzx (%eax), %edx - movzx (%eax), %dx + movzxb %al, %si + movzxb %al, %esi + movzxw %ax, %esi movzxb (%eax), %dx movzxb (%eax), %edx movzxw (%eax), %edx diff --git a/gas/testsuite/gas/i386/iamcu-1.d b/gas/testsuite/gas/i386/iamcu-1.d index 2b1df5de4b..f5b0f0bd4d 100644 --- a/gas/testsuite/gas/i386/iamcu-1.d +++ b/gas/testsuite/gas/i386/iamcu-1.d @@ -10,8 +10,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi [ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi -[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx -[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx +[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi +[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx [ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx [ ]*[a-f0-9]+: 0f bf 10 movswl \(%eax\),%edx @@ -21,8 +22,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si [ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi [ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi -[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx -[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx +[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si +[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi +[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx [ ]*[a-f0-9]+: 0f b7 10 movzwl \(%eax\),%edx diff --git a/gas/testsuite/gas/i386/iamcu-1.s b/gas/testsuite/gas/i386/iamcu-1.s index b631dfa17e..df9874ba85 100644 --- a/gas/testsuite/gas/i386/iamcu-1.s +++ b/gas/testsuite/gas/i386/iamcu-1.s @@ -4,8 +4,9 @@ movsx %al, %si movsx %al, %esi movsx %ax, %esi - movsx (%eax), %edx - movsx (%eax), %dx + movsxb %al, %si + movsxb %al, %esi + movsxw %ax, %esi movsxb (%eax), %dx movsxb (%eax), %edx movsxw (%eax), %edx @@ -16,8 +17,9 @@ movzx %al, %si movzx %al, %esi movzx %ax, %esi - movzx (%eax), %edx - movzx (%eax), %dx + movzxb %al, %si + movzxb %al, %esi + movzxw %ax, %esi movzxb (%eax), %dx movzxb (%eax), %edx movzxw (%eax), %edx diff --git a/gas/testsuite/gas/i386/ilp32/x86-64.d b/gas/testsuite/gas/i386/ilp32/x86-64.d index 33722c90f9..745f8c2094 100644 --- a/gas/testsuite/gas/i386/ilp32/x86-64.d +++ b/gas/testsuite/gas/i386/ilp32/x86-64.d @@ -162,9 +162,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi [ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi [ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi -[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx -[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx -[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx +[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi +[ ]*[a-f0-9]+: 48 0f be f0 movsbq %al,%rsi +[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi +[ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi +[ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi [ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx @@ -175,9 +178,11 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi [ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi [ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi -[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx -[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx -[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx +[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si +[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi +[ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi +[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi +[ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx @@ -219,9 +224,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: df e0 fnstsw %ax [ ]*[a-f0-9]+: 9b df e0 fstsw %ax [ ]*[a-f0-9]+: 9b df e0 fstsw %ax -[ ]*[a-f0-9]+: 66 0f be 00 movsbw \(%rax\),%ax -[ ]*[a-f0-9]+: 0f be 00 movsbl \(%rax\),%eax -[ ]*[a-f0-9]+: 48 0f be 00 movsbq \(%rax\),%rax [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx @@ -229,9 +231,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f bf 10 movswq \(%rax\),%rdx [ ]*[a-f0-9]+: 48 63 10 movslq \(%rax\),%rdx [ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax -[ ]*[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax -[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax -[ ]*[a-f0-9]+: 48 0f b6 00 movzbq \(%rax\),%rax [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx diff --git a/gas/testsuite/gas/i386/ilp32/x86-64.s b/gas/testsuite/gas/i386/ilp32/x86-64.s index d1f7ae3b49..c7d7ef2e5b 100644 --- a/gas/testsuite/gas/i386/ilp32/x86-64.s +++ b/gas/testsuite/gas/i386/ilp32/x86-64.s @@ -194,9 +194,12 @@ cmpxchg16b oword ptr [rax] movsx %ax, %esi movsx %ax, %rsi movsx %eax, %rsi - movsx (%rax), %edx - movsx (%rax), %rdx - movsx (%rax), %dx + movsxb %al, %si + movsxb %al, %esi + movsxb %al, %rsi + movsxw %ax, %esi + movsxw %ax, %rsi + movsxl %eax, %rsi movsbl (%rax), %edx movsbq (%rax), %rdx movsbw (%rax), %dx @@ -208,9 +211,11 @@ cmpxchg16b oword ptr [rax] movzx %al, %rsi movzx %ax, %esi movzx %ax, %rsi - movzx (%rax), %edx - movzx (%rax), %rdx - movzx (%rax), %dx + movzxb %al, %si + movzxb %al, %esi + movzxb %al, %rsi + movzxw %ax, %esi + movzxw %ax, %rsi movzb (%rax), %edx movzb (%rax), %rdx movzb (%rax), %dx @@ -262,9 +267,6 @@ cmpxchg16b oword ptr [rax] fstsw ax .att_syntax -movsx (%rax),%ax -movsx (%rax),%eax -movsx (%rax),%rax movsxb (%rax), %dx movsxb (%rax), %edx movsxb (%rax), %rdx @@ -272,9 +274,6 @@ movsxw (%rax), %edx movsxw (%rax), %rdx movsxl (%rax), %rdx movsxd (%rax),%rax -movzx (%rax),%ax -movzx (%rax),%eax -movzx (%rax),%rax movzxb (%rax), %dx movzxb (%rax), %edx movzxb (%rax), %rdx diff --git a/gas/testsuite/gas/i386/k1om.d b/gas/testsuite/gas/i386/k1om.d index 7767f5b418..7995803ce1 100644 --- a/gas/testsuite/gas/i386/k1om.d +++ b/gas/testsuite/gas/i386/k1om.d @@ -175,9 +175,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi [ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi [ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi -[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx -[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx -[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx +[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi +[ ]*[a-f0-9]+: 48 0f be f0 movsbq %al,%rsi +[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi +[ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi +[ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi [ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx @@ -188,9 +191,11 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi [ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi [ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi -[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx -[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx -[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx +[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si +[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi +[ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi +[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi +[ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx @@ -232,9 +237,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: df e0 fnstsw %ax [ ]*[a-f0-9]+: 9b df e0 fstsw %ax [ ]*[a-f0-9]+: 9b df e0 fstsw %ax -[ ]*[a-f0-9]+: 66 0f be 00 movsbw \(%rax\),%ax -[ ]*[a-f0-9]+: 0f be 00 movsbl \(%rax\),%eax -[ ]*[a-f0-9]+: 48 0f be 00 movsbq \(%rax\),%rax [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx @@ -242,9 +244,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f bf 10 movswq \(%rax\),%rdx [ ]*[a-f0-9]+: 48 63 10 movslq \(%rax\),%rdx [ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax -[ ]*[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax -[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax -[ ]*[a-f0-9]+: 48 0f b6 00 movzbq \(%rax\),%rax [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx diff --git a/gas/testsuite/gas/i386/l1om.d b/gas/testsuite/gas/i386/l1om.d index 858d1827f9..95d9823e8a 100644 --- a/gas/testsuite/gas/i386/l1om.d +++ b/gas/testsuite/gas/i386/l1om.d @@ -175,9 +175,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi [ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi [ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi -[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx -[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx -[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx +[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi +[ ]*[a-f0-9]+: 48 0f be f0 movsbq %al,%rsi +[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi +[ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi +[ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi [ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx @@ -188,9 +191,11 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi [ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi [ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi -[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx -[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx -[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx +[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si +[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi +[ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi +[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi +[ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx @@ -232,9 +237,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: df e0 fnstsw %ax [ ]*[a-f0-9]+: 9b df e0 fstsw %ax [ ]*[a-f0-9]+: 9b df e0 fstsw %ax -[ ]*[a-f0-9]+: 66 0f be 00 movsbw \(%rax\),%ax -[ ]*[a-f0-9]+: 0f be 00 movsbl \(%rax\),%eax -[ ]*[a-f0-9]+: 48 0f be 00 movsbq \(%rax\),%rax [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx @@ -242,9 +244,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f bf 10 movswq \(%rax\),%rdx [ ]*[a-f0-9]+: 48 63 10 movslq \(%rax\),%rdx [ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax -[ ]*[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax -[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax -[ ]*[a-f0-9]+: 48 0f b6 00 movzbq \(%rax\),%rax [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx diff --git a/gas/testsuite/gas/i386/movszx-inval.l b/gas/testsuite/gas/i386/movszx-inval.l new file mode 100644 index 0000000000..10c2803729 --- /dev/null +++ b/gas/testsuite/gas/i386/movszx-inval.l @@ -0,0 +1,29 @@ +.*: Assembler messages: +.*:4: Error: .* +.*:5: Error: .* +.*:6: Error: .* +.*:7: Error: .* +.*:10: Error: .* +.*:11: Error: .* +.*:12: Error: .* +.*:13: Error: .* +.*:14: Error: .* +.*:15: Error: .* +GAS LISTING .* + + +[ ]*1[ ]+\# Invalid 32-bit movsx and movzx\. +[ ]*2[ ]+\.text +[ ]*3[ ]+_start: +[ ]*4[ ]+movsx \(%eax\), %edx +[ ]*5[ ]+movsx \(%eax\), %dx +[ ]*6[ ]+movzx \(%eax\), %edx +[ ]*7[ ]+movzx \(%eax\), %dx +[ ]*8[ ]+ +[ ]*9[ ]+\.intel_syntax noprefix +[ ]*10[ ]+movsxb ax, BYTE PTR \[eax\] +[ ]*11[ ]+movsxb eax, BYTE PTR \[eax\] +[ ]*12[ ]+movsxw eax, WORD PTR \[eax\] +[ ]*13[ ]+movzxb ax, BYTE PTR \[eax\] +[ ]*14[ ]+movzxb eax, BYTE PTR \[eax\] +[ ]*15[ ]+movzxw eax, WORD PTR \[eax\] diff --git a/gas/testsuite/gas/i386/movszx-inval.s b/gas/testsuite/gas/i386/movszx-inval.s new file mode 100644 index 0000000000..9a81d16e2c --- /dev/null +++ b/gas/testsuite/gas/i386/movszx-inval.s @@ -0,0 +1,15 @@ +# Invalid 32-bit movsx and movzx. + .text +_start: + movsx (%eax), %edx + movsx (%eax), %dx + movzx (%eax), %edx + movzx (%eax), %dx + + .intel_syntax noprefix + movsxb ax, BYTE PTR [eax] + movsxb eax, BYTE PTR [eax] + movsxw eax, WORD PTR [eax] + movzxb ax, BYTE PTR [eax] + movzxb eax, BYTE PTR [eax] + movzxw eax, WORD PTR [eax] diff --git a/gas/testsuite/gas/i386/x86-64-movszx-inval.l b/gas/testsuite/gas/i386/x86-64-movszx-inval.l new file mode 100644 index 0000000000..08ff0bd1a4 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-movszx-inval.l @@ -0,0 +1,41 @@ +.*: Assembler messages: +.*:4: Error: .* +.*:5: Error: .* +.*:6: Error: .* +.*:7: Error: .* +.*:8: Error: .* +.*:9: Error: .* +.*:12: Error: .* +.*:13: Error: .* +.*:14: Error: .* +.*:15: Error: .* +.*:16: Error: .* +.*:17: Error: .* +.*:18: Error: .* +.*:19: Error: .* +.*:20: Error: .* +.*:21: Error: .* +GAS LISTING .* + + +[ ]*1[ ]+\# Invalid 64-bit movsx and movzx\. +[ ]*2[ ]+\.text +[ ]*3[ ]+_start: +[ ]*4[ ]+movsx \(%rax\), %rdx +[ ]*5[ ]+movsx \(%rax\), %edx +[ ]*6[ ]+movsx \(%rax\), %dx +[ ]*7[ ]+movzx \(%rax\), %rdx +[ ]*8[ ]+movzx \(%rax\), %edx +[ ]*9[ ]+movzx \(%rax\), %dx +[ ]*10[ ]+ +[ ]*11[ ]+\.intel_syntax noprefix +[ ]*12[ ]+movsxb ax, BYTE PTR \[rax\] +[ ]*13[ ]+movsxb eax, BYTE PTR \[rax\] +[ ]*14[ ]+movsxb rax, BYTE PTR \[rax\] +[ ]*15[ ]+movsxw eax, WORD PTR \[rax\] +[ ]*16[ ]+movsxw rax, WORD PTR \[rax\] +[ ]*17[ ]+movzxb ax, BYTE PTR \[rax\] +[ ]*18[ ]+movzxb eax, BYTE PTR \[rax\] +[ ]*19[ ]+movzxb rax, BYTE PTR \[rax\] +[ ]*20[ ]+movzxw eax, WORD PTR \[rax\] +[ ]*21[ ]+movzxw rax, WORD PTR \[rax\] diff --git a/gas/testsuite/gas/i386/x86-64-movszx-inval.s b/gas/testsuite/gas/i386/x86-64-movszx-inval.s new file mode 100644 index 0000000000..c74f64a1f2 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-movszx-inval.s @@ -0,0 +1,21 @@ +# Invalid 64-bit movsx and movzx. + .text +_start: + movsx (%rax), %rdx + movsx (%rax), %edx + movsx (%rax), %dx + movzx (%rax), %rdx + movzx (%rax), %edx + movzx (%rax), %dx + + .intel_syntax noprefix + movsxb ax, BYTE PTR [rax] + movsxb eax, BYTE PTR [rax] + movsxb rax, BYTE PTR [rax] + movsxw eax, WORD PTR [rax] + movsxw rax, WORD PTR [rax] + movzxb ax, BYTE PTR [rax] + movzxb eax, BYTE PTR [rax] + movzxb rax, BYTE PTR [rax] + movzxw eax, WORD PTR [rax] + movzxw rax, WORD PTR [rax] diff --git a/gas/testsuite/gas/i386/x86_64-intel.d b/gas/testsuite/gas/i386/x86_64-intel.d index 8dd8893e79..6e9e3a070f 100644 --- a/gas/testsuite/gas/i386/x86_64-intel.d +++ b/gas/testsuite/gas/i386/x86_64-intel.d @@ -173,9 +173,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f bf f0 movsx esi,ax [ ]*[a-f0-9]+: 48 0f bf f0 movsx rsi,ax [ ]*[a-f0-9]+: 48 63 f0 movsxd rsi,eax -[ ]*[a-f0-9]+: 0f be 10 movsx edx,BYTE PTR \[rax\] -[ ]*[a-f0-9]+: 48 0f be 10 movsx rdx,BYTE PTR \[rax\] -[ ]*[a-f0-9]+: 66 0f be 10 movsx dx,BYTE PTR \[rax\] +[ ]*[a-f0-9]+: 66 0f be f0 movsx si,al +[ ]*[a-f0-9]+: 0f be f0 movsx esi,al +[ ]*[a-f0-9]+: 48 0f be f0 movsx rsi,al +[ ]*[a-f0-9]+: 0f bf f0 movsx esi,ax +[ ]*[a-f0-9]+: 48 0f bf f0 movsx rsi,ax +[ ]*[a-f0-9]+: 48 63 f0 movsxd rsi,eax [ ]*[a-f0-9]+: 0f be 10 movsx edx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 48 0f be 10 movsx rdx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 66 0f be 10 movsx dx,BYTE PTR \[rax\] @@ -186,9 +189,11 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f b6 f0 movzx rsi,al [ ]*[a-f0-9]+: 0f b7 f0 movzx esi,ax [ ]*[a-f0-9]+: 48 0f b7 f0 movzx rsi,ax -[ ]*[a-f0-9]+: 0f b6 10 movzx edx,BYTE PTR \[rax\] -[ ]*[a-f0-9]+: 48 0f b6 10 movzx rdx,BYTE PTR \[rax\] -[ ]*[a-f0-9]+: 66 0f b6 10 movzx dx,BYTE PTR \[rax\] +[ ]*[a-f0-9]+: 66 0f b6 f0 movzx si,al +[ ]*[a-f0-9]+: 0f b6 f0 movzx esi,al +[ ]*[a-f0-9]+: 48 0f b6 f0 movzx rsi,al +[ ]*[a-f0-9]+: 0f b7 f0 movzx esi,ax +[ ]*[a-f0-9]+: 48 0f b7 f0 movzx rsi,ax [ ]*[a-f0-9]+: 0f b6 10 movzx edx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 48 0f b6 10 movzx rdx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 66 0f b6 10 movzx dx,BYTE PTR \[rax\] @@ -230,9 +235,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: df e0 fnstsw ax [ ]*[a-f0-9]+: 9b df e0 fstsw ax [ ]*[a-f0-9]+: 9b df e0 fstsw ax -[ ]*[a-f0-9]+: 66 0f be 00 movsx ax,BYTE PTR \[rax\] -[ ]*[a-f0-9]+: 0f be 00 movsx eax,BYTE PTR \[rax\] -[ ]*[a-f0-9]+: 48 0f be 00 movsx rax,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 66 0f be 10 movsx dx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 0f be 10 movsx edx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 48 0f be 10 movsx rdx,BYTE PTR \[rax\] @@ -240,9 +242,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f bf 10 movsx rdx,WORD PTR \[rax\] [ ]*[a-f0-9]+: 48 63 10 movsxd rdx,DWORD PTR \[rax\] [ ]*[a-f0-9]+: 48 63 00 movsxd rax,DWORD PTR \[rax\] -[ ]*[a-f0-9]+: 66 0f b6 00 movzx ax,BYTE PTR \[rax\] -[ ]*[a-f0-9]+: 0f b6 00 movzx eax,BYTE PTR \[rax\] -[ ]*[a-f0-9]+: 48 0f b6 00 movzx rax,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 66 0f b6 10 movzx dx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 0f b6 10 movzx edx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 48 0f b6 10 movzx rdx,BYTE PTR \[rax\] diff --git a/gas/testsuite/gas/i386/x86_64.d b/gas/testsuite/gas/i386/x86_64.d index 0bdbc79021..8c980fe3cf 100644 --- a/gas/testsuite/gas/i386/x86_64.d +++ b/gas/testsuite/gas/i386/x86_64.d @@ -173,9 +173,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi [ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi [ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi -[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx -[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx -[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx +[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi +[ ]*[a-f0-9]+: 48 0f be f0 movsbq %al,%rsi +[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi +[ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi +[ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi [ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx @@ -186,9 +189,11 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi [ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi [ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi -[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx -[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx -[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx +[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si +[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi +[ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi +[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi +[ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx @@ -230,9 +235,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: df e0 fnstsw %ax [ ]*[a-f0-9]+: 9b df e0 fstsw %ax [ ]*[a-f0-9]+: 9b df e0 fstsw %ax -[ ]*[a-f0-9]+: 66 0f be 00 movsbw \(%rax\),%ax -[ ]*[a-f0-9]+: 0f be 00 movsbl \(%rax\),%eax -[ ]*[a-f0-9]+: 48 0f be 00 movsbq \(%rax\),%rax [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx @@ -240,9 +242,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f bf 10 movswq \(%rax\),%rdx [ ]*[a-f0-9]+: 48 63 10 movslq \(%rax\),%rdx [ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax -[ ]*[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax -[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax -[ ]*[a-f0-9]+: 48 0f b6 00 movzbq \(%rax\),%rax [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx diff --git a/gas/testsuite/gas/i386/x86_64.s b/gas/testsuite/gas/i386/x86_64.s index 377580be34..45c9825869 100644 --- a/gas/testsuite/gas/i386/x86_64.s +++ b/gas/testsuite/gas/i386/x86_64.s @@ -208,9 +208,12 @@ cmpxchg16b oword ptr [rax] movsx %ax, %esi movsx %ax, %rsi movsx %eax, %rsi - movsx (%rax), %edx - movsx (%rax), %rdx - movsx (%rax), %dx + movsxb %al, %si + movsxb %al, %esi + movsxb %al, %rsi + movsxw %ax, %esi + movsxw %ax, %rsi + movsxl %eax, %rsi movsbl (%rax), %edx movsbq (%rax), %rdx movsbw (%rax), %dx @@ -222,9 +225,11 @@ cmpxchg16b oword ptr [rax] movzx %al, %rsi movzx %ax, %esi movzx %ax, %rsi - movzx (%rax), %edx - movzx (%rax), %rdx - movzx (%rax), %dx + movzxb %al, %si + movzxb %al, %esi + movzxb %al, %rsi + movzxw %ax, %esi + movzxw %ax, %rsi movzb (%rax), %edx movzb (%rax), %rdx movzb (%rax), %dx @@ -276,9 +281,6 @@ cmpxchg16b oword ptr [rax] fstsw ax .att_syntax -movsx (%rax),%ax -movsx (%rax),%eax -movsx (%rax),%rax movsxb (%rax), %dx movsxb (%rax), %edx movsxb (%rax), %rdx @@ -286,9 +288,6 @@ movsxw (%rax), %edx movsxw (%rax), %rdx movsxl (%rax), %rdx movsxd (%rax),%rax -movzx (%rax),%ax -movzx (%rax),%eax -movzx (%rax),%rax movzxb (%rax), %dx movzxb (%rax), %edx movzxb (%rax), %rdx diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index d805e6916a..889d63fc2f 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -132,13 +132,16 @@ movswl, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf movsbq, 2, 0xfbe, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg8|Byte|Unspecified|BaseIndex, Reg64 } movswq, 2, 0xfbf, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg16|Word|Unspecified|BaseIndex, Reg64 } movslq, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg32|Dword|Unspecified|BaseIndex, Reg64 } +movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8, Reg16|Reg32|Reg64 } +movsxb, 2, 0xfbe, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16, Reg32|Reg64 } +movsxw, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 } +movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg32, Reg64 } +movsxl, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg32|Unspecified|BaseIndex, Reg64 } // Intel Syntax next 3 insns -movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 } -movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|ATTSyntax, { Reg32|Unspecified|BaseIndex, Reg64 } -movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg8|Byte|BaseIndex, Reg16|Reg32|Reg64 } -movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex, Reg32|Reg64 } -movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|IntelSyntax, { Reg32|Dword|BaseIndex, Reg64 } +movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg8|Byte|BaseIndex, Reg16|Reg32|Reg64 } +movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex, Reg32|Reg64 } +movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|IntelSyntax, { Reg32|Dword|BaseIndex, Reg64 } movsxd, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 } movsxd, 2, 0x63, None, 1, Cpu64, Amd64|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg16 } movsxd, 2, 0x63, None, 1, Cpu64, Intel64|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Unspecified|BaseIndex, Reg16 } @@ -146,12 +149,14 @@ movsxd, 2, 0x63, None, 1, Cpu64, Intel64|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N // Move with zero extend. movzb, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } movzw, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32|Reg64 } +movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8, Reg16|Reg32|Reg64 } +movzxb, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16, Reg32|Reg64 } +movzxw, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 } // Intel Syntax next 2 insns (the 64-bit variants are not particulary // useful since the zero extend 32->64 is implicit, but we can encode them). -movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 } -movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg8|Byte|BaseIndex, Reg16|Reg32|Reg64 } -movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex, Reg32|Reg64 } +movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg8|Byte|BaseIndex, Reg16|Reg32|Reg64 } +movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex, Reg32|Reg64 } // Push instructions. push, 1, 0x50, None, 1, CpuNo64, No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 860646c923..5a9a4c3def 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -351,11 +351,11 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 }, - { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, - 0, 0, 0, 0, 1, 0 } }, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0 } } } }, { "movsx", 0xfbf, None, 2, 2, @@ -365,11 +365,11 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 0, 0, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 }, - { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, - 0, 0, 0, 0, 1, 0 } }, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0 } } } }, { "movsx", 0x63, None, 1, 2, @@ -379,11 +379,11 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 }, - { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, - 0, 0, 0, 0, 1, 0 } }, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, + 0, 0, 0, 0, 0, 0 } }, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } } } }, { "movsx", 0xfbe, None, 2, 2, @@ -393,7 +393,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, @@ -407,7 +407,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 0, 0, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, @@ -421,13 +421,55 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } } } }, + { "movsxb", 0xfbe, None, 2, 2, + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 }, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, + 0, 0, 0, 0, 1, 0 } }, + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, + 0, 0, 0, 0, 0, 0 } } } }, + { "movsxw", 0xfbf, None, 2, 2, + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 }, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 1, 0 } }, + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, + 0, 0, 0, 0, 0, 0 } } } }, + { "movsxl", 0x63, None, 1, 2, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 }, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, + 0, 0, 0, 0, 1, 0 } }, + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, + 0, 0, 0, 0, 0, 0 } } } }, { "movsxd", 0x63, None, 1, 2, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -505,11 +547,11 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 }, - { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, - 0, 0, 0, 0, 1, 0 } }, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0 } } } }, { "movzx", 0xfb7, None, 2, 2, @@ -519,11 +561,11 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 0, 0, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 }, - { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, - 0, 0, 0, 0, 1, 0 } }, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0 } } } }, { "movzx", 0xfb6, None, 2, 2, @@ -533,7 +575,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, @@ -547,13 +589,41 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 0, 0, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0 } } } }, + { "movzxb", 0xfb6, None, 2, 2, + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 }, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, + 0, 0, 0, 0, 1, 0 } }, + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, + 0, 0, 0, 0, 0, 0 } } } }, + { "movzxw", 0xfb7, None, 2, 2, + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 }, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 1, 0 } }, + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, + 0, 0, 0, 0, 0, 0 } } } }, { "push", 0x50, None, 1, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 2.24.1 ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH] x86: Remove movsx/movzx with memory operand from AT&T syntax 2020-02-11 23:34 ` H.J. Lu @ 2020-02-11 23:52 ` H.J. Lu 2020-02-12 3:19 ` [PATCH] x86: Remove movsx/movzx with 16/32-bit " H.J. Lu 0 siblings, 1 reply; 26+ messages in thread From: H.J. Lu @ 2020-02-11 23:52 UTC (permalink / raw) To: Jan Beulich; +Cc: binutils On Tue, Feb 11, 2020 at 3:34 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > On Tue, Feb 11, 2020 at 12:11 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > > > On Tue, Feb 11, 2020 at 9:04 AM H.J. Lu <hjl.tools@gmail.com> wrote: > > > > > > On Tue, Feb 11, 2020 at 8:45 AM Jan Beulich <jbeulich@suse.com> wrote: > > > > > > > > On 11.02.2020 14:07, H.J. Lu wrote: > > > > > On Tue, Feb 11, 2020 at 5:04 AM Jan Beulich <jbeulich@suse.com> wrote: > > > > >> > > > > >> On 11.02.2020 14:01, H.J. Lu wrote: > > > > >>> On Tue, Feb 11, 2020 at 4:58 AM Jan Beulich <jbeulich@suse.com> wrote: > > > > >>>> > > > > >>>> On 11.02.2020 13:19, H.J. Lu wrote: > > > > >>>>> On Tue, Feb 11, 2020 at 3:55 AM Jan Beulich <jbeulich@suse.com> wrote: > > > > >>>>>> > > > > >>>>>> On 11.02.2020 12:42, H.J. Lu wrote: > > > > >>>>>>> On Tue, Feb 11, 2020 at 2:25 AM Jan Beulich <jbeulich@suse.com> wrote: > > > > >>>>>>>> > > > > >>>>>>>> Some encodings are about to gain a warning - move them from test cases > > > > >>>>>>>> not expecting any diagnostics to the new, dedicated ones, to allow > > > > >>>>>>>> better focus on the actual changes in the subsequent patch. > > > > >>>>>>>> > > > > >>>>>>>> The new tests added have some wrong expectations right now, which will > > > > >>>>>>>> be corrected by the next patch. The test is being added here to make > > > > >>>>>>>> more visible which cases actually were wrong (and hence get changed), > > > > >>>>>>>> besides demonstrating that in the vast majority of cases the subsequent > > > > >>>>>>>> change doesn't alter generated code. > > > > >>>>>>>> > > > > >>>>>>>> gas/ > > > > >>>>>>>> 2020-02-XX Jan Beulich <jbeulich@suse.com> > > > > >>>>>>>> > > > > >>>>>>>> * testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s, > > > > >>>>>>>> testsuite/gas/i386/ilp32/x86-64.s: Move ambiguous operand size > > > > >>>>>>>> tests ... > > > > >>>>>>>> * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s, > > > > >>>>>>>> testsuite/gas/i386/noreg64.s, testsuite/gas/i386/x86_64.s: ... > > > > >>>>>>>> here. > > > > >>>>>>>> * testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d > > > > >>>>>>>> testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d, > > > > >>>>>>>> testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d, > > > > >>>>>>>> testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d, > > > > >>>>>>>> testsuite/gas/i386/noreg64.d, testsuite/gas/i386/x86_64-intel.d, > > > > >>>>>>>> testsuite/gas/i386/x86_64.d: Adjust expectations. > > > > >>>>>>>> * testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l, > > > > >>>>>>>> testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l, > > > > >>>>>>>> testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New. > > > > >>>>>>>> * testsuite/gas/i386/i386.exp: Run new tests. > > > > >>>>>>> > > > > >>>>>>> Please make a separate patch to address MOVSX/MOVZX. > > > > >>>>>> > > > > >>>>>> I don't understand what you mean here. This patch simply documents the > > > > >>>>>> status quo, to make it (much) easier to see what the next patch > > > > >>>>>> actually adjusts. It doesn't "address" anything. If, for the purpose > > > > >>>>>> of committing, you'd like to see both patches folded - fine by me. But > > > > >>>>>> only then, not any earlier. > > > > >>>>>> > > > > >>>>>>> MOVSX and MOVZX > > > > >>>>>>> should take no suffixes. AT&T syntax is supported if there is no > > > > >>>>>>> ambiguity. AT&T > > > > >>>>>>> syntax also supports movsXY and movzXY. > > > > >>>>>> > > > > >>>>>> Please could you clarify what specifically you'd like to see changed, > > > > >>>>>> at the very least by pointing out one case each where you think I'm > > > > >>>>>> moving in the wrong direction (presumably in the next patch really)? > > > > >>>>>> I'm afraid your response isn't such that I can derive from it what > > > > >>>>>> exactly you want. > > > > >>>>> > > > > >>>>> We support > > > > >>>>> > > > > >>>>> movsx %ax, %ecx > > > > >>>>> movzx %ax, %ecx > > > > >>>>> movswl %ax, %ecx > > > > >>>>> movzwl %ax, %ecx > > > > >>>>> > > > > >>>>> We disallow > > > > >>>>> > > > > >>>>> movsxw %ax, %ecx > > > > >>>>> movzxw %ax, %ecx > > > > >>>> > > > > >>>> We don't (as this patch demonstrates, along with pre-existing tests, > > > > >>>> unless you mean once again to have an inconsistency between insns > > > > >>>> with all register operands and similar ones with e memory source), > > > > >>>> and if you want it to be this way, then please do so yourself, but > > > > >>> > > > > >>> I will do it. > > > > >>> > > > > >>>> please also only on top of my changes, so I won't need to re-base > > > > >>> > > > > >>> Which changes of yours are you referring to? > > > > >> > > > > >> This patch and the subsequent one. > > > > >> > > > > > > > > > > Both changes won't be necessary after my changes. > > > > > > > > I'm confused. What you want to deal with is - afaict - orthogonal to > > > > what the next patch in the series here does. > > > > > > > > > > You will see what I mean when I post my patch for review. > > > > > > > AT&T syntax requires suffix to specify memory operand size. Since > > movsx and movzx can have different memory operand sizes with the same > > destination register, this patch removes movsx and movzx with memory > > operand from AT&T syntax. Since AT&T syntax uses different mnemonics > > for movsx and movzx, this change should have little impact on assembly > > sources. Tested with Linux kernel 5.5.3 for x86-64 and glibc 2.31 for > > i686 and x86-64. > > > > Updated patch to add more testcases and allow register operand with > mov[sz]x[bwl]. > I found usage of movzx 4(%edx), %eax We also need to support: movsx 4(%edx), %eax I will update my patch. -- H.J. ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH] x86: Remove movsx/movzx with 16/32-bit memory operand from AT&T syntax 2020-02-11 23:52 ` H.J. Lu @ 2020-02-12 3:19 ` H.J. Lu 2020-02-12 9:19 ` Jan Beulich 0 siblings, 1 reply; 26+ messages in thread From: H.J. Lu @ 2020-02-12 3:19 UTC (permalink / raw) To: Jan Beulich, binutils On Tue, Feb 11, 2020 at 03:51:29PM -0800, H.J. Lu wrote: > On Tue, Feb 11, 2020 at 3:34 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > > > On Tue, Feb 11, 2020 at 12:11 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > > > > > On Tue, Feb 11, 2020 at 9:04 AM H.J. Lu <hjl.tools@gmail.com> wrote: > > > > > > > > On Tue, Feb 11, 2020 at 8:45 AM Jan Beulich <jbeulich@suse.com> wrote: > > > > > > > > > > On 11.02.2020 14:07, H.J. Lu wrote: > > > > > > On Tue, Feb 11, 2020 at 5:04 AM Jan Beulich <jbeulich@suse.com> wrote: > > > > > >> > > > > > >> On 11.02.2020 14:01, H.J. Lu wrote: > > > > > >>> On Tue, Feb 11, 2020 at 4:58 AM Jan Beulich <jbeulich@suse.com> wrote: > > > > > >>>> > > > > > >>>> On 11.02.2020 13:19, H.J. Lu wrote: > > > > > >>>>> On Tue, Feb 11, 2020 at 3:55 AM Jan Beulich <jbeulich@suse.com> wrote: > > > > > >>>>>> > > > > > >>>>>> On 11.02.2020 12:42, H.J. Lu wrote: > > > > > >>>>>>> On Tue, Feb 11, 2020 at 2:25 AM Jan Beulich <jbeulich@suse.com> wrote: > > > > > >>>>>>>> > > > > > >>>>>>>> Some encodings are about to gain a warning - move them from test cases > > > > > >>>>>>>> not expecting any diagnostics to the new, dedicated ones, to allow > > > > > >>>>>>>> better focus on the actual changes in the subsequent patch. > > > > > >>>>>>>> > > > > > >>>>>>>> The new tests added have some wrong expectations right now, which will > > > > > >>>>>>>> be corrected by the next patch. The test is being added here to make > > > > > >>>>>>>> more visible which cases actually were wrong (and hence get changed), > > > > > >>>>>>>> besides demonstrating that in the vast majority of cases the subsequent > > > > > >>>>>>>> change doesn't alter generated code. > > > > > >>>>>>>> > > > > > >>>>>>>> gas/ > > > > > >>>>>>>> 2020-02-XX Jan Beulich <jbeulich@suse.com> > > > > > >>>>>>>> > > > > > >>>>>>>> * testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s, > > > > > >>>>>>>> testsuite/gas/i386/ilp32/x86-64.s: Move ambiguous operand size > > > > > >>>>>>>> tests ... > > > > > >>>>>>>> * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s, > > > > > >>>>>>>> testsuite/gas/i386/noreg64.s, testsuite/gas/i386/x86_64.s: ... > > > > > >>>>>>>> here. > > > > > >>>>>>>> * testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d > > > > > >>>>>>>> testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d, > > > > > >>>>>>>> testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d, > > > > > >>>>>>>> testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d, > > > > > >>>>>>>> testsuite/gas/i386/noreg64.d, testsuite/gas/i386/x86_64-intel.d, > > > > > >>>>>>>> testsuite/gas/i386/x86_64.d: Adjust expectations. > > > > > >>>>>>>> * testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l, > > > > > >>>>>>>> testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l, > > > > > >>>>>>>> testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New. > > > > > >>>>>>>> * testsuite/gas/i386/i386.exp: Run new tests. > > > > > >>>>>>> > > > > > >>>>>>> Please make a separate patch to address MOVSX/MOVZX. > > > > > >>>>>> > > > > > >>>>>> I don't understand what you mean here. This patch simply documents the > > > > > >>>>>> status quo, to make it (much) easier to see what the next patch > > > > > >>>>>> actually adjusts. It doesn't "address" anything. If, for the purpose > > > > > >>>>>> of committing, you'd like to see both patches folded - fine by me. But > > > > > >>>>>> only then, not any earlier. > > > > > >>>>>> > > > > > >>>>>>> MOVSX and MOVZX > > > > > >>>>>>> should take no suffixes. AT&T syntax is supported if there is no > > > > > >>>>>>> ambiguity. AT&T > > > > > >>>>>>> syntax also supports movsXY and movzXY. > > > > > >>>>>> > > > > > >>>>>> Please could you clarify what specifically you'd like to see changed, > > > > > >>>>>> at the very least by pointing out one case each where you think I'm > > > > > >>>>>> moving in the wrong direction (presumably in the next patch really)? > > > > > >>>>>> I'm afraid your response isn't such that I can derive from it what > > > > > >>>>>> exactly you want. > > > > > >>>>> > > > > > >>>>> We support > > > > > >>>>> > > > > > >>>>> movsx %ax, %ecx > > > > > >>>>> movzx %ax, %ecx > > > > > >>>>> movswl %ax, %ecx > > > > > >>>>> movzwl %ax, %ecx > > > > > >>>>> > > > > > >>>>> We disallow > > > > > >>>>> > > > > > >>>>> movsxw %ax, %ecx > > > > > >>>>> movzxw %ax, %ecx > > > > > >>>> > > > > > >>>> We don't (as this patch demonstrates, along with pre-existing tests, > > > > > >>>> unless you mean once again to have an inconsistency between insns > > > > > >>>> with all register operands and similar ones with e memory source), > > > > > >>>> and if you want it to be this way, then please do so yourself, but > > > > > >>> > > > > > >>> I will do it. > > > > > >>> > > > > > >>>> please also only on top of my changes, so I won't need to re-base > > > > > >>> > > > > > >>> Which changes of yours are you referring to? > > > > > >> > > > > > >> This patch and the subsequent one. > > > > > >> > > > > > > > > > > > > Both changes won't be necessary after my changes. > > > > > > > > > > I'm confused. What you want to deal with is - afaict - orthogonal to > > > > > what the next patch in the series here does. > > > > > > > > > > > > > You will see what I mean when I post my patch for review. > > > > > > > > > > AT&T syntax requires suffix to specify memory operand size. Since > > > movsx and movzx can have different memory operand sizes with the same > > > destination register, this patch removes movsx and movzx with memory > > > operand from AT&T syntax. Since AT&T syntax uses different mnemonics > > > for movsx and movzx, this change should have little impact on assembly > > > sources. Tested with Linux kernel 5.5.3 for x86-64 and glibc 2.31 for > > > i686 and x86-64. > > > > > > > Updated patch to add more testcases and allow register operand with > > mov[sz]x[bwl]. > > > > I found usage of > > movzx 4(%edx), %eax > > We also need to support: > > movsx 4(%edx), %eax > > I will update my patch. > > -- > H.J. Here is the updated patch. H.J. --- AT&T syntax requires suffix to specify memory operand size. Since movsx and movzx can have different memory operand sizes with the same destination register, this patch removes movsx and movzx with 16/32-bit memory operand from AT&T syntax. Now movzx and movsx with incorrect suffix and register are error in AT&T syntax. gas/ PR gas/25438 * config/tc-i386.c (md_assemble): Zap i.suffix with movzx and movsx only for the 'b' suffix or Intel syntax. (check_word_reg): Issue an error, not a warning, for incorrect suffix and register for movzx and movsx. * doc/c-i386.texi: Document movsx, movsxd and movzx for AT&T syntax. * testsuite/gas/i386/i386-intel.d: Updated. * testsuite/gas/i386/i386.d: Likewise. * testsuite/gas/i386/iamcu-1.d: Likewise. * testsuite/gas/i386/ilp32/x86-64.d: Likewise. * testsuite/gas/i386/k1om.d: Likewise. * testsuite/gas/i386/l1om.d: Likewise. * testsuite/gas/i386/x86_64-intel.d: Likewise. * testsuite/gas/i386/x86_64.d: Likewise. * testsuite/gas/i386/i386.exp: Run movszx-inval and x86-64-movszx-inval. * testsuite/gas/i386/i386.s: Add movsxb, movsxw, movsxl, movzxb, and movzxw tests with register operand in AT&T syntax. * testsuite/gas/i386/iamcu-1.s: Likewise. * testsuite/gas/i386/x86_64.s: Likewise. * testsuite/gas/i386/ilp32/x86-64.s: Likewise. * testsuite/gas/i386/movszx-inval.l: New file. * testsuite/gas/i386/movszx-inval.s: Likewise. * testsuite/gas/i386/x86-64-movszx-inval.l: Likewise. * testsuite/gas/i386/x86-64-movszx-inval.s: Likewise. opcodes/ PR gas/25438 * i386-opc.tbl: Remove movsx and movzx with 16/32-bit memory operand from AT&T syntax. Don't allow suffix with movsx nor movzx, except for 8-bit operand in AT&T syntax. Add movsxw, movsxl, movzxw for AT&T syntax. * i386-tbl.h: Regenerated. --- gas/config/tc-i386.c | 10 ++- gas/doc/c-i386.texi | 43 ++++++++++ gas/testsuite/gas/i386/i386-intel.d | 6 ++ gas/testsuite/gas/i386/i386.d | 6 ++ gas/testsuite/gas/i386/i386.exp | 2 + gas/testsuite/gas/i386/i386.s | 6 ++ gas/testsuite/gas/i386/iamcu-1.d | 6 ++ gas/testsuite/gas/i386/iamcu-1.s | 6 ++ gas/testsuite/gas/i386/ilp32/x86-64.d | 11 +++ gas/testsuite/gas/i386/ilp32/x86-64.s | 11 +++ gas/testsuite/gas/i386/k1om.d | 11 +++ gas/testsuite/gas/i386/l1om.d | 11 +++ gas/testsuite/gas/i386/movszx-inval.l | 66 +++++++++++++++ gas/testsuite/gas/i386/movszx-inval.s | 33 ++++++++ gas/testsuite/gas/i386/x86-64-movszx-inval.l | 86 ++++++++++++++++++++ gas/testsuite/gas/i386/x86-64-movszx-inval.s | 43 ++++++++++ gas/testsuite/gas/i386/x86_64-intel.d | 11 +++ gas/testsuite/gas/i386/x86_64.d | 11 +++ gas/testsuite/gas/i386/x86_64.s | 11 +++ opcodes/i386-opc.tbl | 23 +++--- opcodes/i386-tbl.h | 72 ++++++++++++---- 21 files changed, 457 insertions(+), 28 deletions(-) create mode 100644 gas/testsuite/gas/i386/movszx-inval.l create mode 100644 gas/testsuite/gas/i386/movszx-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-movszx-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-movszx-inval.s diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index fec132ab760..69c05561ed1 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -4395,7 +4395,9 @@ md_assemble (char *line) && intel_syntax) as_bad (_("ambiguous operand size for `%s'"), i.tm.name); - i.suffix = 0; + /* movzx and movsx only allow the 'b' suffix in AT&T syntax. */ + if (i.suffix == BYTE_MNEM_SUFFIX || intel_syntax) + i.suffix = 0; } if (i.tm.opcode_modifier.fwait) @@ -6826,8 +6828,10 @@ check_word_reg (void) && i.tm.operand_types[op].bitfield.word) { /* Prohibit these changes in the 64bit mode, since the - lowering is more complicated. */ - if (flag_code == CODE_64BIT) + lowering is more complicated. FIXME: This should be + an error for all. */ + if (flag_code == CODE_64BIT + || (i.tm.base_opcode & ~9) == 0x0fb6) { as_bad (_("incorrect register `%s%s' used with `%c' suffix"), register_prefix, i.op[op].regs->reg_name, diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index f0189ccb443..9682a48d074 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -835,6 +835,49 @@ are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these instructions. +@cindex extension instructions, i386 +@cindex i386 extension instructions +@cindex extension instructions, x86-64 +@cindex x86-64 extension instructions +The Intel-syntax extension instructions + +@itemize @bullet +@item +@samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg16}. + +@samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg32}. + +@samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg64} +(x86-64 only). + +@samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg32} + +@samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg64} +(x86-64 only). + +@samp{movsxd} --- sign-extend @samp{reg32/mem32} to @samp{reg64} +(x86-64 only). + +@samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg16}. + +@samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg32}. + +@samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg64} +(x86-64 only). + +@samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg32} + +@samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg64} +(x86-64 only). +@end itemize + +@noindent +are called @samp{movsbw/movsxb/movsx}, @samp{movsbl/movsxb/movsx}, +@samp{movsbq/movsb/movsx}, @samp{movswl/movsxw}, @samp{movswq/movsxw}, +@samp{movslq/movsxl}, @samp{movzbw/movzxb/movzx}, +@samp{movzbl/movzxb/movzx}, @samp{movzbq/movzxb/movzx}, +@samp{movzwl/movzxw} and @samp{movzwq/movzxw} in AT&T syntax. + @cindex jump instructions, i386 @cindex call instructions, i386 @cindex jump instructions, x86-64 diff --git a/gas/testsuite/gas/i386/i386-intel.d b/gas/testsuite/gas/i386/i386-intel.d index 1913e8da191..27fc83062a1 100644 --- a/gas/testsuite/gas/i386/i386-intel.d +++ b/gas/testsuite/gas/i386/i386-intel.d @@ -14,6 +14,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f be f0 movsx si,al [ ]*[a-f0-9]+: 0f be f0 movsx esi,al [ ]*[a-f0-9]+: 0f bf f0 movsx esi,ax +[ ]*[a-f0-9]+: 66 0f be f0 movsx si,al +[ ]*[a-f0-9]+: 0f be f0 movsx esi,al +[ ]*[a-f0-9]+: 0f bf f0 movsx esi,ax [ ]*[a-f0-9]+: 0f be 10 movsx edx,BYTE PTR \[eax\] [ ]*[a-f0-9]+: 66 0f be 10 movsx dx,BYTE PTR \[eax\] [ ]*[a-f0-9]+: 66 0f be 10 movsx dx,BYTE PTR \[eax\] @@ -25,6 +28,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f b6 f0 movzx si,al [ ]*[a-f0-9]+: 0f b6 f0 movzx esi,al [ ]*[a-f0-9]+: 0f b7 f0 movzx esi,ax +[ ]*[a-f0-9]+: 66 0f b6 f0 movzx si,al +[ ]*[a-f0-9]+: 0f b6 f0 movzx esi,al +[ ]*[a-f0-9]+: 0f b7 f0 movzx esi,ax [ ]*[a-f0-9]+: 0f b6 10 movzx edx,BYTE PTR \[eax\] [ ]*[a-f0-9]+: 66 0f b6 10 movzx dx,BYTE PTR \[eax\] [ ]*[a-f0-9]+: 66 0f b6 10 movzx dx,BYTE PTR \[eax\] diff --git a/gas/testsuite/gas/i386/i386.d b/gas/testsuite/gas/i386/i386.d index 1c6c4cc3fd5..5d967ac8fe3 100644 --- a/gas/testsuite/gas/i386/i386.d +++ b/gas/testsuite/gas/i386/i386.d @@ -13,6 +13,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi [ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi +[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi +[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi [ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx @@ -24,6 +27,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si [ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi [ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi +[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si +[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi +[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index c4280417c58..40154f39c9c 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -491,6 +491,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_list_test "inval-pseudo" "-al" run_dump_test "nop-1" run_dump_test "nop-2" + run_list_test "movszx-inval" "-al" run_dump_test "optimize-1" run_dump_test "optimize-1a" run_dump_test "optimize-2" @@ -1052,6 +1053,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_dump_test "x86-64-movd-intel" run_dump_test "x86-64-nop-1" run_dump_test "x86-64-nop-2" + run_list_test "x86-64-movszx-inval" "-al" run_dump_test "x86-64-movsxd" run_dump_test "x86-64-movsxd-intel" run_list_test "x86-64-movsxd-inval" "-al" diff --git a/gas/testsuite/gas/i386/i386.s b/gas/testsuite/gas/i386/i386.s index 7da361f5f85..8812a18814a 100644 --- a/gas/testsuite/gas/i386/i386.s +++ b/gas/testsuite/gas/i386/i386.s @@ -9,6 +9,9 @@ movsx %al, %si movsx %al, %esi movsx %ax, %esi + movsxb %al, %si + movsxb %al, %esi + movsxw %ax, %esi movsx (%eax), %edx movsx (%eax), %dx movsxb (%eax), %dx @@ -21,6 +24,9 @@ movzx %al, %si movzx %al, %esi movzx %ax, %esi + movzxb %al, %si + movzxb %al, %esi + movzxw %ax, %esi movzx (%eax), %edx movzx (%eax), %dx movzxb (%eax), %dx diff --git a/gas/testsuite/gas/i386/iamcu-1.d b/gas/testsuite/gas/i386/iamcu-1.d index 2b1df5de4b7..aad623adc55 100644 --- a/gas/testsuite/gas/i386/iamcu-1.d +++ b/gas/testsuite/gas/i386/iamcu-1.d @@ -10,6 +10,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi [ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi +[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi +[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi [ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx @@ -21,6 +24,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si [ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi [ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi +[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si +[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi +[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx diff --git a/gas/testsuite/gas/i386/iamcu-1.s b/gas/testsuite/gas/i386/iamcu-1.s index b631dfa17ef..fc33c73c745 100644 --- a/gas/testsuite/gas/i386/iamcu-1.s +++ b/gas/testsuite/gas/i386/iamcu-1.s @@ -4,6 +4,9 @@ movsx %al, %si movsx %al, %esi movsx %ax, %esi + movsxb %al, %si + movsxb %al, %esi + movsxw %ax, %esi movsx (%eax), %edx movsx (%eax), %dx movsxb (%eax), %dx @@ -16,6 +19,9 @@ movzx %al, %si movzx %al, %esi movzx %ax, %esi + movzxb %al, %si + movzxb %al, %esi + movzxw %ax, %esi movzx (%eax), %edx movzx (%eax), %dx movzxb (%eax), %dx diff --git a/gas/testsuite/gas/i386/ilp32/x86-64.d b/gas/testsuite/gas/i386/ilp32/x86-64.d index 33722c90f9c..f58b3ba8546 100644 --- a/gas/testsuite/gas/i386/ilp32/x86-64.d +++ b/gas/testsuite/gas/i386/ilp32/x86-64.d @@ -162,6 +162,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi [ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi [ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi +[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi +[ ]*[a-f0-9]+: 48 0f be f0 movsbq %al,%rsi +[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi +[ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi +[ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi [ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx @@ -175,6 +181,11 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi [ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi [ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi +[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si +[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi +[ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi +[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi +[ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx diff --git a/gas/testsuite/gas/i386/ilp32/x86-64.s b/gas/testsuite/gas/i386/ilp32/x86-64.s index d1f7ae3b495..c6015947cb9 100644 --- a/gas/testsuite/gas/i386/ilp32/x86-64.s +++ b/gas/testsuite/gas/i386/ilp32/x86-64.s @@ -194,6 +194,12 @@ cmpxchg16b oword ptr [rax] movsx %ax, %esi movsx %ax, %rsi movsx %eax, %rsi + movsxb %al, %si + movsxb %al, %esi + movsxb %al, %rsi + movsxw %ax, %esi + movsxw %ax, %rsi + movsxl %eax, %rsi movsx (%rax), %edx movsx (%rax), %rdx movsx (%rax), %dx @@ -208,6 +214,11 @@ cmpxchg16b oword ptr [rax] movzx %al, %rsi movzx %ax, %esi movzx %ax, %rsi + movzxb %al, %si + movzxb %al, %esi + movzxb %al, %rsi + movzxw %ax, %esi + movzxw %ax, %rsi movzx (%rax), %edx movzx (%rax), %rdx movzx (%rax), %dx diff --git a/gas/testsuite/gas/i386/k1om.d b/gas/testsuite/gas/i386/k1om.d index 7767f5b4188..617e5275bcd 100644 --- a/gas/testsuite/gas/i386/k1om.d +++ b/gas/testsuite/gas/i386/k1om.d @@ -175,6 +175,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi [ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi [ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi +[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi +[ ]*[a-f0-9]+: 48 0f be f0 movsbq %al,%rsi +[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi +[ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi +[ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi [ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx @@ -188,6 +194,11 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi [ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi [ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi +[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si +[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi +[ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi +[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi +[ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx diff --git a/gas/testsuite/gas/i386/l1om.d b/gas/testsuite/gas/i386/l1om.d index 858d1827f92..8c279dcfb2c 100644 --- a/gas/testsuite/gas/i386/l1om.d +++ b/gas/testsuite/gas/i386/l1om.d @@ -175,6 +175,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi [ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi [ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi +[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi +[ ]*[a-f0-9]+: 48 0f be f0 movsbq %al,%rsi +[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi +[ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi +[ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi [ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx @@ -188,6 +194,11 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi [ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi [ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi +[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si +[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi +[ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi +[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi +[ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx diff --git a/gas/testsuite/gas/i386/movszx-inval.l b/gas/testsuite/gas/i386/movszx-inval.l new file mode 100644 index 00000000000..bb6b48963fd --- /dev/null +++ b/gas/testsuite/gas/i386/movszx-inval.l @@ -0,0 +1,66 @@ +.*: Assembler messages: +.*:4: Error: .* +.*:5: Error: .* +.*:6: Error: .* +.*:7: Error: .* +.*:8: Error: .* +.*:9: Error: .* +.*:10: Error: .* +.*:11: Error: .* +.*:12: Error: .* +.*:13: Error: .* +.*:14: Error: .* +.*:15: Error: .* +.*:16: Error: .* +.*:17: Error: .* +.*:18: Error: .* +.*:19: Error: .* +.*:20: Error: .* +.*:21: Error: .* +.*:22: Error: .* +.*:23: Error: .* +.*:24: Error: .* +.*:25: Error: .* +.*:28: Error: .* +.*:29: Error: .* +.*:30: Error: .* +.*:31: Error: .* +.*:32: Error: .* +.*:33: Error: .* +GAS LISTING .* + + +[ ]*1[ ]+\# Invalid 32-bit movsx and movzx\. +[ ]*2[ ]+\.text +[ ]*3[ ]+_start: +[ ]*4[ ]+movsbw %al, %ecx +[ ]*5[ ]+movsbl %al, %cx +[ ]*6[ ]+movsbw %al, %ecx +[ ]*7[ ]+movsbw %al, %ecx +[ ]*8[ ]+movsbl %al, %cx +[ ]*9[ ]+movsbw %al, %ecx +[ ]*10[ ]+movsbw %al, %ecx +[ ]*11[ ]+movsbl %al, %cx +[ ]*12[ ]+movsbq %al, %cx +[ ]*13[ ]+movsbq %al, %ecx +[ ]*14[ ]+movswq %ax, %ecx +[ ]*15[ ]+movzbw %al, %ecx +[ ]*16[ ]+movzbl %al, %cx +[ ]*17[ ]+movzbw %al, %ecx +[ ]*18[ ]+movzbw %al, %ecx +[ ]*19[ ]+movzbl %al, %cx +[ ]*20[ ]+movzbw %al, %ecx +[ ]*21[ ]+movzbw %al, %ecx +[ ]*22[ ]+movzbl %al, %cx +[ ]*23[ ]+movzbq %al, %cx +[ ]*24[ ]+movzbq %al, %ecx +[ ]*25[ ]+movzwq %ax, %ecx +[ ]*26[ ]+ +[ ]*27[ ]+\.intel_syntax noprefix +[ ]*28[ ]+movsxb ax, BYTE PTR \[eax\] +[ ]*29[ ]+movsxb eax, BYTE PTR \[eax\] +[ ]*30[ ]+movsxw eax, WORD PTR \[eax\] +[ ]*31[ ]+movzxb ax, BYTE PTR \[eax\] +[ ]*32[ ]+movzxb eax, BYTE PTR \[eax\] +[ ]*33[ ]+movzxw eax, WORD PTR \[eax\] +#pass diff --git a/gas/testsuite/gas/i386/movszx-inval.s b/gas/testsuite/gas/i386/movszx-inval.s new file mode 100644 index 00000000000..7e10f736be0 --- /dev/null +++ b/gas/testsuite/gas/i386/movszx-inval.s @@ -0,0 +1,33 @@ +# Invalid 32-bit movsx and movzx. + .text +_start: + movsbw %al, %ecx + movsbl %al, %cx + movsbw %al, %ecx + movsbw %al, %ecx + movsbl %al, %cx + movsbw %al, %ecx + movsbw %al, %ecx + movsbl %al, %cx + movsbq %al, %cx + movsbq %al, %ecx + movswq %ax, %ecx + movzbw %al, %ecx + movzbl %al, %cx + movzbw %al, %ecx + movzbw %al, %ecx + movzbl %al, %cx + movzbw %al, %ecx + movzbw %al, %ecx + movzbl %al, %cx + movzbq %al, %cx + movzbq %al, %ecx + movzwq %ax, %ecx + + .intel_syntax noprefix + movsxb ax, BYTE PTR [eax] + movsxb eax, BYTE PTR [eax] + movsxw eax, WORD PTR [eax] + movzxb ax, BYTE PTR [eax] + movzxb eax, BYTE PTR [eax] + movzxw eax, WORD PTR [eax] diff --git a/gas/testsuite/gas/i386/x86-64-movszx-inval.l b/gas/testsuite/gas/i386/x86-64-movszx-inval.l new file mode 100644 index 00000000000..fdb149425be --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-movszx-inval.l @@ -0,0 +1,86 @@ +.*: Assembler messages: +.*:4: Error: .* +.*:5: Error: .* +.*:6: Error: .* +.*:7: Error: .* +.*:8: Error: .* +.*:9: Error: .* +.*:10: Error: .* +.*:11: Error: .* +.*:12: Error: .* +.*:13: Error: .* +.*:14: Error: .* +.*:15: Error: .* +.*:16: Error: .* +.*:17: Error: .* +.*:18: Error: .* +.*:19: Error: .* +.*:20: Error: .* +.*:21: Error: .* +.*:22: Error: .* +.*:23: Error: .* +.*:24: Error: .* +.*:25: Error: .* +.*:26: Error: .* +.*:27: Error: .* +.*:28: Error: .* +.*:29: Error: .* +.*:30: Error: .* +.*:31: Error: .* +.*:34: Error: .* +.*:35: Error: .* +.*:36: Error: .* +.*:37: Error: .* +.*:38: Error: .* +.*:39: Error: .* +.*:40: Error: .* +.*:41: Error: .* +.*:42: Error: .* +.*:43: Error: .* +GAS LISTING .* + + +[ ]*1[ ]+\# Invalid 64-bit movsx and movzx\. +[ ]*2[ ]+\.text +[ ]*3[ ]+_start: +[ ]*4[ ]+movsbw %al, %ecx +[ ]*5[ ]+movsbl %al, %cx +[ ]*6[ ]+movsbw %al, %ecx +[ ]*7[ ]+movsbw %al, %ecx +[ ]*8[ ]+movsbl %al, %cx +[ ]*9[ ]+movsbw %al, %ecx +[ ]*10[ ]+movsbw %al, %ecx +[ ]*11[ ]+movsbw %al, %rcx +[ ]*12[ ]+movsbl %al, %cx +[ ]*13[ ]+movsbl %al, %rcx +[ ]*14[ ]+movsbq %al, %cx +[ ]*15[ ]+movsbq %al, %ecx +[ ]*16[ ]+movswl %ax, %rcx +[ ]*17[ ]+movswq %ax, %ecx +[ ]*18[ ]+movzbw %al, %ecx +[ ]*19[ ]+movzbl %al, %cx +[ ]*20[ ]+movzbw %al, %ecx +[ ]*21[ ]+movzbw %al, %ecx +[ ]*22[ ]+movzbl %al, %cx +[ ]*23[ ]+movzbw %al, %ecx +[ ]*24[ ]+movzbw %al, %ecx +[ ]*25[ ]+movzbw %al, %rcx +[ ]*26[ ]+movzbl %al, %cx +[ ]*27[ ]+movzbl %al, %rcx +[ ]*28[ ]+movzbq %al, %cx +[ ]*29[ ]+movzbq %al, %ecx +[ ]*30[ ]+movzwl %ax, %rcx +[ ]*31[ ]+movzwq %ax, %ecx +[ ]*32[ ]+ +[ ]*33[ ]+\.intel_syntax noprefix +[ ]*34[ ]+movsxb ax, BYTE PTR \[rax\] +[ ]*35[ ]+movsxb eax, BYTE PTR \[rax\] +[ ]*36[ ]+movsxb rax, BYTE PTR \[rax\] +[ ]*37[ ]+movsxw eax, WORD PTR \[rax\] +[ ]*38[ ]+movsxw rax, WORD PTR \[rax\] +[ ]*39[ ]+movzxb ax, BYTE PTR \[rax\] +[ ]*40[ ]+movzxb eax, BYTE PTR \[rax\] +[ ]*41[ ]+movzxb rax, BYTE PTR \[rax\] +[ ]*42[ ]+movzxw eax, WORD PTR \[rax\] +[ ]*43[ ]+movzxw rax, WORD PTR \[rax\] +#pass diff --git a/gas/testsuite/gas/i386/x86-64-movszx-inval.s b/gas/testsuite/gas/i386/x86-64-movszx-inval.s new file mode 100644 index 00000000000..81b6d11bb44 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-movszx-inval.s @@ -0,0 +1,43 @@ +# Invalid 64-bit movsx and movzx. + .text +_start: + movsbw %al, %ecx + movsbl %al, %cx + movsbw %al, %ecx + movsbw %al, %ecx + movsbl %al, %cx + movsbw %al, %ecx + movsbw %al, %ecx + movsbw %al, %rcx + movsbl %al, %cx + movsbl %al, %rcx + movsbq %al, %cx + movsbq %al, %ecx + movswl %ax, %rcx + movswq %ax, %ecx + movzbw %al, %ecx + movzbl %al, %cx + movzbw %al, %ecx + movzbw %al, %ecx + movzbl %al, %cx + movzbw %al, %ecx + movzbw %al, %ecx + movzbw %al, %rcx + movzbl %al, %cx + movzbl %al, %rcx + movzbq %al, %cx + movzbq %al, %ecx + movzwl %ax, %rcx + movzwq %ax, %ecx + + .intel_syntax noprefix + movsxb ax, BYTE PTR [rax] + movsxb eax, BYTE PTR [rax] + movsxb rax, BYTE PTR [rax] + movsxw eax, WORD PTR [rax] + movsxw rax, WORD PTR [rax] + movzxb ax, BYTE PTR [rax] + movzxb eax, BYTE PTR [rax] + movzxb rax, BYTE PTR [rax] + movzxw eax, WORD PTR [rax] + movzxw rax, WORD PTR [rax] diff --git a/gas/testsuite/gas/i386/x86_64-intel.d b/gas/testsuite/gas/i386/x86_64-intel.d index 8dd8893e79a..f66785ab78e 100644 --- a/gas/testsuite/gas/i386/x86_64-intel.d +++ b/gas/testsuite/gas/i386/x86_64-intel.d @@ -173,6 +173,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f bf f0 movsx esi,ax [ ]*[a-f0-9]+: 48 0f bf f0 movsx rsi,ax [ ]*[a-f0-9]+: 48 63 f0 movsxd rsi,eax +[ ]*[a-f0-9]+: 66 0f be f0 movsx si,al +[ ]*[a-f0-9]+: 0f be f0 movsx esi,al +[ ]*[a-f0-9]+: 48 0f be f0 movsx rsi,al +[ ]*[a-f0-9]+: 0f bf f0 movsx esi,ax +[ ]*[a-f0-9]+: 48 0f bf f0 movsx rsi,ax +[ ]*[a-f0-9]+: 48 63 f0 movsxd rsi,eax [ ]*[a-f0-9]+: 0f be 10 movsx edx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 48 0f be 10 movsx rdx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 66 0f be 10 movsx dx,BYTE PTR \[rax\] @@ -186,6 +192,11 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f b6 f0 movzx rsi,al [ ]*[a-f0-9]+: 0f b7 f0 movzx esi,ax [ ]*[a-f0-9]+: 48 0f b7 f0 movzx rsi,ax +[ ]*[a-f0-9]+: 66 0f b6 f0 movzx si,al +[ ]*[a-f0-9]+: 0f b6 f0 movzx esi,al +[ ]*[a-f0-9]+: 48 0f b6 f0 movzx rsi,al +[ ]*[a-f0-9]+: 0f b7 f0 movzx esi,ax +[ ]*[a-f0-9]+: 48 0f b7 f0 movzx rsi,ax [ ]*[a-f0-9]+: 0f b6 10 movzx edx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 48 0f b6 10 movzx rdx,BYTE PTR \[rax\] [ ]*[a-f0-9]+: 66 0f b6 10 movzx dx,BYTE PTR \[rax\] diff --git a/gas/testsuite/gas/i386/x86_64.d b/gas/testsuite/gas/i386/x86_64.d index 0bdbc79021a..72ed23aa4ba 100644 --- a/gas/testsuite/gas/i386/x86_64.d +++ b/gas/testsuite/gas/i386/x86_64.d @@ -173,6 +173,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi [ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi [ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi +[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi +[ ]*[a-f0-9]+: 48 0f be f0 movsbq %al,%rsi +[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi +[ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi +[ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi [ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx @@ -186,6 +192,11 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi [ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi [ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi +[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si +[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi +[ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi +[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi +[ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi [ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx [ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx [ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx diff --git a/gas/testsuite/gas/i386/x86_64.s b/gas/testsuite/gas/i386/x86_64.s index 377580be341..b8dfafbcd53 100644 --- a/gas/testsuite/gas/i386/x86_64.s +++ b/gas/testsuite/gas/i386/x86_64.s @@ -208,6 +208,12 @@ cmpxchg16b oword ptr [rax] movsx %ax, %esi movsx %ax, %rsi movsx %eax, %rsi + movsxb %al, %si + movsxb %al, %esi + movsxb %al, %rsi + movsxw %ax, %esi + movsxw %ax, %rsi + movsxl %eax, %rsi movsx (%rax), %edx movsx (%rax), %rdx movsx (%rax), %dx @@ -222,6 +228,11 @@ cmpxchg16b oword ptr [rax] movzx %al, %rsi movzx %ax, %esi movzx %ax, %rsi + movzxb %al, %si + movzxb %al, %esi + movzxb %al, %rsi + movzxw %ax, %esi + movzxw %ax, %rsi movzx (%rax), %edx movzx (%rax), %rdx movzx (%rax), %dx diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index d805e6916a1..3c4d67baf1e 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -132,13 +132,15 @@ movswl, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf movsbq, 2, 0xfbe, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg8|Byte|Unspecified|BaseIndex, Reg64 } movswq, 2, 0xfbf, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg16|Word|Unspecified|BaseIndex, Reg64 } movslq, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg32|Dword|Unspecified|BaseIndex, Reg64 } -// Intel Syntax next 3 insns movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 } -movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|ATTSyntax, { Reg32|Unspecified|BaseIndex, Reg64 } -movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg8|Byte|BaseIndex, Reg16|Reg32|Reg64 } -movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex, Reg32|Reg64 } -movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|IntelSyntax, { Reg32|Dword|BaseIndex, Reg64 } +movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16, Reg32|Reg64 } +movsxw, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 } +movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg32, Reg64 } +movsxl, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg32|Unspecified|BaseIndex, Reg64 } +// Intel Syntax next 3 insns +movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg8|Byte|BaseIndex, Reg16|Reg32|Reg64 } +movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex, Reg32|Reg64 } +movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|IntelSyntax, { Reg32|Dword|BaseIndex, Reg64 } movsxd, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 } movsxd, 2, 0x63, None, 1, Cpu64, Amd64|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg16 } movsxd, 2, 0x63, None, 1, Cpu64, Intel64|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Unspecified|BaseIndex, Reg16 } @@ -146,12 +148,13 @@ movsxd, 2, 0x63, None, 1, Cpu64, Intel64|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N // Move with zero extend. movzb, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } movzw, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32|Reg64 } +movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16, Reg32|Reg64 } +movzxw, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 } // Intel Syntax next 2 insns (the 64-bit variants are not particulary // useful since the zero extend 32->64 is implicit, but we can encode them). -movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 } -movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg8|Byte|BaseIndex, Reg16|Reg32|Reg64 } -movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex, Reg32|Reg64 } +movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg8|Byte|BaseIndex, Reg16|Reg32|Reg64 } +movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex, Reg32|Reg64 } // Push instructions. push, 1, 0x50, None, 1, CpuNo64, No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 } ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH] x86: Remove movsx/movzx with 16/32-bit memory operand from AT&T syntax 2020-02-12 3:19 ` [PATCH] x86: Remove movsx/movzx with 16/32-bit " H.J. Lu @ 2020-02-12 9:19 ` Jan Beulich 0 siblings, 0 replies; 26+ messages in thread From: Jan Beulich @ 2020-02-12 9:19 UTC (permalink / raw) To: H.J. Lu; +Cc: binutils On 12.02.2020 04:19, H.J. Lu wrote: > AT&T syntax requires suffix to specify memory operand size. Since > movsx and movzx can have different memory operand sizes with the same > destination register, this patch removes movsx and movzx with 16/32-bit > memory operand from AT&T syntax. Now movzx and movsx with incorrect > suffix and register are error in AT&T syntax. Before we discuss this patch in detail, I think we need to come to an agreement what is and what is not meant to be permitted. My position of this is shown by the final shape of the new tests that the series at the root of this thread first adds and then adjusts. It was for this very reason why I had asked that you please point out specifically against the two patches you put under question what you think is wrong once those patches would be in place. What you say above makes no sense to me at all: Why would you remove support for something that's supposed to work? You know my underlying thinking - things should be as consistent as possible. What you do here moves us farther away from consistency. This is demonstrated by both increasing the number of templates (whereas my proposed patch shrinks them) as well as ... > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -4395,7 +4395,9 @@ md_assemble (char *line) > && intel_syntax) > as_bad (_("ambiguous operand size for `%s'"), i.tm.name); > > - i.suffix = 0; > + /* movzx and movsx only allow the 'b' suffix in AT&T syntax. */ > + if (i.suffix == BYTE_MNEM_SUFFIX || intel_syntax) > + i.suffix = 0; > } ... a change like this. Recall that mine does away with this rather arbitrary check here altogether, putting in place less arbitrary (imo) checks/adjustments elsewhere instead? While secondary, I also get the impression that, other than my patch again, and in contrast to the adjustments recently done for MOVSXD, the (not very useful) form having 16-bit source and destination doesn't get supported by this change. Which underlines what I've said initially: There first of all needs to be a clear (and consistent) picture of what is or is not supposed to work. Jan ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v5 4/5] x86: correct VFPCLASSP{S,D} operand size handling 2020-02-11 10:23 [PATCH v5 0/5] x86: operand size handling improvements Jan Beulich ` (2 preceding siblings ...) 2020-02-11 10:25 ` [PATCH v5 2/5] x86: move certain MOVSX/MOVZX tests Jan Beulich @ 2020-02-11 10:26 ` Jan Beulich 2020-02-11 11:50 ` H.J. Lu 2020-02-11 10:27 ` [PATCH v5 5/5] x86-64: Intel64 adjustments for insns dealing with far pointers Jan Beulich 4 siblings, 1 reply; 26+ messages in thread From: Jan Beulich @ 2020-02-11 10:26 UTC (permalink / raw) To: binutils; +Cc: H.J. Lu With AVX512VL disabled (e.g. when writing code for the Knights family of processors) these insns aren't ambiguous when used with a memory source, and hence should be accepted without suffix or operand size specifier. When AVX512VL is enabled, to be consistent with this as well as other ambiguous operand size handling it would seem better to just warn about the ambiguity in AT&T mode, and still default to 512-bit operands (on the assumption that the code may have been written without AVX512VL in mind yet), but it was requested to leave AT&T syntax mode alone here. gas/ 2020-02-XX Jan Beulich <jbeulich@suse.com> * config/tc-i386.c (avx512): New (at file scope), moved from (check_VecOperands): ... here. (process_suffix): Add [XYZ]MMword operand size handling. * testsuite/gas/i386/avx512dq-inval.s: Add VFPCLASS tests. * testsuite/gas/i386/noavx512-2.s: Add Intel syntax VFPCLASS tests. * testsuite/gas/i386/avx512dq-inval.l, testsuite/gas/i386/noavx512-2.l: Adjust expectations. opcodes/ 2020-02-XX Jan Beulich <jbeulich@suse.com> * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form with Unspecified, making the present one AT&T syntax only. * i386-tbl.h: Re-generate. --- v5: Re-base. v4: Restrict to just Intel syntax mode. Re-base. v3: Re-base. --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1840,6 +1840,8 @@ cpu_flags_and_not (i386_cpu_flags x, i38 return x; } +static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; + #define CPU_FLAGS_ARCH_MATCH 0x1 #define CPU_FLAGS_64BIT_MATCH 0x2 @@ -5352,7 +5354,6 @@ check_VecOperands (const insn_template * { unsigned int op; i386_cpu_flags cpu; - static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; /* Templates allowing for ZMMword as well as YMMword and/or XMMword for any one operand are implicity requiring AVX512VL support if the actual @@ -6447,7 +6448,8 @@ process_suffix (void) /* Accept FLDENV et al without suffix. */ && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf)) { - unsigned int suffixes; + unsigned int suffixes, evex = 0; + i386_cpu_flags cpu; suffixes = !i.tm.opcode_modifier.no_bsuf; if (!i.tm.opcode_modifier.no_wsuf) @@ -6461,7 +6463,55 @@ process_suffix (void) if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) suffixes |= 1 << 5; - /* Are multiple suffixes allowed? */ + /* For [XYZ]MMWORD operands inspect operand sizes. */ + cpu = cpu_flags_and (i.tm.cpu_flags, avx512); + if (!cpu_flags_all_zero (&cpu) && !i.broadcast) + { + unsigned int op; + + for (op = 0; op < i.tm.operands; ++op) + { + if (!cpu_arch_flags.bitfield.cpuavx512vl) + { + if (i.tm.operand_types[op].bitfield.ymmword) + i.tm.operand_types[op].bitfield.xmmword = 0; + if (i.tm.operand_types[op].bitfield.zmmword) + i.tm.operand_types[op].bitfield.ymmword = 0; + if (!i.tm.opcode_modifier.evex + || i.tm.opcode_modifier.evex == EVEXDYN) + i.tm.opcode_modifier.evex = EVEX512; + } + + if (i.tm.operand_types[op].bitfield.xmmword + + i.tm.operand_types[op].bitfield.ymmword + + i.tm.operand_types[op].bitfield.zmmword < 2) + continue; + + /* Any properly sized operand disambiguates the insn. */ + if (i.types[op].bitfield.xmmword + || i.types[op].bitfield.ymmword + || i.types[op].bitfield.zmmword) + { + suffixes &= ~(7 << 6); + evex = 0; + break; + } + + if ((i.flags[op] & Operand_Mem) + && i.tm.operand_types[op].bitfield.unspecified) + { + if (i.tm.operand_types[op].bitfield.xmmword) + suffixes |= 1 << 6; + if (i.tm.operand_types[op].bitfield.ymmword) + suffixes |= 1 << 7; + if (i.tm.operand_types[op].bitfield.zmmword) + suffixes |= 1 << 8; + evex = EVEX512; + } + } + } + + /* Are multiple suffixes / operand sizes allowed? */ if (suffixes & (suffixes - 1)) { if (intel_syntax @@ -6491,6 +6541,8 @@ process_suffix (void) || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64)) /* handled below */; + else if (evex) + i.tm.opcode_modifier.evex = evex; else if (flag_code == CODE_16BIT) i.suffix = WORD_MNEM_SUFFIX; else if (!i.tm.opcode_modifier.no_lsuf) --- a/gas/testsuite/gas/i386/avx512dq-inval.l +++ b/gas/testsuite/gas/i386/avx512dq-inval.l @@ -11,3 +11,7 @@ .*:[0-9]*: Error:.* `vpinsrq' .* .*:[0-9]*: Error:.* `vpinsrq' .* .*:[0-9]*: Error:.* `vpinsrq' .* +.*:[0-9]*: Error:.* `vfpclasspd' +.*:[0-9]*: Error:.* `vfpclassps' +.*:[0-9]*: Error:.* `vfpclasspd' +.*:[0-9]*: Error:.* `vfpclassps' --- a/gas/testsuite/gas/i386/avx512dq-inval.s +++ b/gas/testsuite/gas/i386/avx512dq-inval.s @@ -1,4 +1,4 @@ -# Check AVX512DQ instructions not to be accepted outside of 64-bit mode +# Check AVX512DQ instructions not to be accepted (in part only outside of 64-bit mode) .text _start: @@ -20,3 +20,10 @@ _start: vpinsrq xmm0, xmm0, qword ptr [eax], 0 {evex} vpinsrq xmm0, xmm0, qword ptr [eax], 0 + vfpclasspd k0, [eax], 0 + vfpclassps k0, [eax], 0 + + .att_syntax prefix + + vfpclasspd $0, (%eax), %k0 + vfpclassps $0, (%eax), %k0 --- a/gas/testsuite/gas/i386/noavx512-2.l +++ b/gas/testsuite/gas/i386/noavx512-2.l @@ -101,5 +101,10 @@ GAS LISTING .* [ ]*50[ ]+F5 [ ]*51[ ]+\?\?\?\? 660F58F4 addpd %xmm4, %xmm6 [ ]*52[ ]+ -[ ]*53[ ]+\?\?\?\? 0F1F00 \.p2align 4 +[ ]*[1-9][0-9]*[ ]+\.intel_syntax noprefix +[ ]*[1-9][0-9]*[ ]+\?\?\?\? 62F3FD48 vfpclasspd k0, \[eax], 0 +[ ]*[1-9][0-9]*[ ]+660000 +[ ]*[1-9][0-9]*[ ]+\?\?\?\? 62F37D48 vfpclassps k0, \[eax], 0 +[ ]*[1-9][0-9]*[ ]+660000 +[ ]*[1-9][0-9]*[ ]+ #pass --- a/gas/testsuite/gas/i386/noavx512-2.s +++ b/gas/testsuite/gas/i386/noavx512-2.s @@ -50,4 +50,8 @@ pabsb %xmm5, %xmm6 addpd %xmm4, %xmm6 + .intel_syntax noprefix + vfpclasspd k0, [eax], 0 + vfpclassps k0, [eax], 0 + .p2align 4 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -4504,12 +4504,14 @@ vextracti64x2, 3, 0x6639, None, 1, CpuAV vinsertf64x2, 4, 0x6618, None, 1, CpuAVX512DQ, Modrm|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } vinserti64x2, 4, 0x6638, None, 1, CpuAVX512DQ, Modrm|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vfpclasspd, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|BaseIndex, RegMask } +vfpclasspd, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Imm8, RegXMM|RegYMM|RegZMM|Qword|BaseIndex, RegMask } +vfpclasspd, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegMask } vfpclasspdz, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|Qword|Unspecified|BaseIndex, RegMask } vfpclasspdx, 3, 0x6666, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegMask } vfpclasspdy, 3, 0x6666, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|Unspecified|BaseIndex, RegMask } -vfpclassps, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|BaseIndex, RegMask } +vfpclassps, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Imm8, RegXMM|RegYMM|RegZMM|Dword|BaseIndex, RegMask } +vfpclassps, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegMask } vfpclasspsz, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|Dword|Unspecified|BaseIndex, RegMask } vfpclasspsx, 3, 0x6666, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegMask } vfpclasspsy, 3, 0x6666, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Dword|Unspecified|BaseIndex, RegMask } ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 4/5] x86: correct VFPCLASSP{S,D} operand size handling 2020-02-11 10:26 ` [PATCH v5 4/5] x86: correct VFPCLASSP{S,D} operand size handling Jan Beulich @ 2020-02-11 11:50 ` H.J. Lu 2020-02-11 12:49 ` Jan Beulich 0 siblings, 1 reply; 26+ messages in thread From: H.J. Lu @ 2020-02-11 11:50 UTC (permalink / raw) To: Jan Beulich; +Cc: binutils On Tue, Feb 11, 2020 at 2:26 AM Jan Beulich <jbeulich@suse.com> wrote: > > With AVX512VL disabled (e.g. when writing code for the Knights family > of processors) these insns aren't ambiguous when used with a memory > source, and hence should be accepted without suffix or operand size > specifier. When AVX512VL is enabled, to be consistent with this as > well as other ambiguous operand size handling it would seem better to > just warn about the ambiguity in AT&T mode, and still default to 512-bit > operands (on the assumption that the code may have been written without > AVX512VL in mind yet), but it was requested to leave AT&T syntax mode > alone here. > > gas/ > 2020-02-XX Jan Beulich <jbeulich@suse.com> > > * config/tc-i386.c (avx512): New (at file scope), moved from > (check_VecOperands): ... here. > (process_suffix): Add [XYZ]MMword operand size handling. > * testsuite/gas/i386/avx512dq-inval.s: Add VFPCLASS tests. > * testsuite/gas/i386/noavx512-2.s: Add Intel syntax VFPCLASS > tests. > * testsuite/gas/i386/avx512dq-inval.l, > testsuite/gas/i386/noavx512-2.l: Adjust expectations. > > opcodes/ > 2020-02-XX Jan Beulich <jbeulich@suse.com> > > * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form > with Unspecified, making the present one AT&T syntax only. > * i386-tbl.h: Re-generate. > --- > v5: Re-base. > v4: Restrict to just Intel syntax mode. Re-base. > v3: Re-base. > > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -1840,6 +1840,8 @@ cpu_flags_and_not (i386_cpu_flags x, i38 > return x; > } > > +static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; > + > #define CPU_FLAGS_ARCH_MATCH 0x1 > #define CPU_FLAGS_64BIT_MATCH 0x2 > > @@ -5352,7 +5354,6 @@ check_VecOperands (const insn_template * > { > unsigned int op; > i386_cpu_flags cpu; > - static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; > > /* Templates allowing for ZMMword as well as YMMword and/or XMMword for > any one operand are implicity requiring AVX512VL support if the actual > @@ -6447,7 +6448,8 @@ process_suffix (void) > /* Accept FLDENV et al without suffix. */ > && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf)) > { > - unsigned int suffixes; > + unsigned int suffixes, evex = 0; > + i386_cpu_flags cpu; > > suffixes = !i.tm.opcode_modifier.no_bsuf; > if (!i.tm.opcode_modifier.no_wsuf) > @@ -6461,7 +6463,55 @@ process_suffix (void) > if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) > suffixes |= 1 << 5; > > - /* Are multiple suffixes allowed? */ > + /* For [XYZ]MMWORD operands inspect operand sizes. */ > + cpu = cpu_flags_and (i.tm.cpu_flags, avx512); > + if (!cpu_flags_all_zero (&cpu) && !i.broadcast) > + { > + unsigned int op; > + > + for (op = 0; op < i.tm.operands; ++op) > + { > + if (!cpu_arch_flags.bitfield.cpuavx512vl) > + { > + if (i.tm.operand_types[op].bitfield.ymmword) > + i.tm.operand_types[op].bitfield.xmmword = 0; > + if (i.tm.operand_types[op].bitfield.zmmword) > + i.tm.operand_types[op].bitfield.ymmword = 0; > + if (!i.tm.opcode_modifier.evex > + || i.tm.opcode_modifier.evex == EVEXDYN) > + i.tm.opcode_modifier.evex = EVEX512; > + } > + > + if (i.tm.operand_types[op].bitfield.xmmword > + + i.tm.operand_types[op].bitfield.ymmword > + + i.tm.operand_types[op].bitfield.zmmword < 2) > + continue; > + > + /* Any properly sized operand disambiguates the insn. */ > + if (i.types[op].bitfield.xmmword > + || i.types[op].bitfield.ymmword > + || i.types[op].bitfield.zmmword) > + { > + suffixes &= ~(7 << 6); > + evex = 0; > + break; > + } > + > + if ((i.flags[op] & Operand_Mem) > + && i.tm.operand_types[op].bitfield.unspecified) > + { > + if (i.tm.operand_types[op].bitfield.xmmword) > + suffixes |= 1 << 6; > + if (i.tm.operand_types[op].bitfield.ymmword) > + suffixes |= 1 << 7; > + if (i.tm.operand_types[op].bitfield.zmmword) > + suffixes |= 1 << 8; > + evex = EVEX512; > + } > + } > + } > + > + /* Are multiple suffixes / operand sizes allowed? */ > if (suffixes & (suffixes - 1)) > { > if (intel_syntax > @@ -6491,6 +6541,8 @@ process_suffix (void) > || (i.tm.base_opcode == 0x63 > && i.tm.cpu_flags.bitfield.cpu64)) > /* handled below */; > + else if (evex) > + i.tm.opcode_modifier.evex = evex; > else if (flag_code == CODE_16BIT) > i.suffix = WORD_MNEM_SUFFIX; > else if (!i.tm.opcode_modifier.no_lsuf) So this change only impacts Intel syntax with AVX512VL disabled. Why are there so many assembler changes? If they are really needed, can you make them conditioned on Intel syntax? -- H.J. ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 4/5] x86: correct VFPCLASSP{S,D} operand size handling 2020-02-11 11:50 ` H.J. Lu @ 2020-02-11 12:49 ` Jan Beulich 2020-02-11 12:56 ` H.J. Lu 0 siblings, 1 reply; 26+ messages in thread From: Jan Beulich @ 2020-02-11 12:49 UTC (permalink / raw) To: H.J. Lu; +Cc: binutils On 11.02.2020 12:49, H.J. Lu wrote: > On Tue, Feb 11, 2020 at 2:26 AM Jan Beulich <jbeulich@suse.com> wrote: >> >> With AVX512VL disabled (e.g. when writing code for the Knights family >> of processors) these insns aren't ambiguous when used with a memory >> source, and hence should be accepted without suffix or operand size >> specifier. When AVX512VL is enabled, to be consistent with this as >> well as other ambiguous operand size handling it would seem better to >> just warn about the ambiguity in AT&T mode, and still default to 512-bit >> operands (on the assumption that the code may have been written without >> AVX512VL in mind yet), but it was requested to leave AT&T syntax mode >> alone here. >> >> gas/ >> 2020-02-XX Jan Beulich <jbeulich@suse.com> >> >> * config/tc-i386.c (avx512): New (at file scope), moved from >> (check_VecOperands): ... here. >> (process_suffix): Add [XYZ]MMword operand size handling. >> * testsuite/gas/i386/avx512dq-inval.s: Add VFPCLASS tests. >> * testsuite/gas/i386/noavx512-2.s: Add Intel syntax VFPCLASS >> tests. >> * testsuite/gas/i386/avx512dq-inval.l, >> testsuite/gas/i386/noavx512-2.l: Adjust expectations. >> >> opcodes/ >> 2020-02-XX Jan Beulich <jbeulich@suse.com> >> >> * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form >> with Unspecified, making the present one AT&T syntax only. >> * i386-tbl.h: Re-generate. >> --- >> v5: Re-base. >> v4: Restrict to just Intel syntax mode. Re-base. >> v3: Re-base. >> >> --- a/gas/config/tc-i386.c >> +++ b/gas/config/tc-i386.c >> @@ -1840,6 +1840,8 @@ cpu_flags_and_not (i386_cpu_flags x, i38 >> return x; >> } >> >> +static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; >> + >> #define CPU_FLAGS_ARCH_MATCH 0x1 >> #define CPU_FLAGS_64BIT_MATCH 0x2 >> >> @@ -5352,7 +5354,6 @@ check_VecOperands (const insn_template * >> { >> unsigned int op; >> i386_cpu_flags cpu; >> - static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; >> >> /* Templates allowing for ZMMword as well as YMMword and/or XMMword for >> any one operand are implicity requiring AVX512VL support if the actual >> @@ -6447,7 +6448,8 @@ process_suffix (void) >> /* Accept FLDENV et al without suffix. */ >> && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf)) >> { >> - unsigned int suffixes; >> + unsigned int suffixes, evex = 0; >> + i386_cpu_flags cpu; >> >> suffixes = !i.tm.opcode_modifier.no_bsuf; >> if (!i.tm.opcode_modifier.no_wsuf) >> @@ -6461,7 +6463,55 @@ process_suffix (void) >> if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) >> suffixes |= 1 << 5; >> >> - /* Are multiple suffixes allowed? */ >> + /* For [XYZ]MMWORD operands inspect operand sizes. */ >> + cpu = cpu_flags_and (i.tm.cpu_flags, avx512); >> + if (!cpu_flags_all_zero (&cpu) && !i.broadcast) >> + { >> + unsigned int op; >> + >> + for (op = 0; op < i.tm.operands; ++op) >> + { >> + if (!cpu_arch_flags.bitfield.cpuavx512vl) >> + { >> + if (i.tm.operand_types[op].bitfield.ymmword) >> + i.tm.operand_types[op].bitfield.xmmword = 0; >> + if (i.tm.operand_types[op].bitfield.zmmword) >> + i.tm.operand_types[op].bitfield.ymmword = 0; >> + if (!i.tm.opcode_modifier.evex >> + || i.tm.opcode_modifier.evex == EVEXDYN) >> + i.tm.opcode_modifier.evex = EVEX512; >> + } >> + >> + if (i.tm.operand_types[op].bitfield.xmmword >> + + i.tm.operand_types[op].bitfield.ymmword >> + + i.tm.operand_types[op].bitfield.zmmword < 2) >> + continue; >> + >> + /* Any properly sized operand disambiguates the insn. */ >> + if (i.types[op].bitfield.xmmword >> + || i.types[op].bitfield.ymmword >> + || i.types[op].bitfield.zmmword) >> + { >> + suffixes &= ~(7 << 6); >> + evex = 0; >> + break; >> + } >> + >> + if ((i.flags[op] & Operand_Mem) >> + && i.tm.operand_types[op].bitfield.unspecified) >> + { >> + if (i.tm.operand_types[op].bitfield.xmmword) >> + suffixes |= 1 << 6; >> + if (i.tm.operand_types[op].bitfield.ymmword) >> + suffixes |= 1 << 7; >> + if (i.tm.operand_types[op].bitfield.zmmword) >> + suffixes |= 1 << 8; >> + evex = EVEX512; >> + } >> + } >> + } >> + >> + /* Are multiple suffixes / operand sizes allowed? */ >> if (suffixes & (suffixes - 1)) >> { >> if (intel_syntax >> @@ -6491,6 +6541,8 @@ process_suffix (void) >> || (i.tm.base_opcode == 0x63 >> && i.tm.cpu_flags.bitfield.cpu64)) >> /* handled below */; >> + else if (evex) >> + i.tm.opcode_modifier.evex = evex; >> else if (flag_code == CODE_16BIT) >> i.suffix = WORD_MNEM_SUFFIX; >> else if (!i.tm.opcode_modifier.no_lsuf) > > So this change only impacts Intel syntax with AVX512VL disabled. Why > are there so many > assembler changes? There aren't "many" changes, it's just one larger block of code that needs adding (paralleling the suffix checking for GPR(-like) operands). > If they are really needed, can you make them > conditioned on Intel > syntax? Well, that block of code is the meat of the change, so yes, it is needed. Some of what it does may also be beneficial for AT&T mode, but yes, I think I can make all of it Intel-syntax only (with a comment saying why this is). Jan ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 4/5] x86: correct VFPCLASSP{S,D} operand size handling 2020-02-11 12:49 ` Jan Beulich @ 2020-02-11 12:56 ` H.J. Lu 0 siblings, 0 replies; 26+ messages in thread From: H.J. Lu @ 2020-02-11 12:56 UTC (permalink / raw) To: Jan Beulich; +Cc: binutils On Tue, Feb 11, 2020 at 4:49 AM Jan Beulich <jbeulich@suse.com> wrote: > > On 11.02.2020 12:49, H.J. Lu wrote: > > On Tue, Feb 11, 2020 at 2:26 AM Jan Beulich <jbeulich@suse.com> wrote: > >> > >> With AVX512VL disabled (e.g. when writing code for the Knights family > >> of processors) these insns aren't ambiguous when used with a memory > >> source, and hence should be accepted without suffix or operand size > >> specifier. When AVX512VL is enabled, to be consistent with this as > >> well as other ambiguous operand size handling it would seem better to > >> just warn about the ambiguity in AT&T mode, and still default to 512-bit > >> operands (on the assumption that the code may have been written without > >> AVX512VL in mind yet), but it was requested to leave AT&T syntax mode > >> alone here. > >> > >> gas/ > >> 2020-02-XX Jan Beulich <jbeulich@suse.com> > >> > >> * config/tc-i386.c (avx512): New (at file scope), moved from > >> (check_VecOperands): ... here. > >> (process_suffix): Add [XYZ]MMword operand size handling. > >> * testsuite/gas/i386/avx512dq-inval.s: Add VFPCLASS tests. > >> * testsuite/gas/i386/noavx512-2.s: Add Intel syntax VFPCLASS > >> tests. > >> * testsuite/gas/i386/avx512dq-inval.l, > >> testsuite/gas/i386/noavx512-2.l: Adjust expectations. > >> > >> opcodes/ > >> 2020-02-XX Jan Beulich <jbeulich@suse.com> > >> > >> * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form > >> with Unspecified, making the present one AT&T syntax only. > >> * i386-tbl.h: Re-generate. > >> --- > >> v5: Re-base. > >> v4: Restrict to just Intel syntax mode. Re-base. > >> v3: Re-base. > >> > >> --- a/gas/config/tc-i386.c > >> +++ b/gas/config/tc-i386.c > >> @@ -1840,6 +1840,8 @@ cpu_flags_and_not (i386_cpu_flags x, i38 > >> return x; > >> } > >> > >> +static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; > >> + > >> #define CPU_FLAGS_ARCH_MATCH 0x1 > >> #define CPU_FLAGS_64BIT_MATCH 0x2 > >> > >> @@ -5352,7 +5354,6 @@ check_VecOperands (const insn_template * > >> { > >> unsigned int op; > >> i386_cpu_flags cpu; > >> - static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; > >> > >> /* Templates allowing for ZMMword as well as YMMword and/or XMMword for > >> any one operand are implicity requiring AVX512VL support if the actual > >> @@ -6447,7 +6448,8 @@ process_suffix (void) > >> /* Accept FLDENV et al without suffix. */ > >> && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf)) > >> { > >> - unsigned int suffixes; > >> + unsigned int suffixes, evex = 0; > >> + i386_cpu_flags cpu; > >> > >> suffixes = !i.tm.opcode_modifier.no_bsuf; > >> if (!i.tm.opcode_modifier.no_wsuf) > >> @@ -6461,7 +6463,55 @@ process_suffix (void) > >> if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) > >> suffixes |= 1 << 5; > >> > >> - /* Are multiple suffixes allowed? */ > >> + /* For [XYZ]MMWORD operands inspect operand sizes. */ > >> + cpu = cpu_flags_and (i.tm.cpu_flags, avx512); > >> + if (!cpu_flags_all_zero (&cpu) && !i.broadcast) > >> + { > >> + unsigned int op; > >> + > >> + for (op = 0; op < i.tm.operands; ++op) > >> + { > >> + if (!cpu_arch_flags.bitfield.cpuavx512vl) > >> + { > >> + if (i.tm.operand_types[op].bitfield.ymmword) > >> + i.tm.operand_types[op].bitfield.xmmword = 0; > >> + if (i.tm.operand_types[op].bitfield.zmmword) > >> + i.tm.operand_types[op].bitfield.ymmword = 0; > >> + if (!i.tm.opcode_modifier.evex > >> + || i.tm.opcode_modifier.evex == EVEXDYN) > >> + i.tm.opcode_modifier.evex = EVEX512; > >> + } > >> + > >> + if (i.tm.operand_types[op].bitfield.xmmword > >> + + i.tm.operand_types[op].bitfield.ymmword > >> + + i.tm.operand_types[op].bitfield.zmmword < 2) > >> + continue; > >> + > >> + /* Any properly sized operand disambiguates the insn. */ > >> + if (i.types[op].bitfield.xmmword > >> + || i.types[op].bitfield.ymmword > >> + || i.types[op].bitfield.zmmword) > >> + { > >> + suffixes &= ~(7 << 6); > >> + evex = 0; > >> + break; > >> + } > >> + > >> + if ((i.flags[op] & Operand_Mem) > >> + && i.tm.operand_types[op].bitfield.unspecified) > >> + { > >> + if (i.tm.operand_types[op].bitfield.xmmword) > >> + suffixes |= 1 << 6; > >> + if (i.tm.operand_types[op].bitfield.ymmword) > >> + suffixes |= 1 << 7; > >> + if (i.tm.operand_types[op].bitfield.zmmword) > >> + suffixes |= 1 << 8; > >> + evex = EVEX512; > >> + } > >> + } > >> + } > >> + > >> + /* Are multiple suffixes / operand sizes allowed? */ > >> if (suffixes & (suffixes - 1)) > >> { > >> if (intel_syntax > >> @@ -6491,6 +6541,8 @@ process_suffix (void) > >> || (i.tm.base_opcode == 0x63 > >> && i.tm.cpu_flags.bitfield.cpu64)) > >> /* handled below */; > >> + else if (evex) > >> + i.tm.opcode_modifier.evex = evex; > >> else if (flag_code == CODE_16BIT) > >> i.suffix = WORD_MNEM_SUFFIX; > >> else if (!i.tm.opcode_modifier.no_lsuf) > > > > So this change only impacts Intel syntax with AVX512VL disabled. Why > > are there so many > > assembler changes? > > There aren't "many" changes, it's just one larger block of code that > needs adding (paralleling the suffix checking for GPR(-like) operands). > > > If they are really needed, can you make them > > conditioned on Intel > > syntax? > > Well, that block of code is the meat of the change, so yes, it is > needed. Some of what it does may also be beneficial for AT&T mode, Do you have a testcase to show that it is useful for AT&T syntax? If not, please enable the code path only for Intel syntax with a comment. > but yes, I think I can make all of it Intel-syntax only (with a > comment saying why this is). > > Jan -- H.J. ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v5 5/5] x86-64: Intel64 adjustments for insns dealing with far pointers 2020-02-11 10:23 [PATCH v5 0/5] x86: operand size handling improvements Jan Beulich ` (3 preceding siblings ...) 2020-02-11 10:26 ` [PATCH v5 4/5] x86: correct VFPCLASSP{S,D} operand size handling Jan Beulich @ 2020-02-11 10:27 ` Jan Beulich 2020-02-11 11:53 ` H.J. Lu 4 siblings, 1 reply; 26+ messages in thread From: Jan Beulich @ 2020-02-11 10:27 UTC (permalink / raw) To: binutils; +Cc: H.J. Lu AMD and Intel differ in their handling of far indirect branches as well as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note how the latter three were hybrids so far, while far branches were fully AMD-like.) gas/ 2020-02-XX Jan Beulich <jbeulich@suse.com> PR gas/24546 * config/tc-i386-intel.c (i386_intel_operand): Also handle CALL/JMP in O_tbyte_ptr case. * doc/c-i386.texi: Mention far call and full pointer load ISA differences. * testsuite/gas/i386/x86-64-branch-3.s, testsuite/gas/i386/x86-64-intel64.s: Add 64-bit far call cases. * testsuite/gas/i386/x86-64-branch-3.d, testsuite/gas/i386/x86-64-intel64.d: Adjust expectations. * testsuite/gas/i386/x86-64-branch-5.l, testsuite/gas/i386/x86-64-branch-5.s: New. * testsuite/gas/i386/i386.exp: Run new test. opcodes/ 2020-02-XX Jan Beulich <jbeulich@suse.com> PR gas/24546 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode. * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into Amd64 and Intel64 templates. (call, jmp): Likewise for far indirect variants. Dro Unspecified. * i386-tbl.h: Re-generate. --- v5: Re-base. v4: Add documentation. v3: New. --- a/gas/config/tc-i386-intel.c +++ b/gas/config/tc-i386-intel.c @@ -694,9 +694,11 @@ i386_intel_operand (char *operand_string if (got_a_float == 1) suffix = LONG_DOUBLE_MNEM_SUFFIX; else if ((current_templates->start->operand_types[0].bitfield.fword - || current_templates->start->operand_types[0].bitfield.tbyte) + || current_templates->start->operand_types[0].bitfield.tbyte + || current_templates->start->opcode_modifier.jump == JUMP_DWORD + || current_templates->start->opcode_modifier.jump == JUMP) && flag_code == CODE_64BIT) - suffix = QWORD_MNEM_SUFFIX; /* l[fgs]s, [ls][gi]dt */ + suffix = QWORD_MNEM_SUFFIX; /* l[fgs]s, [ls][gi]dt, call, jmp */ else i.types[this_operand].bitfield.byte = 1; /* cause an error */ break; --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -1455,6 +1455,18 @@ There are some discrepancies between AMD @item For @samp{movsxd} with 16-bit destination register, AMD64 supports 32-bit source operand and Intel64 supports 16-bit source operand. + +@item For far branches (with explicit memory operand), both ISAs support +32- and 16-bit operand size. Intel64 additionally supports 64-bit +operand size, encoded as @samp{ljmpq} and @samp{lcallq} in AT&T syntax +and with an explicit @samp{tbyte ptr} operand size specifier in Intel +syntax. + +@item @samp{lfs}, @samp{lgs}, and @samp{lss} similarly allow for 16- +and 32-bit operand size (32- and 48-bit memory operand) in both ISAs, +while Intel64 additionally supports 64-bit operand sise (80-bit memory +operands). + @end itemize @node i386-Bugs --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -1142,6 +1142,7 @@ if [expr ([istarget "i*86-*-*"] || [ista run_dump_test "x86-64-branch-2" run_dump_test "x86-64-branch-3" run_list_test "x86-64-branch-4" "-al -mintel64" + run_list_test "x86-64-branch-5" "-al" run_dump_test "x86-64-gotpcrel" run_dump_test "x86-64-gotpcrel-no-relax" --- a/gas/testsuite/gas/i386/x86-64-branch-3.d +++ b/gas/testsuite/gas/i386/x86-64-branch-3.d @@ -16,4 +16,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 48 e8 00 00 00 00 data16 rex\.W callq 1c <bar\+0xf> 18: R_X86_64_PLT32 foo-0x4 [ ]*[a-f0-9]+: 66 c7 f8 00 00 xbeginw 21 <bar\+0x14> 1f: R_X86_64_PC16 foo-0x2 [ ]*[a-f0-9]+: 66 48 c7 f8 00 00 00 00 data16 xbeginq 29 <bar\+0x1c> 25: R_X86_64_PLT32 foo-0x4 +[ ]*[a-f0-9]+: 48 ff 18 lcallq \*\(%rax\) +[ ]*[a-f0-9]+: 48 ff 29 ljmpq \*\(%rcx\) #pass --- a/gas/testsuite/gas/i386/x86-64-branch-3.s +++ b/gas/testsuite/gas/i386/x86-64-branch-3.s @@ -10,3 +10,6 @@ bar: data16 xbegin foo data16 rex.w xbegin foo + + lcallq *(%rax) + ljmpq *(%rcx) --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-branch-5.l @@ -0,0 +1,19 @@ +.*: Assembler messages: +.*:2: Error: unsupported syntax for `lcall' +.*:3: Error: unsupported syntax for `lfs' +.*:4: Error: unsupported syntax for `lfs' +.*:5: Error: unsupported syntax for `lgs' +.*:6: Error: unsupported syntax for `lgs' +.*:7: Error: unsupported syntax for `ljmp' +.*:8: Error: unsupported syntax for `lss' +.*:9: Error: unsupported syntax for `lss' +.*:12: Error: unsupported syntax for `call' +.*:13: Error: unsupported syntax for `lfs' +.*:14: Error: unsupported syntax for `lfs' +.*:15: Error: unsupported syntax for `lgs' +.*:16: Error: unsupported syntax for `lgs' +.*:17: Error: unsupported syntax for `jmp' +.*:18: Error: unsupported syntax for `lss' +.*:19: Error: unsupported syntax for `lss' +GAS LISTING .* +#pass --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-branch-5.s @@ -0,0 +1,19 @@ + .text + lcallq *(%rax) + lfs (%rax), %rax + lfsq (%rax), %rax + lgs (%rax), %rax + lgsq (%rax), %rax + ljmpq *(%rax) + lss (%rax), %rax + lssq (%rax), %rax + + .intel_syntax noprefix + call TBYTE PTR [rax] + lfs rax, [rax] + lfs rax, TBYTE PTR [rax] + lgs rax, [rax] + lgs rax, TBYTE PTR [rax] + jmp TBYTE PTR [rax] + lss rax, [rax] + lss rax, TBYTE PTR [rax] --- a/gas/testsuite/gas/i386/x86-64-intel64.d +++ b/gas/testsuite/gas/i386/x86-64-intel64.d @@ -12,6 +12,8 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f b5 11 lgs \(%rcx\),%rdx [ ]*[a-f0-9]+: 48 0f b2 1a lss \(%rdx\),%rbx [ ]*[a-f0-9]+: 48 0f b2 1a lss \(%rdx\),%rbx +[ ]*[a-f0-9]+: 48 ff 18 rex\.W lcall \*\(%rax\) +[ ]*[a-f0-9]+: 48 ff 29 rex\.W ljmp \*\(%rcx\) [ ]*[a-f0-9]+: 0f 05 syscall [ ]*[a-f0-9]+: 0f 07 sysret [ ]*[a-f0-9]+: 48 0f 07 sysretq * @@ -21,4 +23,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f b5 0a lgs \(%rdx\),%rcx [ ]*[a-f0-9]+: 48 0f b2 13 lss \(%rbx\),%rdx [ ]*[a-f0-9]+: 48 0f b2 13 lss \(%rbx\),%rdx +[ ]*[a-f0-9]+: 48 ff 19 rex\.W lcall \*\(%rcx\) +[ ]*[a-f0-9]+: 48 ff 2a rex\.W ljmp \*\(%rdx\) #pass --- a/gas/testsuite/gas/i386/x86-64-intel64.s +++ b/gas/testsuite/gas/i386/x86-64-intel64.s @@ -10,6 +10,9 @@ _start: lss (%rdx), %rbx lssq (%rdx), %rbx + lcallq *(%rax) + ljmpq *(%rcx) + syscall sysretl sysretq @@ -21,3 +24,6 @@ _start: lgs rcx, tbyte ptr [rdx] lss rdx, [rbx] lss rdx, tbyte ptr [rbx] + + call tbyte ptr [rcx] + jmp tbyte ptr [rdx] --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -2331,8 +2331,8 @@ struct dis386 { 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise '!' => change condition from true to false or from false to true. '%' => add 1 upper case letter to the macro. - '^' => print 'w' or 'l' depending on operand size prefix or - suffix_always is true (lcall/ljmp). + '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size + prefix or suffix_always is true (lcall/ljmp). '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending on operand size prefix. '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction @@ -13296,6 +13296,12 @@ case_S: case '^': if (intel_syntax) break; + if (isa64 == intel64 && (rex & REX_W)) + { + USED_REX (REX_W); + *obufp++ = 'q'; + break; + } if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) { if (sizeflag & DFLAG) --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -197,9 +197,12 @@ lea, 2, 0x8d, None, 1, 0, Modrm|Anysize| // Load segment registers from memory. lds, 2, 0xc5, None, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 } les, 2, 0xc4, None, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 } -lfs, 2, 0xfb4, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { DWord|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -lgs, 2, 0xfb5, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { DWord|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -lss, 2, 0xfb2, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { DWord|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +lfs, 2, 0xfb4, None, 2, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } +lfs, 2, 0xfb4, None, 2, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf|No_ldSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +lgs, 2, 0xfb5, None, 2, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } +lgs, 2, 0xfb5, None, 2, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf|No_ldSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +lss, 2, 0xfb2, None, 2, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } +lss, 2, 0xfb2, None, 2, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf|No_ldSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // Flags register instructions. clc, 0, 0xf8, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } @@ -375,12 +378,13 @@ call, 1, 0xe8, None, 1, Cpu64, Intel64|J call, 1, 0xff, 0x2, 1, CpuNo64, Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex } call, 1, 0xff, 0x2, 1, Cpu64, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex } call, 1, 0xff, 0x2, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex } -// Intel Syntax +// Intel Syntax remaining call instances. call, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 } -// Intel Syntax -call, 1, 0xff, 0x3, 1, 0, Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex } +call, 1, 0xff, 0x3, 1, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|Fword|BaseIndex } +call, 1, 0xff, 0x3, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Fword|Tbyte|BaseIndex } lcall, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 } -lcall, 1, 0xff, 0x3, 1, 0, Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex } +lcall, 1, 0xff, 0x3, 1, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex } +lcall, 1, 0xff, 0x3, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex } jmp, 1, 0xeb, None, 1, CpuNo64, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 } jmp, 1, 0xeb, None, 1, Cpu64, Amd64|Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32S } @@ -388,12 +392,13 @@ jmp, 1, 0xeb, None, 1, Cpu64, Intel64|Ju jmp, 1, 0xff, 0x4, 1, CpuNo64, Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex } jmp, 1, 0xff, 0x4, 1, Cpu64, Amd64|Modrm|JumpAbsolute|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex } jmp, 1, 0xff, 0x4, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex } -// Intel Syntax. +// Intel Syntax remaining jmp instances. jmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 } -// Intel Syntax. -jmp, 1, 0xff, 0x5, 1, 0, Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex } +jmp, 1, 0xff, 0x5, 1, 0, Amd64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|Fword|BaseIndex } +jmp, 1, 0xff, 0x5, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Fword|Tbyte|BaseIndex } ljmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 } -ljmp, 1, 0xff, 0x5, 1, 0, Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex } +ljmp, 1, 0xff, 0x5, 1, 0, Amd64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex } +ljmp, 1, 0xff, 0x5, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex } ret, 0, 0xc3, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk|BNDPrefixOk, { 0 } ret, 1, 0xc2, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk|BNDPrefixOk, { Imm16 } ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 5/5] x86-64: Intel64 adjustments for insns dealing with far pointers 2020-02-11 10:27 ` [PATCH v5 5/5] x86-64: Intel64 adjustments for insns dealing with far pointers Jan Beulich @ 2020-02-11 11:53 ` H.J. Lu 2020-02-12 8:11 ` Jan Beulich 0 siblings, 1 reply; 26+ messages in thread From: H.J. Lu @ 2020-02-11 11:53 UTC (permalink / raw) To: Jan Beulich; +Cc: binutils On Tue, Feb 11, 2020 at 2:26 AM Jan Beulich <jbeulich@suse.com> wrote: > > AMD and Intel differ in their handling of far indirect branches as well > as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note > how the latter three were hybrids so far, while far branches were fully > AMD-like.) > > gas/ > 2020-02-XX Jan Beulich <jbeulich@suse.com> > > PR gas/24546 > * config/tc-i386-intel.c (i386_intel_operand): Also handle CALL/JMP > in O_tbyte_ptr case. > * doc/c-i386.texi: Mention far call and full pointer load ISA > differences. > * testsuite/gas/i386/x86-64-branch-3.s, > testsuite/gas/i386/x86-64-intel64.s: Add 64-bit far call cases. > * testsuite/gas/i386/x86-64-branch-3.d, > testsuite/gas/i386/x86-64-intel64.d: Adjust expectations. > * testsuite/gas/i386/x86-64-branch-5.l, > testsuite/gas/i386/x86-64-branch-5.s: New. > * testsuite/gas/i386/i386.exp: Run new test. > > opcodes/ > 2020-02-XX Jan Beulich <jbeulich@suse.com> > > PR gas/24546 > * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode. > * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into > Amd64 and Intel64 templates. > (call, jmp): Likewise for far indirect variants. Dro > Unspecified. > * i386-tbl.h: Re-generate. OK. Thanks. -- H.J. ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 5/5] x86-64: Intel64 adjustments for insns dealing with far pointers 2020-02-11 11:53 ` H.J. Lu @ 2020-02-12 8:11 ` Jan Beulich 0 siblings, 0 replies; 26+ messages in thread From: Jan Beulich @ 2020-02-12 8:11 UTC (permalink / raw) To: H.J. Lu; +Cc: binutils On 11.02.2020 12:52, H.J. Lu wrote: > On Tue, Feb 11, 2020 at 2:26 AM Jan Beulich <jbeulich@suse.com> wrote: >> >> AMD and Intel differ in their handling of far indirect branches as well >> as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note >> how the latter three were hybrids so far, while far branches were fully >> AMD-like.) >> >> gas/ >> 2020-02-XX Jan Beulich <jbeulich@suse.com> >> >> PR gas/24546 >> * config/tc-i386-intel.c (i386_intel_operand): Also handle CALL/JMP >> in O_tbyte_ptr case. >> * doc/c-i386.texi: Mention far call and full pointer load ISA >> differences. >> * testsuite/gas/i386/x86-64-branch-3.s, >> testsuite/gas/i386/x86-64-intel64.s: Add 64-bit far call cases. >> * testsuite/gas/i386/x86-64-branch-3.d, >> testsuite/gas/i386/x86-64-intel64.d: Adjust expectations. >> * testsuite/gas/i386/x86-64-branch-5.l, >> testsuite/gas/i386/x86-64-branch-5.s: New. >> * testsuite/gas/i386/i386.exp: Run new test. >> >> opcodes/ >> 2020-02-XX Jan Beulich <jbeulich@suse.com> >> >> PR gas/24546 >> * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode. >> * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into >> Amd64 and Intel64 templates. >> (call, jmp): Likewise for far indirect variants. Dro >> Unspecified. >> * i386-tbl.h: Re-generate. > > OK. There'll need to be a v6, as I've spotted an issue with non-64-bit code in -mintel64 mode (which occurred to me only when starting to deal with the vendor difference also for Jcc). v4 had an adjustment for this, and I wrongly thought it could be dropped altogether when re-basing over your Intel64-only change. (On the positive side I think a few other templates will be able to be folded as a follow-on to the fix I'm intending to make.) Jan ^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2020-02-12 9:19 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
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2020-02-11 10:23 [PATCH v5 0/5] x86: operand size handling improvements Jan Beulich
2020-02-11 10:25 ` [PATCH v5 1/5] x86: also disallow non-byte/-word registers with byte/word suffix Jan Beulich
2020-02-11 11:27 ` H.J. Lu
2020-02-11 10:25 ` [PATCH v5 3/5] x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZX Jan Beulich
2020-02-11 10:25 ` [PATCH v5 2/5] x86: move certain MOVSX/MOVZX tests Jan Beulich
2020-02-11 11:43 ` H.J. Lu
2020-02-11 11:55 ` Jan Beulich
2020-02-11 12:20 ` H.J. Lu
2020-02-11 12:58 ` Jan Beulich
2020-02-11 13:02 ` H.J. Lu
2020-02-11 13:04 ` Jan Beulich
2020-02-11 13:07 ` H.J. Lu
2020-02-11 16:45 ` Jan Beulich
2020-02-11 17:04 ` H.J. Lu
2020-02-11 20:12 ` [PATCH] x86: Remove movsx/movzx with memory operand from AT&T syntax H.J. Lu
2020-02-11 23:34 ` H.J. Lu
2020-02-11 23:52 ` H.J. Lu
2020-02-12 3:19 ` [PATCH] x86: Remove movsx/movzx with 16/32-bit " H.J. Lu
2020-02-12 9:19 ` Jan Beulich
2020-02-11 10:26 ` [PATCH v5 4/5] x86: correct VFPCLASSP{S,D} operand size handling Jan Beulich
2020-02-11 11:50 ` H.J. Lu
2020-02-11 12:49 ` Jan Beulich
2020-02-11 12:56 ` H.J. Lu
2020-02-11 10:27 ` [PATCH v5 5/5] x86-64: Intel64 adjustments for insns dealing with far pointers Jan Beulich
2020-02-11 11:53 ` H.J. Lu
2020-02-12 8:11 ` Jan Beulich
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