From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 83506 invoked by alias); 25 Feb 2020 08:29:41 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 83497 invoked by uid 89); 25 Feb 2020 08:29:41 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.8 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.1 spammy=HX-Received:Tue, H*Ad:U*claziss, HX-Languages-Length:1477, HContent-Transfer-Encoding:8bit X-HELO: mail-wm1-f53.google.com Received: from mail-wm1-f53.google.com (HELO mail-wm1-f53.google.com) (209.85.128.53) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 25 Feb 2020 08:29:31 +0000 Received: by mail-wm1-f53.google.com with SMTP id m3so1960908wmi.0 for ; Tue, 25 Feb 2020 00:29:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=s+mhicImsSAmyrsya8zaMSz7ZN5EIY5C87aRQEuGYNY=; b=cMHkR0GdVdPaVEQ06YLnMuIMpBdSkf2GJ2/zHjM9lylbEX9UBoWQcLV5oUuhqvBuM7 2T7Qio+Dguq/X0+/z1SQMQwBOVxNpBF41mf5S4zvvs0Jr6ReQ8UZiENj2OvQSr/dBI37 rZ1mj00pGBa2j52qYQ8yhm5ECg0hEOTrg8rmaBk+CXiw+pJPtuYwgozGyOfBNA5hNl8e cSPx6KXD/4+U6H/phqfUF5ABhT+ORQSe5oOcxWpXHHXAPTt2j8hxPAocoCb+C7fQOROz LdBNY7x7SBuwVpxNt1LPM5v6jLAE0mSUDeyvKzYKqmru9DqcAT2Iq7E2maw6lIFe+nLG Wrcw== Return-Path: Received: from localhost.localdomain ([79.115.250.90]) by smtp.gmail.com with ESMTPSA id g14sm12687202wrv.58.2020.02.25.00.29.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Feb 2020 00:29:28 -0800 (PST) From: Claudiu Zissulescu To: binutils@sourceware.org Cc: claziss@synopsys.com, fbedard@synopsys.com Subject: [PATCH] [ARC][committed] Update int_vector_base aux register. Date: Tue, 25 Feb 2020 08:29:00 -0000 Message-Id: <20200225082921.199701-1-claziss@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-IsSubscribed: yes X-SW-Source: 2020-02/txt/msg00535.txt.bz2 INT_VECTOR_BASE auxiliary register is available across all ARC architectures. xxxx-xx-xx Claudiu Zissulescu * arc-regs.h (int_vector_base): Make it available for all ARC CPUs. Signed-off-by: Claudiu Zissulescu --- opcodes/ChangeLog | 5 +++++ opcodes/arc-regs.h | 3 +-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 73091b9e61..5d83578641 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2020-02-25 Claudiu Zissulescu + + * arc-regs.h (int_vector_base): Make it available for all ARC + CPUs. + 2020-02-20 Nelson Chu * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is diff --git a/opcodes/arc-regs.h b/opcodes/arc-regs.h index a1d98bf179..4494a0630a 100644 --- a/opcodes/arc-regs.h +++ b/opcodes/arc-regs.h @@ -71,8 +71,7 @@ DEF (0x21, ARC_OPCODE_ARCALL, NONE, count0) DEF (0x22, ARC_OPCODE_ARCALL, NONE, control0) DEF (0x23, ARC_OPCODE_ARCALL, NONE, limit0) DEF (0x24, ARC_OPCODE_ARCV1, NONE, pcport) -DEF (0x25, ARC_OPCODE_ARC700, NONE, int_vector_base) -DEF (0x25, ARC_OPCODE_ARCV2, NONE, int_vector_base) +DEF (0x25, ARC_OPCODE_ARCALL, NONE, int_vector_base) DEF (0x26, ARC_OPCODE_ARC600, NONE, aux_vbfdw_mode) DEF (0x27, ARC_OPCODE_ARC600, NONE, aux_vbfdw_bm0) DEF (0x28, ARC_OPCODE_ARC600, NONE, aux_vbfdw_bm1) -- 2.24.1