* [PATCH 1/2][Binutils][Arm] Fix thumb2 PLT branch offsets
@ 2020-03-30 8:08 Tamar Christina
2020-03-30 10:55 ` Nick Clifton
0 siblings, 1 reply; 2+ messages in thread
From: Tamar Christina @ 2020-03-30 8:08 UTC (permalink / raw)
To: binutils; +Cc: nd, Richard.Earnshaw, nickc, ramana.radhakrishnan
[-- Attachment #1: Type: text/plain, Size: 1007 bytes --]
Hi All,
When I previously changed these offsets I had incorrectly used an offset of -2
for this Thumb2 PLT. Unfortunately because we had no tests for this PLT I had
missed that the result was incorrect.
This patch fixes the offset to PC .-4 so that it correctly addresses the
previous instruction and adds a test for this PLT stub.
build on native hardware and regtested on
arm-none-elf, arm-none-elf (32 bit host),
arm-none-linux-gnueabihf, arm-none-linux-gnueabihf (32 bit host)
Cross-compiled and regtested on
arm-none-linux-gnueabihf, armeb-none-elf, arm-wince-pe
and no issues.
Ok for master? and for backport to binutils-2.34?
Thanks,
Tamar
bfd/ChangeLog:
2020-03-30 Tamar Christina <tamar.christina@arm.com>
* elf32-arm.c (elf32_thumb2_plt_entry): Fix PC-rel offset.
ld/ChangeLog:
2020-03-30 Tamar Christina <tamar.christina@arm.com>
* testsuite/ld-arm/arm-elf.exp (thumb-plt): New.
* testsuite/ld-arm/thumb-plt.d: New test.
* testsuite/ld-arm/thumb-plt.s: New test.
--
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diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 1ccbf143e0aea0ec5c5218285ba110ee8d06b9b0..0036ff96e593456e602c47775f1695fc0e629ea7 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -2453,8 +2453,8 @@ static const bfd_vma elf32_thumb2_plt_entry [] =
0x0c00f240, /* movw ip, #0xNNNN */
0x0c00f2c0, /* movt ip, #0xNNNN */
0xf8dc44fc, /* add ip, pc */
- 0xe7fdf000 /* ldr.w pc, [ip] */
- /* b .-2 */
+ 0xe7fcf000 /* ldr.w pc, [ip] */
+ /* b .-4 */
};
/* The format of the first entry in the procedure linkage table
diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp
index 18177d19224f7d40c3c8832206615e758cb979af..99a313999e7327fbeb0c344af4a66d2ee73771b6 100644
--- a/ld/testsuite/ld-arm/arm-elf.exp
+++ b/ld/testsuite/ld-arm/arm-elf.exp
@@ -1268,3 +1268,5 @@ run_dump_test "non-contiguous-arm3"
run_dump_test "non-contiguous-arm4"
run_dump_test "non-contiguous-arm5"
run_dump_test "non-contiguous-arm6"
+
+run_dump_test "thumb-plt"
diff --git a/ld/testsuite/ld-arm/thumb-plt.d b/ld/testsuite/ld-arm/thumb-plt.d
new file mode 100644
index 0000000000000000000000000000000000000000..441325b21db33bb12dfb21ca1d19045b951ba9fd
--- /dev/null
+++ b/ld/testsuite/ld-arm/thumb-plt.d
@@ -0,0 +1,34 @@
+#source: thumb-plt.s
+#name: Thumb only PLT and GOT
+#ld: -shared -e0
+#objdump: -dr
+#skip: *-*-pe *-*-wince *-*-vxworks armeb-*-* *-*-gnueabihf
+
+.*: +file format .*arm.*
+
+
+Disassembly of section \.plt:
+
+00000110 <\.plt>:
+ 110: b500 push {lr}
+ 112: f8df e008 ldr.w lr, \[pc, #8\] ; 11c <\.plt\+0xc>
+ 116: 44fe add lr, pc
+ 118: f85e ff08 ldr.w pc, \[lr, #8\]!
+ 11c: 0001009c \.word 0x0001009c
+
+00000120 <foo@plt>:
+ 120: f240 0c98 movw ip, #152 ; 0x98
+ 124: f2c0 0c01 movt ip, #1
+ 128: 44fc add ip, pc
+ 12a: f8dc f000 ldr.w pc, \[ip\]
+ 12e: e7fc b.n 12a <foo@plt\+0xa>
+
+Disassembly of section .text:
+
+00000130 <bar>:
+ 130: b580 push {r7, lr}
+ 132: af00 add r7, sp, #0
+ 134: f7ff fff4 bl 120 <foo@plt>
+ 138: 4603 mov r3, r0
+ 13a: 4618 mov r0, r3
+ 13c: bd80 pop {r7, pc}
diff --git a/ld/testsuite/ld-arm/thumb-plt.s b/ld/testsuite/ld-arm/thumb-plt.s
new file mode 100644
index 0000000000000000000000000000000000000000..e3fd80f0f1d34ac1cdc1c46752aa8786e09ed9e5
--- /dev/null
+++ b/ld/testsuite/ld-arm/thumb-plt.s
@@ -0,0 +1,18 @@
+ .cpu cortex-m3
+ .text
+ .align 1
+ .global bar
+ .arch armv7-m
+ .syntax unified
+ .thumb
+ .thumb_func
+ .fpu softvfp
+ .type bar, %function
+bar:
+ push {r7, lr}
+ add r7, sp, #0
+ bl foo(PLT)
+ mov r3, r0
+ mov r0, r3
+ pop {r7, pc}
+ .size bar, .-bar
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH 1/2][Binutils][Arm] Fix thumb2 PLT branch offsets
2020-03-30 8:08 [PATCH 1/2][Binutils][Arm] Fix thumb2 PLT branch offsets Tamar Christina
@ 2020-03-30 10:55 ` Nick Clifton
0 siblings, 0 replies; 2+ messages in thread
From: Nick Clifton @ 2020-03-30 10:55 UTC (permalink / raw)
To: Tamar Christina, binutils; +Cc: nd, Richard.Earnshaw, ramana.radhakrishnan
Hi Tamar,
> bfd/ChangeLog:
>
> 2020-03-30 Tamar Christina <tamar.christina@arm.com>
>
> * elf32-arm.c (elf32_thumb2_plt_entry): Fix PC-rel offset.
>
> ld/ChangeLog:
>
> 2020-03-30 Tamar Christina <tamar.christina@arm.com>
>
> * testsuite/ld-arm/arm-elf.exp (thumb-plt): New.
> * testsuite/ld-arm/thumb-plt.d: New test.
> * testsuite/ld-arm/thumb-plt.s: New test.
Approved - please apply (branch and mainline).
Cheers
Nick
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