Hi All,

When you have a Thumb only PLT then the address in the GOT for PLT0 needs to
have the Thumb bit set since the instruction used in PLTn to get there is
`ldr.w	pc` which is an inter-working instruction:

the PLT sequence in question is

00000120 <foo@plt>:
 120:	f240 0c98 	movw	ip, #152	; 0x98
 124:	f2c0 0c01 	movt	ip, #1
 128:	44fc      	add	ip, pc
 12a:	f8dc f000 	ldr.w	pc, [ip]
 12e:	e7fc      	b.n	12a <foo@plt+0xa>

Disassembly of section .text:

00000130 <bar>:
 130:	b580      	push	{r7, lr}
 132:	af00      	add	r7, sp, #0
 134:	f7ff fff4 	bl	120 <foo@plt>

and previously the linker would generate

Hex dump of section '.got':
 ...
  0x000101b8 40010100 00000000 00000000 10010000 @...............

Which would make it jump and transition out of thumb mode and crash since you
only have thumb mode on such cores.

Now it correctly generates

Hex dump of section '.got':
 ...
  0x000101b8 40010100 00000000 00000000 11010000 @...............

build on native hardware and regtested on
  arm-none-elf, arm-none-elf (32 bit host),
  arm-none-linux-gnueabihf, arm-none-linux-gnueabihf (32 bit host)

Cross-compiled and regtested on
  arm-none-linux-gnueabihf, armeb-none-elf, arm-wince-pe
and no issues.

However I have not been able to do an execution test since I do not have a way
to actually test this. I am hoping the user who reported it can test it but the
patch is sound based on principles.

Amol would you be able to confirm the patch works on your setup?

Ok for master? and for backport to binutils-2.34?

Thanks,
Tamar

bfd/ChangeLog:

2020-03-30  Tamar Christina  <tamar.christina@arm.com>

	PR ld/16017
	* elf32-arm.c (elf32_arm_populate_plt_entry): Set LSB of the PLT0
	address in the GOT if in thumb only mode.

ld/ChangeLog:

2020-03-30  Tamar Christina  <tamar.christina@arm.com>

	PR ld/16017
	* testsuite/ld-arm/arm-elf.exp (thumb-plt-got): New.
	* testsuite/ld-arm/thumb-plt-got.d: New test.

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