From: "Marcus Comstedt" <marcus@mc.pp.se>
To: binutils@sourceware.org
Cc: Marcus Comstedt <marcus@mc.pp.se>
Subject: [PATCH v3 6/8] RISC-V: Mention -mbig-endian and -mlittle-endian in doc
Date: Sun, 27 Dec 2020 15:53:33 +0100 [thread overview]
Message-ID: <20201227145335.10521-7-marcus@mc.pp.se> (raw)
In-Reply-To: <20201227145335.10521-1-marcus@mc.pp.se>
gas/
* doc/as.texi: Add -mlittle-endian and -mbig-endian to docs.
* doc/c-riscv.texi: Likewise.
---
gas/doc/as.texi | 1 +
gas/doc/c-riscv.texi | 10 ++++++++++
2 files changed, 11 insertions(+)
diff --git a/gas/doc/as.texi b/gas/doc/as.texi
index 983cec3cbf..2f8142472f 100644
--- a/gas/doc/as.texi
+++ b/gas/doc/as.texi
@@ -536,6 +536,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
[@b{-fpic}|@b{-fPIC}|@b{-fno-pic}]
[@b{-march}=@var{ISA}]
[@b{-mabi}=@var{ABI}]
+ [@b{-mlittle}|@b{-mlittle-endian}|@b{-mbig}|@b{-mbig-endian}]
@end ifset
@ifset RL78
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index d63b1f3990..481bfbbfbb 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -99,6 +99,16 @@ read-only CSR can not be written by the CSR instructions.
@cindex @samp{-mno-csr-check} option, RISC-V
@item -mno-csr-check
Don't do CSR checking.
+
+@cindex @samp{-mlittle} option, RISC-V
+@cindex @samp{-mlittle-endian} option, RISC-V
+@item -mlittle, -mlittle-endian
+Generate code for a little endian machine.
+
+@cindex @samp{-mbig} option, RISC-V
+@cindex @samp{-mbig-endian} option, RISC-V
+@item -mbig, -mbig-endian
+Generate code for a big endian machine.
@end table
@c man end
--
2.26.2
next prev parent reply other threads:[~2020-12-27 14:53 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-27 14:53 [PATCH v3 0/8] RISC-V: Implement support for big endian targets Marcus Comstedt
2020-12-27 14:53 ` [PATCH v3 1/8] RISC-V: Support assembly and disassembly in big endian mode Marcus Comstedt
2020-12-27 14:53 ` [PATCH v3 2/8] RISC-V: Fix relocations " Marcus Comstedt
2020-12-27 14:53 ` [PATCH v3 3/8] RISC-V: Add big endian linker scripts Marcus Comstedt
2020-12-27 14:53 ` [PATCH v3 4/8] RISC-V: Recognize riscvNNbe* as target Marcus Comstedt
2020-12-27 14:53 ` [PATCH v3 5/8] RISC-V: Fix branch frag conversion on big endian Marcus Comstedt
2020-12-27 14:53 ` Marcus Comstedt [this message]
2021-01-04 23:03 ` [PATCH v3 6/8] RISC-V: Mention -mbig-endian and -mlittle-endian in doc Jim Wilson
2021-01-05 8:01 ` Marcus Comstedt
2021-01-05 18:12 ` Jim Wilson
2021-01-05 18:59 ` Jim Wilson
2021-01-05 21:19 ` Marcus Comstedt
2020-12-27 14:53 ` [PATCH v3 7/8] RISC-V: Fix nop generation on big endian Marcus Comstedt
2020-12-27 14:53 ` [PATCH v3 8/8] RISC-V: Fix testsuite failures Marcus Comstedt
2020-12-29 5:25 ` [PATCH v3 0/8] RISC-V: Implement support for big endian targets Nelson Chu
2020-12-29 11:26 ` Marcus Comstedt
2020-12-29 11:47 ` Marcus Comstedt
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